chipsfb_ofbus.c revision 1.1.6.2
1 /* $NetBSD: chipsfb_ofbus.c,v 1.1.6.2 2011/06/06 09:06:44 jruoho Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* 29 * C&T 6555x series. 30 * ofbus attachment for chipsfb 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: chipsfb_ofbus.c,v 1.1.6.2 2011/06/06 09:06:44 jruoho Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/kernel.h> 39 #include <sys/device.h> 40 #include <sys/malloc.h> 41 #include <sys/buf.h> 42 #include <uvm/uvm.h> 43 44 #include <machine/bus.h> 45 #include <machine/intr.h> 46 #include <machine/ofw.h> 47 #include <machine/pmap.h> 48 49 #include <dev/isa/isavar.h> 50 51 #include <dev/wscons/wsdisplayvar.h> 52 #include <dev/wscons/wsconsio.h> 53 #include <dev/rasops/rasops.h> 54 #include <dev/wscons/wsdisplay_vconsvar.h> 55 #include <dev/ofw/openfirm.h> 56 57 #include <dev/ic/ct65550reg.h> 58 #include <dev/ic/ct65550var.h> 59 #include <shark/ofw/igsfb_ofbusvar.h> 60 61 static int chipsfb_ofbus_is_console(int); 62 63 static int chipsfb_ofbus_console = 0; 64 static int chipsfb_ofbus_phandle = 0; 65 66 67 68 static int chipsfb_ofbus_match(device_t, struct cfdata *, void *); 69 static void chipsfb_ofbus_attach(device_t, device_t, void *); 70 static paddr_t chipsfb_ofbus_mmap(void *, void *, off_t, int); 71 int chipsfb_ofbus_cnattach(bus_space_tag_t, bus_space_tag_t); 72 73 CFATTACH_DECL_NEW(chipsfb_ofbus, sizeof(struct chipsfb_softc), 74 chipsfb_ofbus_match, chipsfb_ofbus_attach, NULL, NULL); 75 76 static const char const *compat_strings[] = { "CHPS,ct65550", NULL }; 77 78 vaddr_t chipsfb_mem_vaddr = 0, chipsfb_mmio_vaddr = 0; 79 paddr_t chipsfb_mem_paddr; 80 extern paddr_t isa_io_physaddr; 81 struct bus_space chipsfb_memt, chipsfb_iot; 82 83 #if (NCHIPSFB_OFBUS > 0) || (NVGA_OFBUS > 0) 84 extern int console_ihandle; 85 #endif 86 87 int 88 chipsfb_ofbus_cnattach(bus_space_tag_t iot, bus_space_tag_t memt) 89 { 90 int chosen_phandle, ct_node; 91 int stdout_ihandle, stdout_phandle; 92 uint32_t regs[16]; 93 //char mode_buffer[64]; 94 95 stdout_phandle = 0; 96 97 /* first find out if there's a ct65550 at all in this machine */ 98 ct_node = OF_finddevice("/vlbus/display"); 99 if (ct_node == -1) 100 return ENXIO; 101 if (of_compatible(ct_node, compat_strings) < 0) 102 return ENXIO; 103 104 /* 105 * now we know there's a CyberPro in this machine so map it into 106 * kernel space, even if it's not the console 107 */ 108 if (OF_getprop(ct_node, "reg", regs, sizeof(regs)) <= 0) 109 return ENXIO; 110 111 chipsfb_mem_paddr = be32toh(regs[10]); 112 /* 2MB RAM aperture, bufferable and cacheable */ 113 chipsfb_mem_vaddr = ofw_map(chipsfb_mem_paddr, 0x00200000, L2_B | L2_C); 114 /* 128kB MMIO registers */ 115 chipsfb_mmio_vaddr = ofw_map(chipsfb_mem_paddr + CT_OFF_BITBLT, 116 0x00020000, 0); 117 118 memcpy(&chipsfb_memt, memt, sizeof(struct bus_space)); 119 chipsfb_memt.bs_cookie = (void *)chipsfb_mem_vaddr; 120 memcpy(&chipsfb_iot, memt, sizeof(struct bus_space)); 121 chipsfb_iot.bs_cookie = (void *)chipsfb_mmio_vaddr; 122 123 /* 124 * check if the firmware output device is indeed the ct65550 125 */ 126 if ((chosen_phandle = OF_finddevice("/chosen")) == -1 || 127 OF_getprop(chosen_phandle, "stdout", &stdout_ihandle, 128 sizeof(stdout_ihandle)) != sizeof(stdout_ihandle)) { 129 return ENXIO; 130 } 131 stdout_ihandle = of_decode_int((void *)&stdout_ihandle); 132 stdout_phandle = OF_instance_to_package(stdout_ihandle); 133 134 if (stdout_phandle != ct_node) 135 return ENXIO; 136 137 138 chipsfb_ofbus_console = 1; 139 chipsfb_ofbus_phandle = stdout_phandle; 140 #if (NCHIPSFB_OFBUS > 0) || (NVGA_OFBUS > 0) 141 console_ihandle = stdout_ihandle; 142 #endif 143 /* we're all set, now let's wait for chipsfb to attach */ 144 145 return 0; 146 } 147 148 static int 149 chipsfb_ofbus_is_console(int phandle) 150 { 151 152 return chipsfb_ofbus_console && (phandle == chipsfb_ofbus_phandle); 153 } 154 155 156 static int 157 chipsfb_ofbus_match(device_t parent, struct cfdata *match, void *aux) 158 { 159 struct ofbus_attach_args *oba = aux; 160 161 if (of_compatible(oba->oba_phandle, compat_strings) < 0) 162 return 0; 163 164 return 10; /* beat vga etc. */ 165 } 166 167 static void 168 chipsfb_ofbus_attach(device_t parent, device_t self, void *aux) 169 { 170 struct chipsfb_softc *sc = device_private(self); 171 struct ofbus_attach_args *oba = aux; 172 prop_dictionary_t dict; 173 int isconsole, width, height, linebytes, depth; 174 175 printf(": Chips & Technologies 65550 at 0x%08x\n", 176 (uint32_t)chipsfb_mem_paddr); 177 178 sc->sc_dev = self; 179 sc->sc_memt = &chipsfb_memt; 180 sc->sc_iot = &chipsfb_iot; 181 sc->sc_fb = chipsfb_mem_paddr; 182 sc->sc_fbsize = 0x00800000; /* 8MB aperture */ 183 sc->sc_fbh = chipsfb_mem_vaddr; 184 sc->sc_mmregh = chipsfb_mmio_vaddr; 185 sc->sc_mmap = chipsfb_ofbus_mmap; 186 sc->sc_ioctl = NULL; 187 sc->memsize = 0x00200000; 188 189 dict = device_properties(sc->sc_dev); 190 if (OF_getprop(oba->oba_phandle, "width", &width, sizeof(width)) == 4) { 191 width = be32toh(width); 192 } else 193 width = 640; 194 if (OF_getprop(oba->oba_phandle, "height", &height, sizeof(height)) 195 == 4) { 196 height = be32toh(height); 197 } else 198 height = 480; 199 if (OF_getprop(oba->oba_phandle, "depth", &depth, sizeof(depth)) == 4) { 200 depth = be32toh(depth); 201 } else 202 depth = 8; 203 if (OF_getprop(oba->oba_phandle, "linebytes", &linebytes, 204 sizeof(linebytes)) == 4) { 205 linebytes = be32toh(linebytes); 206 } else 207 linebytes = width * (depth >> 3); 208 isconsole = chipsfb_ofbus_is_console(oba->oba_phandle); 209 210 prop_dictionary_set_uint32(dict, "width", width); 211 prop_dictionary_set_uint32(dict, "height", height); 212 prop_dictionary_set_uint32(dict, "linebytes", linebytes); 213 prop_dictionary_set_uint32(dict, "depth", depth); 214 prop_dictionary_set_bool(dict, "is_console", isconsole); 215 216 if (bus_space_map(sc->sc_iot, 0, 0x400, 0, &sc->sc_ioregh) != 0) { 217 aprint_error("unable to map IO registers\n"); 218 return; 219 } 220 chipsfb_do_attach(sc); 221 } 222 223 static paddr_t 224 chipsfb_ofbus_mmap(void *v, void *vs, off_t offset, int prot) 225 { 226 227 #ifdef PCI_MAGIC_IO_RANGE 228 /* access to IO ports */ 229 if ((offset >= PCI_MAGIC_IO_RANGE) && 230 (offset < (PCI_MAGIC_IO_RANGE + 0x10000))) { 231 paddr_t pa; 232 233 pa = isa_io_physaddr + offset - PCI_MAGIC_IO_RANGE; 234 return arm_btop(pa); 235 } 236 #endif 237 238 if ((offset >= chipsfb_mem_paddr) && 239 (offset < (chipsfb_mem_paddr + CT_OFF_BITBLT))) { 240 return (arm_btop(offset) | ARM32_MMAP_WRITECOMBINE); 241 } else if ((offset >= (chipsfb_mem_paddr + CT_OFF_BITBLT)) && 242 (offset < (chipsfb_mem_paddr + 0x00800000))) { 243 return arm_btop(offset); 244 } else if ((offset >= 0xa0000) && 245 (offset < 0xbffff)) { 246 return (arm_btop(offset) | ARM32_MMAP_WRITECOMBINE); 247 } 248 249 return -1; 250 } 251
Indexes created Tue Oct 28 12:10:06 GMT 2025