1 /* $NetBSD: vlpci.h,v 1.1 2017/04/18 14:11:42 flxd Exp $ */ 2 3 /*- 4 * Copyright (c) 2017, Felix Deichmann 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef _VLPCI_H 30 #define _VLPCI_H 31 32 #include <sys/param.h> 33 #include <sys/cdefs.h> 34 #include <sys/bitops.h> 35 36 /* 37 * VT82C505 register definitions according to: 38 * 39 * VIA Technologies, Inc. "Configuration Registers of VT82C505-F", December 40 * 1994. Application Note AN-025B. 41 * 42 * VIA Technologies, Inc. "VIA VT82C505 Pentium/486 VL to PCI BRIDGE", May 1994. 43 * Datasheet. 44 */ 45 46 #define VLPCI_INTREG_BASE 0xa8 47 #define VLPCI_INTREG_IDX_OFF 0 48 #define VLPCI_INTREG_DATA_OFF 1 49 #define VLPCI_INTREG_SZ 2 50 51 #define VLPCI_CFGREG_BASE 0xcf8 52 #define VLPCI_CFGREG_ADDR_OFF 0 53 #define VLPCI_CFGREG_DATA_OFF 4 54 #define VLPCI_CFGREG_SZ 8 55 56 #define VLPCI_DIP_SW_REG 0x80 57 #define VLPCI_DIP_SW_PCLK_CCLK __BIT(7) 58 #define VLPCI_DIP_SW_SYNC_CLK __BIT(6) 59 #define VLPCI_DIP_SW_IRQ14_15_PIN __BIT(5) 60 #define VLPCI_DIP_SW_BLAST_PIN __BIT(4) 61 #define VLPCI_DIP_SW_STRAP __BITS(7, 4) 62 #define VLPCI_DIP_SW_REV_ID __BITS(3, 0) 63 #define VLPCI_DIP_SW_REV_ID_D 0x1 64 #define VLPCI_DIP_SW_REV_ID_E 0x2 65 #define VLPCI_DIP_SW_REV_ID_F 0x3 66 67 #define VLPCI_OBD_MEM_SZ_REG 0x81 68 69 #define VLPCI_BUF_CTL_REG 0x82 70 #define VLPCI_BUF_CTL_CPU2PCI_WR_BUF __BIT(7) 71 #define VLPCI_BUF_CTL_PCI2CPU_WR_BUF __BIT(6) 72 #define VLPCI_BUF_CTL_CPU2PCI_PREF_BUF __BIT(5) 73 #define VLPCI_BUF_CTL_PCI2CPU_PREF_BUF __BIT(4) 74 #define VLPCI_BUF_CTL_PCI_DYN_ACC_DEC __BIT(3) 75 #define VLPCI_BUF_CTL_BST_B4_LST_BRDY __BIT(2) 76 #define VLPCI_BUF_CTL_OBD_MEM_WR_BST __BIT(1) 77 #define VLPCI_BUF_CTL_OBD_MEM_RD_BST __BIT(0) 78 79 #define VLPCI_VL_TIM_REG 0x83 80 #define VLPCI_VL_TIM_CPU2VL_WR_0WS __BIT(7) 81 #define VLPCI_VL_TIM_LDEV_2ND_T2 __BIT(6) 82 #define VLPCI_VL_TIM_TRDY2LRDY_BYP __BIT(5) /* AN-025B */ 83 #define VLPCI_VL_TIM_TRDY2LRDY_RESYNC __BIT(5) /* DS */ 84 #define VLPCI_VL_TIM_RDYRTN2TRDY_BYP __BIT(4) /* AN-025B */ 85 #define VLPCI_VL_TIM_RDYRTN2TRDY_RESYNC __BIT(4) /* DS */ 86 #define VLPCI_VL_TIM_OBD_MEM_1ST_DAT __BIT(3) 87 #define VLPCI_VL_TIM_CPU2PCI_WR_BST __BIT(2) 88 #define VLPCI_VL_TIM_PADS_DIS __BIT(1) 89 #define VLPCI_VL_TIM_TST_MODE __BIT(0) 90 91 #define VLPCI_PCI_TIM_REG 0x84 92 #define VLPCI_PCI_TIM_SLV_LOCK __BIT(7) 93 #define VLPCI_PCI_TIM_RTY_CNT_64 __BIT(6) 94 #define VLPCI_PCI_TIM_RTY_DEADL_ERR_REP __BIT(5) 95 #define VLPCI_PCI_TIM_RTY_STS_OCCU __BIT(4) 96 #define VLPCI_PCI_TIM_CPU2PCI_FAST_B2B __BIT(3) 97 #define VLPCI_PCI_TIM_FAST_FRAME __BIT(2) 98 #define VLPCI_PCI_TIM_DEVSEL_DEC __BITS(1, 0) 99 #define VLPCI_PCI_TIM_DEVSEL_DEC_SUBTR 0x3 100 #define VLPCI_PCI_TIM_DEVSEL_DEC_SLOW 0x2 101 #define VLPCI_PCI_TIM_DEVSEL_DEC_MDM 0x1 102 #define VLPCI_PCI_TIM_DEVSEL_DEC_FAST 0x0 103 104 #define VLPCI_PCI_ARB_REG 0x85 105 #define VLPCI_PCI_ARB_FAIR __BIT(7) 106 #define VLPCI_PCI_ARB_FRAME __BIT(6) 107 #define VLPCI_PCI_ARB_CPU_TIM_SLT __BITS(5, 4) 108 #define VLPCI_PCI_ARB_CPU_TIM_SLT_32CLK 0x3 109 #define VLPCI_PCI_ARB_CPU_TIM_SLT_16CLK 0x2 110 #define VLPCI_PCI_ARB_CPU_TIM_SLT_8CLK 0x1 111 #define VLPCI_PCI_ARB_CPU_TIM_SLT_4CLK 0x0 112 #define VLPCI_PCI_ARB_PCI_MST_TMO __BITS(3, 0) 113 #define VLPCI_PCI_ARB_PCI_MST_TMO_DIS 0x0 114 #define VLPCI_PCI_ARB_PCI_MST_TMO_1X32CLK 0x1 115 #define VLPCI_PCI_ARB_PCI_MST_TMO_2X32CLK 0x2 116 #define VLPCI_PCI_ARB_PCI_MST_TMO_3X32CLK 0x3 117 #define VLPCI_PCI_ARB_PCI_MST_TMO_4X32CLK 0x4 118 #define VLPCI_PCI_ARB_PCI_MST_TMO_5X32CLK 0x5 119 #define VLPCI_PCI_ARB_PCI_MST_TMO_6X32CLK 0x6 120 #define VLPCI_PCI_ARB_PCI_MST_TMO_7X32CLK 0x7 121 #define VLPCI_PCI_ARB_PCI_MST_TMO_8X32CLK 0x8 122 #define VLPCI_PCI_ARB_PCI_MST_TMO_9X32CLK 0x9 123 #define VLPCI_PCI_ARB_PCI_MST_TMO_10X32CLK 0xa 124 #define VLPCI_PCI_ARB_PCI_MST_TMO_11X32CLK 0xb 125 #define VLPCI_PCI_ARB_PCI_MST_TMO_12X32CLK 0xc 126 #define VLPCI_PCI_ARB_PCI_MST_TMO_13X32CLK 0xd 127 #define VLPCI_PCI_ARB_PCI_MST_TMO_14X32CLK 0xe 128 #define VLPCI_PCI_ARB_PCI_MST_TMO_15X32CLK 0xf 129 130 #define VLPCI_CFG_MISC_CTL_REG 0x86 131 #define VLPCI_CFG_MISC_CTL_PCI_CFG_MECHN_2 __BIT(7) 132 #define VLPCI_CFG_MISC_CTL_INT_CTL __BITS(5, 6) 133 #define VLPCI_CFG_MISC_CTL_INT_CTL_TRSP 0x0 134 #define VLPCI_CFG_MISC_CTL_INT_CTL_CONV_INTL 0x1 135 #define VLPCI_CFG_MISC_CTL_INT_CTL_TRSP_INV 0x2 136 #define VLPCI_CFG_MISC_CTL_INT_CTL_CONV 0x3 137 #define VLPCI_CFG_MISC_CTL_TST_MODE __BIT(4) 138 #define VLPCI_CFG_MISC_CTL_SERR_NMI __BIT(3) 139 #define VLPCI_CFG_MISC_CTL_SERR_STS __BIT(2) 140 #define VLPCI_CFG_MISC_CTL_PCI_MST_BRK_TMR __BIT(1) 141 #define VLPCI_CFG_MISC_CTL_LREQI_LGNTO_PIN __BIT(0) 142 143 #define VLPCI_PCI_WND_NO_1 1 144 #define VLPCI_PCI_WND_NO_2 2 145 #define VLPCI_PCI_WND_NO_3 3 146 147 #define VLPCI_PCI_WND_HIADDR_REG(no) (0x87 + 3 * ((no) - 1)) 148 #define VLPCI_PCI_WND_HIADDR_IO(x) (((x) >> 8) & 0xff) 149 #define VLPCI_PCI_WND_HIADDR_MEM(x) (((x) >> 24) & 0xff) 150 151 #define VLPCI_PCI_WND_LOADDR_REG(no) (0x88 + 3 * ((no) - 1)) 152 #define VLPCI_PCI_WND_LOADDR_IO(x) (((x) >> 0) & 0xff) 153 #define VLPCI_PCI_WND_LOADDR_MEM(x) (((x) >> 16) & 0xff) 154 155 /* 156 * Window attributes differ significantly between AN-025B (PCI windows only, 157 * memory and I/O) and DS (PCI and VL windows, memory only). 158 */ 159 #define VLPCI_PCI_WND_ATTR_REG(no) (0x89 + 3 * ((no) - 1)) 160 #define VLPCI_PCI_WND_ATTR_ENA __BIT(7) /* AN-025B */ 161 #define VLPCI_PCI_WND_ATTR_PCI __BIT(7) /* DS */ 162 #define VLPCI_PCI_WND_ATTR_WR_BUF __BIT(6) 163 #define VLPCI_PCI_WND_ATTR_IO __BIT(5) /* AN-025B */ 164 #define VLPCI_PCI_WND_ATTR_VL __BIT(5) /* DS */ 165 #define VLPCI_PCI_WND_ATTR_SZ __BITS(4, 2) 166 /* I/O size only present in AN-025B. */ 167 #define VLPCI_PCI_WND_ATTR_SZ_IO_4 0x0 168 #define VLPCI_PCI_WND_ATTR_SZ_IO_8 0x1 169 #define VLPCI_PCI_WND_ATTR_SZ_IO_16 0x2 170 #define VLPCI_PCI_WND_ATTR_SZ_IO_32 0x3 171 #define VLPCI_PCI_WND_ATTR_SZ_IO_64 0x4 172 #define VLPCI_PCI_WND_ATTR_SZ_IO_128 0x5 173 #define VLPCI_PCI_WND_ATTR_SZ_IO_256 0x6 174 #define VLPCI_PCI_WND_ATTR_SZ_IO_512 0x7 175 #define VLPCI_PCI_WND_ATTR_SZ_IO(b) ilog2((b) >> 2) 176 #define VLPCI_PCI_WND_ATTR_SZ_MEM_64K 0x0 177 #define VLPCI_PCI_WND_ATTR_SZ_MEM_128K 0x1 178 #define VLPCI_PCI_WND_ATTR_SZ_MEM_256K 0x2 179 #define VLPCI_PCI_WND_ATTR_SZ_MEM_512K 0x3 180 #define VLPCI_PCI_WND_ATTR_SZ_MEM_1M 0x4 181 #define VLPCI_PCI_WND_ATTR_SZ_MEM_2M 0x5 182 #define VLPCI_PCI_WND_ATTR_SZ_MEM_4M 0x6 183 #define VLPCI_PCI_WND_ATTR_SZ_MEM_8M 0x7 184 #define VLPCI_PCI_WND_ATTR_SZ_MEM(b) ilog2((b) >> 16) 185 186 #define VLPCI_INT_CTL_REG(int) (0x90 + (int) / 8) 187 #define VLPCI_INT_CTL_ENA(int) __BIT((int) % 8 + 3) 188 #define VLPCI_INT_CTL_INT2IRQ(int) __BITS((int) % 8 + 2, (int) % 8) 189 #define VLPCI_INT_CTL_INTB 12 190 #define VLPCI_INT_CTL_INTA 8 191 #define VLPCI_INT_CTL_INTD 4 192 #define VLPCI_INT_CTL_INTC 0 193 #define VLPCI_INT_CTL_IRQ_NONE 0x0 194 #define VLPCI_INT_CTL_IRQ5 0x1 195 #define VLPCI_INT_CTL_IRQ9 0x2 196 #define VLPCI_INT_CTL_IRQ10 0x3 197 #define VLPCI_INT_CTL_IRQ11 0x4 198 #define VLPCI_INT_CTL_IRQ14 0x5 199 #define VLPCI_INT_CTL_IRQ15 0x6 200 #define VLPCI_INT_CTL_IRQ(irq) \ 201 (((irq) == 5) ? VLPCI_INT_CTL_IRQ5 : \ 202 ((irq) == 9) ? VLPCI_INT_CTL_IRQ9 : \ 203 ((irq) == 10) ? VLPCI_INT_CTL_IRQ10 : \ 204 ((irq) == 11) ? VLPCI_INT_CTL_IRQ11 : \ 205 ((irq) == 14) ? VLPCI_INT_CTL_IRQ14 : \ 206 ((irq) == 15) ? VLPCI_INT_CTL_IRQ15 : \ 207 VLPCI_INT_CTL_IRQ_NONE) 208 209 #define VLPCI_ACC_ISA_CYC_REG 0x92 210 #define VLPCI_ACC_ISA_CYC_A0000 __BIT(7) 211 #define VLPCI_ACC_ISA_CYC_B0000 __BIT(6) 212 #define VLPCI_ACC_ISA_CYC_C0000 __BIT(5) 213 #define VLPCI_ACC_ISA_CYC_C8000 __BIT(4) 214 #define VLPCI_ACC_ISA_CYC_D0000 __BIT(3) 215 #define VLPCI_ACC_ISA_CYC_D8000 __BIT(2) 216 #define VLPCI_ACC_ISA_CYC_E0000 __BIT(1) 217 #define VLPCI_ACC_ISA_CYC_E8000 __BIT(0) 218 /* F0000h to FFFFFh is always accelerated ISA cycle. */ 219 220 #define VLPCI_MISC_CTL_REG 0x93 221 #define VLPCI_MISC_CTL_HIADDR (__BITS(7, 6) | __BIT(4)) 222 #define VLPCI_MISC_CTL_HIADDR_CA26_ABV 0x0 /* 0b00x0 */ 223 #define VLPCI_MISC_CTL_HIADDR_CA27_ABV 0x4 /* 0b01x0 */ 224 #define VLPCI_MISC_CTL_HIADDR_CA28_ABV 0x8 /* 0b10x0 */ 225 #define VLPCI_MISC_CTL_HIADDR_CA29_ABV 0xc /* 0b11x0 */ 226 #define VLPCI_MISC_CTL_HIADDR_CA30_ABV 0x1 /* 0b00x1 */ 227 #define VLPCI_MISC_CTL_HIADDR_CA31_ABV 0x5 /* 0b01x1 */ 228 #define VLPCI_MISC_CTL_HIADDR_DIS 0xd /* 0b11x1 */ 229 #define VLPCI_MISC_CTL_IOCHCK_PIN __BIT(5) 230 #define VLPCI_MISC_CTL_2ND_VL_IDE __BIT(3) 231 #define VLPCI_MISC_CTL_1ST_VL_IDE __BIT(2) 232 #define VLPCI_MISC_CTL_OBD_IO_ACC_ISA __BIT(0) 233 234 #define VLPCI_ACC_PCI_64K_WND_REG 0x94 235 #define VLPCI_ACC_PCI_64K_WND_A0000 __BIT(7) 236 #define VLPCI_ACC_PCI_64K_WND_B0000 __BIT(6) 237 #define VLPCI_ACC_PCI_64K_WND_C0000 __BIT(5) 238 #define VLPCI_ACC_PCI_64K_WND_C8000 __BIT(4) 239 #define VLPCI_ACC_PCI_64K_WND_D0000 __BIT(3) 240 #define VLPCI_ACC_PCI_64K_WND_D8000 __BIT(2) 241 #define VLPCI_ACC_PCI_64K_WND_E0000 __BIT(1) 242 #define VLPCI_ACC_PCI_64K_WND_E8000 __BIT(0) 243 244 #define VLPCI_ACC_PCI_32K_WND_REG 0x95 245 #define VLPCI_ACC_PCI_32K_WND_A0000 __BIT(7) 246 #define VLPCI_ACC_PCI_32K_WND_A8000 __BIT(6) 247 #define VLPCI_ACC_PCI_32K_WND_B0000 __BIT(5) 248 #define VLPCI_ACC_PCI_32K_WND_B8000 __BIT(4) 249 250 #define VLPCI_MISC_1_REG 0x96 251 #define VLPCI_MISC_1_DYN_DEC_MEM_WR __BIT(7) 252 #define VLPCI_MISC_1_RTY_TMO_ACTION __BIT(6) 253 #define VLPCI_MISC_1_DYN_DEC_DIS __BIT(5) 254 #define VLPCI_MISC_1_LOCAL_PIN __BIT(4) 255 #define VLPCI_MISC_1_COMPAT_ISA_BOFF __BIT(3) 256 #define VLPCI_MISC_1_IRQ_IDLE_LOW __BIT(2) 257 #define VLPCI_MISC_1_PCI_MST_1WS_WR __BIT(1) 258 #define VLPCI_MISC_1_PCI_SLV_1WS_BST_WR __BIT(0) 259 260 /* Individual INT[ABCD] mode control from VT82C505-E on. */ 261 #define VLPCI_IRQ_MODE_REG 0x97 262 #define VLPCI_IRQ_MODE_CTL(i) __BITS((i) + 1, (i)) 263 #define VLPCI_IRQ_MODE_CTL_INTA 6 264 #define VLPCI_IRQ_MODE_CTL_INTB 4 265 #define VLPCI_IRQ_MODE_CTL_INTC 2 266 #define VLPCI_IRQ_MODE_CTL_INTD 0 267 268 #define VLPCI_OBD_MEM_EADDR_REG 0x98 269 #define VLPCI_OBD_MEM_EADDR_CA32_CA28 __BITS(4, 0) 270 271 #define VLPCI_MISC_2_REG 0x99 272 #define VLPCI_MISC_2_BYTE_MRG __BIT(7) 273 #define VLPCI_MISC_2_ENH_BYTE_MRG __BIT(6) 274 #define VLPCI_MISC_2_DYN_PCI_BST __BIT(5) 275 #define VLPCI_MISC_2_RTY_FAIL_POP_1_DAT __BIT(4) 276 #define VLPCI_MISC_2_2WAY_DYN_DEC __BIT(3) 277 #define VLPCI_MISC_2_ISAREQ_1CLK_DLY __BIT(1) 278 #define VLPCI_MISC_2_ADS_1CLK_DLY __BIT(0) 279 280 #endif /* !defined(_VLPCI_H) */ 281
Indexes created Mon Sep 22 05:09:51 GMT 2025