fpu_implode.c revision 1.10.16.2
1 /* $NetBSD: fpu_implode.c,v 1.10.16.2 2004/09/18 14:40:38 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)fpu_implode.c 8.1 (Berkeley) 6/11/93 41 */ 42 43 /* 44 * FPU subroutines: `implode' internal format numbers into the machine's 45 * `packed binary' format. 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: fpu_implode.c,v 1.10.16.2 2004/09/18 14:40:38 skrll Exp $"); 50 51 #if defined(_KERNEL_OPT) 52 #include "opt_sparc_arch.h" 53 #endif 54 55 #include <sys/types.h> 56 #include <sys/systm.h> 57 58 #include <machine/ieee.h> 59 #include <machine/instr.h> 60 #include <machine/reg.h> 61 62 #include <sparc/fpu/fpu_arith.h> 63 #include <sparc/fpu/fpu_emu.h> 64 #include <sparc/fpu/fpu_extern.h> 65 66 static int round __P((register struct fpemu *, register struct fpn *)); 67 static int toinf __P((struct fpemu *, int)); 68 69 /* 70 * Round a number (algorithm from Motorola MC68882 manual, modified for 71 * our internal format). Set inexact exception if rounding is required. 72 * Return true iff we rounded up. 73 * 74 * After rounding, we discard the guard and round bits by shifting right 75 * 2 bits (a la fpu_shr(), but we do not bother with fp->fp_sticky). 76 * This saves effort later. 77 * 78 * Note that we may leave the value 2.0 in fp->fp_mant; it is the caller's 79 * responsibility to fix this if necessary. 80 */ 81 static int 82 round(register struct fpemu *fe, register struct fpn *fp) 83 { 84 register u_int m0, m1, m2, m3; 85 register int gr, s; 86 87 m0 = fp->fp_mant[0]; 88 m1 = fp->fp_mant[1]; 89 m2 = fp->fp_mant[2]; 90 m3 = fp->fp_mant[3]; 91 gr = m3 & 3; 92 s = fp->fp_sticky; 93 94 /* mant >>= FP_NG */ 95 m3 = (m3 >> FP_NG) | (m2 << (32 - FP_NG)); 96 m2 = (m2 >> FP_NG) | (m1 << (32 - FP_NG)); 97 m1 = (m1 >> FP_NG) | (m0 << (32 - FP_NG)); 98 m0 >>= FP_NG; 99 100 if ((gr | s) == 0) /* result is exact: no rounding needed */ 101 goto rounddown; 102 103 fe->fe_cx |= FSR_NX; /* inexact */ 104 105 /* Go to rounddown to round down; break to round up. */ 106 switch ((fe->fe_fsr >> FSR_RD_SHIFT) & FSR_RD_MASK) { 107 108 case FSR_RD_RN: 109 default: 110 /* 111 * Round only if guard is set (gr & 2). If guard is set, 112 * but round & sticky both clear, then we want to round 113 * but have a tie, so round to even, i.e., add 1 iff odd. 114 */ 115 if ((gr & 2) == 0) 116 goto rounddown; 117 if ((gr & 1) || fp->fp_sticky || (m3 & 1)) 118 break; 119 goto rounddown; 120 121 case FSR_RD_RZ: 122 /* Round towards zero, i.e., down. */ 123 goto rounddown; 124 125 case FSR_RD_RM: 126 /* Round towards -Inf: up if negative, down if positive. */ 127 if (fp->fp_sign) 128 break; 129 goto rounddown; 130 131 case FSR_RD_RP: 132 /* Round towards +Inf: up if positive, down otherwise. */ 133 if (!fp->fp_sign) 134 break; 135 goto rounddown; 136 } 137 138 /* Bump low bit of mantissa, with carry. */ 139 FPU_ADDS(m3, m3, 1); 140 FPU_ADDCS(m2, m2, 0); 141 FPU_ADDCS(m1, m1, 0); 142 FPU_ADDC(m0, m0, 0); 143 fp->fp_mant[0] = m0; 144 fp->fp_mant[1] = m1; 145 fp->fp_mant[2] = m2; 146 fp->fp_mant[3] = m3; 147 return (1); 148 149 rounddown: 150 fp->fp_mant[0] = m0; 151 fp->fp_mant[1] = m1; 152 fp->fp_mant[2] = m2; 153 fp->fp_mant[3] = m3; 154 return (0); 155 } 156 157 /* 158 * For overflow: return true if overflow is to go to +/-Inf, according 159 * to the sign of the overflowing result. If false, overflow is to go 160 * to the largest magnitude value instead. 161 */ 162 static int 163 toinf(struct fpemu *fe, int sign) 164 { 165 int inf; 166 167 /* look at rounding direction */ 168 switch ((fe->fe_fsr >> FSR_RD_SHIFT) & FSR_RD_MASK) { 169 170 default: 171 case FSR_RD_RN: /* the nearest value is always Inf */ 172 inf = 1; 173 break; 174 175 case FSR_RD_RZ: /* toward 0 => never towards Inf */ 176 inf = 0; 177 break; 178 179 case FSR_RD_RP: /* toward +Inf iff positive */ 180 inf = sign == 0; 181 break; 182 183 case FSR_RD_RM: /* toward -Inf iff negative */ 184 inf = sign; 185 break; 186 } 187 return (inf); 188 } 189 190 /* 191 * fpn -> int (int value returned as return value). 192 * 193 * N.B.: this conversion always rounds towards zero (this is a peculiarity 194 * of the SPARC instruction set). 195 */ 196 u_int 197 fpu_ftoi(fe, fp) 198 struct fpemu *fe; 199 register struct fpn *fp; 200 { 201 register u_int i; 202 register int sign, exp; 203 204 sign = fp->fp_sign; 205 switch (fp->fp_class) { 206 207 case FPC_ZERO: 208 return (0); 209 210 case FPC_NUM: 211 /* 212 * If exp >= 2^32, overflow. Otherwise shift value right 213 * into last mantissa word (this will not exceed 0xffffffff), 214 * shifting any guard and round bits out into the sticky 215 * bit. Then ``round'' towards zero, i.e., just set an 216 * inexact exception if sticky is set (see round()). 217 * If the result is > 0x80000000, or is positive and equals 218 * 0x80000000, overflow; otherwise the last fraction word 219 * is the result. 220 */ 221 if ((exp = fp->fp_exp) >= 32) 222 break; 223 /* NB: the following includes exp < 0 cases */ 224 if (fpu_shr(fp, FP_NMANT - 1 - exp) != 0) 225 fe->fe_cx |= FSR_NX; 226 i = fp->fp_mant[3]; 227 if (i >= ((u_int)0x80000000 + sign)) 228 break; 229 return (sign ? -i : i); 230 231 default: /* Inf, qNaN, sNaN */ 232 break; 233 } 234 /* overflow: replace any inexact exception with invalid */ 235 fe->fe_cx = (fe->fe_cx & ~FSR_NX) | FSR_NV; 236 return (0x7fffffff + sign); 237 } 238 239 #ifdef SUN4U 240 /* 241 * fpn -> extended int (high bits of int value returned as return value). 242 * 243 * N.B.: this conversion always rounds towards zero (this is a peculiarity 244 * of the SPARC instruction set). 245 */ 246 u_int 247 fpu_ftox(fe, fp, res) 248 struct fpemu *fe; 249 register struct fpn *fp; 250 u_int *res; 251 { 252 register u_int64_t i; 253 register int sign, exp; 254 255 sign = fp->fp_sign; 256 switch (fp->fp_class) { 257 258 case FPC_ZERO: 259 res[1] = 0; 260 return (0); 261 262 case FPC_NUM: 263 /* 264 * If exp >= 2^64, overflow. Otherwise shift value right 265 * into last mantissa word (this will not exceed 0xffffffffffffffff), 266 * shifting any guard and round bits out into the sticky 267 * bit. Then ``round'' towards zero, i.e., just set an 268 * inexact exception if sticky is set (see round()). 269 * If the result is > 0x8000000000000000, or is positive and equals 270 * 0x8000000000000000, overflow; otherwise the last fraction word 271 * is the result. 272 */ 273 if ((exp = fp->fp_exp) >= 64) 274 break; 275 /* NB: the following includes exp < 0 cases */ 276 if (fpu_shr(fp, FP_NMANT - 1 - exp) != 0) 277 fe->fe_cx |= FSR_NX; 278 i = ((u_int64_t)fp->fp_mant[2]<<32)|fp->fp_mant[3]; 279 if (i >= ((u_int64_t)0x8000000000000000LL + sign)) 280 break; 281 if (sign) i = -i; 282 res[1] = (int)i; 283 return (i>>32); 284 285 default: /* Inf, qNaN, sNaN */ 286 break; 287 } 288 /* overflow: replace any inexact exception with invalid */ 289 fe->fe_cx = (fe->fe_cx & ~FSR_NX) | FSR_NV; 290 return (0x7fffffffffffffffLL + sign); 291 } 292 #endif /* SUN4U */ 293 294 /* 295 * fpn -> single (32 bit single returned as return value). 296 * We assume <= 29 bits in a single-precision fraction (1.f part). 297 */ 298 u_int 299 fpu_ftos(fe, fp) 300 struct fpemu *fe; 301 register struct fpn *fp; 302 { 303 register u_int sign = fp->fp_sign << 31; 304 register int exp; 305 306 #define SNG_EXP(e) ((e) << SNG_FRACBITS) /* makes e an exponent */ 307 #define SNG_MASK (SNG_EXP(1) - 1) /* mask for fraction */ 308 309 /* Take care of non-numbers first. */ 310 if (ISNAN(fp)) { 311 /* 312 * Preserve upper bits of NaN, per SPARC V8 appendix N. 313 * Note that fp->fp_mant[0] has the quiet bit set, 314 * even if it is classified as a signalling NaN. 315 */ 316 (void) fpu_shr(fp, FP_NMANT - 1 - SNG_FRACBITS); 317 exp = SNG_EXP_INFNAN; 318 goto done; 319 } 320 if (ISINF(fp)) 321 return (sign | SNG_EXP(SNG_EXP_INFNAN)); 322 if (ISZERO(fp)) 323 return (sign); 324 325 /* 326 * Normals (including subnormals). Drop all the fraction bits 327 * (including the explicit ``implied'' 1 bit) down into the 328 * single-precision range. If the number is subnormal, move 329 * the ``implied'' 1 into the explicit range as well, and shift 330 * right to introduce leading zeroes. Rounding then acts 331 * differently for normals and subnormals: the largest subnormal 332 * may round to the smallest normal (1.0 x 2^minexp), or may 333 * remain subnormal. In the latter case, signal an underflow 334 * if the result was inexact or if underflow traps are enabled. 335 * 336 * Rounding a normal, on the other hand, always produces another 337 * normal (although either way the result might be too big for 338 * single precision, and cause an overflow). If rounding a 339 * normal produces 2.0 in the fraction, we need not adjust that 340 * fraction at all, since both 1.0 and 2.0 are zero under the 341 * fraction mask. 342 * 343 * Note that the guard and round bits vanish from the number after 344 * rounding. 345 */ 346 if ((exp = fp->fp_exp + SNG_EXP_BIAS) <= 0) { /* subnormal */ 347 /* -NG for g,r; -SNG_FRACBITS-exp for fraction */ 348 (void) fpu_shr(fp, FP_NMANT - FP_NG - SNG_FRACBITS - exp); 349 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(1)) 350 return (sign | SNG_EXP(1) | 0); 351 if ((fe->fe_cx & FSR_NX) || 352 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT))) 353 fe->fe_cx |= FSR_UF; 354 return (sign | SNG_EXP(0) | fp->fp_mant[3]); 355 } 356 /* -FP_NG for g,r; -1 for implied 1; -SNG_FRACBITS for fraction */ 357 (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - SNG_FRACBITS); 358 #ifdef DIAGNOSTIC 359 if ((fp->fp_mant[3] & SNG_EXP(1 << FP_NG)) == 0) 360 panic("fpu_ftos"); 361 #endif 362 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(2)) 363 exp++; 364 if (exp >= SNG_EXP_INFNAN) { 365 /* overflow to inf or to max single */ 366 fe->fe_cx |= FSR_OF | FSR_NX; 367 if (toinf(fe, sign)) 368 return (sign | SNG_EXP(SNG_EXP_INFNAN)); 369 return (sign | SNG_EXP(SNG_EXP_INFNAN - 1) | SNG_MASK); 370 } 371 done: 372 /* phew, made it */ 373 return (sign | SNG_EXP(exp) | (fp->fp_mant[3] & SNG_MASK)); 374 } 375 376 /* 377 * fpn -> double (32 bit high-order result returned; 32-bit low order result 378 * left in res[1]). Assumes <= 61 bits in double precision fraction. 379 * 380 * This code mimics fpu_ftos; see it for comments. 381 */ 382 u_int 383 fpu_ftod(fe, fp, res) 384 struct fpemu *fe; 385 register struct fpn *fp; 386 u_int *res; 387 { 388 register u_int sign = fp->fp_sign << 31; 389 register int exp; 390 391 #define DBL_EXP(e) ((e) << (DBL_FRACBITS & 31)) 392 #define DBL_MASK (DBL_EXP(1) - 1) 393 394 if (ISNAN(fp)) { 395 (void) fpu_shr(fp, FP_NMANT - 1 - DBL_FRACBITS); 396 exp = DBL_EXP_INFNAN; 397 goto done; 398 } 399 if (ISINF(fp)) { 400 sign |= DBL_EXP(DBL_EXP_INFNAN); 401 goto zero; 402 } 403 if (ISZERO(fp)) { 404 zero: res[1] = 0; 405 return (sign); 406 } 407 408 if ((exp = fp->fp_exp + DBL_EXP_BIAS) <= 0) { 409 (void) fpu_shr(fp, FP_NMANT - FP_NG - DBL_FRACBITS - exp); 410 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(1)) { 411 res[1] = 0; 412 return (sign | DBL_EXP(1) | 0); 413 } 414 if ((fe->fe_cx & FSR_NX) || 415 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT))) 416 fe->fe_cx |= FSR_UF; 417 exp = 0; 418 goto done; 419 } 420 (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - DBL_FRACBITS); 421 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(2)) 422 exp++; 423 if (exp >= DBL_EXP_INFNAN) { 424 fe->fe_cx |= FSR_OF | FSR_NX; 425 if (toinf(fe, sign)) { 426 res[1] = 0; 427 return (sign | DBL_EXP(DBL_EXP_INFNAN) | 0); 428 } 429 res[1] = ~0; 430 return (sign | DBL_EXP(DBL_EXP_INFNAN) | DBL_MASK); 431 } 432 done: 433 res[1] = fp->fp_mant[3]; 434 return (sign | DBL_EXP(exp) | (fp->fp_mant[2] & DBL_MASK)); 435 } 436 437 /* 438 * fpn -> extended (32 bit high-order result returned; low-order fraction 439 * words left in res[1]..res[3]). Like ftod, which is like ftos ... but 440 * our internal format *is* extended precision, plus 2 bits for guard/round, 441 * so we can avoid a small bit of work. 442 */ 443 u_int 444 fpu_ftoq(fe, fp, res) 445 struct fpemu *fe; 446 register struct fpn *fp; 447 u_int *res; 448 { 449 register u_int sign = fp->fp_sign << 31; 450 register int exp; 451 452 #define EXT_EXP(e) ((e) << (EXT_FRACBITS & 31)) 453 #define EXT_MASK (EXT_EXP(1) - 1) 454 455 if (ISNAN(fp)) { 456 (void) fpu_shr(fp, 2); /* since we are not rounding */ 457 exp = EXT_EXP_INFNAN; 458 goto done; 459 } 460 if (ISINF(fp)) { 461 sign |= EXT_EXP(EXT_EXP_INFNAN); 462 goto zero; 463 } 464 if (ISZERO(fp)) { 465 zero: res[1] = res[2] = res[3] = 0; 466 return (sign); 467 } 468 469 if ((exp = fp->fp_exp + EXT_EXP_BIAS) <= 0) { 470 (void) fpu_shr(fp, FP_NMANT - FP_NG - EXT_FRACBITS - exp); 471 if (round(fe, fp) && fp->fp_mant[0] == EXT_EXP(1)) { 472 res[1] = res[2] = res[3] = 0; 473 return (sign | EXT_EXP(1) | 0); 474 } 475 if ((fe->fe_cx & FSR_NX) || 476 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT))) 477 fe->fe_cx |= FSR_UF; 478 exp = 0; 479 goto done; 480 } 481 /* Since internal == extended, no need to shift here. */ 482 if (round(fe, fp) && fp->fp_mant[0] == EXT_EXP(2)) 483 exp++; 484 if (exp >= EXT_EXP_INFNAN) { 485 fe->fe_cx |= FSR_OF | FSR_NX; 486 if (toinf(fe, sign)) { 487 res[1] = res[2] = res[3] = 0; 488 return (sign | EXT_EXP(EXT_EXP_INFNAN) | 0); 489 } 490 res[1] = res[2] = res[3] = ~0; 491 return (sign | EXT_EXP(EXT_EXP_INFNAN) | EXT_MASK); 492 } 493 done: 494 res[1] = fp->fp_mant[1]; 495 res[2] = fp->fp_mant[2]; 496 res[3] = fp->fp_mant[3]; 497 return (sign | EXT_EXP(exp) | (fp->fp_mant[0] & EXT_MASK)); 498 } 499 500 /* 501 * Implode an fpn, writing the result into the given space. 502 */ 503 void 504 fpu_implode(fe, fp, type, space) 505 struct fpemu *fe; 506 register struct fpn *fp; 507 int type; 508 register u_int *space; 509 { 510 511 DPRINTF(FPE_REG, ("\n imploding: ")); 512 DUMPFPN(FPE_REG, fp); 513 DPRINTF(FPE_REG, ("\n")); 514 515 switch (type) { 516 517 #ifdef SUN4U 518 case FTYPE_LNG: 519 space[0] = fpu_ftox(fe, fp, space); 520 break; 521 #endif /* SUN4U */ 522 523 case FTYPE_INT: 524 space[0] = fpu_ftoi(fe, fp); 525 break; 526 527 case FTYPE_SNG: 528 space[0] = fpu_ftos(fe, fp); 529 break; 530 531 case FTYPE_DBL: 532 space[0] = fpu_ftod(fe, fp, space); 533 break; 534 535 case FTYPE_EXT: 536 /* funky rounding precision options ?? */ 537 space[0] = fpu_ftoq(fe, fp, space); 538 break; 539 540 default: 541 panic("fpu_implode"); 542 } 543 #ifdef SUN4U 544 DPRINTF(FPE_REG, ("fpu_implode: %x %x %x %x\n", 545 space[0], space[1], space[2], space[3])); 546 #else 547 DPRINTF(FPE_REG, ("fpu_implode: %x %x\n", 548 space[0], space[1])); 549 #endif 550 } 551
Indexes created Sun Sep 28 16:09:52 GMT 2025