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      1 /*	$NetBSD: memerr.h,v 1.4 2018/02/08 09:05:18 dholland Exp $ */
      2 
      3 /*
      4  * Copyright (c) 1992, 1993
      5  *	The Regents of the University of California.  All rights reserved.
      6  *
      7  * This software was developed by the Computer Systems Engineering group
      8  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
      9  * contributed to Berkeley.
     10  *
     11  * All advertising materials mentioning features or use of this software
     12  * must display the following acknowledgement:
     13  *	This product includes software developed by the University of
     14  *	California, Lawrence Berkeley Laboratory.
     15  *
     16  * Redistribution and use in source and binary forms, with or without
     17  * modification, are permitted provided that the following conditions
     18  * are met:
     19  * 1. Redistributions of source code must retain the above copyright
     20  *    notice, this list of conditions and the following disclaimer.
     21  * 2. Redistributions in binary form must reproduce the above copyright
     22  *    notice, this list of conditions and the following disclaimer in the
     23  *    documentation and/or other materials provided with the distribution.
     24  * 3. Neither the name of the University nor the names of its contributors
     25  *    may be used to endorse or promote products derived from this software
     26  *    without specific prior written permission.
     27  *
     28  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     29  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     30  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     31  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     32  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     33  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     34  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     35  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     36  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     37  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     38  * SUCH DAMAGE.
     39  *
     40  *	@(#)memreg.h	8.1 (Berkeley) 6/11/93
     41  */
     42 
     43 /*
     44  * Sun3 memory error register.
     45  *
     46  * All Sun3 memory systems use either parity checking or
     47  * Error Correction Coding (ECC).  A memory error causes
     48  * the Memory Error Register (MER) to latch information
     49  * about the location and type of error, and if the MER
     50  * interrupt is enabled, generateds a level 7 interrupt.
     51  * The latched information persists (even if more errors
     52  * occur) until the MER is cleared by a write (at mer_er).
     53  */
     54 
     55 
     56 struct memerr {
     57 	volatile u_char	me_csr;		/* MER control/status reg. */
     58 	volatile u_char	me__pad[3];
     59 	volatile u_int	me_vaddr;
     60 };
     61 
     62 /*
     63  * Bits in me_csr common between ECC/parity memory systems:
     64  */
     65 #define	ME_CSR_IPEND	0x80	/* (ro) error interrupt pending */
     66 #define	ME_CSR_IENA 	0x40	/* (rw) error interrupt enable */
     67 
     68 /*
     69  *  Bits in me_csr on parity-checked memory system:
     70  */
     71 #define ME_PAR_TEST 	0x20	/* (rw) write inverse parity */
     72 #define ME_PAR_CHECK	0x10	/* (rw) enable parity checking */
     73 #define ME_PAR_ERR3 	0x08	/* (ro) parity error in <24..31> */
     74 #define ME_PAR_ERR2 	0x04	/* (ro) parity error in <16..23> */
     75 #define ME_PAR_ERR1 	0x02	/* (ro) parity error in <8..15> */
     76 #define ME_PAR_ERR0 	0x01	/* (ro) parity error in <0..7> */
     77 #define	ME_PAR_EMASK	0x0F	/* (ro) mask of above four */
     78 #define ME_PAR_STR	"\20\10IPEND\7IENA\6TEST\5CHK\4ERR3\3ERR2\2ERR1\1ERR0"
     79 
     80 /*
     81  *  Bits in me_csr on an ECC memory system:
     82  */
     83 #define ME_ECC_BUSLK	0x20	/* (rw) hold memory bus mastership */
     84 #define ME_ECC_CE_ENA	0x10	/* (rw) enable CE recording */
     85 #define	ME_ECC_WBTMO	0x08	/* (ro) write-back timeout */
     86 #define	ME_ECC_WBERR	0x04	/* (ro) write-back error */
     87 #define ME_ECC_UE		0x02	/* (ro) UE, uncorrectable error  */
     88 #define ME_ECC_CE		0x01	/* (ro) CE, correctable (single bit) error */
     89 #define	ME_ECC_EMASK	0x0F	/* (ro) mask for some ECC error occurring */
     90 #define ME_ECC_STR	"\20\10IPEND\7IENA\6BUSLK\5CE_ENA\4TMOUT\3WBERR\2UE\1CE"
     91 
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