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      1 /*	$NetBSD: sireg.h,v 1.3 2024/12/20 23:52:00 tsutsui Exp $	*/
      2 
      3 /*
      4  * Register map for the Sun3 SCSI Interface (si)
      5  * The first part of this register map is an NCR5380
      6  * SCSI Bus Interface Controller (SBIC).  The rest is a
      7  * DMA controller and custom logic in one of two flavors,
      8  * one for the OBIO interface (3/50,3/60) and one for the
      9  * VME interface (3/160,3/260,etc.), where some registers
     10  * are implemented only on one or the other, some on both.
     11  */
     12 
     13 /*
     14  * Some of these registers apply to only one interface and some
     15  * apply to both. The registers which apply to the Sun3/50 onboard
     16  * version only are udc_rdata and udc_raddr. The registers which
     17  * apply to the Sun3 vme version only are dma_addr, dma_count, bpr,
     18  * iv_am, and bcrh. Thus, the sbc registers, fifo_data, bcr, and csr
     19  * apply to both interfaces.
     20  * One other feature of the vme interface: a write to the DMA count
     21  * register also causes a write to the fifo byte count register and
     22  * vis versa.
     23  */
     24 
     25 /*
     26  * Am5380 Register map (no padding)
     27  */
     28 struct ncr5380regs {
     29 	volatile u_char sci_r0;
     30 	volatile u_char sci_r1;
     31 	volatile u_char sci_r2;
     32 	volatile u_char sci_r3;
     33 	volatile u_char sci_r4;
     34 	volatile u_char sci_r5;
     35 	volatile u_char sci_r6;
     36 	volatile u_char sci_r7;
     37 };
     38 
     39 struct si_regs {
     40 	struct ncr5380regs sci;
     41 
     42 	/* DMA controller registers */
     43 	u_short			dma_addrh;	/* DMA address (VME only) */
     44 	u_short			dma_addrl;	/* (high word, low word)  */
     45 	u_short			dma_counth;	/* DMA count   (VME only) */
     46 	u_short			dma_countl;	/* (high word, low word)  */
     47 
     48 	/* AMD 9516 regs (OBIO only) see am9516.h */
     49 	u_short			udc_data;	/* Am9516, reg data (OBIO only) */
     50 	u_short			udc_addr;	/* Am9516, reg addr (OBIO only) */
     51 
     52 	/* These three registers are on both OBIO and VME versions. */
     53 	u_short			fifo_data;	/* fifo data register */
     54 						/* holds extra byte on odd */
     55 						/* byte DMA read */
     56 	u_short			fifo_count;		/* fifo byte count */
     57 	u_short			si_csr;		/* control/status register */
     58 
     59 	/* The rest of these are on the VME interface only: */
     60 	u_short			si_bprh;		/* byte pack, high (VME only) */
     61 	u_short			si_bprl;		/* byte pack, low  (VME only) */
     62 	u_short			si_iv_am;		/* bits 0-7: intr vector */
     63 						/* bits 8-13: addr modifier (VME only) */
     64 						/* bits 14-15: unused */
     65 	u_short			fifo_cnt_hi;	/* high part of fifo_count (VME only) */
     66 
     67 	/* Whole thing repeats after 32 bytes. */
     68 	u_short			_space[3];
     69 };
     70 
     71 /* possible values for the address modifier, sun3 vme version only */
     72 #define VME_SUPV_DATA_24	0x3d00
     73 
     74 /*
     75  * Status Register.
     76  * Note:
     77  *	(r)	indicates bit is read only.
     78  *	(rw)	indicates bit is read or write.
     79  *	(v)	vme host adaptor interface only.
     80  *	(o)	sun3/50 onboard host adaptor interface only.
     81  *	(b)	both vme and sun3/50 host adaptor interfaces.
     82  */
     83 #define SI_CSR_DMA_ACTIVE	0x8000	/* (r,o) DMA transfer active */
     84 #define SI_CSR_DMA_CONFLICT	0x4000	/* (r,b) reg accessed while DMA'ing */
     85 #define SI_CSR_DMA_BUS_ERR	0x2000	/* (r,b) bus error during DMA */
     86 #define SI_CSR_ID		0x1000	/* (r,b) 0 for 3/50, 1 for SCSI-3, */
     87 					/* 0 if SCSI-3 unmodified */
     88 #define SI_CSR_FIFO_FULL	0x0800	/* (r,b) fifo full */
     89 #define SI_CSR_FIFO_EMPTY	0x0400	/* (r,b) fifo empty */
     90 #define SI_CSR_SBC_IP		0x0200	/* (r,b) sbc interrupt pending */
     91 #define SI_CSR_DMA_IP		0x0100	/* (r,b) DMA interrupt pending */
     92 #define SI_CSR_LOB		0x00c0	/* (r,v) number of leftover bytes */
     93 #define SI_CSR_LOB_THREE	0x00c0	/* (r,v) three leftover bytes */
     94 #define SI_CSR_LOB_TWO		0x0080	/* (r,v) two leftover bytes */
     95 #define SI_CSR_LOB_ONE		0x0040	/* (r,v) one leftover byte */
     96 #define SI_CSR_BPCON		0x0020	/* (rw,v) byte packing control */
     97 					/* DMA is in 0=longwords, 1=words */
     98 #define SI_CSR_DMA_EN		0x0010	/* (rw,v) DMA/interrupt enable */
     99 #define SI_CSR_SEND		0x0008	/* (rw,b) DMA dir, 1=to device */
    100 #define SI_CSR_INTR_EN		0x0004	/* (rw,b) interrupts enable */
    101 #define SI_CSR_FIFO_RES		0x0002	/* (rw,b) inits fifo, 0=reset */
    102 #define SI_CSR_SCSI_RES		0x0001	/* (rw,b) reset sbc and udc, 0=reset */
    103 
    104