1 /* $NetBSD: mc68851.h,v 1.7 2024/12/20 23:50:00 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jeremy Cooper. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * This file contains the machine-independent definitions 34 * related to the Motorola MC68851 Memory Management Unit (MMU). 35 * Things that depend on the contents of the Translation Control 36 * (TC) register are in <machine/pte.h>. 37 */ 38 39 #ifndef _SUN3X_MC68851_H 40 #define _SUN3X_MC68851_H 41 42 /**************************** MMU STRUCTURES **************************** 43 * MMU structures define the format of data used by the MC68851. * 44 ************************************************************************ 45 ** MC68851 Root Pointer 46 * All address translations begin with the examination of the value 47 * in the MC68851 Root Pointer register. It describes the base address 48 * (in physical memory) of the root table to be used as well as any limits 49 * to the address range it supports. Its structure is identical to a Long 50 * Format Table Descriptor (described below.) 51 */ 52 struct mmu_rootptr { 53 u_long rp_attr; /* Lower/Upper Limit and access flags */ 54 u_long rp_addr; /* Physical Base Address */ 55 }; 56 typedef struct mmu_rootptr mmu_rootptr_t; 57 58 59 /** MC68851 Long Format Table Descriptor 60 * The root table for a sun3x pmap is a 128 element array of 'long format 61 * table descriptors'. The structure of a long format table descriptor is: 62 * 63 * 63 48 64 * +---+---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+ 65 * |L/U| LIMIT | 66 * +---+---.---+---.---.---+---+---+---+---+---+---+---+---+---.---+ 67 * | RAL | WAL |SG | S | 0 | 0 | 0 | 0 | U |WP |DT (10)| 68 * +---.---.---+---.---.---+---+---+---+---+---+---+---+---+---.---+ 69 * | TABLE PHYSICAL ADDRESS (BITS 31-16) | 70 * +---.---.---.---.---.---.---.---.---.---.---.---+---.---.---.---+ 71 * | TABLE PHYSICAL ADDRESS (15-4) | UNUSED | 72 * +---.---.---.---.---.---.---.---.---.---.---.---+---.---.---.---+ 73 * 15 0 74 * 75 * Note: keep the unused bits set to zero so that no masking of the 76 * base address is needed. 77 */ 78 struct mmu_long_dte_struct { /* 'dte' stands for 'descriptor table entry' */ 79 union { 80 struct { 81 char lu_flag:1; /* Lower/Upper Limit flag */ 82 int limit:15; /* Table Size limit */ 83 char ral:3; /* Read Access Level */ 84 char wal:3; /* Write Access Level */ 85 char sg:1; /* Shared Globally flag */ 86 char supv:1; /* Supervisor Only flag */ 87 char rsvd:4; /* Reserved (All zeros) */ 88 char u:1; /* Used flag */ 89 char wp:1; /* Write Protect flag */ 90 char dt:2; /* Descriptor Type */ 91 /* Bit masks for fields above */ 92 #define MMU_LONG_DTE_LU 0x80000000 93 #define MMU_LONG_DTE_LIMIT 0x7fff0000 94 #define MMU_LONG_DTE_RAL 0x0000e000 95 #define MMU_LONG_DTE_WAL 0x00001c00 96 #define MMU_LONG_DTE_SG 0x00000200 97 #define MMU_LONG_DTE_SUPV 0x00000100 98 #define MMU_LONG_DTE_USED 0x00000008 99 #define MMU_LONG_DTE_WP 0x00000004 100 #define MMU_LONG_DTE_DT 0x00000003 101 } attr_struct; 102 u_long raw; /* struct above, addressable as a long */ 103 } attr; 104 union { 105 struct { 106 int base_addr:28; /* Physical base address 107 char unused:4; * of the table pointed to 108 * by this entry. 109 */ 110 /* Bit masks for fields above */ 111 #define MMU_LONG_DTE_BASEADDR 0xfffffff0 112 } addr_struct; 113 u_long raw; /* struct above, addressable as a long */ 114 } addr; 115 }; 116 typedef struct mmu_long_dte_struct mmu_long_dte_t; 117 typedef struct mmu_long_dte_struct *mmu_long_dtbl_t; 118 119 /** MC68851 Long Format Page Descriptor 120 * Although not likely to be used in this implementation, a level 121 * 'A' table may contain long format PAGE descriptors. A long format 122 * page descriptor is the same size as a long format table descriptor. 123 * Its discriminating feature to the MMU is its descriptor field: 01. 124 * 63 48 125 * +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+ 126 * | UNUSED | 127 * +---.---.---+---.---.---+---+---+---+---+---+---+---+---+---.---+ 128 * | RAL | WAL |SG | S | G |CI | L | M | U |WP |DT (01)| 129 * +---.---.---+---.---.---+---+---+---+---+---+---+---+---+---.---+ 130 * | TABLE PHYSICAL ADDRESS (BITS 31-16) | 131 * +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+ 132 * |TABLE PHYS. ADDRESS (15-8) | UNUSED | 133 * +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+ 134 * 15 0 135 */ 136 struct mmu_long_pte_struct { /* 'pte' stands for 'page table entry' */ 137 union { 138 struct { 139 int unused:16; /* Unused */ 140 char ral:3; /* Read Access Level */ 141 char wal:3; /* Write Access Level */ 142 char sg:1; /* Shared Globally flag */ 143 char supv:1; /* Supervisor Only flag */ 144 char g:1; /* Gate allowed */ 145 char ci:1; /* Cache inhibit */ 146 char l:1; /* Lock entry */ 147 char m:1; /* Modified flag */ 148 char u:1; /* Used flag */ 149 char wp:1; /* Write Protect flag */ 150 char dt:2; /* Descriptor Type */ 151 /* Bit masks for fields above */ 152 #define MMU_LONG_PTE_RAL 0x0000e000 153 #define MMU_LONG_PTE_WAL 0x00001c00 154 #define MMU_LONG_PTE_SG 0x00000200 155 #define MMU_LONG_PTE_SUPV 0x00000100 156 #define MMU_LONG_PTE_GATE 0x00000080 157 #define MMU_LONG_PTE_CI 0x00000040 158 #define MMU_LONG_PTE_LOCK 0x00000020 159 #define MMU_LONG_PTE_M 0x00000010 160 #define MMU_LONG_PTE_USED 0x00000008 161 #define MMU_LONG_PTE_WP 0x00000004 162 #define MMU_LONG_PTE_DT 0x00000003 163 } attr_struct; 164 u_long raw; /* struct above, addressable as a long */ 165 } attr; 166 union { 167 struct { 168 long base_addr:24; /* Physical base address 169 char unused:8; * of page this entry 170 * points to. 171 */ 172 /* Bit masks for fields above */ 173 #define MMU_LONG_PTE_BASEADDR 0xffffff00 174 } addr_struct; 175 u_long raw; /* struct above, addressable as a long */ 176 } addr; 177 }; 178 typedef struct mmu_long_pte_struct mmu_long_pte_t; 179 typedef struct mmu_long_pte_struct *mmu_long_ptbl_t; 180 181 /* Every entry in the level A table (except for the page entries 182 * described above) points to a level B table. Level B tables are 183 * arrays of 'short format' table descriptors. Their structure 184 * is smaller than an A table descriptor and is as follows: 185 * 186 * 31 16 187 * +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+ 188 * | TABLE PHYSICAL BASE ADDRESS (BITS 31-16) | 189 * +---.---.---.---.---.---.---.---.---.---.---.---+---+---+---.---+ 190 * | TABLE PHYSICAL BASE ADDRESS (15-4) | U |WP |DT (10)| 191 * +---.---.---.---.---.---.---.---.---.---.---.---+---+---+---.---+ 192 * 15 0 193 */ 194 struct mmu_short_dte_struct { /* 'dte' stands for 'descriptor table entry' */ 195 union { 196 struct { 197 long base_addr:28; 198 char u:1; 199 char wp:1; 200 char dt:2; 201 #define MMU_SHORT_DTE_BASEADDR 0xfffffff0 202 #define MMU_SHORT_DTE_USED 0x00000008 203 #define MMU_SHORT_DTE_WP 0x00000004 204 #define MMU_SHORT_DTE_DT 0x00000003 205 } attr_struct; 206 u_long raw; 207 } attr; 208 }; 209 typedef struct mmu_short_dte_struct mmu_short_dte_t; 210 typedef struct mmu_short_dte_struct *mmu_short_dtbl_t; 211 212 /* Every entry in a level B table points to a level C table. Level C tables 213 * contain arrays of short format page 'entry' descriptors. A short format 214 * page 'entry' is the same size as a short format page 'table' 215 * descriptor (a B table entry). Thus B and C tables can be allocated 216 * interchangeably from the same pool. However, we will keep them separate. 217 * 218 * The descriptor type (DT) field of a Page Table Entry (PTE) is '01'. This 219 * indicates to the MMU that the address contained in the PTE's 'base 220 * address' field is the base address for a physical page in memory to which 221 * the VA should be mapped, and not a base address for a yet another 222 * descriptor table, thus ending the table walk. 223 * 224 * 31 16 225 * +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+ 226 * | TABLE PHYSICAL BASE ADDRESS (BITS 31-16) | 227 * +---.---.---.---.---.---.---.---+---+---+---+---+---+---+---.---+ 228 * |TABLE PHYS. BASE ADDRESS (15-8)| G |CI | L | M | U |WP |DT (10)| 229 * +---.---.---.---.---.---.---.---+---+---+---+---+---+---+---.---+ 230 * 15 0 231 */ 232 struct mmu_short_pte_struct { /* 'pte' stands for 'page table entry' */ 233 union { 234 struct { 235 long base_addr:24; 236 char g:1; 237 char ci:1; 238 char l:1; 239 char m:1; 240 char u:1; 241 char wp:1; 242 char dt:2; 243 #define MMU_SHORT_PTE_BASEADDR 0xffffff00 244 #define MMU_SHORT_PTE_UN2 0x00000080 245 #define MMU_SHORT_PTE_CI 0x00000040 246 #define MMU_SHORT_PTE_UN1 0x00000020 247 #define MMU_SHORT_PTE_M 0x00000010 248 #define MMU_SHORT_PTE_USED 0x00000008 249 #define MMU_SHORT_PTE_WP 0x00000004 250 #define MMU_SHORT_PTE_DT 0x00000003 251 } attr_struct; 252 u_long raw; 253 } attr; 254 }; 255 typedef struct mmu_short_pte_struct mmu_short_pte_t; 256 typedef struct mmu_short_pte_struct *mmu_short_ptbl_t; 257 258 /* These are bit masks and other values that are common to all types of 259 * descriptors. 260 */ 261 /* Page table descriptors have a 'Descriptor Type' field describing the 262 * format of the tables they point to. It is two bits wide and is one of: 263 */ 264 #define MMU_DT_INVALID 0x0 /* Invalid descriptor entry */ 265 #define MMU_DT_PAGE 0x1 /* Descriptor describes a page entry */ 266 #define MMU_DT_SHORT 0x2 /* describes a short format table */ 267 #define MMU_DT_LONG 0x3 /* describes a long format table */ 268 #define MMU_DT_MASK 0x00000003 /* Bit location of the DT field */ 269 270 /* Various macros for manipulating and setting MMU descriptor 271 * characteristics. 272 */ 273 /* returns true if a descriptor is valid. */ 274 #define MMU_VALID_DT(dte) ((dte).attr.raw & MMU_DT_MASK) 275 /* returns true if a descriptor is invalid */ 276 #define MMU_INVALID_DT(dte) (!((dte).attr.raw & MMU_DT_MASK)) 277 /* returns true if a descriptor has been referenced */ 278 #define MMU_PTE_USED(pte) ((pte).attr.raw & MMU_SHORT_PTE_USED) 279 /* returns true if a descriptor has been modified */ 280 #define MMU_PTE_MODIFIED(pte) ((pte).attr.raw & MMU_SHORT_PTE_M) 281 /* extracts the physical address from a pte */ 282 #define MMU_PTE_PA(pte) ((pte).attr.raw & MMU_SHORT_PTE_BASEADDR) 283 /* extracts the physical address from a dte */ 284 #define MMU_DTE_PA(dte) ((dte).attr.raw & MMU_SHORT_DTE_BASEADDR) 285 286 #endif /* _SUN3X_MC68851_H */ 287
Indexes created Sat Sep 20 22:09:52 GMT 2025