mc68851.h revision 1.1
1 /* $NetBSD: mc68851.h,v 1.1 1997/01/14 20:57:07 gwr Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jeremy Cooper. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _SUN3X_MC68851_H 40 #define _SUN3X_MC68851_H 41 42 /**************************** MMU STRUCTURES **************************** 43 * MMU structures define the format of data used by the MC68851. * 44 ************************************************************************ 45 * A virtual address is translated into a physical address by dividing its 46 * bits into four fields. The first three fields are used as indexes into 47 * descriptor tables and the last field (the 13 lowest significant 48 * bits) is an offset to be added to the base address found at the final 49 * table. The first three fields are named TIA, TIB and TIC respectively. 50 * 31 12 0 51 * +-.-.-.-.-.-.-+-.-.-.-.-.-+-.-.-.-.-.-+-.-.-.-.-.-.-.-.-.-.-.-.-+ 52 * | TIA | TIB | TIC | OFFSET | 53 * +-.-.-.-.-.-.-+-.-.-.-.-.-+-.-.-.-.-.-+-.-.-.-.-.-.-.-.-.-.-.-.-+ 54 */ 55 #define MMU_TIA_SHIFT (13+6+6) 56 #define MMU_TIA_MASK (0xfe000000) 57 #define MMU_TIA_RANGE (0x02000000) 58 #define MMU_TIB_SHIFT (13+6) 59 #define MMU_TIB_MASK (0x01f80000) 60 #define MMU_TIB_RANGE (0x00080000) 61 #define MMU_TIC_SHIFT (13) 62 #define MMU_TIC_MASK (0x0007e000) 63 #define MMU_TIC_RANGE (0x00002000) 64 #define MMU_PAGE_SHIFT (13) 65 #define MMU_PAGE_MASK (0xffffe000) 66 #define MMU_PAGE_SIZE (0x00002000) 67 68 /* Macros which extract each of these fields out of a given 69 * VA. 70 */ 71 #define MMU_TIA(va) \ 72 ((unsigned long) ((va) & MMU_TIA_MASK) >> MMU_TIA_SHIFT) 73 #define MMU_TIB(va) \ 74 ((unsigned long) ((va) & MMU_TIB_MASK) >> MMU_TIB_SHIFT) 75 #define MMU_TIC(va) \ 76 ((unsigned long) ((va) & MMU_TIC_MASK) >> MMU_TIC_SHIFT) 77 78 /* The widths of the TIA, TIB, and TIC fields determine the size (in 79 * elements) of the tables they index. 80 */ 81 #define MMU_A_TBL_SIZE (128) 82 #define MMU_B_TBL_SIZE (64) 83 #define MMU_C_TBL_SIZE (64) 84 85 /* Rounding macros. 86 * The MMU_ROUND macros are named misleadingly. MMU_ROUND_A actually 87 * rounds an address to the nearest B table boundary, and so on. 88 * MMU_ROUND_C() is synonmous with sun3x_round_page(). 89 */ 90 #define MMU_ROUND_A(pa)\ 91 ((unsigned long) (pa) & MMU_TIA_MASK) 92 #define MMU_ROUND_UP_A(pa)\ 93 ((unsigned long) (pa + MMU_TIA_RANGE - 1) & MMU_TIA_MASK) 94 #define MMU_ROUND_B(pa)\ 95 ((unsigned long) (pa) & (MMU_TIA_MASK|MMU_TIB_MASK)) 96 #define MMU_ROUND_UP_B(pa)\ 97 ((unsigned long) (pa + MMU_TIB_RANGE - 1) & (MMU_TIA_MASK|MMU_TIB_MASK)) 98 #define MMU_ROUND_C(pa)\ 99 ((unsigned long) (pa) & MMU_PAGE_MASK) 100 #define MMU_ROUND_UP_C(pa)\ 101 ((unsigned long) (pa + MMU_PAGE_SIZE - 1) & MMU_PAGE_MASK) 102 103 #if 0 /* in param.h */ 104 #define sun3x_round_page(pa)\ 105 ((unsigned long) (pa) & MMU_PAGE_MASK) 106 #endif 107 #define sun3x_round_up_page(pa)\ 108 ((unsigned long) (pa + MMU_PAGE_SIZE - 1) & MMU_PAGE_MASK) 109 110 /** MC68851 Long Format Table Descriptor 111 * The root table for a sun3x pmap is a 128 element array of 'long format 112 * table descriptors'. The structure of a long format table descriptor is: 113 * 114 * 63 48 115 * +---+---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+ 116 * |L/U| LIMIT | 117 * +---+---.---+---.---.---+---+---+---+---+---+---+---+---+---.---+ 118 * | RAL | WAL |SG | S | 0 | 0 | 0 | 0 | U |WP |DT (10)| 119 * +---.---.---+---.---.---+---+---+---+---+---+---+---+---+---.---+ 120 * | TABLE PHYSICAL ADDRESS (BITS 31-16) | 121 * +---.---.---.---.---.---.---.---.---.---.---.---+---.---.---.---+ 122 * | TABLE PHYSICAL ADDRESS (15-4) | UNUSED | 123 * +---.---.---.---.---.---.---.---.---.---.---.---+---.---.---.---+ 124 * 15 0 125 * 126 * Note: keep the unused bits set to zero so that no masking of the 127 * base address is needed. 128 */ 129 struct mmu_long_dte_struct { /* 'dte' stands for 'descriptor table entry' */ 130 union { 131 struct { 132 char lu_flag:1; /* Lower/Upper Limit flag */ 133 int limit:15; /* Table Size limit */ 134 char ral:3; /* Read Access Level */ 135 char wal:3; /* Write Access Level */ 136 char sg:1; /* Shared Globally flag */ 137 char supv:1; /* Supervisor Only flag */ 138 char rsvd:4; /* Reserved (All zeros) */ 139 char u:1; /* Used flag */ 140 char wp:1; /* Write Protect flag */ 141 char dt:2; /* Descriptor Type */ 142 /* Bit masks for fields above */ 143 #define MMU_LONG_DTE_LU 0x80000000 144 #define MMU_LONG_DTE_LIMIT 0x7fff0000 145 #define MMU_LONG_DTE_RAL 0x0000e000 146 #define MMU_LONG_DTE_WAL 0x00001c00 147 #define MMU_LONG_DTE_SG 0x00000200 148 #define MMU_LONG_DTE_SUPV 0x00000100 149 #define MMU_LONG_DTE_USED 0x00000008 150 #define MMU_LONG_DTE_WP 0x00000004 151 #define MMU_LONG_DTE_DT 0x00000003 152 } attr_struct; 153 u_long raw; /* struct above, addressable as a long */ 154 } attr; 155 union { 156 struct { 157 int base_addr:28; /* Physical base address 158 char unused:4; * of the table pointed to 159 * by this entry. 160 */ 161 /* Bit masks for fields above */ 162 #define MMU_LONG_DTE_BASEADDR 0xfffffff0 163 } addr_struct; 164 u_long raw; /* struct above, addressable as a long */ 165 } addr; 166 }; 167 typedef struct mmu_long_dte_struct mmu_long_dte_t; 168 typedef struct mmu_long_dte_struct *mmu_long_dtbl_t; 169 170 /** MC68851 Long Format Page Descriptor 171 * Although not likely to be used in this implementation, a level 172 * 'A' table may contain long format PAGE descriptors. A long format 173 * page descriptor is the same size as a long format table descriptor. 174 * Its discriminating feature to the MMU is its descriptor field: 01. 175 * 63 48 176 * +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+ 177 * | UNUSED | 178 * +---.---.---+---.---.---+---+---+---+---+---+---+---+---+---.---+ 179 * | RAL | WAL |SG | S | G |CI | L | M | U |WP |DT (01)| 180 * +---.---.---+---.---.---+---+---+---+---+---+---+---+---+---.---+ 181 * | TABLE PHYSICAL ADDRESS (BITS 31-16) | 182 * +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+ 183 * |TABLE PHYS. ADDRESS (15-8) | UNUSED | 184 * +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+ 185 * 15 0 186 */ 187 struct mmu_long_pte_struct { /* 'pte' stands for 'page table entry' */ 188 union { 189 struct { 190 int unused:16; /* Unused */ 191 char ral:3; /* Read Access Level */ 192 char wal:3; /* Write Access Level */ 193 char sg:1; /* Shared Globally flag */ 194 char supv:1; /* Supervisor Only flag */ 195 char g:1; /* Gate allowed */ 196 char ci:1; /* Cache inhibit */ 197 char l:1; /* Lock entry */ 198 char m:1; /* Modified flag */ 199 char u:1; /* Used flag */ 200 char wp:1; /* Write Protect flag */ 201 char dt:2; /* Descriptor Type */ 202 /* Bit masks for fields above */ 203 #define MMU_LONG_PTE_RAL 0x0000e000 204 #define MMU_LONG_PTE_WAL 0x00001c00 205 #define MMU_LONG_PTE_SG 0x00000200 206 #define MMU_LONG_PTE_SUPV 0x00000100 207 #define MMU_LONG_PTE_GATE 0x00000080 208 #define MMU_LONG_PTE_CI 0x00000040 209 #define MMU_LONG_PTE_LOCK 0x00000020 210 #define MMU_LONG_PTE_M 0x00000010 211 #define MMU_LONG_PTE_USED 0x00000008 212 #define MMU_LONG_PTE_WP 0x00000004 213 #define MMU_LONG_PTE_DT 0x00000003 214 } attr_struct; 215 u_long raw; /* struct above, addressable as a long */ 216 } attr; 217 union { 218 struct { 219 long base_addr:24; /* Physical base address 220 char unused:8; * of page this entry 221 * points to. 222 */ 223 /* Bit masks for fields above */ 224 #define MMU_LONG_PTE_BASEADDR 0xffffff00 225 } addr_struct; 226 u_long raw; /* struct above, addressable as a long */ 227 } addr; 228 }; 229 typedef struct mmu_long_pte_struct mmu_long_pte_t; 230 typedef struct mmu_long_pte_struct *mmu_long_ptbl_t; 231 232 /* Every entry in the level A table (except for the page entries 233 * described above) points to a level B table. Level B tables are 234 * arrays of 'short format' table descriptors. Their structure 235 * is smaller than an A table descriptor and is as follows: 236 * 237 * 31 16 238 * +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+ 239 * | TABLE PHYSICAL BASE ADDRESS (BITS 31-16) | 240 * +---.---.---.---.---.---.---.---.---.---.---.---+---+---+---.---+ 241 * | TABLE PHYSICAL BASE ADDRESS (15-4) | U |WP |DT (10)| 242 * +---.---.---.---.---.---.---.---.---.---.---.---+---+---+---.---+ 243 * 15 0 244 */ 245 struct mmu_short_dte_struct { /* 'dte' stands for 'descriptor table entry' */ 246 union { 247 struct { 248 long base_addr:28; 249 char u:1; 250 char wp:1; 251 char dt:2; 252 #define MMU_SHORT_DTE_BASEADDR 0xfffffff0 253 #define MMU_SHORT_DTE_USED 0x00000008 254 #define MMU_SHORT_DTE_WP 0x00000004 255 #define MMU_SHORT_DTE_DT 0x00000003 256 } attr_struct; 257 u_long raw; 258 } attr; 259 }; 260 typedef struct mmu_short_dte_struct mmu_short_dte_t; 261 typedef struct mmu_short_dte_struct *mmu_short_dtbl_t; 262 263 /* Every entry in a level B table points to a level C table. Level C tables 264 * contain arrays of short format page 'entry' descriptors. A short format 265 * page 'entry' is the same size as a short format page 'table' 266 * descriptor (a B table entry). Thus B and C tables can be allocated 267 * interchangeably from the same pool. However, we will keep them separate. 268 * 269 * The descriptor type (DT) field of a Page Table Entry (PTE) is '01'. This 270 * indicates to the MMU that the address contained in the PTE's 'base 271 * address' field is the base address for a physical page in memory to which 272 * the VA should be mapped, and not a base address for a yet another 273 * descriptor table, thus ending the table walk. 274 * 275 * 31 16 276 * +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+ 277 * | TABLE PHYSICAL BASE ADDRESS (BITS 31-16) | 278 * +---.---.---.---.---.---.---.---+---+---+---+---+---+---+---.---+ 279 * |TABLE PHYS. BASE ADDRESS (15-8)| G |CI | L | M | U |WP |DT (10)| 280 * +---.---.---.---.---.---.---.---+---+---+---+---+---+---+---.---+ 281 * 15 0 282 */ 283 struct mmu_short_pte_struct { /* 'pte' stands for 'page table entry' */ 284 union { 285 struct { 286 long base_addr:24; 287 char g:1; 288 char ci:1; 289 char l:1; 290 char m:1; 291 char u:1; 292 char wp:1; 293 char dt:2; 294 #define MMU_SHORT_PTE_BASEADDR 0xffffff00 295 #define MMU_SHORT_PTE_UN2 0x00000080 296 #define MMU_SHORT_PTE_CI 0x00000040 297 #define MMU_SHORT_PTE_UN1 0x00000020 298 #define MMU_SHORT_PTE_M 0x00000010 299 #define MMU_SHORT_PTE_USED 0x00000008 300 #define MMU_SHORT_PTE_WP 0x00000004 301 #define MMU_SHORT_PTE_DT 0x00000003 302 } attr_struct; 303 u_long raw; 304 } attr; 305 }; 306 typedef struct mmu_short_pte_struct mmu_short_pte_t; 307 typedef struct mmu_short_pte_struct *mmu_short_ptbl_t; 308 309 /* These are bit masks and other values that are common to all types of 310 * descriptors. 311 */ 312 /* Page table descriptors have a 'Descriptor Type' field describing the 313 * format of the tables they point to. It is two bits wide and is one of: 314 */ 315 #define MMU_DT_INVALID 0x0 /* Invalid descriptor entry */ 316 #define MMU_DT_PAGE 0x1 /* Descriptor describes a page entry */ 317 #define MMU_DT_SHORT 0x2 /* describes a short format table */ 318 #define MMU_DT_LONG 0x3 /* describes a long format table */ 319 #define MMU_DT_MASK 0x00000003 /* Bit location of the DT field */ 320 321 /* Various macros for manipulating and setting MMU descriptor 322 * characteristics. 323 */ 324 /* returns true if a descriptor is valid. */ 325 #define MMU_VALID_DT(dte) ((dte).attr.raw & MMU_DT_MASK) 326 /* returns true if a descriptor is invalid */ 327 #define MMU_INVALID_DT(dte) (!((dte).attr.raw & MMU_DT_MASK)) 328 /* returns true if a descriptor has been referenced */ 329 #define MMU_PTE_USED(pte) ((pte).attr.raw & MMU_SHORT_PTE_USED) 330 /* returns true if a descriptor has been modified */ 331 #define MMU_PTE_MODIFIED(pte) ((pte).attr.raw & MMU_SHORT_PTE_M) 332 /* extracts the physical address from a pte */ 333 #define MMU_PTE_PA(pte) ((pte).attr.raw & MMU_SHORT_PTE_BASEADDR) 334 /* extracts the physical address from a dte */ 335 #define MMU_DTE_PA(dte) ((dte).attr.raw & MMU_SHORT_DTE_BASEADDR) 336 337 #endif /* _SUN3X_MC68851_H */ 338
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