mc68851.h revision 1.2
1 /* $NetBSD: mc68851.h,v 1.2 1997/01/16 21:47:31 gwr Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jeremy Cooper. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * This file should contain the machine-independent definitions 41 * related to the Motorola MC68881 Memory Management Unit (MMU). 42 * Things that depend on the contents of the Translation Control 43 * (TC) register should be in <machine/pte.h>, not here. 44 */ 45 46 #ifndef _SUN3X_MC68851_H 47 #define _SUN3X_MC68851_H 48 49 /**************************** MMU STRUCTURES **************************** 50 * MMU structures define the format of data used by the MC68851. * 51 ************************************************************************ 52 * A virtual address is translated into a physical address by dividing its 53 * bits into four fields. The first three fields are used as indexes into 54 * descriptor tables and the last field (the 13 lowest significant 55 * bits) is an offset to be added to the base address found at the final 56 * table. The first three fields are named TIA, TIB and TIC respectively. 57 * 31 12 0 58 * +-.-.-.-.-.-.-+-.-.-.-.-.-+-.-.-.-.-.-+-.-.-.-.-.-.-.-.-.-.-.-.-+ 59 * | TIA | TIB | TIC | OFFSET | 60 * +-.-.-.-.-.-.-+-.-.-.-.-.-+-.-.-.-.-.-+-.-.-.-.-.-.-.-.-.-.-.-.-+ 61 */ 62 #define MMU_TIA_SHIFT (13+6+6) 63 #define MMU_TIA_MASK (0xfe000000) 64 #define MMU_TIA_RANGE (0x02000000) 65 #define MMU_TIB_SHIFT (13+6) 66 #define MMU_TIB_MASK (0x01f80000) 67 #define MMU_TIB_RANGE (0x00080000) 68 #define MMU_TIC_SHIFT (13) 69 #define MMU_TIC_MASK (0x0007e000) 70 #define MMU_TIC_RANGE (0x00002000) 71 #define MMU_PAGE_SHIFT (13) 72 #define MMU_PAGE_MASK (0xffffe000) 73 #define MMU_PAGE_SIZE (0x00002000) 74 75 /* Macros which extract each of these fields out of a given 76 * VA. 77 */ 78 #define MMU_TIA(va) \ 79 ((unsigned long) ((va) & MMU_TIA_MASK) >> MMU_TIA_SHIFT) 80 #define MMU_TIB(va) \ 81 ((unsigned long) ((va) & MMU_TIB_MASK) >> MMU_TIB_SHIFT) 82 #define MMU_TIC(va) \ 83 ((unsigned long) ((va) & MMU_TIC_MASK) >> MMU_TIC_SHIFT) 84 85 /* The widths of the TIA, TIB, and TIC fields determine the size (in 86 * elements) of the tables they index. 87 */ 88 #define MMU_A_TBL_SIZE (128) 89 #define MMU_B_TBL_SIZE (64) 90 #define MMU_C_TBL_SIZE (64) 91 92 /* Rounding macros. 93 * The MMU_ROUND macros are named misleadingly. MMU_ROUND_A actually 94 * rounds an address to the nearest B table boundary, and so on. 95 * MMU_ROUND_C() is synonmous with sun3x_round_page(). 96 */ 97 #define MMU_ROUND_A(pa)\ 98 ((unsigned long) (pa) & MMU_TIA_MASK) 99 #define MMU_ROUND_UP_A(pa)\ 100 ((unsigned long) (pa + MMU_TIA_RANGE - 1) & MMU_TIA_MASK) 101 #define MMU_ROUND_B(pa)\ 102 ((unsigned long) (pa) & (MMU_TIA_MASK|MMU_TIB_MASK)) 103 #define MMU_ROUND_UP_B(pa)\ 104 ((unsigned long) (pa + MMU_TIB_RANGE - 1) & (MMU_TIA_MASK|MMU_TIB_MASK)) 105 #define MMU_ROUND_C(pa)\ 106 ((unsigned long) (pa) & MMU_PAGE_MASK) 107 #define MMU_ROUND_UP_C(pa)\ 108 ((unsigned long) (pa + MMU_PAGE_SIZE - 1) & MMU_PAGE_MASK) 109 110 111 /** MC68851 Root Pointer 112 */ 113 struct mmu_rootptr { 114 u_long limit; /* and type */ 115 u_long paddr; 116 }; 117 118 119 /** MC68851 Long Format Table Descriptor 120 * The root table for a sun3x pmap is a 128 element array of 'long format 121 * table descriptors'. The structure of a long format table descriptor is: 122 * 123 * 63 48 124 * +---+---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+ 125 * |L/U| LIMIT | 126 * +---+---.---+---.---.---+---+---+---+---+---+---+---+---+---.---+ 127 * | RAL | WAL |SG | S | 0 | 0 | 0 | 0 | U |WP |DT (10)| 128 * +---.---.---+---.---.---+---+---+---+---+---+---+---+---+---.---+ 129 * | TABLE PHYSICAL ADDRESS (BITS 31-16) | 130 * +---.---.---.---.---.---.---.---.---.---.---.---+---.---.---.---+ 131 * | TABLE PHYSICAL ADDRESS (15-4) | UNUSED | 132 * +---.---.---.---.---.---.---.---.---.---.---.---+---.---.---.---+ 133 * 15 0 134 * 135 * Note: keep the unused bits set to zero so that no masking of the 136 * base address is needed. 137 */ 138 struct mmu_long_dte_struct { /* 'dte' stands for 'descriptor table entry' */ 139 union { 140 struct { 141 char lu_flag:1; /* Lower/Upper Limit flag */ 142 int limit:15; /* Table Size limit */ 143 char ral:3; /* Read Access Level */ 144 char wal:3; /* Write Access Level */ 145 char sg:1; /* Shared Globally flag */ 146 char supv:1; /* Supervisor Only flag */ 147 char rsvd:4; /* Reserved (All zeros) */ 148 char u:1; /* Used flag */ 149 char wp:1; /* Write Protect flag */ 150 char dt:2; /* Descriptor Type */ 151 /* Bit masks for fields above */ 152 #define MMU_LONG_DTE_LU 0x80000000 153 #define MMU_LONG_DTE_LIMIT 0x7fff0000 154 #define MMU_LONG_DTE_RAL 0x0000e000 155 #define MMU_LONG_DTE_WAL 0x00001c00 156 #define MMU_LONG_DTE_SG 0x00000200 157 #define MMU_LONG_DTE_SUPV 0x00000100 158 #define MMU_LONG_DTE_USED 0x00000008 159 #define MMU_LONG_DTE_WP 0x00000004 160 #define MMU_LONG_DTE_DT 0x00000003 161 } attr_struct; 162 u_long raw; /* struct above, addressable as a long */ 163 } attr; 164 union { 165 struct { 166 int base_addr:28; /* Physical base address 167 char unused:4; * of the table pointed to 168 * by this entry. 169 */ 170 /* Bit masks for fields above */ 171 #define MMU_LONG_DTE_BASEADDR 0xfffffff0 172 } addr_struct; 173 u_long raw; /* struct above, addressable as a long */ 174 } addr; 175 }; 176 typedef struct mmu_long_dte_struct mmu_long_dte_t; 177 typedef struct mmu_long_dte_struct *mmu_long_dtbl_t; 178 179 /** MC68851 Long Format Page Descriptor 180 * Although not likely to be used in this implementation, a level 181 * 'A' table may contain long format PAGE descriptors. A long format 182 * page descriptor is the same size as a long format table descriptor. 183 * Its discriminating feature to the MMU is its descriptor field: 01. 184 * 63 48 185 * +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+ 186 * | UNUSED | 187 * +---.---.---+---.---.---+---+---+---+---+---+---+---+---+---.---+ 188 * | RAL | WAL |SG | S | G |CI | L | M | U |WP |DT (01)| 189 * +---.---.---+---.---.---+---+---+---+---+---+---+---+---+---.---+ 190 * | TABLE PHYSICAL ADDRESS (BITS 31-16) | 191 * +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+ 192 * |TABLE PHYS. ADDRESS (15-8) | UNUSED | 193 * +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+ 194 * 15 0 195 */ 196 struct mmu_long_pte_struct { /* 'pte' stands for 'page table entry' */ 197 union { 198 struct { 199 int unused:16; /* Unused */ 200 char ral:3; /* Read Access Level */ 201 char wal:3; /* Write Access Level */ 202 char sg:1; /* Shared Globally flag */ 203 char supv:1; /* Supervisor Only flag */ 204 char g:1; /* Gate allowed */ 205 char ci:1; /* Cache inhibit */ 206 char l:1; /* Lock entry */ 207 char m:1; /* Modified flag */ 208 char u:1; /* Used flag */ 209 char wp:1; /* Write Protect flag */ 210 char dt:2; /* Descriptor Type */ 211 /* Bit masks for fields above */ 212 #define MMU_LONG_PTE_RAL 0x0000e000 213 #define MMU_LONG_PTE_WAL 0x00001c00 214 #define MMU_LONG_PTE_SG 0x00000200 215 #define MMU_LONG_PTE_SUPV 0x00000100 216 #define MMU_LONG_PTE_GATE 0x00000080 217 #define MMU_LONG_PTE_CI 0x00000040 218 #define MMU_LONG_PTE_LOCK 0x00000020 219 #define MMU_LONG_PTE_M 0x00000010 220 #define MMU_LONG_PTE_USED 0x00000008 221 #define MMU_LONG_PTE_WP 0x00000004 222 #define MMU_LONG_PTE_DT 0x00000003 223 } attr_struct; 224 u_long raw; /* struct above, addressable as a long */ 225 } attr; 226 union { 227 struct { 228 long base_addr:24; /* Physical base address 229 char unused:8; * of page this entry 230 * points to. 231 */ 232 /* Bit masks for fields above */ 233 #define MMU_LONG_PTE_BASEADDR 0xffffff00 234 } addr_struct; 235 u_long raw; /* struct above, addressable as a long */ 236 } addr; 237 }; 238 typedef struct mmu_long_pte_struct mmu_long_pte_t; 239 typedef struct mmu_long_pte_struct *mmu_long_ptbl_t; 240 241 /* Every entry in the level A table (except for the page entries 242 * described above) points to a level B table. Level B tables are 243 * arrays of 'short format' table descriptors. Their structure 244 * is smaller than an A table descriptor and is as follows: 245 * 246 * 31 16 247 * +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+ 248 * | TABLE PHYSICAL BASE ADDRESS (BITS 31-16) | 249 * +---.---.---.---.---.---.---.---.---.---.---.---+---+---+---.---+ 250 * | TABLE PHYSICAL BASE ADDRESS (15-4) | U |WP |DT (10)| 251 * +---.---.---.---.---.---.---.---.---.---.---.---+---+---+---.---+ 252 * 15 0 253 */ 254 struct mmu_short_dte_struct { /* 'dte' stands for 'descriptor table entry' */ 255 union { 256 struct { 257 long base_addr:28; 258 char u:1; 259 char wp:1; 260 char dt:2; 261 #define MMU_SHORT_DTE_BASEADDR 0xfffffff0 262 #define MMU_SHORT_DTE_USED 0x00000008 263 #define MMU_SHORT_DTE_WP 0x00000004 264 #define MMU_SHORT_DTE_DT 0x00000003 265 } attr_struct; 266 u_long raw; 267 } attr; 268 }; 269 typedef struct mmu_short_dte_struct mmu_short_dte_t; 270 typedef struct mmu_short_dte_struct *mmu_short_dtbl_t; 271 272 /* Every entry in a level B table points to a level C table. Level C tables 273 * contain arrays of short format page 'entry' descriptors. A short format 274 * page 'entry' is the same size as a short format page 'table' 275 * descriptor (a B table entry). Thus B and C tables can be allocated 276 * interchangeably from the same pool. However, we will keep them separate. 277 * 278 * The descriptor type (DT) field of a Page Table Entry (PTE) is '01'. This 279 * indicates to the MMU that the address contained in the PTE's 'base 280 * address' field is the base address for a physical page in memory to which 281 * the VA should be mapped, and not a base address for a yet another 282 * descriptor table, thus ending the table walk. 283 * 284 * 31 16 285 * +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+ 286 * | TABLE PHYSICAL BASE ADDRESS (BITS 31-16) | 287 * +---.---.---.---.---.---.---.---+---+---+---+---+---+---+---.---+ 288 * |TABLE PHYS. BASE ADDRESS (15-8)| G |CI | L | M | U |WP |DT (10)| 289 * +---.---.---.---.---.---.---.---+---+---+---+---+---+---+---.---+ 290 * 15 0 291 */ 292 struct mmu_short_pte_struct { /* 'pte' stands for 'page table entry' */ 293 union { 294 struct { 295 long base_addr:24; 296 char g:1; 297 char ci:1; 298 char l:1; 299 char m:1; 300 char u:1; 301 char wp:1; 302 char dt:2; 303 #define MMU_SHORT_PTE_BASEADDR 0xffffff00 304 #define MMU_SHORT_PTE_UN2 0x00000080 305 #define MMU_SHORT_PTE_CI 0x00000040 306 #define MMU_SHORT_PTE_UN1 0x00000020 307 #define MMU_SHORT_PTE_M 0x00000010 308 #define MMU_SHORT_PTE_USED 0x00000008 309 #define MMU_SHORT_PTE_WP 0x00000004 310 #define MMU_SHORT_PTE_DT 0x00000003 311 } attr_struct; 312 u_long raw; 313 } attr; 314 }; 315 typedef struct mmu_short_pte_struct mmu_short_pte_t; 316 typedef struct mmu_short_pte_struct *mmu_short_ptbl_t; 317 318 /* These are bit masks and other values that are common to all types of 319 * descriptors. 320 */ 321 /* Page table descriptors have a 'Descriptor Type' field describing the 322 * format of the tables they point to. It is two bits wide and is one of: 323 */ 324 #define MMU_DT_INVALID 0x0 /* Invalid descriptor entry */ 325 #define MMU_DT_PAGE 0x1 /* Descriptor describes a page entry */ 326 #define MMU_DT_SHORT 0x2 /* describes a short format table */ 327 #define MMU_DT_LONG 0x3 /* describes a long format table */ 328 #define MMU_DT_MASK 0x00000003 /* Bit location of the DT field */ 329 330 /* Various macros for manipulating and setting MMU descriptor 331 * characteristics. 332 */ 333 /* returns true if a descriptor is valid. */ 334 #define MMU_VALID_DT(dte) ((dte).attr.raw & MMU_DT_MASK) 335 /* returns true if a descriptor is invalid */ 336 #define MMU_INVALID_DT(dte) (!((dte).attr.raw & MMU_DT_MASK)) 337 /* returns true if a descriptor has been referenced */ 338 #define MMU_PTE_USED(pte) ((pte).attr.raw & MMU_SHORT_PTE_USED) 339 /* returns true if a descriptor has been modified */ 340 #define MMU_PTE_MODIFIED(pte) ((pte).attr.raw & MMU_SHORT_PTE_M) 341 /* extracts the physical address from a pte */ 342 #define MMU_PTE_PA(pte) ((pte).attr.raw & MMU_SHORT_PTE_BASEADDR) 343 /* extracts the physical address from a dte */ 344 #define MMU_DTE_PA(dte) ((dte).attr.raw & MMU_SHORT_DTE_BASEADDR) 345 346 #endif /* _SUN3X_MC68851_H */ 347
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