mc68851.h revision 1.3
1 /* $NetBSD: mc68851.h,v 1.3 1997/01/23 22:15:41 gwr Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jeremy Cooper. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * This file should contain the machine-independent definitions 41 * related to the Motorola MC68881 Memory Management Unit (MMU). 42 * Things that depend on the contents of the Translation Control 43 * (TC) register should be in <machine/pte.h>, not here. 44 */ 45 46 #ifndef _SUN3X_MC68851_H 47 #define _SUN3X_MC68851_H 48 49 /**************************** MMU STRUCTURES **************************** 50 * MMU structures define the format of data used by the MC68851. * 51 ************************************************************************ 52 * A virtual address is translated into a physical address by dividing its 53 * bits into four fields. The first three fields are used as indexes into 54 * descriptor tables and the last field (the 13 lowest significant 55 * bits) is an offset to be added to the base address found at the final 56 * table. The first three fields are named TIA, TIB and TIC respectively. 57 * 31 12 0 58 * +-.-.-.-.-.-.-+-.-.-.-.-.-+-.-.-.-.-.-+-.-.-.-.-.-.-.-.-.-.-.-.-+ 59 * | TIA | TIB | TIC | OFFSET | 60 * +-.-.-.-.-.-.-+-.-.-.-.-.-+-.-.-.-.-.-+-.-.-.-.-.-.-.-.-.-.-.-.-+ 61 */ 62 #define MMU_TIA_SHIFT (13+6+6) 63 #define MMU_TIA_MASK (0xfe000000) 64 #define MMU_TIA_RANGE (0x02000000) 65 #define MMU_TIB_SHIFT (13+6) 66 #define MMU_TIB_MASK (0x01f80000) 67 #define MMU_TIB_RANGE (0x00080000) 68 #define MMU_TIC_SHIFT (13) 69 #define MMU_TIC_MASK (0x0007e000) 70 #define MMU_TIC_RANGE (0x00002000) 71 #define MMU_PAGE_SHIFT (13) 72 #define MMU_PAGE_MASK (0xffffe000) 73 #define MMU_PAGE_SIZE (0x00002000) 74 75 /* Macros which extract each of these fields out of a given 76 * VA. 77 */ 78 #define MMU_TIA(va) \ 79 ((unsigned long) ((va) & MMU_TIA_MASK) >> MMU_TIA_SHIFT) 80 #define MMU_TIB(va) \ 81 ((unsigned long) ((va) & MMU_TIB_MASK) >> MMU_TIB_SHIFT) 82 #define MMU_TIC(va) \ 83 ((unsigned long) ((va) & MMU_TIC_MASK) >> MMU_TIC_SHIFT) 84 85 /* The widths of the TIA, TIB, and TIC fields determine the size (in 86 * elements) of the tables they index. 87 */ 88 #define MMU_A_TBL_SIZE (128) 89 #define MMU_B_TBL_SIZE (64) 90 #define MMU_C_TBL_SIZE (64) 91 92 /* Rounding macros. 93 * The MMU_ROUND macros are named misleadingly. MMU_ROUND_A actually 94 * rounds an address to the nearest B table boundary, and so on. 95 * MMU_ROUND_C() is synonmous with sun3x_round_page(). 96 */ 97 #define MMU_ROUND_A(pa)\ 98 ((unsigned long) (pa) & MMU_TIA_MASK) 99 #define MMU_ROUND_UP_A(pa)\ 100 ((unsigned long) (pa + MMU_TIA_RANGE - 1) & MMU_TIA_MASK) 101 #define MMU_ROUND_B(pa)\ 102 ((unsigned long) (pa) & (MMU_TIA_MASK|MMU_TIB_MASK)) 103 #define MMU_ROUND_UP_B(pa)\ 104 ((unsigned long) (pa + MMU_TIB_RANGE - 1) & (MMU_TIA_MASK|MMU_TIB_MASK)) 105 #define MMU_ROUND_C(pa)\ 106 ((unsigned long) (pa) & MMU_PAGE_MASK) 107 #define MMU_ROUND_UP_C(pa)\ 108 ((unsigned long) (pa + MMU_PAGE_SIZE - 1) & MMU_PAGE_MASK) 109 110 111 /** MC68851 Root Pointer 112 * All address translations begin with the examination of the value 113 * in the MC68851 Root Pointer register. It describes the base address 114 * (in physical memory) of the root table to be used as well as any limits 115 * to the address range it supports. Its structure is identical to a Long 116 * Format Table Descriptor (described below.) 117 */ 118 struct mmu_rootptr { 119 u_long rp_attr; /* Lower/Upper Limit and access flags */ 120 u_long rp_addr; /* Physical Base Address */ 121 }; 122 typedef struct mmu_rootptr mmu_rootptr_t; 123 124 125 /** MC68851 Long Format Table Descriptor 126 * The root table for a sun3x pmap is a 128 element array of 'long format 127 * table descriptors'. The structure of a long format table descriptor is: 128 * 129 * 63 48 130 * +---+---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+ 131 * |L/U| LIMIT | 132 * +---+---.---+---.---.---+---+---+---+---+---+---+---+---+---.---+ 133 * | RAL | WAL |SG | S | 0 | 0 | 0 | 0 | U |WP |DT (10)| 134 * +---.---.---+---.---.---+---+---+---+---+---+---+---+---+---.---+ 135 * | TABLE PHYSICAL ADDRESS (BITS 31-16) | 136 * +---.---.---.---.---.---.---.---.---.---.---.---+---.---.---.---+ 137 * | TABLE PHYSICAL ADDRESS (15-4) | UNUSED | 138 * +---.---.---.---.---.---.---.---.---.---.---.---+---.---.---.---+ 139 * 15 0 140 * 141 * Note: keep the unused bits set to zero so that no masking of the 142 * base address is needed. 143 */ 144 struct mmu_long_dte_struct { /* 'dte' stands for 'descriptor table entry' */ 145 union { 146 struct { 147 char lu_flag:1; /* Lower/Upper Limit flag */ 148 int limit:15; /* Table Size limit */ 149 char ral:3; /* Read Access Level */ 150 char wal:3; /* Write Access Level */ 151 char sg:1; /* Shared Globally flag */ 152 char supv:1; /* Supervisor Only flag */ 153 char rsvd:4; /* Reserved (All zeros) */ 154 char u:1; /* Used flag */ 155 char wp:1; /* Write Protect flag */ 156 char dt:2; /* Descriptor Type */ 157 /* Bit masks for fields above */ 158 #define MMU_LONG_DTE_LU 0x80000000 159 #define MMU_LONG_DTE_LIMIT 0x7fff0000 160 #define MMU_LONG_DTE_RAL 0x0000e000 161 #define MMU_LONG_DTE_WAL 0x00001c00 162 #define MMU_LONG_DTE_SG 0x00000200 163 #define MMU_LONG_DTE_SUPV 0x00000100 164 #define MMU_LONG_DTE_USED 0x00000008 165 #define MMU_LONG_DTE_WP 0x00000004 166 #define MMU_LONG_DTE_DT 0x00000003 167 } attr_struct; 168 u_long raw; /* struct above, addressable as a long */ 169 } attr; 170 union { 171 struct { 172 int base_addr:28; /* Physical base address 173 char unused:4; * of the table pointed to 174 * by this entry. 175 */ 176 /* Bit masks for fields above */ 177 #define MMU_LONG_DTE_BASEADDR 0xfffffff0 178 } addr_struct; 179 u_long raw; /* struct above, addressable as a long */ 180 } addr; 181 }; 182 typedef struct mmu_long_dte_struct mmu_long_dte_t; 183 typedef struct mmu_long_dte_struct *mmu_long_dtbl_t; 184 185 /** MC68851 Long Format Page Descriptor 186 * Although not likely to be used in this implementation, a level 187 * 'A' table may contain long format PAGE descriptors. A long format 188 * page descriptor is the same size as a long format table descriptor. 189 * Its discriminating feature to the MMU is its descriptor field: 01. 190 * 63 48 191 * +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+ 192 * | UNUSED | 193 * +---.---.---+---.---.---+---+---+---+---+---+---+---+---+---.---+ 194 * | RAL | WAL |SG | S | G |CI | L | M | U |WP |DT (01)| 195 * +---.---.---+---.---.---+---+---+---+---+---+---+---+---+---.---+ 196 * | TABLE PHYSICAL ADDRESS (BITS 31-16) | 197 * +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+ 198 * |TABLE PHYS. ADDRESS (15-8) | UNUSED | 199 * +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+ 200 * 15 0 201 */ 202 struct mmu_long_pte_struct { /* 'pte' stands for 'page table entry' */ 203 union { 204 struct { 205 int unused:16; /* Unused */ 206 char ral:3; /* Read Access Level */ 207 char wal:3; /* Write Access Level */ 208 char sg:1; /* Shared Globally flag */ 209 char supv:1; /* Supervisor Only flag */ 210 char g:1; /* Gate allowed */ 211 char ci:1; /* Cache inhibit */ 212 char l:1; /* Lock entry */ 213 char m:1; /* Modified flag */ 214 char u:1; /* Used flag */ 215 char wp:1; /* Write Protect flag */ 216 char dt:2; /* Descriptor Type */ 217 /* Bit masks for fields above */ 218 #define MMU_LONG_PTE_RAL 0x0000e000 219 #define MMU_LONG_PTE_WAL 0x00001c00 220 #define MMU_LONG_PTE_SG 0x00000200 221 #define MMU_LONG_PTE_SUPV 0x00000100 222 #define MMU_LONG_PTE_GATE 0x00000080 223 #define MMU_LONG_PTE_CI 0x00000040 224 #define MMU_LONG_PTE_LOCK 0x00000020 225 #define MMU_LONG_PTE_M 0x00000010 226 #define MMU_LONG_PTE_USED 0x00000008 227 #define MMU_LONG_PTE_WP 0x00000004 228 #define MMU_LONG_PTE_DT 0x00000003 229 } attr_struct; 230 u_long raw; /* struct above, addressable as a long */ 231 } attr; 232 union { 233 struct { 234 long base_addr:24; /* Physical base address 235 char unused:8; * of page this entry 236 * points to. 237 */ 238 /* Bit masks for fields above */ 239 #define MMU_LONG_PTE_BASEADDR 0xffffff00 240 } addr_struct; 241 u_long raw; /* struct above, addressable as a long */ 242 } addr; 243 }; 244 typedef struct mmu_long_pte_struct mmu_long_pte_t; 245 typedef struct mmu_long_pte_struct *mmu_long_ptbl_t; 246 247 /* Every entry in the level A table (except for the page entries 248 * described above) points to a level B table. Level B tables are 249 * arrays of 'short format' table descriptors. Their structure 250 * is smaller than an A table descriptor and is as follows: 251 * 252 * 31 16 253 * +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+ 254 * | TABLE PHYSICAL BASE ADDRESS (BITS 31-16) | 255 * +---.---.---.---.---.---.---.---.---.---.---.---+---+---+---.---+ 256 * | TABLE PHYSICAL BASE ADDRESS (15-4) | U |WP |DT (10)| 257 * +---.---.---.---.---.---.---.---.---.---.---.---+---+---+---.---+ 258 * 15 0 259 */ 260 struct mmu_short_dte_struct { /* 'dte' stands for 'descriptor table entry' */ 261 union { 262 struct { 263 long base_addr:28; 264 char u:1; 265 char wp:1; 266 char dt:2; 267 #define MMU_SHORT_DTE_BASEADDR 0xfffffff0 268 #define MMU_SHORT_DTE_USED 0x00000008 269 #define MMU_SHORT_DTE_WP 0x00000004 270 #define MMU_SHORT_DTE_DT 0x00000003 271 } attr_struct; 272 u_long raw; 273 } attr; 274 }; 275 typedef struct mmu_short_dte_struct mmu_short_dte_t; 276 typedef struct mmu_short_dte_struct *mmu_short_dtbl_t; 277 278 /* Every entry in a level B table points to a level C table. Level C tables 279 * contain arrays of short format page 'entry' descriptors. A short format 280 * page 'entry' is the same size as a short format page 'table' 281 * descriptor (a B table entry). Thus B and C tables can be allocated 282 * interchangeably from the same pool. However, we will keep them separate. 283 * 284 * The descriptor type (DT) field of a Page Table Entry (PTE) is '01'. This 285 * indicates to the MMU that the address contained in the PTE's 'base 286 * address' field is the base address for a physical page in memory to which 287 * the VA should be mapped, and not a base address for a yet another 288 * descriptor table, thus ending the table walk. 289 * 290 * 31 16 291 * +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+ 292 * | TABLE PHYSICAL BASE ADDRESS (BITS 31-16) | 293 * +---.---.---.---.---.---.---.---+---+---+---+---+---+---+---.---+ 294 * |TABLE PHYS. BASE ADDRESS (15-8)| G |CI | L | M | U |WP |DT (10)| 295 * +---.---.---.---.---.---.---.---+---+---+---+---+---+---+---.---+ 296 * 15 0 297 */ 298 struct mmu_short_pte_struct { /* 'pte' stands for 'page table entry' */ 299 union { 300 struct { 301 long base_addr:24; 302 char g:1; 303 char ci:1; 304 char l:1; 305 char m:1; 306 char u:1; 307 char wp:1; 308 char dt:2; 309 #define MMU_SHORT_PTE_BASEADDR 0xffffff00 310 #define MMU_SHORT_PTE_UN2 0x00000080 311 #define MMU_SHORT_PTE_CI 0x00000040 312 #define MMU_SHORT_PTE_UN1 0x00000020 313 #define MMU_SHORT_PTE_M 0x00000010 314 #define MMU_SHORT_PTE_USED 0x00000008 315 #define MMU_SHORT_PTE_WP 0x00000004 316 #define MMU_SHORT_PTE_DT 0x00000003 317 } attr_struct; 318 u_long raw; 319 } attr; 320 }; 321 typedef struct mmu_short_pte_struct mmu_short_pte_t; 322 typedef struct mmu_short_pte_struct *mmu_short_ptbl_t; 323 324 /* These are bit masks and other values that are common to all types of 325 * descriptors. 326 */ 327 /* Page table descriptors have a 'Descriptor Type' field describing the 328 * format of the tables they point to. It is two bits wide and is one of: 329 */ 330 #define MMU_DT_INVALID 0x0 /* Invalid descriptor entry */ 331 #define MMU_DT_PAGE 0x1 /* Descriptor describes a page entry */ 332 #define MMU_DT_SHORT 0x2 /* describes a short format table */ 333 #define MMU_DT_LONG 0x3 /* describes a long format table */ 334 #define MMU_DT_MASK 0x00000003 /* Bit location of the DT field */ 335 336 /* Various macros for manipulating and setting MMU descriptor 337 * characteristics. 338 */ 339 /* returns true if a descriptor is valid. */ 340 #define MMU_VALID_DT(dte) ((dte).attr.raw & MMU_DT_MASK) 341 /* returns true if a descriptor is invalid */ 342 #define MMU_INVALID_DT(dte) (!((dte).attr.raw & MMU_DT_MASK)) 343 /* returns true if a descriptor has been referenced */ 344 #define MMU_PTE_USED(pte) ((pte).attr.raw & MMU_SHORT_PTE_USED) 345 /* returns true if a descriptor has been modified */ 346 #define MMU_PTE_MODIFIED(pte) ((pte).attr.raw & MMU_SHORT_PTE_M) 347 /* extracts the physical address from a pte */ 348 #define MMU_PTE_PA(pte) ((pte).attr.raw & MMU_SHORT_PTE_BASEADDR) 349 /* extracts the physical address from a dte */ 350 #define MMU_DTE_PA(dte) ((dte).attr.raw & MMU_SHORT_DTE_BASEADDR) 351 352 #endif /* _SUN3X_MC68851_H */ 353
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