1 /* $NetBSD: clock.c,v 1.45 2024/01/19 18:18:55 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1982, 1990, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * the Systems Programming Group of the University of Utah Computer 9 * Science Department. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * from: Utah Hdr: clock.c 1.18 91/01/21$ 36 * from: @(#)clock.c 8.2 (Berkeley) 1/12/94 37 */ 38 39 /* 40 * Copyright (c) 1994 Gordon W. Ross 41 * Copyright (c) 1993 Adam Glass 42 * Copyright (c) 1988 University of Utah. 43 * 44 * This code is derived from software contributed to Berkeley by 45 * the Systems Programming Group of the University of Utah Computer 46 * Science Department. 47 * 48 * Redistribution and use in source and binary forms, with or without 49 * modification, are permitted provided that the following conditions 50 * are met: 51 * 1. Redistributions of source code must retain the above copyright 52 * notice, this list of conditions and the following disclaimer. 53 * 2. Redistributions in binary form must reproduce the above copyright 54 * notice, this list of conditions and the following disclaimer in the 55 * documentation and/or other materials provided with the distribution. 56 * 3. All advertising materials mentioning features or use of this software 57 * must display the following acknowledgement: 58 * This product includes software developed by the University of 59 * California, Berkeley and its contributors. 60 * 4. Neither the name of the University nor the names of its contributors 61 * may be used to endorse or promote products derived from this software 62 * without specific prior written permission. 63 * 64 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 67 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 74 * SUCH DAMAGE. 75 * 76 * from: Utah Hdr: clock.c 1.18 91/01/21$ 77 * from: @(#)clock.c 8.2 (Berkeley) 1/12/94 78 */ 79 80 /* 81 * Machine-dependent clock routines. Sun3X machines may have 82 * either the Mostek 48T02 or the Intersil 7170 clock. 83 * 84 * It is tricky to determine which you have, because there is 85 * always something responding at the address where the Mostek 86 * clock might be found: either a Mostek or plain-old EEPROM. 87 * Therefore, we cheat. If we find an Intersil clock, assume 88 * that what responds at the end of the EEPROM space is just 89 * plain-old EEPROM (not a Mostek clock). Worse, there are 90 * H/W problems with probing for an Intersil on the 3/80, so 91 * on that machine we "know" there is a Mostek clock. 92 * 93 * Note that the probing algorithm described above requires 94 * that we probe the intersil before we probe the mostek! 95 */ 96 97 #include <sys/cdefs.h> 98 __KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.45 2024/01/19 18:18:55 thorpej Exp $"); 99 100 #include <sys/param.h> 101 #include <sys/systm.h> 102 #include <sys/time.h> 103 #include <sys/kernel.h> 104 #include <sys/device.h> 105 106 #include <uvm/uvm_extern.h> 107 108 #include <m68k/asm_single.h> 109 110 #include <machine/autoconf.h> 111 #include <machine/bus.h> 112 #include <machine/cpu.h> 113 #include <machine/idprom.h> 114 #include <machine/leds.h> 115 #include <machine/vectors.h> 116 117 #include <dev/clock_subr.h> 118 #include <dev/ic/intersil7170reg.h> 119 #include <dev/ic/intersil7170var.h> 120 #include <dev/ic/mk48txxreg.h> 121 #include <dev/ic/mk48txxvar.h> 122 123 #include <sun3/sun3/machdep.h> 124 #include <sun3/sun3/interreg.h> 125 126 #define SUN3_470 Yes 127 128 #define CLOCK_PRI 5 129 #define IREG_CLK_BITS (IREG_CLOCK_ENAB_7 | IREG_CLOCK_ENAB_5) 130 131 #define MKCLOCK_REG_OFFSET (MK48T02_CLKOFF + MK48TXX_ICSR) 132 133 /* 134 * Only one of these two variables should be non-zero after 135 * autoconfiguration determines which clock we have. 136 */ 137 static volatile void *intersil_va; 138 static volatile void *mostek_clk_va; 139 140 void _isr_clock(void); /* in locore.s */ 141 void clock_intr(struct clockframe); 142 143 144 static int clock_match(device_t, cfdata_t, void *); 145 static void clock_attach(device_t, device_t, void *); 146 147 CFATTACH_DECL_NEW(clock, sizeof(struct mk48txx_softc), 148 clock_match, clock_attach, NULL, NULL); 149 150 #ifdef SUN3_470 151 152 #define intersil_clock ((volatile struct intersil7170 *)intersil_va) 153 154 #define intersil_clear() (void)intersil_clock->clk_intr_reg 155 156 static int oclock_match(device_t, cfdata_t, void *); 157 static void oclock_attach(device_t, device_t, void *); 158 159 CFATTACH_DECL_NEW(oclock, sizeof(struct intersil7170_softc), 160 oclock_match, oclock_attach, NULL, NULL); 161 162 163 /* 164 * Is there an intersil clock? 165 */ 166 static int 167 oclock_match(device_t parent, cfdata_t cf, void *aux) 168 { 169 struct confargs *ca = aux; 170 171 /* This driver only supports one unit. */ 172 if (intersil_va) 173 return 0; 174 175 /* 176 * The 3/80 can not probe the Intersil absent, 177 * but it never has one, so "just say no." 178 */ 179 if (cpu_machine_id == ID_SUN3X_80) 180 return 0; 181 182 /* OK, really probe for the Intersil. */ 183 if (bus_peek(ca->ca_bustype, ca->ca_paddr, 1) == -1) 184 return 0; 185 186 /* Default interrupt priority. */ 187 if (ca->ca_intpri == -1) 188 ca->ca_intpri = CLOCK_PRI; 189 190 return 1; 191 } 192 193 /* 194 * Attach the intersil clock. 195 */ 196 static void 197 oclock_attach(device_t parent, device_t self, void *aux) 198 { 199 struct intersil7170_softc *sc = device_private(self); 200 struct confargs *ca = aux; 201 202 sc->sc_dev = self; 203 204 /* Get a mapping for it. */ 205 sc->sc_bst = ca->ca_bustag; 206 if (bus_space_map(sc->sc_bst, ca->ca_paddr, sizeof(struct intersil7170), 207 0, &sc->sc_bsh) != 0) { 208 aprint_error(": can't map registers\n"); 209 return; 210 } 211 212 intersil_va = bus_space_vaddr(sc->sc_bst, sc->sc_bsh); 213 214 #ifdef DIAGNOSTIC 215 /* Verify correct probe order... */ 216 if (mostek_clk_va) { 217 mostek_clk_va = NULL; 218 aprint_normal("\n"); 219 aprint_error_dev(self, "warning - mostek found also!\n"); 220 } 221 #endif 222 223 /* 224 * Set the clock to the correct interrupt rate, but 225 * do not enable the interrupt until cpu_initclocks. 226 * XXX: Actually, the interrupt_reg should be zero 227 * at this point, so the clock interrupts should not 228 * affect us, but we need to set the rate... 229 */ 230 bus_space_write_1(sc->sc_bst, sc->sc_bsh, INTERSIL_ICMD, 231 INTERSIL_COMMAND(INTERSIL_CMD_RUN, INTERSIL_CMD_IDISABLE)); 232 (void)bus_space_read_1(sc->sc_bst, sc->sc_bsh, INTERSIL_IINTR); 233 234 /* Set the clock to 100 Hz, but do not enable it yet. */ 235 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 236 INTERSIL_IINTR, INTERSIL_INTER_CSECONDS); 237 238 sc->sc_year0 = 1968; 239 intersil7170_attach(sc); 240 241 aprint_normal("\n"); 242 243 /* 244 * Can not hook up the ISR until cpu_initclocks() 245 * because hardclock is not ready until then. 246 * For now, the handler is _isr_autovec(), which 247 * will complain if it gets clock interrupts. 248 */ 249 } 250 #endif /* SUN3_470 */ 251 252 253 /* 254 * Is there a Mostek clock? Hard to tell... 255 * (See comment at top of this file.) 256 */ 257 static int 258 clock_match(device_t parent, cfdata_t cf, void *args) 259 { 260 struct confargs *ca = args; 261 262 /* This driver only supports one unit. */ 263 if (mostek_clk_va) 264 return 0; 265 266 /* If intersil was found, use that. */ 267 if (intersil_va) 268 return 0; 269 /* Else assume a Mostek is there... */ 270 271 /* Default interrupt priority. */ 272 if (ca->ca_intpri == -1) 273 ca->ca_intpri = CLOCK_PRI; 274 275 return 1; 276 } 277 278 /* 279 * Attach the mostek clock. 280 */ 281 static void 282 clock_attach(device_t parent, device_t self, void *aux) 283 { 284 struct mk48txx_softc *sc = device_private(self); 285 struct confargs *ca = aux; 286 287 sc->sc_dev = self; 288 sc->sc_bst = ca->ca_bustag; 289 if (bus_space_map(sc->sc_bst, ca->ca_paddr - MKCLOCK_REG_OFFSET, 290 MK48T02_CLKSZ, 0, &sc->sc_bsh) != 0) { 291 aprint_error(": can't map device space\n"); 292 return; 293 } 294 295 mostek_clk_va = bus_space_vaddr(sc->sc_bst, sc->sc_bsh); 296 297 sc->sc_model = "mk48t02"; 298 sc->sc_year0 = 1968; 299 300 mk48txx_attach(sc); 301 302 aprint_normal("\n"); 303 } 304 305 /* 306 * Set and/or clear the desired clock bits in the interrupt 307 * register. We have to be extremely careful that we do it 308 * in such a manner that we don't get ourselves lost. 309 * XXX: Watch out! It's really easy to break this! 310 */ 311 void 312 set_clk_mode(u_char on, u_char off, int enable_clk) 313 { 314 u_char interreg; 315 316 /* 317 * If we have not yet mapped the register, 318 * then we do not want to do any of this... 319 */ 320 if (!interrupt_reg) 321 return; 322 323 #ifdef DIAGNOSTIC 324 /* Assertion: were are at splhigh! */ 325 if ((getsr() & PSL_IPL) < PSL_IPL7) 326 panic("set_clk_mode: bad ipl"); 327 #endif 328 329 /* 330 * make sure that we are only playing w/ 331 * clock interrupt register bits 332 */ 333 on &= IREG_CLK_BITS; 334 off &= IREG_CLK_BITS; 335 336 /* First, turn off the "master" enable bit. */ 337 single_inst_bclr_b(*interrupt_reg, IREG_ALL_ENAB); 338 339 /* 340 * Save the current interrupt register clock bits, 341 * and turn off/on the requested bits in the copy. 342 */ 343 interreg = *interrupt_reg & IREG_CLK_BITS; 344 interreg &= ~off; 345 interreg |= on; 346 347 /* Clear the CLK5 and CLK7 bits to clear the flip-flops. */ 348 single_inst_bclr_b(*interrupt_reg, IREG_CLK_BITS); 349 350 #ifdef SUN3_470 351 if (intersil_va) { 352 /* 353 * Then disable clock interrupts, and read the clock's 354 * interrupt register to clear any pending signals there. 355 */ 356 intersil_clock->clk_cmd_reg = 357 INTERSIL_COMMAND(INTERSIL_CMD_RUN, INTERSIL_CMD_IDISABLE); 358 intersil_clear(); 359 } 360 #endif /* SUN3_470 */ 361 362 /* Set the requested bits in the interrupt register. */ 363 single_inst_bset_b(*interrupt_reg, interreg); 364 365 #ifdef SUN3_470 366 /* Turn the clock back on (maybe) */ 367 if (intersil_va && enable_clk) 368 intersil_clock->clk_cmd_reg = 369 INTERSIL_COMMAND(INTERSIL_CMD_RUN, INTERSIL_CMD_IENABLE); 370 #endif /* SUN3_470 */ 371 372 /* Finally, turn the "master" enable back on. */ 373 single_inst_bset_b(*interrupt_reg, IREG_ALL_ENAB); 374 } 375 376 /* 377 * Set up the real-time clock (enable clock interrupts). 378 * Leave stathz 0 since there is no secondary clock available. 379 * Note that clock interrupts MUST STAY DISABLED until here. 380 */ 381 void 382 cpu_initclocks(void) 383 { 384 int s; 385 386 s = splhigh(); 387 388 /* Install isr (in locore.s) that calls clock_intr(). */ 389 vec_set_entry(VECI_INTRAV0 + CLOCK_PRI, (void *)_isr_clock); 390 391 /* Now enable the clock at level 5 in the interrupt reg. */ 392 set_clk_mode(IREG_CLOCK_ENAB_5, 0, 1); 393 394 splx(s); 395 } 396 397 /* 398 * This doesn't need to do anything, as we have only one timer and 399 * profhz==stathz==hz. 400 */ 401 void 402 setstatclockrate(int newhz) 403 { 404 405 /* nothing */ 406 } 407 408 /* 409 * Clock interrupt handler (for both Intersil and Mostek). 410 * XXX - Is it worth the trouble to save a few cycles here 411 * by making two separate interrupt handlers? 412 * 413 * This is called by the "custom" interrupt handler. 414 * Note that we can get ZS interrupts while this runs, 415 * and zshard may touch the interrupt_reg, so we must 416 * be careful to use the single_inst_* macros to modify 417 * the interrupt register atomically. 418 */ 419 void 420 clock_intr(struct clockframe cf) 421 { 422 extern char _Idle[]; /* locore.s */ 423 424 intr_depth++; 425 426 #ifdef SUN3_470 427 if (intersil_va) { 428 /* Read the clock interrupt register. */ 429 intersil_clear(); 430 } 431 #endif /* SUN3_470 */ 432 433 /* Pulse the clock intr. enable low. */ 434 single_inst_bclr_b(*interrupt_reg, IREG_CLOCK_ENAB_5); 435 single_inst_bset_b(*interrupt_reg, IREG_CLOCK_ENAB_5); 436 437 #ifdef SUN3_470 438 if (intersil_va) { 439 /* Read the clock intr. reg. AGAIN! */ 440 intersil_clear(); 441 } 442 #endif /* SUN3_470 */ 443 444 m68k_count_intr(CLOCK_PRI); 445 446 /* Entertainment! */ 447 if (cf.cf_pc == (long)_Idle) 448 leds_intr(); 449 450 /* Call common clock interrupt handler. */ 451 hardclock(&cf); 452 453 intr_depth--; 454 } 455
Indexes created Sat Sep 20 22:09:52 GMT 2025