clock.c revision 1.26
1 /* $NetBSD: clock.c,v 1.26 2003/09/22 17:21:51 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 1982, 1990, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * the Systems Programming Group of the University of Utah Computer 9 * Science Department. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * from: Utah Hdr: clock.c 1.18 91/01/21$ 36 * from: @(#)clock.c 8.2 (Berkeley) 1/12/94 37 */ 38 39 /* 40 * Copyright (c) 1994 Gordon W. Ross 41 * Copyright (c) 1993 Adam Glass 42 * Copyright (c) 1988 University of Utah. 43 * 44 * This code is derived from software contributed to Berkeley by 45 * the Systems Programming Group of the University of Utah Computer 46 * Science Department. 47 * 48 * Redistribution and use in source and binary forms, with or without 49 * modification, are permitted provided that the following conditions 50 * are met: 51 * 1. Redistributions of source code must retain the above copyright 52 * notice, this list of conditions and the following disclaimer. 53 * 2. Redistributions in binary form must reproduce the above copyright 54 * notice, this list of conditions and the following disclaimer in the 55 * documentation and/or other materials provided with the distribution. 56 * 3. All advertising materials mentioning features or use of this software 57 * must display the following acknowledgement: 58 * This product includes software developed by the University of 59 * California, Berkeley and its contributors. 60 * 4. Neither the name of the University nor the names of its contributors 61 * may be used to endorse or promote products derived from this software 62 * without specific prior written permission. 63 * 64 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 67 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 74 * SUCH DAMAGE. 75 * 76 * from: Utah Hdr: clock.c 1.18 91/01/21$ 77 * from: @(#)clock.c 8.2 (Berkeley) 1/12/94 78 */ 79 80 /* 81 * Machine-dependent clock routines. Sun3X machines may have 82 * either the Mostek 48T02 or the Intersil 7170 clock. 83 * 84 * It is tricky to determine which you have, because there is 85 * always something responding at the address where the Mostek 86 * clock might be found: either a Mostek or plain-old EEPROM. 87 * Therefore, we cheat. If we find an Intersil clock, assume 88 * that what responds at the end of the EEPROM space is just 89 * plain-old EEPROM (not a Mostek clock). Worse, there are 90 * H/W problems with probing for an Intersil on the 3/80, so 91 * on that machine we "know" there is a Mostek clock. 92 * 93 * Note that the probing algorithm described above requires 94 * that we probe the intersil before we probe the mostek! 95 */ 96 97 #include <sys/cdefs.h> 98 __KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.26 2003/09/22 17:21:51 tsutsui Exp $"); 99 100 #include <sys/param.h> 101 #include <sys/systm.h> 102 #include <sys/time.h> 103 #include <sys/kernel.h> 104 #include <sys/device.h> 105 106 #include <m68k/asm_single.h> 107 108 #include <machine/autoconf.h> 109 #include <machine/cpu.h> 110 #include <machine/idprom.h> 111 #include <machine/leds.h> 112 113 #include <dev/clock_subr.h> 114 #include <dev/ic/intersil7170.h> 115 116 #include <sun3/sun3/machdep.h> 117 #include <sun3/sun3/interreg.h> 118 119 #include <sun3/sun3x/mk48t02.h> 120 121 #define SUN3_470 Yes 122 123 #define CLOCK_PRI 5 124 #define IREG_CLK_BITS (IREG_CLOCK_ENAB_7 | IREG_CLOCK_ENAB_5) 125 126 /* 127 * Only one of these two variables should be non-zero after 128 * autoconfiguration determines which clock we have. 129 */ 130 static volatile void *intersil_va; 131 static volatile void *mostek_clk_va; 132 133 void _isr_clock __P((void)); /* in locore.s */ 134 void clock_intr __P((struct clockframe)); 135 136 137 static int clock_match __P((struct device *, struct cfdata *, void *args)); 138 static void clock_attach __P((struct device *, struct device *, void *)); 139 140 CFATTACH_DECL(clock, sizeof(struct device), 141 clock_match, clock_attach, NULL, NULL); 142 143 #ifdef SUN3_470 144 145 #define intersil_clock ((volatile struct intersil7170 *) intersil_va) 146 147 #define intersil_command(run, interrupt) \ 148 (run | interrupt | INTERSIL_CMD_FREQ_32K | INTERSIL_CMD_24HR_MODE | \ 149 INTERSIL_CMD_NORMAL_MODE) 150 151 #define intersil_clear() (void)intersil_clock->clk_intr_reg 152 153 static int oclock_match __P((struct device *, struct cfdata *, void *args)); 154 static void oclock_attach __P((struct device *, struct device *, void *)); 155 156 CFATTACH_DECL(oclock, sizeof(struct device), 157 oclock_match, oclock_attach, NULL, NULL); 158 159 /* 160 * Is there an intersil clock? 161 */ 162 static int 163 oclock_match(parent, cf, args) 164 struct device *parent; 165 struct cfdata *cf; 166 void *args; 167 { 168 struct confargs *ca = args; 169 170 /* This driver only supports one unit. */ 171 if (intersil_va) 172 return (0); 173 174 /* 175 * The 3/80 can not probe the Intersil absent, 176 * but it never has one, so "just say no." 177 */ 178 if (cpu_machine_id == SUN3X_MACH_80) 179 return (0); 180 181 /* OK, really probe for the Intersil. */ 182 if (bus_peek(ca->ca_bustype, ca->ca_paddr, 1) == -1) 183 return (0); 184 185 /* Default interrupt priority. */ 186 if (ca->ca_intpri == -1) 187 ca->ca_intpri = CLOCK_PRI; 188 189 return (1); 190 } 191 192 /* 193 * Attach the intersil clock. 194 */ 195 static void 196 oclock_attach(parent, self, args) 197 struct device *parent; 198 struct device *self; 199 void *args; 200 { 201 struct confargs *ca = args; 202 caddr_t va; 203 204 printf("\n"); 205 206 /* Get a mapping for it. */ 207 va = bus_mapin(ca->ca_bustype, 208 ca->ca_paddr, sizeof(struct intersil7170)); 209 if (!va) 210 panic("oclock_attach"); 211 intersil_va = va; 212 213 #ifdef DIAGNOSTIC 214 /* Verify correct probe order... */ 215 if (mostek_clk_va) { 216 mostek_clk_va = 0; 217 printf("%s: warning - mostek found also!\n", self->dv_xname); 218 } 219 #endif 220 221 /* 222 * Set the clock to the correct interrupt rate, but 223 * do not enable the interrupt until cpu_initclocks. 224 * XXX: Actually, the interrupt_reg should be zero 225 * at this point, so the clock interrupts should not 226 * affect us, but we need to set the rate... 227 */ 228 intersil_clock->clk_cmd_reg = 229 intersil_command(INTERSIL_CMD_RUN, INTERSIL_CMD_IDISABLE); 230 intersil_clear(); 231 232 /* Set the clock to 100 Hz, but do not enable it yet. */ 233 intersil_clock->clk_intr_reg = INTERSIL_INTER_CSECONDS; 234 235 /* 236 * Can not hook up the ISR until cpu_initclocks() 237 * because hardclock is not ready until then. 238 * For now, the handler is _isr_autovec(), which 239 * will complain if it gets clock interrupts. 240 */ 241 } 242 #endif /* SUN3_470 */ 243 244 245 /* 246 * Is there a Mostek clock? Hard to tell... 247 * (See comment at top of this file.) 248 */ 249 static int 250 clock_match(parent, cf, args) 251 struct device *parent; 252 struct cfdata *cf; 253 void *args; 254 { 255 struct confargs *ca = args; 256 257 /* This driver only supports one unit. */ 258 if (mostek_clk_va) 259 return (0); 260 261 /* If intersil was found, use that. */ 262 if (intersil_va) 263 return (0); 264 /* Else assume a Mostek is there... */ 265 266 /* Default interrupt priority. */ 267 if (ca->ca_intpri == -1) 268 ca->ca_intpri = CLOCK_PRI; 269 270 return (1); 271 } 272 273 /* 274 * Attach the mostek clock. 275 */ 276 static void 277 clock_attach(parent, self, args) 278 struct device *parent; 279 struct device *self; 280 void *args; 281 { 282 struct confargs *ca = args; 283 caddr_t va; 284 285 printf("\n"); 286 287 /* Get a mapping for it. */ 288 va = bus_mapin(ca->ca_bustype, 289 ca->ca_paddr, sizeof(struct mostek_clkreg)); 290 if (!va) 291 panic("clock_attach"); 292 mostek_clk_va = va; 293 294 /* 295 * Can not hook up the ISR until cpu_initclocks() 296 * because hardclock is not ready until then. 297 * For now, the handler is _isr_autovec(), which 298 * will complain if it gets clock interrupts. 299 */ 300 } 301 302 /* 303 * Set and/or clear the desired clock bits in the interrupt 304 * register. We have to be extremely careful that we do it 305 * in such a manner that we don't get ourselves lost. 306 * XXX: Watch out! It's really easy to break this! 307 */ 308 void 309 set_clk_mode(on, off, enable_clk) 310 u_char on, off; 311 int enable_clk; 312 { 313 u_char interreg; 314 315 /* 316 * If we have not yet mapped the register, 317 * then we do not want to do any of this... 318 */ 319 if (!interrupt_reg) 320 return; 321 322 #ifdef DIAGNOSTIC 323 /* Assertion: were are at splhigh! */ 324 if ((getsr() & PSL_IPL) < PSL_IPL7) 325 panic("set_clk_mode: bad ipl"); 326 #endif 327 328 /* 329 * make sure that we are only playing w/ 330 * clock interrupt register bits 331 */ 332 on &= IREG_CLK_BITS; 333 off &= IREG_CLK_BITS; 334 335 /* First, turn off the "master" enable bit. */ 336 single_inst_bclr_b(*interrupt_reg, IREG_ALL_ENAB); 337 338 /* 339 * Save the current interrupt register clock bits, 340 * and turn off/on the requested bits in the copy. 341 */ 342 interreg = *interrupt_reg & IREG_CLK_BITS; 343 interreg &= ~off; 344 interreg |= on; 345 346 /* Clear the CLK5 and CLK7 bits to clear the flip-flops. */ 347 single_inst_bclr_b(*interrupt_reg, IREG_CLK_BITS); 348 349 #ifdef SUN3_470 350 if (intersil_va) { 351 /* 352 * Then disable clock interrupts, and read the clock's 353 * interrupt register to clear any pending signals there. 354 */ 355 intersil_clock->clk_cmd_reg = 356 intersil_command(INTERSIL_CMD_RUN, INTERSIL_CMD_IDISABLE); 357 intersil_clear(); 358 } 359 #endif /* SUN3_470 */ 360 361 /* Set the requested bits in the interrupt register. */ 362 single_inst_bset_b(*interrupt_reg, interreg); 363 364 #ifdef SUN3_470 365 /* Turn the clock back on (maybe) */ 366 if (intersil_va && enable_clk) 367 intersil_clock->clk_cmd_reg = 368 intersil_command(INTERSIL_CMD_RUN, INTERSIL_CMD_IENABLE); 369 #endif /* SUN3_470 */ 370 371 /* Finally, turn the "master" enable back on. */ 372 single_inst_bset_b(*interrupt_reg, IREG_ALL_ENAB); 373 } 374 375 /* 376 * Set up the real-time clock (enable clock interrupts). 377 * Leave stathz 0 since there is no secondary clock available. 378 * Note that clock interrupts MUST STAY DISABLED until here. 379 */ 380 void 381 cpu_initclocks(void) 382 { 383 int s; 384 385 s = splhigh(); 386 387 /* Install isr (in locore.s) that calls clock_intr(). */ 388 isr_add_custom(CLOCK_PRI, (void *)_isr_clock); 389 390 /* Now enable the clock at level 5 in the interrupt reg. */ 391 set_clk_mode(IREG_CLOCK_ENAB_5, 0, 1); 392 393 splx(s); 394 } 395 396 /* 397 * This doesn't need to do anything, as we have only one timer and 398 * profhz==stathz==hz. 399 */ 400 void 401 setstatclockrate(newhz) 402 int newhz; 403 { 404 405 /* nothing */ 406 } 407 408 /* 409 * Clock interrupt handler (for both Intersil and Mostek). 410 * XXX - Is it worth the trouble to save a few cycles here 411 * by making two separate interrupt handlers? 412 * 413 * This is is called by the "custom" interrupt handler. 414 * Note that we can get ZS interrupts while this runs, 415 * and zshard may touch the interrupt_reg, so we must 416 * be careful to use the single_inst_* macros to modify 417 * the interrupt register atomically. 418 */ 419 void 420 clock_intr(cf) 421 struct clockframe cf; 422 { 423 extern char _Idle[]; /* locore.s */ 424 425 #ifdef SUN3_470 426 if (intersil_va) { 427 /* Read the clock interrupt register. */ 428 intersil_clear(); 429 } 430 #endif /* SUN3_470 */ 431 432 /* Pulse the clock intr. enable low. */ 433 single_inst_bclr_b(*interrupt_reg, IREG_CLOCK_ENAB_5); 434 single_inst_bset_b(*interrupt_reg, IREG_CLOCK_ENAB_5); 435 436 #ifdef SUN3_470 437 if (intersil_va) { 438 /* Read the clock intr. reg. AGAIN! */ 439 intersil_clear(); 440 } 441 #endif /* SUN3_470 */ 442 443 /* Entertainment! */ 444 if (cf.cf_pc == (long)_Idle) 445 leds_intr(); 446 447 /* Call common clock interrupt handler. */ 448 hardclock(&cf); 449 } 450 451 452 /* 453 * Return the best possible estimate of the time in the timeval 454 * to which tvp points. We do this by returning the current time 455 * plus the amount of time since the last clock interrupt. 456 * 457 * Check that this time is no less than any previously-reported time, 458 * which could happen around the time of a clock adjustment. Just for 459 * fun, we guarantee that the time will be greater than the value 460 * obtained by a previous call. 461 */ 462 void 463 microtime(tvp) 464 struct timeval *tvp; 465 { 466 int s; 467 static struct timeval lasttime; 468 469 s = splhigh(); 470 *tvp = time; 471 tvp->tv_usec++; /* XXX */ 472 while (tvp->tv_usec >= 1000000) { 473 tvp->tv_sec++; 474 tvp->tv_usec -= 1000000; 475 } 476 if (tvp->tv_sec == lasttime.tv_sec && 477 tvp->tv_usec <= lasttime.tv_usec && 478 (tvp->tv_usec = lasttime.tv_usec + 1) >= 1000000) { 479 tvp->tv_sec++; 480 tvp->tv_usec -= 1000000; 481 } 482 lasttime = *tvp; 483 splx(s); 484 } 485 486 487 /* 488 * Machine-dependent clock routines. 489 * 490 * Inittodr initializes the time of day hardware which provides 491 * date functions. 492 * 493 * Resettodr restores the time of day hardware after a time change. 494 */ 495 496 static long clk_get_secs __P((void)); 497 static void clk_set_secs __P((long)); 498 499 /* 500 * Initialize the time of day register, based on the time base 501 * which is, e.g. from a filesystem. 502 */ 503 void inittodr(fs_time) 504 time_t fs_time; 505 { 506 long diff, clk_time; 507 long long_ago = (5 * SECYR); 508 int clk_bad = 0; 509 510 /* 511 * Sanity check time from file system. 512 * If it is zero,assume filesystem time is just unknown 513 * instead of preposterous. Don't bark. 514 */ 515 if (fs_time < long_ago) { 516 /* 517 * If fs_time is zero, assume filesystem time is just 518 * unknown instead of preposterous. Don't bark. 519 */ 520 if (fs_time != 0) 521 printf("WARNING: preposterous time in file system\n"); 522 /* 1991/07/01 12:00:00 */ 523 fs_time = 21 * SECYR + 186 * SECDAY + SECDAY / 2; 524 } 525 526 clk_time = clk_get_secs(); 527 528 /* Sanity check time from clock. */ 529 if (clk_time < long_ago) { 530 printf("WARNING: bad date in battery clock"); 531 clk_bad = 1; 532 clk_time = fs_time; 533 } else { 534 /* Does the clock time jive with the file system? */ 535 diff = clk_time - fs_time; 536 if (diff < 0) 537 diff = -diff; 538 if (diff >= (SECDAY*2)) { 539 printf("WARNING: clock %s %d days", 540 (clk_time < fs_time) ? "lost" : "gained", 541 (int) (diff / SECDAY)); 542 clk_bad = 1; 543 } 544 } 545 if (clk_bad) 546 printf(" -- CHECK AND RESET THE DATE!\n"); 547 time.tv_sec = clk_time; 548 } 549 550 /* 551 * Resettodr restores the time of day hardware after a time change. 552 */ 553 void resettodr() 554 { 555 556 clk_set_secs(time.tv_sec); 557 } 558 559 560 /* 561 * Now routines to get and set clock as POSIX time. 562 * Our clock keeps "years since 1/1/1968". 563 */ 564 #define CLOCK_BASE_YEAR 1968 565 #ifdef SUN3_470 566 static void intersil_get_dt __P((struct clock_ymdhms *)); 567 static void intersil_set_dt __P((struct clock_ymdhms *)); 568 #endif /* SUN3_470 */ 569 static void mostek_get_dt __P((struct clock_ymdhms *)); 570 static void mostek_set_dt __P((struct clock_ymdhms *)); 571 572 static long 573 clk_get_secs() 574 { 575 struct clock_ymdhms dt; 576 long secs; 577 578 memset(&dt, 0, sizeof(dt)); 579 580 #ifdef SUN3_470 581 if (intersil_va) 582 intersil_get_dt(&dt); 583 #endif /* SUN3_470 */ 584 if (mostek_clk_va) { 585 /* Read the Mostek. */ 586 mostek_get_dt(&dt); 587 /* Convert BCD values to binary. */ 588 dt.dt_sec = FROMBCD(dt.dt_sec); 589 dt.dt_min = FROMBCD(dt.dt_min); 590 dt.dt_hour = FROMBCD(dt.dt_hour); 591 dt.dt_day = FROMBCD(dt.dt_day); 592 dt.dt_mon = FROMBCD(dt.dt_mon); 593 dt.dt_year = FROMBCD(dt.dt_year); 594 } 595 596 if ((dt.dt_hour > 24) || 597 (dt.dt_day > 31) || 598 (dt.dt_mon > 12)) 599 return (0); 600 601 dt.dt_year += CLOCK_BASE_YEAR; 602 secs = clock_ymdhms_to_secs(&dt); 603 return (secs); 604 } 605 606 static void 607 clk_set_secs(secs) 608 long secs; 609 { 610 struct clock_ymdhms dt; 611 612 clock_secs_to_ymdhms(secs, &dt); 613 dt.dt_year -= CLOCK_BASE_YEAR; 614 615 #ifdef SUN3_470 616 if (intersil_va) 617 intersil_set_dt(&dt); 618 #endif /* SUN3_470 */ 619 620 if (mostek_clk_va) { 621 /* Convert binary values to BCD. */ 622 dt.dt_sec = TOBCD(dt.dt_sec); 623 dt.dt_min = TOBCD(dt.dt_min); 624 dt.dt_hour = TOBCD(dt.dt_hour); 625 dt.dt_day = TOBCD(dt.dt_day); 626 dt.dt_mon = TOBCD(dt.dt_mon); 627 dt.dt_year = TOBCD(dt.dt_year); 628 /* Write the Mostek. */ 629 mostek_set_dt(&dt); 630 } 631 } 632 633 #ifdef SUN3_470 634 635 /* 636 * Routines to copy state into and out of the clock. 637 * The intersil registers have to be read or written 638 * in sequential order (or so it appears). -gwr 639 */ 640 static void 641 intersil_get_dt(struct clock_ymdhms *dt) 642 { 643 volatile struct intersil_dt *isdt; 644 int s; 645 646 isdt = &intersil_clock->counters; 647 s = splhigh(); 648 649 /* Enable read (stop time) */ 650 intersil_clock->clk_cmd_reg = 651 intersil_command(INTERSIL_CMD_STOP, INTERSIL_CMD_IENABLE); 652 653 /* Copy the info. Careful about the order! */ 654 dt->dt_sec = isdt->dt_csec; /* throw-away */ 655 dt->dt_hour = isdt->dt_hour; 656 dt->dt_min = isdt->dt_min; 657 dt->dt_sec = isdt->dt_sec; 658 dt->dt_mon = isdt->dt_month; 659 dt->dt_day = isdt->dt_day; 660 dt->dt_year = isdt->dt_year; 661 dt->dt_wday = isdt->dt_dow; 662 663 /* Done reading (time wears on) */ 664 intersil_clock->clk_cmd_reg = 665 intersil_command(INTERSIL_CMD_RUN, INTERSIL_CMD_IENABLE); 666 splx(s); 667 } 668 669 static void 670 intersil_set_dt(struct clock_ymdhms *dt) 671 { 672 volatile struct intersil_dt *isdt; 673 int s; 674 675 isdt = &intersil_clock->counters; 676 s = splhigh(); 677 678 /* Enable write (stop time) */ 679 intersil_clock->clk_cmd_reg = 680 intersil_command(INTERSIL_CMD_STOP, INTERSIL_CMD_IENABLE); 681 682 /* Copy the info. Careful about the order! */ 683 isdt->dt_csec = 0; 684 isdt->dt_hour = dt->dt_hour; 685 isdt->dt_min = dt->dt_min; 686 isdt->dt_sec = dt->dt_sec; 687 isdt->dt_month= dt->dt_mon; 688 isdt->dt_day = dt->dt_day; 689 isdt->dt_year = dt->dt_year; 690 isdt->dt_dow = dt->dt_wday; 691 692 /* Done writing (time wears on) */ 693 intersil_clock->clk_cmd_reg = 694 intersil_command(INTERSIL_CMD_RUN, INTERSIL_CMD_IENABLE); 695 splx(s); 696 } 697 698 #endif /* SUN3_470 */ 699 700 701 /* 702 * Routines to copy state into and out of the clock. 703 * The clock CSR has to be set for read or write. 704 */ 705 static void 706 mostek_get_dt(struct clock_ymdhms *dt) 707 { 708 volatile struct mostek_clkreg *cl = mostek_clk_va; 709 int s; 710 711 s = splhigh(); 712 713 /* enable read (stop time) */ 714 cl->cl_csr |= CLK_READ; 715 716 /* Copy the info */ 717 dt->dt_sec = cl->cl_sec; 718 dt->dt_min = cl->cl_min; 719 dt->dt_hour = cl->cl_hour; 720 dt->dt_wday = cl->cl_wday; 721 dt->dt_day = cl->cl_mday; 722 dt->dt_mon = cl->cl_month; 723 dt->dt_year = cl->cl_year; 724 725 /* Done reading (time wears on) */ 726 cl->cl_csr &= ~CLK_READ; 727 splx(s); 728 } 729 730 static void 731 mostek_set_dt(struct clock_ymdhms *dt) 732 { 733 volatile struct mostek_clkreg *cl = mostek_clk_va; 734 int s; 735 736 s = splhigh(); 737 /* enable write */ 738 cl->cl_csr |= CLK_WRITE; 739 740 /* Copy the info */ 741 cl->cl_sec = dt->dt_sec; 742 cl->cl_min = dt->dt_min; 743 cl->cl_hour = dt->dt_hour; 744 cl->cl_wday = dt->dt_wday; 745 cl->cl_mday = dt->dt_day; 746 cl->cl_month = dt->dt_mon; 747 cl->cl_year = dt->dt_year; 748 749 /* load them up */ 750 cl->cl_csr &= ~CLK_WRITE; 751 splx(s); 752 } 753 754
Indexes created Thu Sep 25 16:09:42 GMT 2025