clock.c revision 1.31
1 /* $NetBSD: clock.c,v 1.31 2006/09/05 06:45:05 gdamore Exp $ */ 2 3 /* 4 * Copyright (c) 1982, 1990, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * the Systems Programming Group of the University of Utah Computer 9 * Science Department. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * from: Utah Hdr: clock.c 1.18 91/01/21$ 36 * from: @(#)clock.c 8.2 (Berkeley) 1/12/94 37 */ 38 39 /* 40 * Copyright (c) 1994 Gordon W. Ross 41 * Copyright (c) 1993 Adam Glass 42 * Copyright (c) 1988 University of Utah. 43 * 44 * This code is derived from software contributed to Berkeley by 45 * the Systems Programming Group of the University of Utah Computer 46 * Science Department. 47 * 48 * Redistribution and use in source and binary forms, with or without 49 * modification, are permitted provided that the following conditions 50 * are met: 51 * 1. Redistributions of source code must retain the above copyright 52 * notice, this list of conditions and the following disclaimer. 53 * 2. Redistributions in binary form must reproduce the above copyright 54 * notice, this list of conditions and the following disclaimer in the 55 * documentation and/or other materials provided with the distribution. 56 * 3. All advertising materials mentioning features or use of this software 57 * must display the following acknowledgement: 58 * This product includes software developed by the University of 59 * California, Berkeley and its contributors. 60 * 4. Neither the name of the University nor the names of its contributors 61 * may be used to endorse or promote products derived from this software 62 * without specific prior written permission. 63 * 64 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 67 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 74 * SUCH DAMAGE. 75 * 76 * from: Utah Hdr: clock.c 1.18 91/01/21$ 77 * from: @(#)clock.c 8.2 (Berkeley) 1/12/94 78 */ 79 80 /* 81 * Machine-dependent clock routines. Sun3X machines may have 82 * either the Mostek 48T02 or the Intersil 7170 clock. 83 * 84 * It is tricky to determine which you have, because there is 85 * always something responding at the address where the Mostek 86 * clock might be found: either a Mostek or plain-old EEPROM. 87 * Therefore, we cheat. If we find an Intersil clock, assume 88 * that what responds at the end of the EEPROM space is just 89 * plain-old EEPROM (not a Mostek clock). Worse, there are 90 * H/W problems with probing for an Intersil on the 3/80, so 91 * on that machine we "know" there is a Mostek clock. 92 * 93 * Note that the probing algorithm described above requires 94 * that we probe the intersil before we probe the mostek! 95 */ 96 97 #include <sys/cdefs.h> 98 __KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.31 2006/09/05 06:45:05 gdamore Exp $"); 99 100 #include <sys/param.h> 101 #include <sys/systm.h> 102 #include <sys/time.h> 103 #include <sys/kernel.h> 104 #include <sys/device.h> 105 106 #include <uvm/uvm_extern.h> 107 108 #include <m68k/asm_single.h> 109 110 #include <machine/autoconf.h> 111 #include <machine/cpu.h> 112 #include <machine/idprom.h> 113 #include <machine/leds.h> 114 115 #include <dev/clock_subr.h> 116 #include <dev/ic/intersil7170.h> 117 118 #include <sun3/sun3/machdep.h> 119 #include <sun3/sun3/interreg.h> 120 121 #include <sun3/sun3x/mk48t02.h> 122 123 extern int intrcnt[]; 124 125 #define SUN3_470 Yes 126 127 #define CLOCK_PRI 5 128 #define IREG_CLK_BITS (IREG_CLOCK_ENAB_7 | IREG_CLOCK_ENAB_5) 129 130 /* 131 * Only one of these two variables should be non-zero after 132 * autoconfiguration determines which clock we have. 133 */ 134 static volatile void *intersil_va; 135 static volatile void *mostek_clk_va; 136 137 void _isr_clock(void); /* in locore.s */ 138 void clock_intr(struct clockframe); 139 140 141 static int clock_match(struct device *, struct cfdata *, void *); 142 static void clock_attach(struct device *, struct device *, void *); 143 144 CFATTACH_DECL(clock, sizeof(struct device), 145 clock_match, clock_attach, NULL, NULL); 146 147 #ifdef SUN3_470 148 149 #define intersil_clock ((volatile struct intersil7170 *) intersil_va) 150 151 #define intersil_command(run, interrupt) \ 152 (run | interrupt | INTERSIL_CMD_FREQ_32K | INTERSIL_CMD_24HR_MODE | \ 153 INTERSIL_CMD_NORMAL_MODE) 154 155 #define intersil_clear() (void)intersil_clock->clk_intr_reg 156 157 static int oclock_match(struct device *, struct cfdata *, void *); 158 static void oclock_attach(struct device *, struct device *, void *); 159 160 CFATTACH_DECL(oclock, sizeof(struct device), 161 oclock_match, oclock_attach, NULL, NULL); 162 163 static int clk_get_secs(todr_chip_handle_t, volatile struct timeval *); 164 static int clk_set_secs(todr_chip_handle_t, volatile struct timeval *); 165 static struct todr_chip_handle clk_hdl = { 166 .todr_gettime = clk_get_secs, 167 .todr_settime = clk_set_secs, 168 }; 169 170 /* 171 * Is there an intersil clock? 172 */ 173 static int 174 oclock_match(struct device *parent, struct cfdata *cf, void *args) 175 { 176 struct confargs *ca = args; 177 178 /* This driver only supports one unit. */ 179 if (intersil_va) 180 return (0); 181 182 /* 183 * The 3/80 can not probe the Intersil absent, 184 * but it never has one, so "just say no." 185 */ 186 if (cpu_machine_id == ID_SUN3X_80) 187 return (0); 188 189 /* OK, really probe for the Intersil. */ 190 if (bus_peek(ca->ca_bustype, ca->ca_paddr, 1) == -1) 191 return (0); 192 193 /* Default interrupt priority. */ 194 if (ca->ca_intpri == -1) 195 ca->ca_intpri = CLOCK_PRI; 196 197 return (1); 198 } 199 200 /* 201 * Attach the intersil clock. 202 */ 203 static void 204 oclock_attach(struct device *parent, struct device *self, void *args) 205 { 206 struct confargs *ca = args; 207 caddr_t va; 208 209 printf("\n"); 210 211 /* Get a mapping for it. */ 212 va = bus_mapin(ca->ca_bustype, 213 ca->ca_paddr, sizeof(struct intersil7170)); 214 if (!va) 215 panic("oclock_attach"); 216 intersil_va = va; 217 218 #ifdef DIAGNOSTIC 219 /* Verify correct probe order... */ 220 if (mostek_clk_va) { 221 mostek_clk_va = 0; 222 printf("%s: warning - mostek found also!\n", self->dv_xname); 223 } 224 #endif 225 226 /* 227 * Set the clock to the correct interrupt rate, but 228 * do not enable the interrupt until cpu_initclocks. 229 * XXX: Actually, the interrupt_reg should be zero 230 * at this point, so the clock interrupts should not 231 * affect us, but we need to set the rate... 232 */ 233 intersil_clock->clk_cmd_reg = 234 intersil_command(INTERSIL_CMD_RUN, INTERSIL_CMD_IDISABLE); 235 intersil_clear(); 236 237 /* Set the clock to 100 Hz, but do not enable it yet. */ 238 intersil_clock->clk_intr_reg = INTERSIL_INTER_CSECONDS; 239 240 /* 241 * Can not hook up the ISR until cpu_initclocks() 242 * because hardclock is not ready until then. 243 * For now, the handler is _isr_autovec(), which 244 * will complain if it gets clock interrupts. 245 */ 246 247 todr_attach(&clk_hdl); 248 } 249 #endif /* SUN3_470 */ 250 251 252 /* 253 * Is there a Mostek clock? Hard to tell... 254 * (See comment at top of this file.) 255 */ 256 static int 257 clock_match(struct device *parent, struct cfdata *cf, void *args) 258 { 259 struct confargs *ca = args; 260 261 /* This driver only supports one unit. */ 262 if (mostek_clk_va) 263 return (0); 264 265 /* If intersil was found, use that. */ 266 if (intersil_va) 267 return (0); 268 /* Else assume a Mostek is there... */ 269 270 /* Default interrupt priority. */ 271 if (ca->ca_intpri == -1) 272 ca->ca_intpri = CLOCK_PRI; 273 274 return (1); 275 } 276 277 /* 278 * Attach the mostek clock. 279 */ 280 static void 281 clock_attach(struct device *parent, struct device *self, void *args) 282 { 283 struct confargs *ca = args; 284 caddr_t va; 285 286 printf("\n"); 287 288 /* Get a mapping for it. */ 289 va = bus_mapin(ca->ca_bustype, 290 ca->ca_paddr, sizeof(struct mostek_clkreg)); 291 if (!va) 292 panic("clock_attach"); 293 mostek_clk_va = va; 294 295 /* 296 * Can not hook up the ISR until cpu_initclocks() 297 * because hardclock is not ready until then. 298 * For now, the handler is _isr_autovec(), which 299 * will complain if it gets clock interrupts. 300 */ 301 302 todr_attach(&clk_hdl); 303 } 304 305 /* 306 * Set and/or clear the desired clock bits in the interrupt 307 * register. We have to be extremely careful that we do it 308 * in such a manner that we don't get ourselves lost. 309 * XXX: Watch out! It's really easy to break this! 310 */ 311 void 312 set_clk_mode(u_char on, u_char off, int enable_clk) 313 { 314 u_char interreg; 315 316 /* 317 * If we have not yet mapped the register, 318 * then we do not want to do any of this... 319 */ 320 if (!interrupt_reg) 321 return; 322 323 #ifdef DIAGNOSTIC 324 /* Assertion: were are at splhigh! */ 325 if ((getsr() & PSL_IPL) < PSL_IPL7) 326 panic("set_clk_mode: bad ipl"); 327 #endif 328 329 /* 330 * make sure that we are only playing w/ 331 * clock interrupt register bits 332 */ 333 on &= IREG_CLK_BITS; 334 off &= IREG_CLK_BITS; 335 336 /* First, turn off the "master" enable bit. */ 337 single_inst_bclr_b(*interrupt_reg, IREG_ALL_ENAB); 338 339 /* 340 * Save the current interrupt register clock bits, 341 * and turn off/on the requested bits in the copy. 342 */ 343 interreg = *interrupt_reg & IREG_CLK_BITS; 344 interreg &= ~off; 345 interreg |= on; 346 347 /* Clear the CLK5 and CLK7 bits to clear the flip-flops. */ 348 single_inst_bclr_b(*interrupt_reg, IREG_CLK_BITS); 349 350 #ifdef SUN3_470 351 if (intersil_va) { 352 /* 353 * Then disable clock interrupts, and read the clock's 354 * interrupt register to clear any pending signals there. 355 */ 356 intersil_clock->clk_cmd_reg = 357 intersil_command(INTERSIL_CMD_RUN, INTERSIL_CMD_IDISABLE); 358 intersil_clear(); 359 } 360 #endif /* SUN3_470 */ 361 362 /* Set the requested bits in the interrupt register. */ 363 single_inst_bset_b(*interrupt_reg, interreg); 364 365 #ifdef SUN3_470 366 /* Turn the clock back on (maybe) */ 367 if (intersil_va && enable_clk) 368 intersil_clock->clk_cmd_reg = 369 intersil_command(INTERSIL_CMD_RUN, INTERSIL_CMD_IENABLE); 370 #endif /* SUN3_470 */ 371 372 /* Finally, turn the "master" enable back on. */ 373 single_inst_bset_b(*interrupt_reg, IREG_ALL_ENAB); 374 } 375 376 /* 377 * Set up the real-time clock (enable clock interrupts). 378 * Leave stathz 0 since there is no secondary clock available. 379 * Note that clock interrupts MUST STAY DISABLED until here. 380 */ 381 void 382 cpu_initclocks(void) 383 { 384 int s; 385 386 s = splhigh(); 387 388 /* Install isr (in locore.s) that calls clock_intr(). */ 389 isr_add_custom(CLOCK_PRI, (void *)_isr_clock); 390 391 /* Now enable the clock at level 5 in the interrupt reg. */ 392 set_clk_mode(IREG_CLOCK_ENAB_5, 0, 1); 393 394 splx(s); 395 } 396 397 /* 398 * This doesn't need to do anything, as we have only one timer and 399 * profhz==stathz==hz. 400 */ 401 void 402 setstatclockrate(int newhz) 403 { 404 405 /* nothing */ 406 } 407 408 /* 409 * Clock interrupt handler (for both Intersil and Mostek). 410 * XXX - Is it worth the trouble to save a few cycles here 411 * by making two separate interrupt handlers? 412 * 413 * This is is called by the "custom" interrupt handler. 414 * Note that we can get ZS interrupts while this runs, 415 * and zshard may touch the interrupt_reg, so we must 416 * be careful to use the single_inst_* macros to modify 417 * the interrupt register atomically. 418 */ 419 void 420 clock_intr(struct clockframe cf) 421 { 422 extern char _Idle[]; /* locore.s */ 423 424 #ifdef SUN3_470 425 if (intersil_va) { 426 /* Read the clock interrupt register. */ 427 intersil_clear(); 428 } 429 #endif /* SUN3_470 */ 430 431 /* Pulse the clock intr. enable low. */ 432 single_inst_bclr_b(*interrupt_reg, IREG_CLOCK_ENAB_5); 433 single_inst_bset_b(*interrupt_reg, IREG_CLOCK_ENAB_5); 434 435 #ifdef SUN3_470 436 if (intersil_va) { 437 /* Read the clock intr. reg. AGAIN! */ 438 intersil_clear(); 439 } 440 #endif /* SUN3_470 */ 441 442 intrcnt[CLOCK_PRI]++; 443 uvmexp.intrs++; 444 445 /* Entertainment! */ 446 if (cf.cf_pc == (long)_Idle) 447 leds_intr(); 448 449 /* Call common clock interrupt handler. */ 450 hardclock(&cf); 451 } 452 453 /* 454 * Machine-dependent clock routines. 455 * 456 * Inittodr initializes the time of day hardware which provides 457 * date functions. 458 * 459 * Resettodr restores the time of day hardware after a time change. 460 */ 461 462 463 /* 464 * Now routines to get and set clock as POSIX time. 465 * Our clock keeps "years since 1/1/1968". 466 */ 467 #define CLOCK_BASE_YEAR 1968 468 #ifdef SUN3_470 469 static void intersil_get_dt(struct clock_ymdhms *); 470 static void intersil_set_dt(struct clock_ymdhms *); 471 #endif /* SUN3_470 */ 472 static void mostek_get_dt(struct clock_ymdhms *); 473 static void mostek_set_dt(struct clock_ymdhms *); 474 475 static int 476 clk_get_secs(todr_chip_handle_t tch, volatile struct timeval *tvp) 477 { 478 struct clock_ymdhms dt; 479 480 memset(&dt, 0, sizeof(dt)); 481 482 #ifdef SUN3_470 483 if (intersil_va) 484 intersil_get_dt(&dt); 485 #endif /* SUN3_470 */ 486 if (mostek_clk_va) { 487 /* Read the Mostek. */ 488 mostek_get_dt(&dt); 489 /* Convert BCD values to binary. */ 490 dt.dt_sec = FROMBCD(dt.dt_sec); 491 dt.dt_min = FROMBCD(dt.dt_min); 492 dt.dt_hour = FROMBCD(dt.dt_hour); 493 dt.dt_day = FROMBCD(dt.dt_day); 494 dt.dt_mon = FROMBCD(dt.dt_mon); 495 dt.dt_year = FROMBCD(dt.dt_year); 496 } 497 498 if ((dt.dt_hour > 24) || 499 (dt.dt_day > 31) || 500 (dt.dt_mon > 12)) 501 return (-1); 502 503 dt.dt_year += CLOCK_BASE_YEAR; 504 tvp->tv_sec = clock_ymdhms_to_secs(&dt); 505 return 0; 506 } 507 508 static int 509 clk_set_secs(todr_chip_handle_t tch, volatile struct timeval *tvp) 510 { 511 struct clock_ymdhms dt; 512 513 clock_secs_to_ymdhms(tvp->tv_sec, &dt); 514 dt.dt_year -= CLOCK_BASE_YEAR; 515 516 #ifdef SUN3_470 517 if (intersil_va) 518 intersil_set_dt(&dt); 519 #endif /* SUN3_470 */ 520 521 if (mostek_clk_va) { 522 /* Convert binary values to BCD. */ 523 dt.dt_sec = TOBCD(dt.dt_sec); 524 dt.dt_min = TOBCD(dt.dt_min); 525 dt.dt_hour = TOBCD(dt.dt_hour); 526 dt.dt_day = TOBCD(dt.dt_day); 527 dt.dt_mon = TOBCD(dt.dt_mon); 528 dt.dt_year = TOBCD(dt.dt_year); 529 /* Write the Mostek. */ 530 mostek_set_dt(&dt); 531 } 532 return 0; 533 } 534 535 #ifdef SUN3_470 536 537 /* 538 * Routines to copy state into and out of the clock. 539 * The intersil registers have to be read or written 540 * in sequential order (or so it appears). -gwr 541 */ 542 static void 543 intersil_get_dt(struct clock_ymdhms *dt) 544 { 545 volatile struct intersil_dt *isdt; 546 int s; 547 548 isdt = &intersil_clock->counters; 549 s = splhigh(); 550 551 /* Enable read (stop time) */ 552 intersil_clock->clk_cmd_reg = 553 intersil_command(INTERSIL_CMD_STOP, INTERSIL_CMD_IENABLE); 554 555 /* Copy the info. Careful about the order! */ 556 dt->dt_sec = isdt->dt_csec; /* throw-away */ 557 dt->dt_hour = isdt->dt_hour; 558 dt->dt_min = isdt->dt_min; 559 dt->dt_sec = isdt->dt_sec; 560 dt->dt_mon = isdt->dt_month; 561 dt->dt_day = isdt->dt_day; 562 dt->dt_year = isdt->dt_year; 563 dt->dt_wday = isdt->dt_dow; 564 565 /* Done reading (time wears on) */ 566 intersil_clock->clk_cmd_reg = 567 intersil_command(INTERSIL_CMD_RUN, INTERSIL_CMD_IENABLE); 568 splx(s); 569 } 570 571 static void 572 intersil_set_dt(struct clock_ymdhms *dt) 573 { 574 volatile struct intersil_dt *isdt; 575 int s; 576 577 isdt = &intersil_clock->counters; 578 s = splhigh(); 579 580 /* Enable write (stop time) */ 581 intersil_clock->clk_cmd_reg = 582 intersil_command(INTERSIL_CMD_STOP, INTERSIL_CMD_IENABLE); 583 584 /* Copy the info. Careful about the order! */ 585 isdt->dt_csec = 0; 586 isdt->dt_hour = dt->dt_hour; 587 isdt->dt_min = dt->dt_min; 588 isdt->dt_sec = dt->dt_sec; 589 isdt->dt_month= dt->dt_mon; 590 isdt->dt_day = dt->dt_day; 591 isdt->dt_year = dt->dt_year; 592 isdt->dt_dow = dt->dt_wday; 593 594 /* Done writing (time wears on) */ 595 intersil_clock->clk_cmd_reg = 596 intersil_command(INTERSIL_CMD_RUN, INTERSIL_CMD_IENABLE); 597 splx(s); 598 } 599 600 #endif /* SUN3_470 */ 601 602 603 /* 604 * Routines to copy state into and out of the clock. 605 * The clock CSR has to be set for read or write. 606 */ 607 static void 608 mostek_get_dt(struct clock_ymdhms *dt) 609 { 610 volatile struct mostek_clkreg *cl = mostek_clk_va; 611 int s; 612 613 s = splhigh(); 614 615 /* enable read (stop time) */ 616 cl->cl_csr |= CLK_READ; 617 618 /* Copy the info */ 619 dt->dt_sec = cl->cl_sec; 620 dt->dt_min = cl->cl_min; 621 dt->dt_hour = cl->cl_hour; 622 dt->dt_wday = cl->cl_wday; 623 dt->dt_day = cl->cl_mday; 624 dt->dt_mon = cl->cl_month; 625 dt->dt_year = cl->cl_year; 626 627 /* Done reading (time wears on) */ 628 cl->cl_csr &= ~CLK_READ; 629 splx(s); 630 } 631 632 static void 633 mostek_set_dt(struct clock_ymdhms *dt) 634 { 635 volatile struct mostek_clkreg *cl = mostek_clk_va; 636 int s; 637 638 s = splhigh(); 639 /* enable write */ 640 cl->cl_csr |= CLK_WRITE; 641 642 /* Copy the info */ 643 cl->cl_sec = dt->dt_sec; 644 cl->cl_min = dt->dt_min; 645 cl->cl_hour = dt->dt_hour; 646 cl->cl_wday = dt->dt_wday; 647 cl->cl_mday = dt->dt_day; 648 cl->cl_month = dt->dt_mon; 649 cl->cl_year = dt->dt_year; 650 651 /* load them up */ 652 cl->cl_csr &= ~CLK_WRITE; 653 splx(s); 654 } 655 656
Indexes created Thu Sep 25 16:09:42 GMT 2025