1 /* $NetBSD: ka420.h,v 1.4 2017/05/22 17:12:11 ragge Exp $ */ 2 /* 3 * Copyright (c) 1996 Ludd, University of Lule}, Sweden. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Ludd by Bertram Barth. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef _VAX_KA420_H_ 30 #define _VAX_KA420_H_ 31 32 /* 33 * Definitions for I/O addresses of 34 * 35 * VAXstation 3100 models 30, 40 (PVAX) 36 * MicroVAX 3100 models 10, 20 (Teammate II) 37 * MicroVAX 3100 models 10e, 20e (Teammate II) 38 * VAXstation 3100 models 38, 48 (PVAX rev#7) 39 */ 40 41 #define KA420_SIDEX 0x20040004 /* SID extension register */ 42 43 #define KA420_CH2_BASE 0x10000000 /* 2nd level cache data area */ 44 #define KA420_CH2_END 0x10007FFF 45 #define KA420_CH2_SIZE 0x8000 46 #define KA420_CT2_BASE 0x10010000 /* 2nd level cache tag area */ 47 #define KA420_CT2_END 0x10017FFF 48 #define KA420_CT2_SIZE 0x8000 49 #define KA420_CH2_CREG 0x20084000 /* 2nd level cache control register */ 50 51 #define KA420_CFGTST 0x20020000 /* Configuration and Test register */ 52 #define KA420_IORESET 0x20020000 /* I/O Reset register */ 53 54 #define KA420_ROM_BASE 0x20040000 /* System module ROM */ 55 #define KA420_ROM_END 0x2007FFFF 56 #define KA420_ROM_SIZE 0x40000 /* ??? */ 57 58 #define KA420_IVN_BASE 0x20040020 /* Interrupt Vector Numbers */ 59 #define KA420_IVN_END 0x2004003F 60 #define KA420_IVN_SIZE 0x20 61 62 #define KA420_HLTCOD 0x20080000 /* Halt Code Register */ 63 #define KA420_MSER 0x20080004 /* Memory System Error register */ 64 #define KA420_MEAR 0x20080008 /* Memory Error Address register */ 65 #define KA420_INTMSK 0x2008000C /* Interrupt Mask register */ 66 #define KA420_VDCORG 0x2008000D /* Video Controller Origin Register */ 67 #define KA420_VDCSEL 0x2008000E /* Video Controller Select Register */ 68 #define KA420_INTREQ 0x2008000F /* Interrupt Request register */ 69 #define KA420_INTCLR 0x2008000F /* Interrupt Request clear register */ 70 71 #define KA420_CACR 0x20084000 /* L2 cache ctrl reg */ 72 73 /* 74 * Other fixed addresses which should be mapped 75 */ 76 #define KA420_NWA_BASE 0x20090000 /* Network Address ROM */ 77 #define KA420_NWA_END 0x2009007F 78 #define KA420_NWA_SIZE 0x80 79 #define KA420_SER_BASE 0x200A0000 /* Serial line controller */ 80 #define KA420_SER_END 0x200A000F 81 #define KA420_SER_SIZE 0x10 82 #define KA420_WAT_BASE 0x200B0000 /* TOY clock and NV-RAM */ 83 #define KA420_WAT_END 0x200B00FF 84 #define KA420_WAT_SIZE 0x100 85 #define KA420_DKC_BASE 0x200C0000 /* Disk Controller Ports */ 86 #define KA420_DKC_END 0x200C0007 87 #define KA420_DKC_SIZE 0x08 88 #define KA420_SCS_BASE 0x200C0080 /* Tape (SCSI) Controller Chip */ 89 #define KA420_SCS_END 0x200C009F 90 #define KA420_SCS_SIZE 0x20 91 #define KA420_D16_BASE 0x200D0000 /* 16KB (compatibility) Data Buffer */ 92 #define KA420_D16_END 0x200D3FFF 93 #define KA420_D16_SIZE 0x4000 94 #define KA420_LAN_BASE 0x200E0000 /* LANCE chip registers */ 95 #define KA420_LAN_END 0x200E0007 96 #define KA420_LAN_SIZE 0x08 97 #define KA420_CUR_BASE 0x200F0000 /* Monochrome video cursor chip */ 98 #define KA420_CUR_END 0x200F0007 99 #define KA420_CUR_SIZE 0x08 100 #define KA420_DMA_BASE 0x202D0000 /* 128KB Data Buffer */ 101 #define KA420_DMA_END 0x202EFFFF 102 #define KA420_DMA_SIZE 0x20000 103 104 #define KA420_SCD_DADR 0x200C00A0 /* Tape(SCSI) DMA address register */ 105 #define KA420_SCD_DCNT 0x200C00C0 /* Tape(SCSI) DMA byte count reg. */ 106 #define KA420_SCD_DDIR 0x200C00C4 /* Tape(SCSI) DMA transfer direction */ 107 108 #define KA420_STC_MODE 0x200C00E0 /* Storage Controller Mode register */ 109 110 #define KA420_CUR_CMD 0x200F0000 /* Cursor Command Register */ 111 #define KA420_CUR_XPOS 0x200F0004 /* Cursor X position */ 112 #define KA420_CUR_YPOS 0x200F0008 /* Cursor Y position */ 113 114 #define KA420_CUR_XMIN1 0x200F000C /* Region 1 left edge */ 115 #define KA420_CUR_XMAX1 0x200F0010 /* Region 1 right edge */ 116 #define KA420_CUR_YMIN1 0x200F0014 /* Region 1 top edge */ 117 #define KA420_CUR_YMAX1 0x200F0018 /* Region 1 bottom edge */ 118 119 #define KA420_CUR_XMIN2 0x200F002C /* Region 2 left edge */ 120 #define KA420_CUR_XMAX2 0x200F0030 /* Region 2 right edge */ 121 #define KA420_CUR_YMIN2 0x200F0034 /* Region 2 top edge */ 122 #define KA420_CUR_YMAX2 0x200F0038 /* Region 2 bottom edge */ 123 124 /* 125 * Clock-Chip data in NVRAM 126 */ 127 #define KA420_CPMBX 0x200B0038 /* Console Mailbox (1 byte) */ 128 #define KA420_CPFLG 0x200B003C /* Console Program Flags (1 byte) */ 129 #define KA420_LK201_ID 0x200B0040 /* Keyboard Variation (1 byte) */ 130 #define KA420_CONS_ID 0x200B0044 /* Console Device Type (1 byte) */ 131 #define KA420_SCR 0x200B0048 /* Console Scratch RAM */ 132 #define KA420_TEMP 0x200B0058 /* Used by System Firmware */ 133 #define KA420_BAT_CHK 0x200B0088 /* Battery Check Data */ 134 #define KA420_BOOTDEV 0x200B0098 /* Default Boot Device (4 bytes) */ 135 #define KA420_BOOTFLG 0x200B00A8 /* Default Boot Flags (4 bytes) */ 136 #define KA420_SCRLEN 0x200B00B8 /* Number of pages of SCR (1 byte) */ 137 #define KA420_SCSIPORT 0x200B00BC /* Tape Controller Port Data */ 138 #define KA420_RESERVED 0x200B00C0 /* Reserved (16 bytes) */ 139 140 /* Used bits in the CFGTST (20020000) register */ 141 #define KA420_CFG_STCMSK 0xc000 /* Storage controller mask */ 142 #define KA420_CFG_RB 0x0000 /* RB (ST506/SCSI) present */ 143 #define KA420_CFG_RD 0x4000 /* RD (SCSI/SCSI) present */ 144 #define KA420_CFG_NONE 0xc000 /* No storage ctlr present */ 145 #define KA420_CFG_MULTU 0x80 /* MicroVAX or VAXstation */ 146 #define KA420_CFG_CACHPR 0x40 /* Secondary cache present */ 147 #define KA420_CFG_L3CON 0x20 /* Console on line #3 of dc */ 148 #define KA420_CFG_CURTEST 0x10 /* Cursor Test (monochrom) */ 149 #define KA420_CFG_VIDOPT 0x08 /* Video option present */ 150 151 /* Primary cache bits (CADR, IPR 37) */ 152 #define KA420_CADR_S2E 0x80 /* set 2 enable */ 153 #define KA420_CADR_S1E 0x40 /* set 1 enable */ 154 #define KA420_CADR_ISE 0x20 /* insn caching enable */ 155 #define KA420_CADR_DSE 0x10 /* data caching enable */ 156 #define KA420_CADR_WWP 0x02 /* write wrong parity */ 157 #define KA420_CADR_DIA 0x01 /* diagnostic mode */ 158 159 /* Secondary cache bits (CACR, 20084000) */ 160 #define KA420_CACR_CP3 0x80000000 /* last parity read */ 161 #define KA420_CACR_CP2 0x40000000 /* last parity read */ 162 #define KA420_CACR_CP1 0x20000000 /* last parity read */ 163 #define KA420_CACR_CP0 0x10000000 /* last parity read */ 164 #define KA420_CACR_TPP 0x00100000 /* tag predicted parity */ 165 #define KA420_CACR_TGP 0x00080000 /* tag parity read */ 166 #define KA420_CACR_TGV 0x00040000 /* valid flag */ 167 #define KA420_CACR_TPE 0x00000020 /* tag parity error */ 168 #define KA420_CACR_CEN 0x00000010 /* cache enable */ 169 170 #endif /* _VAX_KA420_H_ */ 171
Indexes created Sat Sep 20 22:09:52 GMT 2025