ka43.c revision 1.18 1 1.18 ragge /* $NetBSD: ka43.c,v 1.18 1999/08/07 10:36:48 ragge Exp $ */
2 1.1 ragge /*
3 1.1 ragge * Copyright (c) 1996 Ludd, University of Lule}, Sweden.
4 1.1 ragge * All rights reserved.
5 1.1 ragge *
6 1.1 ragge * This code is derived from software contributed to Ludd by Bertram Barth.
7 1.1 ragge *
8 1.1 ragge * Redistribution and use in source and binary forms, with or without
9 1.1 ragge * modification, are permitted provided that the following conditions
10 1.1 ragge * are met:
11 1.1 ragge * 1. Redistributions of source code must retain the above copyright
12 1.1 ragge * notice, this list of conditions and the following disclaimer.
13 1.1 ragge * 2. Redistributions in binary form must reproduce the above copyright
14 1.1 ragge * notice, this list of conditions and the following disclaimer in the
15 1.1 ragge * documentation and/or other materials provided with the distribution.
16 1.1 ragge * 3. All advertising materials mentioning features or use of this software
17 1.1 ragge * must display the following acknowledgement:
18 1.4 ragge * This product includes software developed at Ludd, University of
19 1.4 ragge * Lule}, Sweden and its contributors.
20 1.1 ragge * 4. The name of the author may not be used to endorse or promote products
21 1.1 ragge * derived from this software without specific prior written permission
22 1.1 ragge *
23 1.1 ragge * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
24 1.1 ragge * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 1.1 ragge * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 1.1 ragge * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27 1.1 ragge * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 1.1 ragge * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 1.1 ragge * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 1.1 ragge * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 1.1 ragge * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 1.1 ragge * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 1.1 ragge */
34 1.1 ragge
35 1.1 ragge #include <sys/param.h>
36 1.1 ragge #include <sys/types.h>
37 1.1 ragge #include <sys/device.h>
38 1.1 ragge #include <sys/kernel.h>
39 1.6 ragge #include <sys/systm.h>
40 1.1 ragge
41 1.1 ragge #include <vm/vm.h>
42 1.1 ragge #include <vm/vm_kern.h>
43 1.1 ragge
44 1.1 ragge #include <machine/pte.h>
45 1.4 ragge #include <machine/cpu.h>
46 1.1 ragge #include <machine/mtpr.h>
47 1.1 ragge #include <machine/sid.h>
48 1.1 ragge #include <machine/pmap.h>
49 1.1 ragge #include <machine/nexus.h>
50 1.1 ragge #include <machine/uvax.h>
51 1.6 ragge #include <machine/vsbus.h>
52 1.1 ragge #include <machine/ka43.h>
53 1.1 ragge #include <machine/clock.h>
54 1.1 ragge
55 1.18 ragge static void ka43_conf __P((void));
56 1.14 ragge static void ka43_steal_pages __P((void));
57 1.9 ragge
58 1.14 ragge static int ka43_mchk __P((caddr_t));
59 1.14 ragge static void ka43_memerr __P((void));
60 1.14 ragge #if 0
61 1.14 ragge static void ka43_clear_errors __P((void));
62 1.14 ragge #endif
63 1.14 ragge static int ka43_cache_init __P((void)); /* "int mapen" as argument? */
64 1.14 ragge static int ka43_cache_reset __P((void));
65 1.14 ragge static int ka43_cache_enable __P((void));
66 1.14 ragge static int ka43_cache_disable __P((void));
67 1.14 ragge static int ka43_cache_invalidate __P((void));
68 1.14 ragge static void ka43_halt __P((void));
69 1.14 ragge static void ka43_reboot __P((int));
70 1.14 ragge static void ka43_clrf __P((void));
71 1.1 ragge
72 1.1 ragge
73 1.4 ragge struct cpu_dep ka43_calls = {
74 1.4 ragge ka43_steal_pages,
75 1.4 ragge ka43_mchk,
76 1.4 ragge ka43_memerr,
77 1.4 ragge ka43_conf,
78 1.5 ragge chip_clkread,
79 1.5 ragge chip_clkwrite,
80 1.5 ragge 7, /* 7.6 VUP */
81 1.13 ragge 2, /* SCB pages */
82 1.14 ragge ka43_halt,
83 1.14 ragge ka43_reboot,
84 1.14 ragge ka43_clrf,
85 1.4 ragge };
86 1.4 ragge
87 1.5 ragge /*
88 1.5 ragge * ka43_steal_pages() is called with MMU disabled, after that call MMU gets
89 1.5 ragge * enabled. Thus we initialize these four pointers with physical addresses,
90 1.5 ragge * but before leving ka43_steal_pages() we reset them to virtual addresses.
91 1.5 ragge */
92 1.16 ragge static volatile struct ka43_cpu *ka43_cpu = (void*)KA43_CPU_BASE;
93 1.14 ragge extern short *clk_page;
94 1.1 ragge
95 1.16 ragge static volatile u_int *ka43_creg = (void*)KA43_CH2_CREG;
96 1.16 ragge static volatile u_int *ka43_ctag = (void*)KA43_CT2_BASE;
97 1.1 ragge
98 1.5 ragge #define KA43_MC_RESTART 0x00008000 /* Restart possible*/
99 1.5 ragge #define KA43_PSL_FPDONE 0x00010000 /* First Part Done */
100 1.1 ragge
101 1.5 ragge struct ka43_mcframe { /* Format of RigelMAX machine check frame: */
102 1.5 ragge int mc43_bcnt; /* byte count, always 24 (0x18) */
103 1.5 ragge int mc43_code; /* machine check type code and restart bit */
104 1.5 ragge int mc43_addr; /* most recent (faulting?) virtual address */
105 1.5 ragge int mc43_viba; /* contents of VIBA register */
106 1.5 ragge int mc43_sisr; /* ICCS bit 6 and SISR bits 15:0 */
107 1.5 ragge int mc43_istate; /* internal state */
108 1.5 ragge int mc43_sc; /* shift count register */
109 1.5 ragge int mc43_pc; /* trapped PC */
110 1.5 ragge int mc43_psl; /* trapped PSL */
111 1.5 ragge };
112 1.1 ragge
113 1.5 ragge static char *ka43_mctype[] = {
114 1.5 ragge "no error (0)", /* Code 0: No error */
115 1.5 ragge "FPA: protocol error", /* Code 1-5: FPA errors */
116 1.5 ragge "FPA: illegal opcode",
117 1.5 ragge "FPA: operand parity error",
118 1.5 ragge "FPA: unknown status",
119 1.5 ragge "FPA: result parity error",
120 1.5 ragge "unused (6)", /* Code 6-7: Unused */
121 1.1 ragge "unused (7)",
122 1.5 ragge "MMU error (TLB miss)", /* Code 8-9: MMU errors */
123 1.1 ragge "MMU error (TLB hit)",
124 1.5 ragge "HW interrupt at unused IPL", /* Code 10: Interrupt error */
125 1.5 ragge "MOVCx impossible state", /* Code 11-13: Microcode errors */
126 1.1 ragge "undefined trap code (i-box)",
127 1.1 ragge "undefined control store address",
128 1.5 ragge "unused (14)", /* Code 14-15: Unused */
129 1.1 ragge "unused (15)",
130 1.5 ragge "PC tag or data parity error", /* Code 16: Cache error */
131 1.5 ragge "data bus parity error", /* Code 17: Read error */
132 1.5 ragge "data bus error (NXM)", /* Code 18: Write error */
133 1.5 ragge "undefined data bus state", /* Code 19: Bus error */
134 1.1 ragge };
135 1.5 ragge #define MC43_MAX 19
136 1.5 ragge
137 1.5 ragge static int ka43_error_count = 0;
138 1.1 ragge
139 1.1 ragge int
140 1.1 ragge ka43_mchk(addr)
141 1.1 ragge caddr_t addr;
142 1.1 ragge {
143 1.5 ragge register struct ka43_mcframe *mcf = (void*)addr;
144 1.5 ragge
145 1.5 ragge mtpr(0x00, PR_MCESR); /* Acknowledge the machine check */
146 1.5 ragge printf("machine check %d (0x%x)\n", mcf->mc43_code, mcf->mc43_code);
147 1.5 ragge printf("reason: %s\n", ka43_mctype[mcf->mc43_code & 0xff]);
148 1.5 ragge if (++ka43_error_count > 10) {
149 1.5 ragge printf("error_count exceeded: %d\n", ka43_error_count);
150 1.5 ragge return (-1);
151 1.5 ragge }
152 1.1 ragge
153 1.5 ragge /*
154 1.5 ragge * If either the Restart flag is set or the First-Part-Done flag
155 1.5 ragge * is set, and the TRAP2 (double error) bit is not set, the the
156 1.5 ragge * error is recoverable.
157 1.5 ragge */
158 1.5 ragge if (mfpr(PR_PCSTS) & KA43_PCS_TRAP2) {
159 1.5 ragge printf("TRAP2 (double error) in ka43_mchk.\n");
160 1.5 ragge panic("unrecoverable state in ka43_mchk.\n");
161 1.5 ragge return (-1);
162 1.5 ragge }
163 1.5 ragge if ((mcf->mc43_code & KA43_MC_RESTART) ||
164 1.5 ragge (mcf->mc43_psl & KA43_PSL_FPDONE)) {
165 1.5 ragge printf("ka43_mchk: recovering from machine-check.\n");
166 1.5 ragge ka43_cache_reset(); /* reset caches */
167 1.5 ragge return (0); /* go on; */
168 1.5 ragge }
169 1.5 ragge
170 1.5 ragge /*
171 1.5 ragge * Unknown error state, panic/halt the machine!
172 1.5 ragge */
173 1.5 ragge printf("ka43_mchk: unknown error state!\n");
174 1.1 ragge return (-1);
175 1.1 ragge }
176 1.1 ragge
177 1.5 ragge void
178 1.5 ragge ka43_memerr()
179 1.5 ragge {
180 1.5 ragge /*
181 1.5 ragge * Don\'t know what to do here. So just print some messages
182 1.5 ragge * and try to go on...
183 1.5 ragge */
184 1.5 ragge printf("memory error!\n");
185 1.5 ragge printf("primary cache status: %b\n", mfpr(PR_PCSTS), KA43_PCSTS_BITS);
186 1.5 ragge printf("secondary cache status: %b\n", *ka43_creg, KA43_SESR_BITS);
187 1.5 ragge }
188 1.5 ragge
189 1.1 ragge int
190 1.5 ragge ka43_cache_init()
191 1.1 ragge {
192 1.5 ragge return (ka43_cache_reset());
193 1.5 ragge }
194 1.1 ragge
195 1.14 ragge #if 0
196 1.6 ragge void
197 1.5 ragge ka43_clear_errors()
198 1.5 ragge {
199 1.5 ragge int val = *ka43_creg;
200 1.5 ragge val |= KA43_SESR_SERR | KA43_SESR_LERR | KA43_SESR_CERR;
201 1.5 ragge *ka43_creg = val;
202 1.1 ragge }
203 1.14 ragge #endif
204 1.1 ragge
205 1.5 ragge int
206 1.5 ragge ka43_cache_reset()
207 1.1 ragge {
208 1.5 ragge /*
209 1.5 ragge * resetting primary and secondary caches is done in three steps:
210 1.5 ragge * 1. disable both caches
211 1.5 ragge * 2. manually clear secondary cache
212 1.5 ragge * 3. enable both caches
213 1.5 ragge */
214 1.5 ragge ka43_cache_disable();
215 1.5 ragge ka43_cache_invalidate();
216 1.5 ragge ka43_cache_enable();
217 1.5 ragge
218 1.5 ragge printf("primary cache status: %b\n", mfpr(PR_PCSTS), KA43_PCSTS_BITS);
219 1.5 ragge printf("secondary cache status: %b\n", *ka43_creg, KA43_SESR_BITS);
220 1.1 ragge
221 1.1 ragge return (0);
222 1.5 ragge }
223 1.5 ragge
224 1.5 ragge int
225 1.5 ragge ka43_cache_disable()
226 1.5 ragge {
227 1.6 ragge int val;
228 1.1 ragge
229 1.1 ragge /*
230 1.5 ragge * first disable primary cache and clear error flags
231 1.1 ragge */
232 1.5 ragge mtpr(KA43_PCS_REFRESH, PR_PCSTS); /* disable primary cache */
233 1.5 ragge val = mfpr(PR_PCSTS);
234 1.5 ragge mtpr(val, PR_PCSTS); /* clear error flags */
235 1.5 ragge
236 1.1 ragge /*
237 1.5 ragge * now disable secondary cache and clear error flags
238 1.1 ragge */
239 1.5 ragge val = *ka43_creg & ~KA43_SESR_CENB; /* BICL !!! */
240 1.5 ragge *ka43_creg = val; /* disable secondary cache */
241 1.5 ragge val = KA43_SESR_SERR | KA43_SESR_LERR | KA43_SESR_CERR;
242 1.5 ragge *ka43_creg = val; /* clear error flags */
243 1.5 ragge
244 1.5 ragge return (0);
245 1.5 ragge }
246 1.5 ragge
247 1.5 ragge int
248 1.5 ragge ka43_cache_invalidate()
249 1.5 ragge {
250 1.5 ragge int i, val;
251 1.5 ragge
252 1.5 ragge val = KA43_PCTAG_PARITY; /* clear valid flag, set parity bit */
253 1.5 ragge for (i = 0; i < 256; i++) { /* 256 Quadword entries */
254 1.5 ragge mtpr(i*8, PR_PCIDX); /* write index of tag */
255 1.5 ragge mtpr(val, PR_PCTAG); /* write value into tag */
256 1.5 ragge }
257 1.5 ragge val = KA43_PCS_FLUSH | KA43_PCS_REFRESH;
258 1.5 ragge mtpr(val, PR_PCSTS); /* flush primary cache */
259 1.5 ragge
260 1.5 ragge /*
261 1.5 ragge * Rigel\'s secondary cache doesn\'t implement a valid-flag.
262 1.5 ragge * Thus we initialize all entries with out-of-range/dummy
263 1.5 ragge * addresses which will never be referenced (ie. never hit).
264 1.5 ragge * After enabling cache we also access 128K of memory starting
265 1.5 ragge * at 0x00 so that secondary cache will be filled with these
266 1.5 ragge * valid addresses...
267 1.5 ragge */
268 1.5 ragge val = 0xff;
269 1.5 ragge /* if (memory > 28 MB) val = 0x55; */
270 1.5 ragge for (i = 0; i < KA43_CT2_SIZE; i+= 4) { /* Quadword entries ?? */
271 1.5 ragge ka43_ctag[i/4] = val; /* reset upper and lower */
272 1.1 ragge }
273 1.5 ragge
274 1.5 ragge return (0);
275 1.1 ragge }
276 1.1 ragge
277 1.5 ragge
278 1.5 ragge int
279 1.5 ragge ka43_cache_enable()
280 1.1 ragge {
281 1.5 ragge volatile char *membase = (void*)0x80000000; /* physical 0x00 */
282 1.5 ragge int i, val;
283 1.5 ragge
284 1.5 ragge val = KA43_PCS_FLUSH | KA43_PCS_REFRESH;
285 1.5 ragge mtpr(val, PR_PCSTS); /* flush primary cache */
286 1.1 ragge
287 1.1 ragge /*
288 1.5 ragge * now we enable secondary cache and access first 128K of memory
289 1.5 ragge * so that secondary cache gets really initialized and holds
290 1.5 ragge * valid addresses/data...
291 1.1 ragge */
292 1.5 ragge *ka43_creg = KA43_SESR_CENB; /* enable secondary cache */
293 1.5 ragge for (i=0; i<128*1024; i++) {
294 1.5 ragge val += membase[i]; /* some dummy operation... */
295 1.1 ragge }
296 1.1 ragge
297 1.5 ragge val = KA43_PCS_ENABLE | KA43_PCS_REFRESH;
298 1.5 ragge mtpr(val, PR_PCSTS); /* enable primary cache */
299 1.5 ragge
300 1.5 ragge return (0);
301 1.1 ragge }
302 1.1 ragge
303 1.1 ragge void
304 1.18 ragge ka43_conf()
305 1.1 ragge {
306 1.14 ragge extern int clk_adrshift, clk_tweak;
307 1.1 ragge
308 1.18 ragge printf("cpu: KA43\n");
309 1.14 ragge ka43_cpu = (void *)vax_map_physmem(VS_REGS, 1);
310 1.14 ragge
311 1.14 ragge ka43_creg = (void *)vax_map_physmem(KA43_CH2_CREG, 1);
312 1.14 ragge ka43_ctag = (void *)vax_map_physmem(KA43_CT2_BASE,
313 1.14 ragge (KA43_CT2_SIZE/VAX_NBPG));
314 1.14 ragge
315 1.5 ragge /*
316 1.5 ragge * ka43_conf() gets called with MMU enabled, now it's save to
317 1.5 ragge * init/reset the caches.
318 1.5 ragge */
319 1.5 ragge ka43_cache_init();
320 1.14 ragge
321 1.14 ragge clk_adrshift = 1; /* Addressed at long's... */
322 1.14 ragge clk_tweak = 2; /* ...and shift two */
323 1.14 ragge clk_page = (short *)vax_map_physmem(VS_CLOCK, 1);
324 1.1 ragge }
325 1.1 ragge
326 1.1 ragge
327 1.1 ragge /*
328 1.5 ragge * The interface for communication with the LANCE ethernet controller
329 1.5 ragge * is setup in the xxx_steal_pages() routine. We decrease highest
330 1.5 ragge * available address by 64K and use this area as communication buffer.
331 1.1 ragge */
332 1.1 ragge
333 1.1 ragge void
334 1.1 ragge ka43_steal_pages()
335 1.1 ragge {
336 1.14 ragge int val;
337 1.1 ragge
338 1.1 ragge
339 1.5 ragge /*
340 1.5 ragge * if LANCE\'s io-buffer is above 16 MB, then the appropriate flag
341 1.5 ragge * in the parity control register has to be set (it works as an
342 1.5 ragge * additional address bit). In any case, don\'t enable CPEN and
343 1.5 ragge * DPEN in the PARCTL register, somewhow they are internally managed
344 1.5 ragge * by the RIGEL chip itself!?!
345 1.5 ragge */
346 1.5 ragge val = ka43_cpu->parctl & 0x03; /* read the old value */
347 1.5 ragge ka43_cpu->parctl = val; /* and write new value */
348 1.14 ragge }
349 1.14 ragge
350 1.14 ragge static void
351 1.14 ragge ka43_clrf()
352 1.14 ragge {
353 1.14 ragge struct ka43_clock *clk = (void *)clk_page;
354 1.1 ragge
355 1.14 ragge /*
356 1.14 ragge * Clear restart and boot in progress flags in the CPMBX.
357 1.14 ragge */
358 1.14 ragge clk->cpmbx = (clk->cpmbx & ~0xf0);
359 1.14 ragge }
360 1.14 ragge
361 1.14 ragge static void
362 1.14 ragge ka43_halt()
363 1.14 ragge {
364 1.14 ragge asm("movl $0xc, (%0)"::"r"((int)clk_page + 0x38)); /* Don't ask */
365 1.14 ragge asm("halt");
366 1.14 ragge }
367 1.14 ragge
368 1.14 ragge static void
369 1.14 ragge ka43_reboot(arg)
370 1.14 ragge int arg;
371 1.14 ragge {
372 1.14 ragge asm("movl $0xc, (%0)"::"r"((int)clk_page + 0x38)); /* Don't ask */
373 1.14 ragge asm("halt");
374 1.1 ragge }
375 1.14 ragge
376