ka43.c revision 1.23 1 1.23 mrg /* $NetBSD: ka43.c,v 1.23 2000/06/29 07:14:25 mrg Exp $ */
2 1.1 ragge /*
3 1.1 ragge * Copyright (c) 1996 Ludd, University of Lule}, Sweden.
4 1.1 ragge * All rights reserved.
5 1.1 ragge *
6 1.1 ragge * This code is derived from software contributed to Ludd by Bertram Barth.
7 1.1 ragge *
8 1.1 ragge * Redistribution and use in source and binary forms, with or without
9 1.1 ragge * modification, are permitted provided that the following conditions
10 1.1 ragge * are met:
11 1.1 ragge * 1. Redistributions of source code must retain the above copyright
12 1.1 ragge * notice, this list of conditions and the following disclaimer.
13 1.1 ragge * 2. Redistributions in binary form must reproduce the above copyright
14 1.1 ragge * notice, this list of conditions and the following disclaimer in the
15 1.1 ragge * documentation and/or other materials provided with the distribution.
16 1.1 ragge * 3. All advertising materials mentioning features or use of this software
17 1.1 ragge * must display the following acknowledgement:
18 1.4 ragge * This product includes software developed at Ludd, University of
19 1.4 ragge * Lule}, Sweden and its contributors.
20 1.1 ragge * 4. The name of the author may not be used to endorse or promote products
21 1.1 ragge * derived from this software without specific prior written permission
22 1.1 ragge *
23 1.1 ragge * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
24 1.1 ragge * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 1.1 ragge * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 1.1 ragge * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27 1.1 ragge * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 1.1 ragge * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 1.1 ragge * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 1.1 ragge * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 1.1 ragge * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 1.1 ragge * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 1.1 ragge */
34 1.1 ragge
35 1.1 ragge #include <sys/param.h>
36 1.1 ragge #include <sys/types.h>
37 1.1 ragge #include <sys/device.h>
38 1.1 ragge #include <sys/kernel.h>
39 1.6 ragge #include <sys/systm.h>
40 1.1 ragge
41 1.23 mrg #include <uvm/uvm_extern.h>
42 1.1 ragge
43 1.1 ragge #include <machine/pte.h>
44 1.4 ragge #include <machine/cpu.h>
45 1.1 ragge #include <machine/mtpr.h>
46 1.1 ragge #include <machine/sid.h>
47 1.1 ragge #include <machine/pmap.h>
48 1.1 ragge #include <machine/nexus.h>
49 1.1 ragge #include <machine/uvax.h>
50 1.6 ragge #include <machine/vsbus.h>
51 1.1 ragge #include <machine/ka43.h>
52 1.1 ragge #include <machine/clock.h>
53 1.1 ragge
54 1.18 ragge static void ka43_conf __P((void));
55 1.14 ragge static void ka43_steal_pages __P((void));
56 1.9 ragge
57 1.14 ragge static int ka43_mchk __P((caddr_t));
58 1.14 ragge static void ka43_memerr __P((void));
59 1.14 ragge #if 0
60 1.14 ragge static void ka43_clear_errors __P((void));
61 1.14 ragge #endif
62 1.14 ragge static int ka43_cache_init __P((void)); /* "int mapen" as argument? */
63 1.14 ragge static int ka43_cache_reset __P((void));
64 1.14 ragge static int ka43_cache_enable __P((void));
65 1.14 ragge static int ka43_cache_disable __P((void));
66 1.14 ragge static int ka43_cache_invalidate __P((void));
67 1.14 ragge static void ka43_halt __P((void));
68 1.14 ragge static void ka43_reboot __P((int));
69 1.14 ragge static void ka43_clrf __P((void));
70 1.1 ragge
71 1.1 ragge
72 1.4 ragge struct cpu_dep ka43_calls = {
73 1.4 ragge ka43_steal_pages,
74 1.4 ragge ka43_mchk,
75 1.4 ragge ka43_memerr,
76 1.4 ragge ka43_conf,
77 1.5 ragge chip_clkread,
78 1.5 ragge chip_clkwrite,
79 1.5 ragge 7, /* 7.6 VUP */
80 1.13 ragge 2, /* SCB pages */
81 1.14 ragge ka43_halt,
82 1.14 ragge ka43_reboot,
83 1.14 ragge ka43_clrf,
84 1.21 ragge NULL,
85 1.21 ragge CPU_RAISEIPL,
86 1.4 ragge };
87 1.4 ragge
88 1.5 ragge /*
89 1.5 ragge * ka43_steal_pages() is called with MMU disabled, after that call MMU gets
90 1.5 ragge * enabled. Thus we initialize these four pointers with physical addresses,
91 1.5 ragge * but before leving ka43_steal_pages() we reset them to virtual addresses.
92 1.5 ragge */
93 1.16 ragge static volatile struct ka43_cpu *ka43_cpu = (void*)KA43_CPU_BASE;
94 1.16 ragge static volatile u_int *ka43_creg = (void*)KA43_CH2_CREG;
95 1.16 ragge static volatile u_int *ka43_ctag = (void*)KA43_CT2_BASE;
96 1.1 ragge
97 1.5 ragge #define KA43_MC_RESTART 0x00008000 /* Restart possible*/
98 1.5 ragge #define KA43_PSL_FPDONE 0x00010000 /* First Part Done */
99 1.1 ragge
100 1.5 ragge struct ka43_mcframe { /* Format of RigelMAX machine check frame: */
101 1.5 ragge int mc43_bcnt; /* byte count, always 24 (0x18) */
102 1.5 ragge int mc43_code; /* machine check type code and restart bit */
103 1.5 ragge int mc43_addr; /* most recent (faulting?) virtual address */
104 1.5 ragge int mc43_viba; /* contents of VIBA register */
105 1.5 ragge int mc43_sisr; /* ICCS bit 6 and SISR bits 15:0 */
106 1.5 ragge int mc43_istate; /* internal state */
107 1.5 ragge int mc43_sc; /* shift count register */
108 1.5 ragge int mc43_pc; /* trapped PC */
109 1.5 ragge int mc43_psl; /* trapped PSL */
110 1.5 ragge };
111 1.1 ragge
112 1.5 ragge static char *ka43_mctype[] = {
113 1.5 ragge "no error (0)", /* Code 0: No error */
114 1.5 ragge "FPA: protocol error", /* Code 1-5: FPA errors */
115 1.5 ragge "FPA: illegal opcode",
116 1.5 ragge "FPA: operand parity error",
117 1.5 ragge "FPA: unknown status",
118 1.5 ragge "FPA: result parity error",
119 1.5 ragge "unused (6)", /* Code 6-7: Unused */
120 1.1 ragge "unused (7)",
121 1.5 ragge "MMU error (TLB miss)", /* Code 8-9: MMU errors */
122 1.1 ragge "MMU error (TLB hit)",
123 1.5 ragge "HW interrupt at unused IPL", /* Code 10: Interrupt error */
124 1.5 ragge "MOVCx impossible state", /* Code 11-13: Microcode errors */
125 1.1 ragge "undefined trap code (i-box)",
126 1.1 ragge "undefined control store address",
127 1.5 ragge "unused (14)", /* Code 14-15: Unused */
128 1.1 ragge "unused (15)",
129 1.5 ragge "PC tag or data parity error", /* Code 16: Cache error */
130 1.5 ragge "data bus parity error", /* Code 17: Read error */
131 1.5 ragge "data bus error (NXM)", /* Code 18: Write error */
132 1.5 ragge "undefined data bus state", /* Code 19: Bus error */
133 1.1 ragge };
134 1.5 ragge #define MC43_MAX 19
135 1.5 ragge
136 1.5 ragge static int ka43_error_count = 0;
137 1.1 ragge
138 1.1 ragge int
139 1.1 ragge ka43_mchk(addr)
140 1.1 ragge caddr_t addr;
141 1.1 ragge {
142 1.5 ragge register struct ka43_mcframe *mcf = (void*)addr;
143 1.5 ragge
144 1.5 ragge mtpr(0x00, PR_MCESR); /* Acknowledge the machine check */
145 1.5 ragge printf("machine check %d (0x%x)\n", mcf->mc43_code, mcf->mc43_code);
146 1.5 ragge printf("reason: %s\n", ka43_mctype[mcf->mc43_code & 0xff]);
147 1.5 ragge if (++ka43_error_count > 10) {
148 1.5 ragge printf("error_count exceeded: %d\n", ka43_error_count);
149 1.5 ragge return (-1);
150 1.5 ragge }
151 1.1 ragge
152 1.5 ragge /*
153 1.5 ragge * If either the Restart flag is set or the First-Part-Done flag
154 1.20 soren * is set, and the TRAP2 (double error) bit is not set, then the
155 1.5 ragge * error is recoverable.
156 1.5 ragge */
157 1.5 ragge if (mfpr(PR_PCSTS) & KA43_PCS_TRAP2) {
158 1.5 ragge printf("TRAP2 (double error) in ka43_mchk.\n");
159 1.5 ragge panic("unrecoverable state in ka43_mchk.\n");
160 1.5 ragge return (-1);
161 1.5 ragge }
162 1.5 ragge if ((mcf->mc43_code & KA43_MC_RESTART) ||
163 1.5 ragge (mcf->mc43_psl & KA43_PSL_FPDONE)) {
164 1.5 ragge printf("ka43_mchk: recovering from machine-check.\n");
165 1.5 ragge ka43_cache_reset(); /* reset caches */
166 1.5 ragge return (0); /* go on; */
167 1.5 ragge }
168 1.5 ragge
169 1.5 ragge /*
170 1.5 ragge * Unknown error state, panic/halt the machine!
171 1.5 ragge */
172 1.5 ragge printf("ka43_mchk: unknown error state!\n");
173 1.1 ragge return (-1);
174 1.1 ragge }
175 1.1 ragge
176 1.5 ragge void
177 1.5 ragge ka43_memerr()
178 1.5 ragge {
179 1.5 ragge /*
180 1.5 ragge * Don\'t know what to do here. So just print some messages
181 1.5 ragge * and try to go on...
182 1.5 ragge */
183 1.5 ragge printf("memory error!\n");
184 1.5 ragge printf("primary cache status: %b\n", mfpr(PR_PCSTS), KA43_PCSTS_BITS);
185 1.5 ragge printf("secondary cache status: %b\n", *ka43_creg, KA43_SESR_BITS);
186 1.5 ragge }
187 1.5 ragge
188 1.1 ragge int
189 1.5 ragge ka43_cache_init()
190 1.1 ragge {
191 1.5 ragge return (ka43_cache_reset());
192 1.5 ragge }
193 1.1 ragge
194 1.14 ragge #if 0
195 1.6 ragge void
196 1.5 ragge ka43_clear_errors()
197 1.5 ragge {
198 1.5 ragge int val = *ka43_creg;
199 1.5 ragge val |= KA43_SESR_SERR | KA43_SESR_LERR | KA43_SESR_CERR;
200 1.5 ragge *ka43_creg = val;
201 1.1 ragge }
202 1.14 ragge #endif
203 1.1 ragge
204 1.5 ragge int
205 1.5 ragge ka43_cache_reset()
206 1.1 ragge {
207 1.5 ragge /*
208 1.5 ragge * resetting primary and secondary caches is done in three steps:
209 1.5 ragge * 1. disable both caches
210 1.5 ragge * 2. manually clear secondary cache
211 1.5 ragge * 3. enable both caches
212 1.5 ragge */
213 1.5 ragge ka43_cache_disable();
214 1.5 ragge ka43_cache_invalidate();
215 1.5 ragge ka43_cache_enable();
216 1.5 ragge
217 1.5 ragge printf("primary cache status: %b\n", mfpr(PR_PCSTS), KA43_PCSTS_BITS);
218 1.5 ragge printf("secondary cache status: %b\n", *ka43_creg, KA43_SESR_BITS);
219 1.1 ragge
220 1.1 ragge return (0);
221 1.5 ragge }
222 1.5 ragge
223 1.5 ragge int
224 1.5 ragge ka43_cache_disable()
225 1.5 ragge {
226 1.6 ragge int val;
227 1.1 ragge
228 1.1 ragge /*
229 1.5 ragge * first disable primary cache and clear error flags
230 1.1 ragge */
231 1.5 ragge mtpr(KA43_PCS_REFRESH, PR_PCSTS); /* disable primary cache */
232 1.5 ragge val = mfpr(PR_PCSTS);
233 1.5 ragge mtpr(val, PR_PCSTS); /* clear error flags */
234 1.5 ragge
235 1.1 ragge /*
236 1.5 ragge * now disable secondary cache and clear error flags
237 1.1 ragge */
238 1.5 ragge val = *ka43_creg & ~KA43_SESR_CENB; /* BICL !!! */
239 1.5 ragge *ka43_creg = val; /* disable secondary cache */
240 1.5 ragge val = KA43_SESR_SERR | KA43_SESR_LERR | KA43_SESR_CERR;
241 1.5 ragge *ka43_creg = val; /* clear error flags */
242 1.5 ragge
243 1.5 ragge return (0);
244 1.5 ragge }
245 1.5 ragge
246 1.5 ragge int
247 1.5 ragge ka43_cache_invalidate()
248 1.5 ragge {
249 1.5 ragge int i, val;
250 1.5 ragge
251 1.5 ragge val = KA43_PCTAG_PARITY; /* clear valid flag, set parity bit */
252 1.5 ragge for (i = 0; i < 256; i++) { /* 256 Quadword entries */
253 1.5 ragge mtpr(i*8, PR_PCIDX); /* write index of tag */
254 1.5 ragge mtpr(val, PR_PCTAG); /* write value into tag */
255 1.5 ragge }
256 1.5 ragge val = KA43_PCS_FLUSH | KA43_PCS_REFRESH;
257 1.5 ragge mtpr(val, PR_PCSTS); /* flush primary cache */
258 1.5 ragge
259 1.5 ragge /*
260 1.5 ragge * Rigel\'s secondary cache doesn\'t implement a valid-flag.
261 1.5 ragge * Thus we initialize all entries with out-of-range/dummy
262 1.5 ragge * addresses which will never be referenced (ie. never hit).
263 1.5 ragge * After enabling cache we also access 128K of memory starting
264 1.5 ragge * at 0x00 so that secondary cache will be filled with these
265 1.5 ragge * valid addresses...
266 1.5 ragge */
267 1.5 ragge val = 0xff;
268 1.5 ragge /* if (memory > 28 MB) val = 0x55; */
269 1.5 ragge for (i = 0; i < KA43_CT2_SIZE; i+= 4) { /* Quadword entries ?? */
270 1.5 ragge ka43_ctag[i/4] = val; /* reset upper and lower */
271 1.1 ragge }
272 1.5 ragge
273 1.5 ragge return (0);
274 1.1 ragge }
275 1.1 ragge
276 1.5 ragge
277 1.5 ragge int
278 1.5 ragge ka43_cache_enable()
279 1.1 ragge {
280 1.5 ragge volatile char *membase = (void*)0x80000000; /* physical 0x00 */
281 1.5 ragge int i, val;
282 1.5 ragge
283 1.5 ragge val = KA43_PCS_FLUSH | KA43_PCS_REFRESH;
284 1.5 ragge mtpr(val, PR_PCSTS); /* flush primary cache */
285 1.1 ragge
286 1.1 ragge /*
287 1.5 ragge * now we enable secondary cache and access first 128K of memory
288 1.5 ragge * so that secondary cache gets really initialized and holds
289 1.5 ragge * valid addresses/data...
290 1.1 ragge */
291 1.5 ragge *ka43_creg = KA43_SESR_CENB; /* enable secondary cache */
292 1.5 ragge for (i=0; i<128*1024; i++) {
293 1.5 ragge val += membase[i]; /* some dummy operation... */
294 1.1 ragge }
295 1.1 ragge
296 1.5 ragge val = KA43_PCS_ENABLE | KA43_PCS_REFRESH;
297 1.5 ragge mtpr(val, PR_PCSTS); /* enable primary cache */
298 1.5 ragge
299 1.5 ragge return (0);
300 1.1 ragge }
301 1.1 ragge
302 1.1 ragge void
303 1.18 ragge ka43_conf()
304 1.1 ragge {
305 1.18 ragge printf("cpu: KA43\n");
306 1.14 ragge ka43_cpu = (void *)vax_map_physmem(VS_REGS, 1);
307 1.14 ragge
308 1.14 ragge ka43_creg = (void *)vax_map_physmem(KA43_CH2_CREG, 1);
309 1.14 ragge ka43_ctag = (void *)vax_map_physmem(KA43_CT2_BASE,
310 1.14 ragge (KA43_CT2_SIZE/VAX_NBPG));
311 1.14 ragge
312 1.5 ragge /*
313 1.5 ragge * ka43_conf() gets called with MMU enabled, now it's save to
314 1.5 ragge * init/reset the caches.
315 1.5 ragge */
316 1.5 ragge ka43_cache_init();
317 1.14 ragge
318 1.14 ragge clk_adrshift = 1; /* Addressed at long's... */
319 1.14 ragge clk_tweak = 2; /* ...and shift two */
320 1.14 ragge clk_page = (short *)vax_map_physmem(VS_CLOCK, 1);
321 1.1 ragge }
322 1.1 ragge
323 1.1 ragge
324 1.1 ragge /*
325 1.5 ragge * The interface for communication with the LANCE ethernet controller
326 1.5 ragge * is setup in the xxx_steal_pages() routine. We decrease highest
327 1.5 ragge * available address by 64K and use this area as communication buffer.
328 1.1 ragge */
329 1.1 ragge
330 1.1 ragge void
331 1.1 ragge ka43_steal_pages()
332 1.1 ragge {
333 1.14 ragge int val;
334 1.1 ragge
335 1.1 ragge
336 1.5 ragge /*
337 1.5 ragge * if LANCE\'s io-buffer is above 16 MB, then the appropriate flag
338 1.5 ragge * in the parity control register has to be set (it works as an
339 1.5 ragge * additional address bit). In any case, don\'t enable CPEN and
340 1.5 ragge * DPEN in the PARCTL register, somewhow they are internally managed
341 1.5 ragge * by the RIGEL chip itself!?!
342 1.5 ragge */
343 1.5 ragge val = ka43_cpu->parctl & 0x03; /* read the old value */
344 1.5 ragge ka43_cpu->parctl = val; /* and write new value */
345 1.14 ragge }
346 1.14 ragge
347 1.14 ragge static void
348 1.14 ragge ka43_clrf()
349 1.14 ragge {
350 1.14 ragge struct ka43_clock *clk = (void *)clk_page;
351 1.1 ragge
352 1.14 ragge /*
353 1.14 ragge * Clear restart and boot in progress flags in the CPMBX.
354 1.14 ragge */
355 1.14 ragge clk->cpmbx = (clk->cpmbx & ~0xf0);
356 1.14 ragge }
357 1.14 ragge
358 1.14 ragge static void
359 1.14 ragge ka43_halt()
360 1.14 ragge {
361 1.14 ragge asm("movl $0xc, (%0)"::"r"((int)clk_page + 0x38)); /* Don't ask */
362 1.14 ragge asm("halt");
363 1.14 ragge }
364 1.14 ragge
365 1.14 ragge static void
366 1.14 ragge ka43_reboot(arg)
367 1.14 ragge int arg;
368 1.14 ragge {
369 1.14 ragge asm("movl $0xc, (%0)"::"r"((int)clk_page + 0x38)); /* Don't ask */
370 1.14 ragge asm("halt");
371 1.1 ragge }
372 1.14 ragge
373