ka43.c revision 1.30
1 /* $NetBSD: ka43.c,v 1.30 2005/12/24 22:45:40 perry Exp $ */ 2 /* 3 * Copyright (c) 1996 Ludd, University of Lule}, Sweden. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Ludd by Bertram Barth. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed at Ludd, University of 19 * Lule}, Sweden and its contributors. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: ka43.c,v 1.30 2005/12/24 22:45:40 perry Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/types.h> 40 #include <sys/device.h> 41 #include <sys/kernel.h> 42 #include <sys/systm.h> 43 44 #include <uvm/uvm_extern.h> 45 46 #include <machine/pte.h> 47 #include <machine/cpu.h> 48 #include <machine/mtpr.h> 49 #include <machine/sid.h> 50 #include <machine/pmap.h> 51 #include <machine/nexus.h> 52 #include <machine/uvax.h> 53 #include <machine/vsbus.h> 54 #include <machine/ka43.h> 55 #include <machine/clock.h> 56 57 static void ka43_conf __P((void)); 58 static void ka43_steal_pages __P((void)); 59 60 static int ka43_mchk __P((caddr_t)); 61 static void ka43_memerr __P((void)); 62 #if 0 63 static void ka43_clear_errors __P((void)); 64 #endif 65 static int ka43_cache_init __P((void)); /* "int mapen" as argument? */ 66 static int ka43_cache_reset __P((void)); 67 static int ka43_cache_enable __P((void)); 68 static int ka43_cache_disable __P((void)); 69 static int ka43_cache_invalidate __P((void)); 70 static void ka43_halt __P((void)); 71 static void ka43_reboot __P((int)); 72 static void ka43_clrf __P((void)); 73 74 75 struct cpu_dep ka43_calls = { 76 ka43_steal_pages, 77 ka43_mchk, 78 ka43_memerr, 79 ka43_conf, 80 chip_clkread, 81 chip_clkwrite, 82 7, /* 7.6 VUP */ 83 2, /* SCB pages */ 84 ka43_halt, 85 ka43_reboot, 86 ka43_clrf, 87 NULL, 88 CPU_RAISEIPL, 89 }; 90 91 /* 92 * ka43_steal_pages() is called with MMU disabled, after that call MMU gets 93 * enabled. Thus we initialize these four pointers with physical addresses, 94 * but before leving ka43_steal_pages() we reset them to virtual addresses. 95 */ 96 static volatile struct ka43_cpu *ka43_cpu = (void*)KA43_CPU_BASE; 97 static volatile u_int *ka43_creg = (void*)KA43_CH2_CREG; 98 static volatile u_int *ka43_ctag = (void*)KA43_CT2_BASE; 99 100 #define KA43_MC_RESTART 0x00008000 /* Restart possible*/ 101 #define KA43_PSL_FPDONE 0x00010000 /* First Part Done */ 102 103 struct ka43_mcframe { /* Format of RigelMAX machine check frame: */ 104 int mc43_bcnt; /* byte count, always 24 (0x18) */ 105 int mc43_code; /* machine check type code and restart bit */ 106 int mc43_addr; /* most recent (faulting?) virtual address */ 107 int mc43_viba; /* contents of VIBA register */ 108 int mc43_sisr; /* ICCS bit 6 and SISR bits 15:0 */ 109 int mc43_istate; /* internal state */ 110 int mc43_sc; /* shift count register */ 111 int mc43_pc; /* trapped PC */ 112 int mc43_psl; /* trapped PSL */ 113 }; 114 115 static const char *ka43_mctype[] = { 116 "no error (0)", /* Code 0: No error */ 117 "FPA: protocol error", /* Code 1-5: FPA errors */ 118 "FPA: illegal opcode", 119 "FPA: operand parity error", 120 "FPA: unknown status", 121 "FPA: result parity error", 122 "unused (6)", /* Code 6-7: Unused */ 123 "unused (7)", 124 "MMU error (TLB miss)", /* Code 8-9: MMU errors */ 125 "MMU error (TLB hit)", 126 "HW interrupt at unused IPL", /* Code 10: Interrupt error */ 127 "MOVCx impossible state", /* Code 11-13: Microcode errors */ 128 "undefined trap code (i-box)", 129 "undefined control store address", 130 "unused (14)", /* Code 14-15: Unused */ 131 "unused (15)", 132 "PC tag or data parity error", /* Code 16: Cache error */ 133 "data bus parity error", /* Code 17: Read error */ 134 "data bus error (NXM)", /* Code 18: Write error */ 135 "undefined data bus state", /* Code 19: Bus error */ 136 }; 137 #define MC43_MAX 19 138 139 static int ka43_error_count = 0; 140 141 int 142 ka43_mchk(addr) 143 caddr_t addr; 144 { 145 register struct ka43_mcframe *mcf = (void*)addr; 146 147 mtpr(0x00, PR_MCESR); /* Acknowledge the machine check */ 148 printf("machine check %d (0x%x)\n", mcf->mc43_code, mcf->mc43_code); 149 printf("reason: %s\n", ka43_mctype[mcf->mc43_code & 0xff]); 150 if (++ka43_error_count > 10) { 151 printf("error_count exceeded: %d\n", ka43_error_count); 152 return (-1); 153 } 154 155 /* 156 * If either the Restart flag is set or the First-Part-Done flag 157 * is set, and the TRAP2 (double error) bit is not set, then the 158 * error is recoverable. 159 */ 160 if (mfpr(PR_PCSTS) & KA43_PCS_TRAP2) { 161 printf("TRAP2 (double error) in ka43_mchk.\n"); 162 panic("unrecoverable state in ka43_mchk."); 163 return (-1); 164 } 165 if ((mcf->mc43_code & KA43_MC_RESTART) || 166 (mcf->mc43_psl & KA43_PSL_FPDONE)) { 167 printf("ka43_mchk: recovering from machine-check.\n"); 168 ka43_cache_reset(); /* reset caches */ 169 return (0); /* go on; */ 170 } 171 172 /* 173 * Unknown error state, panic/halt the machine! 174 */ 175 printf("ka43_mchk: unknown error state!\n"); 176 return (-1); 177 } 178 179 void 180 ka43_memerr() 181 { 182 char sbuf[256]; 183 184 /* 185 * Don\'t know what to do here. So just print some messages 186 * and try to go on... 187 */ 188 189 printf("memory error!\n"); 190 191 bitmask_snprintf(mfpr(PR_PCSTS), KA43_PCSTS_BITS, sbuf, sizeof(sbuf)); 192 printf("primary cache status: %s\n", sbuf); 193 194 bitmask_snprintf(*ka43_creg, KA43_SESR_BITS, sbuf, sizeof(sbuf)); 195 printf("secondary cache status: %s\n", sbuf); 196 } 197 198 int 199 ka43_cache_init() 200 { 201 return (ka43_cache_reset()); 202 } 203 204 #if 0 205 void 206 ka43_clear_errors() 207 { 208 int val = *ka43_creg; 209 val |= KA43_SESR_SERR | KA43_SESR_LERR | KA43_SESR_CERR; 210 *ka43_creg = val; 211 } 212 #endif 213 214 int 215 ka43_cache_reset() 216 { 217 char sbuf[256]; 218 219 /* 220 * resetting primary and secondary caches is done in three steps: 221 * 1. disable both caches 222 * 2. manually clear secondary cache 223 * 3. enable both caches 224 */ 225 ka43_cache_disable(); 226 ka43_cache_invalidate(); 227 ka43_cache_enable(); 228 229 bitmask_snprintf(mfpr(PR_PCSTS), KA43_PCSTS_BITS, sbuf, sizeof(sbuf)); 230 printf("primary cache status: %s\n", sbuf); 231 232 bitmask_snprintf(*ka43_creg, KA43_SESR_BITS, sbuf, sizeof(sbuf)); 233 printf("secondary cache status: %s\n", sbuf); 234 235 return (0); 236 } 237 238 int 239 ka43_cache_disable() 240 { 241 int val; 242 243 /* 244 * first disable primary cache and clear error flags 245 */ 246 mtpr(KA43_PCS_REFRESH, PR_PCSTS); /* disable primary cache */ 247 val = mfpr(PR_PCSTS); 248 mtpr(val, PR_PCSTS); /* clear error flags */ 249 250 /* 251 * now disable secondary cache and clear error flags 252 */ 253 val = *ka43_creg & ~KA43_SESR_CENB; /* BICL !!! */ 254 *ka43_creg = val; /* disable secondary cache */ 255 val = KA43_SESR_SERR | KA43_SESR_LERR | KA43_SESR_CERR; 256 *ka43_creg = val; /* clear error flags */ 257 258 return (0); 259 } 260 261 int 262 ka43_cache_invalidate() 263 { 264 int i, val; 265 266 val = KA43_PCTAG_PARITY; /* clear valid flag, set parity bit */ 267 for (i = 0; i < 256; i++) { /* 256 Quadword entries */ 268 mtpr(i*8, PR_PCIDX); /* write index of tag */ 269 mtpr(val, PR_PCTAG); /* write value into tag */ 270 } 271 val = KA43_PCS_FLUSH | KA43_PCS_REFRESH; 272 mtpr(val, PR_PCSTS); /* flush primary cache */ 273 274 /* 275 * Rigel\'s secondary cache doesn\'t implement a valid-flag. 276 * Thus we initialize all entries with out-of-range/dummy 277 * addresses which will never be referenced (ie. never hit). 278 * After enabling cache we also access 128K of memory starting 279 * at 0x00 so that secondary cache will be filled with these 280 * valid addresses... 281 */ 282 val = 0xff; 283 /* if (memory > 28 MB) val = 0x55; */ 284 for (i = 0; i < KA43_CT2_SIZE; i+= 4) { /* Quadword entries ?? */ 285 ka43_ctag[i/4] = val; /* reset upper and lower */ 286 } 287 288 return (0); 289 } 290 291 292 int 293 ka43_cache_enable() 294 { 295 volatile char *membase = (void*)0x80000000; /* physical 0x00 */ 296 int i, val; 297 298 val = KA43_PCS_FLUSH | KA43_PCS_REFRESH; 299 mtpr(val, PR_PCSTS); /* flush primary cache */ 300 301 /* 302 * now we enable secondary cache and access first 128K of memory 303 * so that secondary cache gets really initialized and holds 304 * valid addresses/data... 305 */ 306 *ka43_creg = KA43_SESR_CENB; /* enable secondary cache */ 307 for (i=0; i<128*1024; i++) { 308 val += membase[i]; /* some dummy operation... */ 309 } 310 311 val = KA43_PCS_ENABLE | KA43_PCS_REFRESH; 312 mtpr(val, PR_PCSTS); /* enable primary cache */ 313 314 return (0); 315 } 316 317 void 318 ka43_conf() 319 { 320 printf("cpu: KA43\n"); 321 ka43_cpu = (void *)vax_map_physmem(VS_REGS, 1); 322 323 ka43_creg = (void *)vax_map_physmem(KA43_CH2_CREG, 1); 324 ka43_ctag = (void *)vax_map_physmem(KA43_CT2_BASE, 325 (KA43_CT2_SIZE/VAX_NBPG)); 326 327 /* 328 * ka43_conf() gets called with MMU enabled, now it's save to 329 * init/reset the caches. 330 */ 331 ka43_cache_init(); 332 333 clk_adrshift = 1; /* Addressed at long's... */ 334 clk_tweak = 2; /* ...and shift two */ 335 clk_page = (short *)vax_map_physmem(VS_CLOCK, 1); 336 } 337 338 339 /* 340 * The interface for communication with the LANCE ethernet controller 341 * is setup in the xxx_steal_pages() routine. We decrease highest 342 * available address by 64K and use this area as communication buffer. 343 */ 344 345 void 346 ka43_steal_pages() 347 { 348 int val; 349 350 351 /* 352 * if LANCE\'s io-buffer is above 16 MB, then the appropriate flag 353 * in the parity control register has to be set (it works as an 354 * additional address bit). In any case, don\'t enable CPEN and 355 * DPEN in the PARCTL register, somewhow they are internally managed 356 * by the RIGEL chip itself!?! 357 */ 358 val = ka43_cpu->parctl & 0x03; /* read the old value */ 359 ka43_cpu->parctl = val; /* and write new value */ 360 } 361 362 static void 363 ka43_clrf() 364 { 365 volatile struct ka43_clock *clk = (volatile void *)clk_page; 366 367 /* 368 * Clear restart and boot in progress flags in the CPMBX. 369 * The cpmbx is split into two 4-bit fields. 370 * One for the current restart/boot in progress flags, and 371 * one for the permanent halt flag. 372 * The restart/boot in progress flag is also used as the action request 373 * for the CPU at a halt. /BQT 374 */ 375 clk->req = 0; 376 } 377 378 static void 379 ka43_halt() 380 { 381 volatile struct ka43_clock *clk = (volatile void *)clk_page; 382 clk->req = 3; /* 3 is halt. */ 383 __asm("halt"); 384 } 385 386 static void 387 ka43_reboot(arg) 388 int arg; 389 { 390 volatile struct ka43_clock *clk = (volatile void *)clk_page; 391 clk->req = 2; /* 2 is reboot. */ 392 __asm("halt"); 393 } 394 395
Indexes created Wed Sep 24 02:09:48 GMT 2025