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specialreg.h revision 1.23.10.1
      1  1.23.10.1      yamt /*	$NetBSD: specialreg.h,v 1.23.10.1 2009/05/04 08:12:09 yamt Exp $	*/
      2        1.1      fvdl 
      3        1.1      fvdl /*-
      4        1.1      fvdl  * Copyright (c) 1991 The Regents of the University of California.
      5        1.1      fvdl  * All rights reserved.
      6        1.1      fvdl  *
      7        1.1      fvdl  * Redistribution and use in source and binary forms, with or without
      8        1.1      fvdl  * modification, are permitted provided that the following conditions
      9        1.1      fvdl  * are met:
     10        1.1      fvdl  * 1. Redistributions of source code must retain the above copyright
     11        1.1      fvdl  *    notice, this list of conditions and the following disclaimer.
     12        1.1      fvdl  * 2. Redistributions in binary form must reproduce the above copyright
     13        1.1      fvdl  *    notice, this list of conditions and the following disclaimer in the
     14        1.1      fvdl  *    documentation and/or other materials provided with the distribution.
     15        1.3       agc  * 3. Neither the name of the University nor the names of its contributors
     16        1.1      fvdl  *    may be used to endorse or promote products derived from this software
     17        1.1      fvdl  *    without specific prior written permission.
     18        1.1      fvdl  *
     19        1.1      fvdl  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     20        1.1      fvdl  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     21        1.1      fvdl  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     22        1.1      fvdl  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     23        1.1      fvdl  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     24        1.1      fvdl  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     25        1.1      fvdl  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     26        1.1      fvdl  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     27        1.1      fvdl  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     28        1.1      fvdl  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     29        1.1      fvdl  * SUCH DAMAGE.
     30        1.1      fvdl  *
     31        1.1      fvdl  *	@(#)specialreg.h	7.1 (Berkeley) 5/9/91
     32        1.1      fvdl  */
     33        1.1      fvdl 
     34        1.1      fvdl /*
     35        1.1      fvdl  * Bits in 386 special registers:
     36        1.1      fvdl  */
     37        1.1      fvdl #define	CR0_PE	0x00000001	/* Protected mode Enable */
     38        1.1      fvdl #define	CR0_MP	0x00000002	/* "Math" Present (NPX or NPX emulator) */
     39        1.1      fvdl #define	CR0_EM	0x00000004	/* EMulate non-NPX coproc. (trap ESC only) */
     40        1.1      fvdl #define	CR0_TS	0x00000008	/* Task Switched (if MP, trap ESC and WAIT) */
     41        1.1      fvdl #define	CR0_ET	0x00000010	/* Extension Type (387 (if set) vs 287) */
     42        1.1      fvdl #define	CR0_PG	0x80000000	/* PaGing enable */
     43        1.1      fvdl 
     44        1.1      fvdl /*
     45        1.1      fvdl  * Bits in 486 special registers:
     46        1.1      fvdl  */
     47        1.1      fvdl #define CR0_NE	0x00000020	/* Numeric Error enable (EX16 vs IRQ13) */
     48        1.1      fvdl #define CR0_WP	0x00010000	/* Write Protect (honor PG_RW in all modes) */
     49        1.1      fvdl #define CR0_AM	0x00040000	/* Alignment Mask (set to enable AC flag) */
     50        1.1      fvdl #define	CR0_NW	0x20000000	/* Not Write-through */
     51        1.1      fvdl #define	CR0_CD	0x40000000	/* Cache Disable */
     52        1.1      fvdl 
     53        1.1      fvdl /*
     54        1.1      fvdl  * Cyrix 486 DLC special registers, accessible as IO ports.
     55        1.1      fvdl  */
     56        1.1      fvdl #define CCR0	0xc0		/* configuration control register 0 */
     57        1.1      fvdl #define CCR0_NC0	0x01	/* first 64K of each 1M memory region is non-cacheable */
     58        1.1      fvdl #define CCR0_NC1	0x02	/* 640K-1M region is non-cacheable */
     59        1.1      fvdl #define CCR0_A20M	0x04	/* enables A20M# input pin */
     60        1.1      fvdl #define CCR0_KEN	0x08	/* enables KEN# input pin */
     61        1.1      fvdl #define CCR0_FLUSH	0x10	/* enables FLUSH# input pin */
     62        1.1      fvdl #define CCR0_BARB	0x20	/* flushes internal cache when entering hold state */
     63        1.1      fvdl #define CCR0_CO		0x40	/* cache org: 1=direct mapped, 0=2x set assoc */
     64        1.1      fvdl #define CCR0_SUSPEND	0x80	/* enables SUSP# and SUSPA# pins */
     65        1.1      fvdl 
     66        1.1      fvdl #define CCR1	0xc1		/* configuration control register 1 */
     67        1.1      fvdl #define CCR1_RPL	0x01	/* enables RPLSET and RPLVAL# pins */
     68        1.1      fvdl /* the remaining 7 bits of this register are reserved */
     69        1.1      fvdl 
     70        1.1      fvdl /*
     71        1.1      fvdl  * bits in the pentiums %cr4 register:
     72        1.1      fvdl  */
     73        1.1      fvdl 
     74        1.1      fvdl #define CR4_VME	0x00000001	/* virtual 8086 mode extension enable */
     75        1.1      fvdl #define CR4_PVI 0x00000002	/* protected mode virtual interrupt enable */
     76        1.1      fvdl #define CR4_TSD 0x00000004	/* restrict RDTSC instruction to cpl 0 only */
     77        1.1      fvdl #define CR4_DE	0x00000008	/* debugging extension */
     78        1.1      fvdl #define CR4_PSE	0x00000010	/* large (4MB) page size enable */
     79        1.1      fvdl #define CR4_PAE 0x00000020	/* physical address extension enable */
     80        1.1      fvdl #define CR4_MCE	0x00000040	/* machine check enable */
     81        1.1      fvdl #define CR4_PGE	0x00000080	/* page global enable */
     82        1.1      fvdl #define CR4_PCE	0x00000100	/* enable RDPMC instruction for all cpls */
     83        1.1      fvdl #define CR4_OSFXSR	0x00000200	/* enable fxsave/fxrestor and SSE */
     84        1.1      fvdl #define CR4_OSXMMEXCPT	0x00000400	/* enable unmasked SSE exceptions */
     85        1.1      fvdl 
     86        1.1      fvdl /*
     87        1.4     soren  * CPUID "features" bits in %edx
     88        1.1      fvdl  */
     89        1.1      fvdl 
     90  1.23.10.1      yamt /* Fn80000001 %edx feature */
     91        1.1      fvdl #define	CPUID_FPU	0x00000001	/* processor has an FPU? */
     92        1.1      fvdl #define	CPUID_VME	0x00000002	/* has virtual mode (%cr4's VME/PVI) */
     93        1.1      fvdl #define	CPUID_DE	0x00000004	/* has debugging extension */
     94        1.1      fvdl #define	CPUID_PSE	0x00000008	/* has page 4MB page size extension */
     95        1.1      fvdl #define	CPUID_TSC	0x00000010	/* has time stamp counter */
     96        1.1      fvdl #define	CPUID_MSR	0x00000020	/* has mode specific registers */
     97        1.1      fvdl #define	CPUID_PAE	0x00000040	/* has phys address extension */
     98        1.1      fvdl #define	CPUID_MCE	0x00000080	/* has machine check exception */
     99        1.1      fvdl #define	CPUID_CX8	0x00000100	/* has CMPXCHG8B instruction */
    100        1.1      fvdl #define	CPUID_APIC	0x00000200	/* has enabled APIC */
    101        1.1      fvdl #define	CPUID_B10	0x00000400	/* reserved, MTRR */
    102        1.1      fvdl #define	CPUID_SEP	0x00000800	/* has SYSENTER/SYSEXIT extension */
    103        1.1      fvdl #define	CPUID_MTRR	0x00001000	/* has memory type range register */
    104        1.1      fvdl #define	CPUID_PGE	0x00002000	/* has page global extension */
    105        1.1      fvdl #define	CPUID_MCA	0x00004000	/* has machine check architecture */
    106        1.1      fvdl #define	CPUID_CMOV	0x00008000	/* has CMOVcc instruction */
    107        1.1      fvdl #define	CPUID_PAT	0x00010000	/* Page Attribute Table */
    108        1.1      fvdl #define	CPUID_PSE36	0x00020000	/* 36-bit PSE */
    109        1.1      fvdl #define	CPUID_PN	0x00040000	/* processor serial number */
    110        1.1      fvdl #define	CPUID_CFLUSH	0x00080000	/* CFLUSH insn supported */
    111        1.1      fvdl #define	CPUID_B20	0x00100000	/* reserved */
    112        1.1      fvdl #define	CPUID_DS	0x00200000	/* Debug Store */
    113        1.1      fvdl #define	CPUID_ACPI	0x00400000	/* ACPI performance modulation regs */
    114        1.1      fvdl #define	CPUID_MMX	0x00800000	/* MMX supported */
    115        1.1      fvdl #define	CPUID_FXSR	0x01000000	/* fast FP/MMX save/restore */
    116        1.1      fvdl #define	CPUID_SSE	0x02000000	/* streaming SIMD extensions */
    117        1.1      fvdl #define	CPUID_SSE2	0x04000000	/* streaming SIMD extensions #2 */
    118        1.1      fvdl #define	CPUID_SS	0x08000000	/* self-snoop */
    119        1.1      fvdl #define	CPUID_HTT	0x10000000	/* Hyper-Threading Technology */
    120        1.1      fvdl #define	CPUID_TM	0x20000000	/* thermal monitor (TCC) */
    121        1.1      fvdl #define	CPUID_IA64	0x40000000	/* IA-64 architecture */
    122        1.1      fvdl #define	CPUID_SBF	0x80000000	/* signal break on FERR */
    123        1.1      fvdl 
    124        1.1      fvdl #define CPUID_FLAGS1	"\20\1FPU\2VME\3DE\4PSE\5TSC\6MSR\7PAE" \
    125        1.1      fvdl 			    "\10MCE\11CX8\12APIC\13B10\14SEP\15MTRR"
    126        1.1      fvdl #define CPUID_MASK1	0x00001fff
    127        1.1      fvdl #define CPUID_FLAGS2	"\20\16PGE\17MCA\20CMOV\21PAT\22PSE36\23PN\24CFLUSH" \
    128        1.1      fvdl 			    "\25B20\26DS\27ACPI\30MMX"
    129        1.1      fvdl #define CPUID_MASK2	0x00ffe000
    130        1.1      fvdl #define CPUID_FLAGS3	"\20\31FXSR\32SSE\33SSE2\34SS\35HTT\36TM\37IA64\40SBF"
    131        1.1      fvdl #define CPUID_MASK3	0xff000000
    132        1.1      fvdl 
    133        1.1      fvdl /*
    134        1.8        he  * CPUID Intel extended features
    135        1.8        he  */
    136        1.8        he #define CPUID_SYSCALL	0x00000800	/* SYSCALL/SYSRET */
    137       1.10      cube #define CPUID_XD	0x00100000	/* Execute Disable */
    138        1.8        he #define CPUID_EM64T	0x20000000	/* Intel EM64T */
    139        1.8        he 
    140  1.23.10.1      yamt #define CPUID_INTEL_MASK4	0x20100800
    141  1.23.10.1      yamt #define CPUID_INTEL_FLAGS4	"\20\14SYSCALL/SYSRET\25XD\36EM64T"
    142        1.8        he 
    143        1.8        he /*
    144        1.1      fvdl  * AMD/VIA processor specific flags.
    145        1.1      fvdl  */
    146        1.1      fvdl 
    147  1.23.10.1      yamt /*	CPUID_SYSCALL			   SYSCALL/SYSRET */
    148        1.1      fvdl #define CPUID_MPC	0x00080000	/* Multiprocessing Capable */
    149        1.5  drochner #define CPUID_NOX	0x00100000	/* No Execute Page Protection */
    150        1.1      fvdl #define CPUID_MMXX	0x00400000	/* AMD MMX Extensions */
    151  1.23.10.1      yamt #define CPUID_FFXSR	0x02000000	/* FXSAVE/FXSTOR Extensions */
    152  1.23.10.1      yamt #define CPUID_P1GB	0x04000000	/* 1GB Large Page Support */
    153       1.18     njoly #define CPUID_RDTSCP	0x08000000	/* Read TSC Pair Instruction */
    154  1.23.10.1      yamt /*	CPUID_EM64T			   Long mode */
    155        1.1      fvdl #define CPUID_3DNOW2	0x40000000	/* 3DNow! Instruction Extension */
    156        1.1      fvdl #define CPUID_3DNOW	0x80000000	/* 3DNow! Instructions */
    157        1.1      fvdl 
    158  1.23.10.1      yamt #define CPUID_EXT_FLAGS	"\20\14SCALL/RET\24MPC\25NOX\27MXX\32FFXSR\33P1GB" \
    159  1.23.10.1      yamt 			    "\34RDTSCP\36LONG\0373DNOW2\0403DNOW"
    160  1.23.10.1      yamt 
    161  1.23.10.1      yamt 
    162  1.23.10.1      yamt /* AMD Fn80000001 %ecx features */
    163  1.23.10.1      yamt #define CPUID_LAHF	0x00000001	/* LAHF/SAHF instruction */
    164  1.23.10.1      yamt #define CPUID_CMPLEGACY	0x00000002	/* Compare Legacy */
    165  1.23.10.1      yamt #define CPUID_SVM	0x00000004	/* Secure Virtual Machine */
    166  1.23.10.1      yamt #define CPUID_EAPIC	0x00000008	/* Extended APIC space */
    167  1.23.10.1      yamt #define CPUID_ALTMOVCR0	0x00000010	/* Lock Mov Cr0 */
    168  1.23.10.1      yamt #define CPUID_LZCNT	0x00000020	/* LZCNT instruction */
    169  1.23.10.1      yamt #define CPUID_SSE4A	0x00000040	/* SSE4A instruction set */
    170  1.23.10.1      yamt #define CPUID_MISALIGNSSE 0x00000080	/* Misaligned SSE */
    171  1.23.10.1      yamt #define CPUID_3DNOWPF	0x00000100	/* 3DNow Prefetch */
    172  1.23.10.1      yamt #define CPUID_OSVW	0x00000200	/* OS visible workarounds */
    173  1.23.10.1      yamt #define CPUID_IBS	0x00000400	/* Instruction Based Sampling */
    174  1.23.10.1      yamt #define CPUID_SSE5	0x00000800	/* SSE5 instruction set */
    175  1.23.10.1      yamt #define CPUID_SKINIT	0x00001000	/* SKINIT */
    176  1.23.10.1      yamt #define CPUID_WDT	0x00002000	/* watchdog timer support */
    177  1.23.10.1      yamt 
    178  1.23.10.1      yamt #define CPUID_AMD_MASK4	0x00003fff
    179  1.23.10.1      yamt #define CPUID_AMD_FLAGS4	"\20\1LAHF\2CMPLEGACY\3SVM\4EAPIC\5ALTMOVCR0" \
    180  1.23.10.1      yamt 				    "\6LZCNT\7SSE4A\10MISALIGNSSE" \
    181  1.23.10.1      yamt 				    "\0113DNOWPREFETCH\12OSVW\13IBS" \
    182  1.23.10.1      yamt 				    "\14SSE5\15SKINIT\16WDT"
    183  1.23.10.1      yamt 
    184  1.23.10.1      yamt /* AMD Fn8000000a %edx features (SVM features) */
    185  1.23.10.1      yamt #define	CPUID_AMD_SVM_NP		0x00000001
    186  1.23.10.1      yamt #define	CPUID_AMD_SVM_LbrVirt		0x00000002
    187  1.23.10.1      yamt #define	CPUID_AMD_SVM_SVML		0x00000004
    188  1.23.10.1      yamt #define	CPUID_AMD_SVM_NRIPS		0x00000008
    189  1.23.10.1      yamt #define	CPUID_AMD_SVM_Ssse3Sse5Dis	0x00000200
    190  1.23.10.1      yamt #define	CPUID_AMD_SVM_FLAGS	 "\20\1NP\2LbrVirt\3SVML\4NRIPS\12Ssse3Sse5Dis"
    191  1.23.10.1      yamt 
    192  1.23.10.1      yamt /*
    193  1.23.10.1      yamt  * AMD Advanced Power Management
    194  1.23.10.1      yamt  * CPUID Fn8000_0007 %edx
    195  1.23.10.1      yamt  */
    196  1.23.10.1      yamt 
    197  1.23.10.1      yamt #define CPUID_APM_TS	0x00000001	/* Temperature Sensor */
    198  1.23.10.1      yamt #define CPUID_APM_FID	0x00000002	/* Frequency ID control */
    199  1.23.10.1      yamt #define CPUID_APM_VID	0x00000004	/* Voltage ID control */
    200  1.23.10.1      yamt #define CPUID_APM_TTP	0x00000008	/* THERMTRIP (PCI F3xE4 register) */
    201  1.23.10.1      yamt #define CPUID_APM_HTC	0x00000010	/* Hardware thermal control (HTC) */
    202  1.23.10.1      yamt #define CPUID_APM_STC	0x00000020	/* Software thermal control (STC) */
    203  1.23.10.1      yamt #define CPUID_APM_100	0x00000040	/* 100MHz multiplier control */
    204  1.23.10.1      yamt #define CPUID_APM_HWP	0x00000080	/* HW P-State control */
    205  1.23.10.1      yamt #define CPUID_APM_TSC	0x00000100	/* TSC invariant */
    206  1.23.10.1      yamt 
    207  1.23.10.1      yamt #define CPUID_APM_FLAGS			"\20\1TS\2FID\3VID\4TTP\5HTC\6STC\007100\10HWP\11TSC"
    208  1.23.10.1      yamt 
    209        1.1      fvdl 
    210        1.4     soren /*
    211       1.17  christos  * Centaur Extended Feature flags
    212       1.15    daniel  */
    213       1.17  christos #define CPUID_VIA_HAS_RNG	0x00000004	/* Random number generator */
    214       1.17  christos #define CPUID_VIA_DO_RNG	0x00000008
    215       1.17  christos #define CPUID_VIA_HAS_ACE	0x00000040	/* AES Encryption */
    216       1.17  christos #define CPUID_VIA_DO_ACE	0x00000080
    217       1.17  christos #define CPUID_VIA_HAS_ACE2	0x00000100	/* AES+CTR instructions */
    218       1.17  christos #define CPUID_VIA_DO_ACE2	0x00000200
    219       1.17  christos #define CPUID_VIA_HAS_PHE	0x00000400	/* SHA1+SHA256 HMAC */
    220       1.17  christos #define CPUID_VIA_DO_PHE	0x00000800
    221       1.17  christos #define CPUID_VIA_HAS_PMM	0x00001000	/* RSA Instructions */
    222       1.17  christos #define CPUID_VIA_DO_PMM	0x00002000
    223       1.15    daniel 
    224       1.17  christos #define CPUID_FLAGS_PADLOCK	"\20\3RNG\7AES\11AES/CTR\13SHA1/SHA256\15RSA"
    225       1.15    daniel 
    226       1.15    daniel /*
    227  1.23.10.1      yamt  * CPUID "features" bits in Fn00000001 %ecx
    228        1.4     soren  */
    229        1.4     soren 
    230        1.6      joda #define	CPUID2_SSE3	0x00000001	/* Streaming SIMD Extensions 3 */
    231       1.23   xtraeme #define	CPUID2_DTES64	0x00000004	/* 64-bit Debug Trace */
    232        1.6      joda #define	CPUID2_MONITOR	0x00000008	/* MONITOR/MWAIT instructions */
    233        1.6      joda #define	CPUID2_DS_CPL	0x00000010	/* CPL Qualified Debug Store */
    234        1.7  drochner #define	CPUID2_VMX	0x00000020	/* Virtual Machine Extensions */
    235       1.16   xtraeme #define	CPUID2_SMX	0x00000040	/* Safer Mode Extensions */
    236        1.6      joda #define	CPUID2_EST	0x00000080	/* Enhanced SpeedStep Technology */
    237        1.6      joda #define	CPUID2_TM2	0x00000100	/* Thermal Monitor 2 */
    238       1.22  drochner #define CPUID2_SSSE3	0x00000200	/* Supplemental SSE3 */
    239        1.4     soren #define	CPUID2_CID	0x00000400	/* Context ID */
    240       1.16   xtraeme #define	CPUID2_CX16	0x00002000	/* has CMPXCHG16B instruction */
    241        1.7  drochner #define	CPUID2_xTPR	0x00004000	/* Task Priority Messages disabled? */
    242       1.16   xtraeme #define	CPUID2_PDCM	0x00008000	/* Perf/Debug Capability MSR */
    243       1.16   xtraeme #define	CPUID2_DCA	0x00040000	/* Direct Cache Access */
    244       1.23   xtraeme #define	CPUID2_SSE41	0x00080000	/* Streaming SIMD Extensions 4.1 */
    245       1.23   xtraeme #define	CPUID2_SSE42	0x00100000	/* Streaming SIMD Extensions 4.2 */
    246       1.23   xtraeme #define	CPUID2_X2APIC	0x00200000	/* xAPIC Extensions */
    247       1.23   xtraeme #define	CPUID2_POPCNT	0x00800000
    248       1.23   xtraeme 
    249       1.23   xtraeme #define CPUID2_FLAGS "\20\1SSE3\3DTES64\4MONITOR\5DS-CPL\6VMX\7SMX\10EST" \
    250       1.23   xtraeme 			"\11TM2\12SSSE3\13CID\16CX16\17xTPR\20PDCM\23DCA" \
    251       1.23   xtraeme 			"\24SSE41\25SSE42\26X2APIC\30POPCNT"
    252        1.4     soren 
    253       1.14  christos #define CPUID2FAMILY(cpuid)	(((cpuid) >> 8) & 0xf)
    254       1.14  christos #define CPUID2MODEL(cpuid)	(((cpuid) >> 4) & 0xf)
    255       1.14  christos #define CPUID2STEPPING(cpuid)	((cpuid) & 0xf)
    256       1.14  christos 
    257       1.14  christos /* Extended family and model are defined on amd64 processors */
    258       1.14  christos #define CPUID2EXTFAMILY(cpuid)	(((cpuid) >> 20) & 0xff)
    259       1.14  christos #define CPUID2EXTMODEL(cpuid)	(((cpuid) >> 16) & 0xf)
    260        1.2      fvdl 
    261        1.1      fvdl /*
    262        1.1      fvdl  * Model-specific registers for the i386 family
    263        1.1      fvdl  */
    264        1.1      fvdl #define MSR_P5_MC_ADDR		0x000	/* P5 only */
    265        1.1      fvdl #define MSR_P5_MC_TYPE		0x001	/* P5 only */
    266        1.1      fvdl #define MSR_TSC			0x010
    267        1.1      fvdl #define	MSR_CESR		0x011	/* P5 only (trap on P6) */
    268        1.1      fvdl #define	MSR_CTR0		0x012	/* P5 only (trap on P6) */
    269        1.1      fvdl #define	MSR_CTR1		0x013	/* P5 only (trap on P6) */
    270        1.1      fvdl #define MSR_APICBASE		0x01b
    271        1.1      fvdl #define MSR_EBL_CR_POWERON	0x02a
    272       1.11   xtraeme #define MSR_EBC_FREQUENCY_ID	0x02c	/* PIV only */
    273        1.1      fvdl #define	MSR_TEST_CTL		0x033
    274        1.1      fvdl #define MSR_BIOS_UPDT_TRIG	0x079
    275        1.1      fvdl #define	MSR_BBL_CR_D0		0x088	/* PII+ only */
    276        1.1      fvdl #define	MSR_BBL_CR_D1		0x089	/* PII+ only */
    277        1.1      fvdl #define	MSR_BBL_CR_D2		0x08a	/* PII+ only */
    278        1.1      fvdl #define MSR_BIOS_SIGN		0x08b
    279        1.1      fvdl #define MSR_PERFCTR0		0x0c1
    280        1.1      fvdl #define MSR_PERFCTR1		0x0c2
    281       1.11   xtraeme #define MSR_FSB_FREQ		0x0cd	/* Core Duo/Solo only */
    282       1.21   xtraeme #define MSR_IA32_EXT_CONFIG	0x0ee	/* Undocumented. Core Solo/Duo only */
    283        1.1      fvdl #define MSR_MTRRcap		0x0fe
    284        1.1      fvdl #define	MSR_BBL_CR_ADDR		0x116	/* PII+ only */
    285        1.1      fvdl #define	MSR_BBL_CR_DECC		0x118	/* PII+ only */
    286        1.1      fvdl #define	MSR_BBL_CR_CTL		0x119	/* PII+ only */
    287        1.1      fvdl #define	MSR_BBL_CR_TRIG		0x11a	/* PII+ only */
    288        1.1      fvdl #define	MSR_BBL_CR_BUSY		0x11b	/* PII+ only */
    289        1.1      fvdl #define	MSR_BBL_CR_CTR3		0x11e	/* PII+ only */
    290        1.1      fvdl #define	MSR_SYSENTER_CS		0x174 	/* PII+ only */
    291        1.1      fvdl #define	MSR_SYSENTER_ESP	0x175 	/* PII+ only */
    292        1.1      fvdl #define	MSR_SYSENTER_EIP	0x176   /* PII+ only */
    293        1.1      fvdl #define MSR_MCG_CAP		0x179
    294        1.1      fvdl #define MSR_MCG_STATUS		0x17a
    295        1.1      fvdl #define MSR_MCG_CTL		0x17b
    296        1.1      fvdl #define MSR_EVNTSEL0		0x186
    297        1.1      fvdl #define MSR_EVNTSEL1		0x187
    298        1.4     soren #define MSR_PERF_STATUS		0x198	/* Pentium M */
    299        1.4     soren #define MSR_PERF_CTL		0x199	/* Pentium M */
    300        1.4     soren #define MSR_THERM_CONTROL	0x19a
    301        1.4     soren #define MSR_THERM_INTERRUPT	0x19b
    302        1.4     soren #define MSR_THERM_STATUS	0x19c
    303        1.4     soren #define MSR_THERM2_CTL		0x19d	/* Pentium M */
    304        1.4     soren #define MSR_MISC_ENABLE		0x1a0
    305        1.1      fvdl #define MSR_DEBUGCTLMSR		0x1d9
    306        1.1      fvdl #define MSR_LASTBRANCHFROMIP	0x1db
    307        1.1      fvdl #define MSR_LASTBRANCHTOIP	0x1dc
    308        1.1      fvdl #define MSR_LASTINTFROMIP	0x1dd
    309        1.1      fvdl #define MSR_LASTINTTOIP		0x1de
    310        1.1      fvdl #define MSR_ROB_CR_BKUPTMPDR6	0x1e0
    311        1.1      fvdl #define	MSR_MTRRphysBase0	0x200
    312        1.1      fvdl #define	MSR_MTRRphysMask0	0x201
    313        1.1      fvdl #define	MSR_MTRRphysBase1	0x202
    314        1.1      fvdl #define	MSR_MTRRphysMask1	0x203
    315        1.1      fvdl #define	MSR_MTRRphysBase2	0x204
    316        1.1      fvdl #define	MSR_MTRRphysMask2	0x205
    317        1.1      fvdl #define	MSR_MTRRphysBase3	0x206
    318        1.1      fvdl #define	MSR_MTRRphysMask3	0x207
    319        1.1      fvdl #define	MSR_MTRRphysBase4	0x208
    320        1.1      fvdl #define	MSR_MTRRphysMask4	0x209
    321        1.1      fvdl #define	MSR_MTRRphysBase5	0x20a
    322        1.1      fvdl #define	MSR_MTRRphysMask5	0x20b
    323        1.1      fvdl #define	MSR_MTRRphysBase6	0x20c
    324        1.1      fvdl #define	MSR_MTRRphysMask6	0x20d
    325        1.1      fvdl #define	MSR_MTRRphysBase7	0x20e
    326        1.1      fvdl #define	MSR_MTRRphysMask7	0x20f
    327        1.1      fvdl #define	MSR_MTRRfix64K_00000	0x250
    328        1.1      fvdl #define	MSR_MTRRfix16K_80000	0x258
    329        1.1      fvdl #define	MSR_MTRRfix16K_A0000	0x259
    330        1.1      fvdl #define	MSR_MTRRfix4K_C0000	0x268
    331        1.1      fvdl #define	MSR_MTRRfix4K_C8000	0x269
    332        1.1      fvdl #define	MSR_MTRRfix4K_D0000	0x26a
    333        1.1      fvdl #define	MSR_MTRRfix4K_D8000	0x26b
    334        1.1      fvdl #define	MSR_MTRRfix4K_E0000	0x26c
    335        1.1      fvdl #define	MSR_MTRRfix4K_E8000	0x26d
    336        1.1      fvdl #define	MSR_MTRRfix4K_F0000	0x26e
    337        1.1      fvdl #define	MSR_MTRRfix4K_F8000	0x26f
    338        1.1      fvdl #define MSR_MTRRdefType		0x2ff
    339        1.1      fvdl #define MSR_MC0_CTL		0x400
    340        1.1      fvdl #define MSR_MC0_STATUS		0x401
    341        1.1      fvdl #define MSR_MC0_ADDR		0x402
    342        1.1      fvdl #define MSR_MC0_MISC		0x403
    343        1.1      fvdl #define MSR_MC1_CTL		0x404
    344        1.1      fvdl #define MSR_MC1_STATUS		0x405
    345        1.1      fvdl #define MSR_MC1_ADDR		0x406
    346        1.1      fvdl #define MSR_MC1_MISC		0x407
    347        1.1      fvdl #define MSR_MC2_CTL		0x408
    348        1.1      fvdl #define MSR_MC2_STATUS		0x409
    349        1.1      fvdl #define MSR_MC2_ADDR		0x40a
    350        1.1      fvdl #define MSR_MC2_MISC		0x40b
    351        1.1      fvdl #define MSR_MC4_CTL		0x40c
    352        1.1      fvdl #define MSR_MC4_STATUS		0x40d
    353        1.1      fvdl #define MSR_MC4_ADDR		0x40e
    354        1.1      fvdl #define MSR_MC4_MISC		0x40f
    355        1.1      fvdl #define MSR_MC3_CTL		0x410
    356        1.1      fvdl #define MSR_MC3_STATUS		0x411
    357        1.1      fvdl #define MSR_MC3_ADDR		0x412
    358        1.1      fvdl #define MSR_MC3_MISC		0x413
    359        1.1      fvdl 
    360        1.1      fvdl /*
    361       1.15    daniel  * VIA "Nehemiah" MSRs
    362       1.15    daniel  */
    363       1.15    daniel #define MSR_VIA_RNG		0x0000110b
    364       1.15    daniel #define MSR_VIA_RNG_ENABLE	0x00000040
    365       1.15    daniel #define MSR_VIA_RNG_NOISE_MASK	0x00000300
    366       1.15    daniel #define MSR_VIA_RNG_NOISE_A	0x00000000
    367       1.15    daniel #define MSR_VIA_RNG_NOISE_B	0x00000100
    368       1.15    daniel #define MSR_VIA_RNG_2NOISE	0x00000300
    369       1.15    daniel #define MSR_VIA_ACE		0x00001107
    370       1.15    daniel #define MSR_VIA_ACE_ENABLE	0x10000000
    371       1.15    daniel 
    372       1.15    daniel /*
    373        1.1      fvdl  * AMD K6/K7 MSRs.
    374        1.1      fvdl  */
    375        1.1      fvdl #define	MSR_K6_UWCCR		0xc0000085
    376        1.1      fvdl #define	MSR_K7_EVNTSEL0		0xc0010000
    377        1.1      fvdl #define	MSR_K7_EVNTSEL1		0xc0010001
    378        1.1      fvdl #define	MSR_K7_EVNTSEL2		0xc0010002
    379        1.1      fvdl #define	MSR_K7_EVNTSEL3		0xc0010003
    380        1.1      fvdl #define	MSR_K7_PERFCTR0		0xc0010004
    381        1.1      fvdl #define	MSR_K7_PERFCTR1		0xc0010005
    382        1.1      fvdl #define	MSR_K7_PERFCTR2		0xc0010006
    383        1.1      fvdl #define	MSR_K7_PERFCTR3		0xc0010007
    384        1.1      fvdl 
    385        1.1      fvdl /*
    386       1.12        ad  * AMD K8 (Opteron) MSRs.
    387       1.12        ad  */
    388       1.12        ad #define	MSR_SYSCFG	0xc0000010
    389       1.12        ad 
    390       1.12        ad #define MSR_EFER	0xc0000080		/* Extended feature enable */
    391       1.12        ad #define 	EFER_SCE		0x00000001	/* SYSCALL extension */
    392       1.12        ad #define 	EFER_LME		0x00000100	/* Long Mode Active */
    393       1.12        ad #define		EFER_LMA		0x00000400	/* Long Mode Enabled */
    394       1.12        ad #define 	EFER_NXE		0x00000800	/* No-Execute Enabled */
    395       1.12        ad 
    396       1.12        ad #define MSR_STAR	0xc0000081		/* 32 bit syscall gate addr */
    397       1.12        ad #define MSR_LSTAR	0xc0000082		/* 64 bit syscall gate addr */
    398       1.12        ad #define MSR_CSTAR	0xc0000083		/* compat syscall gate addr */
    399       1.12        ad #define MSR_SFMASK	0xc0000084		/* flags to clear on syscall */
    400       1.12        ad 
    401       1.12        ad #define MSR_FSBASE	0xc0000100		/* 64bit offset for fs: */
    402       1.12        ad #define MSR_GSBASE	0xc0000101		/* 64bit offset for gs: */
    403       1.12        ad #define MSR_KERNELGSBASE 0xc0000102		/* storage for swapgs ins */
    404       1.12        ad 
    405  1.23.10.1      yamt #define MSR_VMCR	0xc0010114	/* Virtual Machine Control Register */
    406  1.23.10.1      yamt #define 	VMCR_DPD	0x00000001	/* Debug port disable */
    407  1.23.10.1      yamt #define		VMCR_RINIT	0x00000002	/* intercept init */
    408  1.23.10.1      yamt #define		VMCR_DISA20	0x00000004	/* Disable A20 masking */
    409  1.23.10.1      yamt #define		VMCR_LOCK	0x00000008	/* SVM Lock */
    410  1.23.10.1      yamt #define		VMCR_SVMED	0x00000010	/* SVME Disable */
    411  1.23.10.1      yamt #define MSR_SVMLOCK	0xc0010118	/* SVM Lock key */
    412  1.23.10.1      yamt 
    413       1.12        ad /*
    414       1.12        ad  * These require a 'passcode' for access.  See cpufunc.h.
    415       1.12        ad  */
    416       1.13        ad #define	MSR_HWCR	0xc0010015
    417  1.23.10.1      yamt #define		HWCR_TLBCACHEDIS	0x00000008
    418       1.13        ad #define		HWCR_FFDIS		0x00000040
    419       1.13        ad 
    420       1.12        ad #define	MSR_NB_CFG	0xc001001f
    421       1.12        ad #define		NB_CFG_DISIOREQLOCK	0x0000000000000004ULL
    422       1.12        ad #define		NB_CFG_DISDATMSK	0x0000001000000000ULL
    423       1.12        ad 
    424       1.12        ad #define	MSR_LS_CFG	0xc0011020
    425       1.12        ad #define		LS_CFG_DIS_LS2_SQUISH	0x02000000
    426       1.12        ad 
    427       1.12        ad #define	MSR_IC_CFG	0xc0011021
    428       1.12        ad #define		IC_CFG_DIS_SEQ_PREFETCH	0x00000800
    429       1.12        ad 
    430       1.12        ad #define	MSR_DC_CFG	0xc0011022
    431       1.12        ad #define		DC_CFG_DIS_CNV_WC_SSO	0x00000004
    432       1.12        ad #define		DC_CFG_DIS_SMC_CHK_BUF	0x00000400
    433  1.23.10.1      yamt #define		DC_CFG_ERRATA_261	0x01000000
    434       1.12        ad 
    435       1.12        ad #define	MSR_BU_CFG	0xc0011023
    436  1.23.10.1      yamt #define		BU_CFG_ERRATA_298	0x0000000000000002ULL
    437  1.23.10.1      yamt #define		BU_CFG_ERRATA_254	0x0000000000200000ULL
    438  1.23.10.1      yamt #define		BU_CFG_ERRATA_309	0x0000000000800000ULL
    439       1.12        ad #define		BU_CFG_THRL2IDXCMPDIS	0x0000080000000000ULL
    440       1.12        ad #define		BU_CFG_WBPFSMCCHKDIS	0x0000200000000000ULL
    441       1.12        ad #define		BU_CFG_WBENHWSBDIS	0x0001000000000000ULL
    442       1.12        ad 
    443       1.12        ad /*
    444        1.1      fvdl  * Constants related to MTRRs
    445        1.1      fvdl  */
    446        1.1      fvdl #define MTRR_N64K		8	/* numbers of fixed-size entries */
    447        1.1      fvdl #define MTRR_N16K		16
    448        1.1      fvdl #define MTRR_N4K		64
    449        1.1      fvdl 
    450        1.1      fvdl /*
    451        1.1      fvdl  * the following four 3-byte registers control the non-cacheable regions.
    452        1.1      fvdl  * These registers must be written as three separate bytes.
    453        1.1      fvdl  *
    454        1.1      fvdl  * NCRx+0: A31-A24 of starting address
    455        1.1      fvdl  * NCRx+1: A23-A16 of starting address
    456        1.1      fvdl  * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
    457        1.1      fvdl  *
    458        1.1      fvdl  * The non-cacheable region's starting address must be aligned to the
    459        1.1      fvdl  * size indicated by the NCR_SIZE_xx field.
    460        1.1      fvdl  */
    461        1.1      fvdl #define NCR1	0xc4
    462        1.1      fvdl #define NCR2	0xc7
    463        1.1      fvdl #define NCR3	0xca
    464        1.1      fvdl #define NCR4	0xcd
    465        1.1      fvdl 
    466        1.1      fvdl #define NCR_SIZE_0K	0
    467        1.1      fvdl #define NCR_SIZE_4K	1
    468        1.1      fvdl #define NCR_SIZE_8K	2
    469        1.1      fvdl #define NCR_SIZE_16K	3
    470        1.1      fvdl #define NCR_SIZE_32K	4
    471        1.1      fvdl #define NCR_SIZE_64K	5
    472        1.1      fvdl #define NCR_SIZE_128K	6
    473        1.1      fvdl #define NCR_SIZE_256K	7
    474        1.1      fvdl #define NCR_SIZE_512K	8
    475        1.1      fvdl #define NCR_SIZE_1M	9
    476        1.1      fvdl #define NCR_SIZE_2M	10
    477        1.1      fvdl #define NCR_SIZE_4M	11
    478        1.1      fvdl #define NCR_SIZE_8M	12
    479        1.1      fvdl #define NCR_SIZE_16M	13
    480        1.1      fvdl #define NCR_SIZE_32M	14
    481        1.1      fvdl #define NCR_SIZE_4G	15
    482        1.1      fvdl 
    483        1.1      fvdl /*
    484        1.1      fvdl  * Performance monitor events.
    485        1.1      fvdl  *
    486        1.1      fvdl  * Note that 586-class and 686-class CPUs have different performance
    487        1.1      fvdl  * monitors available, and they are accessed differently:
    488        1.1      fvdl  *
    489        1.1      fvdl  *	686-class: `rdpmc' instruction
    490        1.1      fvdl  *	586-class: `rdmsr' instruction, CESR MSR
    491        1.1      fvdl  *
    492        1.1      fvdl  * The descriptions of these events are too lenghy to include here.
    493        1.1      fvdl  * See Appendix A of "Intel Architecture Software Developer's
    494        1.1      fvdl  * Manual, Volume 3: System Programming" for more information.
    495        1.1      fvdl  */
    496        1.1      fvdl 
    497        1.1      fvdl /*
    498        1.1      fvdl  * 586-class CESR MSR format.  Lower 16 bits is CTR0, upper 16 bits
    499        1.1      fvdl  * is CTR1.
    500        1.1      fvdl  */
    501        1.1      fvdl 
    502        1.1      fvdl #define	PMC5_CESR_EVENT			0x003f
    503        1.1      fvdl #define	PMC5_CESR_OS			0x0040
    504        1.1      fvdl #define	PMC5_CESR_USR			0x0080
    505        1.1      fvdl #define	PMC5_CESR_E			0x0100
    506        1.1      fvdl #define	PMC5_CESR_P			0x0200
    507        1.1      fvdl 
    508        1.1      fvdl #define PMC5_DATA_READ			0x00
    509        1.1      fvdl #define PMC5_DATA_WRITE			0x01
    510        1.1      fvdl #define PMC5_DATA_TLB_MISS		0x02
    511        1.1      fvdl #define PMC5_DATA_READ_MISS		0x03
    512        1.1      fvdl #define PMC5_DATA_WRITE_MISS		0x04
    513        1.1      fvdl #define PMC5_WRITE_M_E			0x05
    514        1.1      fvdl #define PMC5_DATA_LINES_WBACK		0x06
    515        1.1      fvdl #define PMC5_DATA_CACHE_SNOOP		0x07
    516        1.1      fvdl #define PMC5_DATA_CACHE_SNOOP_HIT	0x08
    517        1.1      fvdl #define PMC5_MEM_ACCESS_BOTH_PIPES	0x09
    518        1.1      fvdl #define PMC5_BANK_CONFLICTS		0x0a
    519        1.1      fvdl #define PMC5_MISALIGNED_DATA		0x0b
    520        1.1      fvdl #define PMC5_INST_READ			0x0c
    521        1.1      fvdl #define PMC5_INST_TLB_MISS		0x0d
    522        1.1      fvdl #define PMC5_INST_CACHE_MISS		0x0e
    523        1.1      fvdl #define PMC5_SEGMENT_REG_LOAD		0x0f
    524        1.1      fvdl #define PMC5_BRANCHES		 	0x12
    525        1.1      fvdl #define PMC5_BTB_HITS		 	0x13
    526        1.1      fvdl #define PMC5_BRANCH_TAKEN		0x14
    527        1.1      fvdl #define PMC5_PIPELINE_FLUSH		0x15
    528        1.1      fvdl #define PMC5_INST_EXECUTED		0x16
    529        1.1      fvdl #define PMC5_INST_EXECUTED_V_PIPE	0x17
    530        1.1      fvdl #define PMC5_BUS_UTILIZATION		0x18
    531        1.1      fvdl #define PMC5_WRITE_BACKUP_STALL		0x19
    532        1.1      fvdl #define PMC5_DATA_READ_STALL		0x1a
    533        1.1      fvdl #define PMC5_WRITE_E_M_STALL		0x1b
    534        1.1      fvdl #define PMC5_LOCKED_BUS			0x1c
    535        1.1      fvdl #define PMC5_IO_CYCLE			0x1d
    536        1.1      fvdl #define PMC5_NONCACHE_MEM_READ		0x1e
    537        1.1      fvdl #define PMC5_AGI_STALL			0x1f
    538        1.1      fvdl #define PMC5_FLOPS			0x22
    539        1.1      fvdl #define PMC5_BP0_MATCH			0x23
    540        1.1      fvdl #define PMC5_BP1_MATCH			0x24
    541        1.1      fvdl #define PMC5_BP2_MATCH			0x25
    542        1.1      fvdl #define PMC5_BP3_MATCH			0x26
    543        1.1      fvdl #define PMC5_HARDWARE_INTR		0x27
    544        1.1      fvdl #define PMC5_DATA_RW			0x28
    545        1.1      fvdl #define PMC5_DATA_RW_MISS		0x29
    546        1.1      fvdl 
    547        1.1      fvdl /*
    548        1.1      fvdl  * 686-class Event Selector MSR format.
    549        1.1      fvdl  */
    550        1.1      fvdl 
    551        1.1      fvdl #define	PMC6_EVTSEL_EVENT		0x000000ff
    552        1.1      fvdl #define	PMC6_EVTSEL_UNIT		0x0000ff00
    553        1.1      fvdl #define	PMC6_EVTSEL_UNIT_SHIFT		8
    554        1.1      fvdl #define	PMC6_EVTSEL_USR			(1 << 16)
    555        1.1      fvdl #define	PMC6_EVTSEL_OS			(1 << 17)
    556        1.1      fvdl #define	PMC6_EVTSEL_E			(1 << 18)
    557        1.1      fvdl #define	PMC6_EVTSEL_PC			(1 << 19)
    558        1.1      fvdl #define	PMC6_EVTSEL_INT			(1 << 20)
    559        1.1      fvdl #define	PMC6_EVTSEL_EN			(1 << 22)	/* PerfEvtSel0 only */
    560        1.1      fvdl #define	PMC6_EVTSEL_INV			(1 << 23)
    561        1.1      fvdl #define	PMC6_EVTSEL_COUNTER_MASK	0xff000000
    562        1.1      fvdl #define	PMC6_EVTSEL_COUNTER_MASK_SHIFT	24
    563        1.1      fvdl 
    564        1.1      fvdl /* Data Cache Unit */
    565        1.1      fvdl #define	PMC6_DATA_MEM_REFS		0x43
    566        1.1      fvdl #define	PMC6_DCU_LINES_IN		0x45
    567        1.1      fvdl #define	PMC6_DCU_M_LINES_IN		0x46
    568        1.1      fvdl #define	PMC6_DCU_M_LINES_OUT		0x47
    569        1.1      fvdl #define	PMC6_DCU_MISS_OUTSTANDING	0x48
    570        1.1      fvdl 
    571        1.1      fvdl /* Instruction Fetch Unit */
    572        1.1      fvdl #define	PMC6_IFU_IFETCH			0x80
    573        1.1      fvdl #define	PMC6_IFU_IFETCH_MISS		0x81
    574        1.1      fvdl #define	PMC6_ITLB_MISS			0x85
    575        1.1      fvdl #define	PMC6_IFU_MEM_STALL		0x86
    576        1.1      fvdl #define	PMC6_ILD_STALL			0x87
    577        1.1      fvdl 
    578        1.1      fvdl /* L2 Cache */
    579        1.1      fvdl #define	PMC6_L2_IFETCH			0x28
    580        1.1      fvdl #define	PMC6_L2_LD			0x29
    581        1.1      fvdl #define	PMC6_L2_ST			0x2a
    582        1.1      fvdl #define	PMC6_L2_LINES_IN		0x24
    583        1.1      fvdl #define	PMC6_L2_LINES_OUT		0x26
    584        1.1      fvdl #define	PMC6_L2_M_LINES_INM		0x25
    585        1.1      fvdl #define	PMC6_L2_M_LINES_OUTM		0x27
    586        1.1      fvdl #define	PMC6_L2_RQSTS			0x2e
    587        1.1      fvdl #define	PMC6_L2_ADS			0x21
    588        1.1      fvdl #define	PMC6_L2_DBUS_BUSY		0x22
    589        1.1      fvdl #define	PMC6_L2_DBUS_BUSY_RD		0x23
    590        1.1      fvdl 
    591        1.1      fvdl /* External Bus Logic */
    592        1.1      fvdl #define	PMC6_BUS_DRDY_CLOCKS		0x62
    593        1.1      fvdl #define	PMC6_BUS_LOCK_CLOCKS		0x63
    594        1.1      fvdl #define	PMC6_BUS_REQ_OUTSTANDING	0x60
    595        1.1      fvdl #define	PMC6_BUS_TRAN_BRD		0x65
    596        1.1      fvdl #define	PMC6_BUS_TRAN_RFO		0x66
    597        1.1      fvdl #define	PMC6_BUS_TRANS_WB		0x67
    598        1.1      fvdl #define	PMC6_BUS_TRAN_IFETCH		0x68
    599        1.1      fvdl #define	PMC6_BUS_TRAN_INVAL		0x69
    600        1.1      fvdl #define	PMC6_BUS_TRAN_PWR		0x6a
    601        1.1      fvdl #define	PMC6_BUS_TRANS_P		0x6b
    602        1.1      fvdl #define	PMC6_BUS_TRANS_IO		0x6c
    603        1.1      fvdl #define	PMC6_BUS_TRAN_DEF		0x6d
    604        1.1      fvdl #define	PMC6_BUS_TRAN_BURST		0x6e
    605        1.1      fvdl #define	PMC6_BUS_TRAN_ANY		0x70
    606        1.1      fvdl #define	PMC6_BUS_TRAN_MEM		0x6f
    607        1.1      fvdl #define	PMC6_BUS_DATA_RCV		0x64
    608        1.1      fvdl #define	PMC6_BUS_BNR_DRV		0x61
    609        1.1      fvdl #define	PMC6_BUS_HIT_DRV		0x7a
    610        1.1      fvdl #define	PMC6_BUS_HITM_DRDV		0x7b
    611        1.1      fvdl #define	PMC6_BUS_SNOOP_STALL		0x7e
    612        1.1      fvdl 
    613        1.1      fvdl /* Floating Point Unit */
    614        1.1      fvdl #define	PMC6_FLOPS			0xc1
    615        1.1      fvdl #define	PMC6_FP_COMP_OPS_EXE		0x10
    616        1.1      fvdl #define	PMC6_FP_ASSIST			0x11
    617        1.1      fvdl #define	PMC6_MUL			0x12
    618        1.1      fvdl #define	PMC6_DIV			0x12
    619        1.1      fvdl #define	PMC6_CYCLES_DIV_BUSY		0x14
    620        1.1      fvdl 
    621        1.1      fvdl /* Memory Ordering */
    622        1.1      fvdl #define	PMC6_LD_BLOCKS			0x03
    623        1.1      fvdl #define	PMC6_SB_DRAINS			0x04
    624        1.1      fvdl #define	PMC6_MISALIGN_MEM_REF		0x05
    625        1.1      fvdl #define	PMC6_EMON_KNI_PREF_DISPATCHED	0x07	/* P-III only */
    626        1.1      fvdl #define	PMC6_EMON_KNI_PREF_MISS		0x4b	/* P-III only */
    627        1.1      fvdl 
    628        1.1      fvdl /* Instruction Decoding and Retirement */
    629        1.1      fvdl #define	PMC6_INST_RETIRED		0xc0
    630        1.1      fvdl #define	PMC6_UOPS_RETIRED		0xc2
    631        1.1      fvdl #define	PMC6_INST_DECODED		0xd0
    632        1.1      fvdl #define	PMC6_EMON_KNI_INST_RETIRED	0xd8
    633        1.1      fvdl #define	PMC6_EMON_KNI_COMP_INST_RET	0xd9
    634        1.1      fvdl 
    635        1.1      fvdl /* Interrupts */
    636        1.1      fvdl #define	PMC6_HW_INT_RX			0xc8
    637        1.1      fvdl #define	PMC6_CYCLES_INT_MASKED		0xc6
    638        1.1      fvdl #define	PMC6_CYCLES_INT_PENDING_AND_MASKED 0xc7
    639        1.1      fvdl 
    640        1.1      fvdl /* Branches */
    641        1.1      fvdl #define	PMC6_BR_INST_RETIRED		0xc4
    642        1.1      fvdl #define	PMC6_BR_MISS_PRED_RETIRED	0xc5
    643        1.1      fvdl #define	PMC6_BR_TAKEN_RETIRED		0xc9
    644        1.1      fvdl #define	PMC6_BR_MISS_PRED_TAKEN_RET	0xca
    645        1.1      fvdl #define	PMC6_BR_INST_DECODED		0xe0
    646        1.1      fvdl #define	PMC6_BTB_MISSES			0xe2
    647        1.1      fvdl #define	PMC6_BR_BOGUS			0xe4
    648        1.1      fvdl #define	PMC6_BACLEARS			0xe6
    649        1.1      fvdl 
    650        1.1      fvdl /* Stalls */
    651        1.1      fvdl #define	PMC6_RESOURCE_STALLS		0xa2
    652        1.1      fvdl #define	PMC6_PARTIAL_RAT_STALLS		0xd2
    653        1.1      fvdl 
    654        1.1      fvdl /* Segment Register Loads */
    655        1.1      fvdl #define	PMC6_SEGMENT_REG_LOADS		0x06
    656        1.1      fvdl 
    657        1.1      fvdl /* Clocks */
    658        1.1      fvdl #define	PMC6_CPU_CLK_UNHALTED		0x79
    659        1.1      fvdl 
    660        1.1      fvdl /* MMX Unit */
    661        1.1      fvdl #define	PMC6_MMX_INSTR_EXEC		0xb0	/* Celeron, P-II, P-IIX only */
    662        1.1      fvdl #define	PMC6_MMX_SAT_INSTR_EXEC		0xb1	/* P-II and P-III only */
    663        1.1      fvdl #define	PMC6_MMX_UOPS_EXEC		0xb2	/* P-II and P-III only */
    664        1.1      fvdl #define	PMC6_MMX_INSTR_TYPE_EXEC	0xb3	/* P-II and P-III only */
    665        1.1      fvdl #define	PMC6_FP_MMX_TRANS		0xcc	/* P-II and P-III only */
    666        1.1      fvdl #define	PMC6_MMX_ASSIST			0xcd	/* P-II and P-III only */
    667        1.1      fvdl #define	PMC6_MMX_INSTR_RET		0xc3	/* P-II only */
    668        1.1      fvdl 
    669        1.1      fvdl /* Segment Register Renaming */
    670        1.1      fvdl #define	PMC6_SEG_RENAME_STALLS		0xd4	/* P-II and P-III only */
    671        1.1      fvdl #define	PMC6_SEG_REG_RENAMES		0xd5	/* P-II and P-III only */
    672        1.1      fvdl #define	PMC6_RET_SEG_RENAMES		0xd6	/* P-II and P-III only */
    673        1.1      fvdl 
    674        1.1      fvdl /*
    675        1.1      fvdl  * AMD K7 Event Selector MSR format.
    676        1.1      fvdl  */
    677        1.1      fvdl 
    678        1.1      fvdl #define	K7_EVTSEL_EVENT			0x000000ff
    679        1.1      fvdl #define	K7_EVTSEL_UNIT			0x0000ff00
    680        1.1      fvdl #define	K7_EVTSEL_UNIT_SHIFT		8
    681        1.1      fvdl #define	K7_EVTSEL_USR			(1 << 16)
    682        1.1      fvdl #define	K7_EVTSEL_OS			(1 << 17)
    683        1.1      fvdl #define	K7_EVTSEL_E			(1 << 18)
    684        1.1      fvdl #define	K7_EVTSEL_PC			(1 << 19)
    685        1.1      fvdl #define	K7_EVTSEL_INT			(1 << 20)
    686        1.1      fvdl #define	K7_EVTSEL_EN			(1 << 22)
    687        1.1      fvdl #define	K7_EVTSEL_INV			(1 << 23)
    688        1.1      fvdl #define	K7_EVTSEL_COUNTER_MASK		0xff000000
    689        1.1      fvdl #define	K7_EVTSEL_COUNTER_MASK_SHIFT	24
    690        1.1      fvdl 
    691        1.1      fvdl /* Segment Register Loads */
    692        1.1      fvdl #define	K7_SEGMENT_REG_LOADS		0x20
    693        1.1      fvdl 
    694        1.1      fvdl #define	K7_STORES_TO_ACTIVE_INST_STREAM	0x21
    695        1.1      fvdl 
    696        1.1      fvdl /* Data Cache Unit */
    697        1.1      fvdl #define	K7_DATA_CACHE_ACCESS		0x40
    698        1.1      fvdl #define	K7_DATA_CACHE_MISS		0x41
    699        1.1      fvdl #define	K7_DATA_CACHE_REFILL		0x42
    700        1.1      fvdl #define	K7_DATA_CACHE_REFILL_SYSTEM	0x43
    701        1.1      fvdl #define	K7_DATA_CACHE_WBACK		0x44
    702        1.1      fvdl #define	K7_L2_DTLB_HIT			0x45
    703        1.1      fvdl #define	K7_L2_DTLB_MISS			0x46
    704        1.1      fvdl #define	K7_MISALIGNED_DATA_REF		0x47
    705        1.1      fvdl #define	K7_SYSTEM_REQUEST		0x64
    706        1.1      fvdl #define	K7_SYSTEM_REQUEST_TYPE		0x65
    707        1.1      fvdl 
    708        1.1      fvdl #define	K7_SNOOP_HIT			0x73
    709        1.1      fvdl #define	K7_SINGLE_BIT_ECC_ERROR		0x74
    710        1.1      fvdl #define	K7_CACHE_LINE_INVAL		0x75
    711        1.1      fvdl #define	K7_CYCLES_PROCESSOR_IS_RUNNING	0x76
    712        1.1      fvdl #define	K7_L2_REQUEST			0x79
    713        1.1      fvdl #define	K7_L2_REQUEST_BUSY		0x7a
    714        1.1      fvdl 
    715        1.1      fvdl /* Instruction Fetch Unit */
    716        1.1      fvdl #define	K7_IFU_IFETCH			0x80
    717        1.1      fvdl #define	K7_IFU_IFETCH_MISS		0x81
    718        1.1      fvdl #define	K7_IFU_REFILL_FROM_L2		0x82
    719        1.1      fvdl #define	K7_IFU_REFILL_FROM_SYSTEM	0x83
    720        1.1      fvdl #define	K7_ITLB_L1_MISS			0x84
    721        1.1      fvdl #define	K7_ITLB_L2_MISS			0x85
    722        1.1      fvdl #define	K7_SNOOP_RESYNC			0x86
    723        1.1      fvdl #define	K7_IFU_STALL			0x87
    724        1.1      fvdl 
    725        1.1      fvdl #define	K7_RETURN_STACK_HITS		0x88
    726        1.1      fvdl #define	K7_RETURN_STACK_OVERFLOW	0x89
    727        1.1      fvdl 
    728        1.1      fvdl /* Retired */
    729        1.1      fvdl #define	K7_RETIRED_INST			0xc0
    730        1.1      fvdl #define	K7_RETIRED_OPS			0xc1
    731        1.1      fvdl #define	K7_RETIRED_BRANCHES		0xc2
    732        1.1      fvdl #define	K7_RETIRED_BRANCH_MISPREDICTED	0xc3
    733        1.1      fvdl #define	K7_RETIRED_TAKEN_BRANCH		0xc4
    734        1.1      fvdl #define	K7_RETIRED_TAKEN_BRANCH_MISPREDICTED	0xc5
    735        1.1      fvdl #define	K7_RETIRED_FAR_CONTROL_TRANSFER	0xc6
    736        1.1      fvdl #define	K7_RETIRED_RESYNC_BRANCH	0xc7
    737        1.1      fvdl #define	K7_RETIRED_NEAR_RETURNS		0xc8
    738        1.1      fvdl #define	K7_RETIRED_NEAR_RETURNS_MISPREDICTED	0xc9
    739        1.1      fvdl #define	K7_RETIRED_INDIRECT_MISPREDICTED	0xca
    740        1.1      fvdl 
    741        1.1      fvdl /* Interrupts */
    742        1.1      fvdl #define	K7_CYCLES_INT_MASKED		0xcd
    743        1.1      fvdl #define	K7_CYCLES_INT_PENDING_AND_MASKED	0xce
    744        1.1      fvdl #define	K7_HW_INTR_RECV			0xcf
    745        1.1      fvdl 
    746        1.1      fvdl #define	K7_INSTRUCTION_DECODER_EMPTY	0xd0
    747        1.1      fvdl #define	K7_DISPATCH_STALLS		0xd1
    748        1.1      fvdl #define	K7_BRANCH_ABORTS_TO_RETIRE	0xd2
    749        1.1      fvdl #define	K7_SERIALIZE			0xd3
    750        1.1      fvdl #define	K7_SEGMENT_LOAD_STALL		0xd4
    751        1.1      fvdl #define	K7_ICU_FULL			0xd5
    752        1.1      fvdl #define	K7_RESERVATION_STATIONS_FULL	0xd6
    753        1.1      fvdl #define	K7_FPU_FULL			0xd7
    754        1.1      fvdl #define	K7_LS_FULL			0xd8
    755        1.1      fvdl #define	K7_ALL_QUIET_STALL		0xd9
    756        1.1      fvdl #define	K7_FAR_TRANSFER_OR_RESYNC_BRANCH_PENDING	0xda
    757        1.1      fvdl 
    758        1.1      fvdl #define	K7_BP0_MATCH			0xdc
    759        1.1      fvdl #define	K7_BP1_MATCH			0xdd
    760        1.1      fvdl #define	K7_BP2_MATCH			0xde
    761        1.1      fvdl #define	K7_BP3_MATCH			0xdf
    762