specialreg.h revision 1.126
1 /* $NetBSD: specialreg.h,v 1.126 2018/05/31 03:29:01 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1991 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of the University nor the names of its contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * @(#)specialreg.h 7.1 (Berkeley) 5/9/91 32 */ 33 34 /* 35 * Bits in 386 special registers: 36 */ 37 #define CR0_PE 0x00000001 /* Protected mode Enable */ 38 #define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */ 39 #define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */ 40 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 41 #define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */ 42 #define CR0_PG 0x80000000 /* PaGing enable */ 43 44 /* 45 * Bits in 486 special registers: 46 */ 47 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 48 #define CR0_WP 0x00010000 /* Write Protect (honor PG_RW in all modes) */ 49 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 50 #define CR0_NW 0x20000000 /* Not Write-through */ 51 #define CR0_CD 0x40000000 /* Cache Disable */ 52 53 /* 54 * Cyrix 486 DLC special registers, accessible as IO ports. 55 */ 56 #define CCR0 0xc0 /* configuration control register 0 */ 57 #define CCR0_NC0 0x01 /* first 64K of each 1M memory region is non-cacheable */ 58 #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 59 #define CCR0_A20M 0x04 /* enables A20M# input pin */ 60 #define CCR0_KEN 0x08 /* enables KEN# input pin */ 61 #define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */ 62 #define CCR0_BARB 0x20 /* flushes internal cache when entering hold state */ 63 #define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */ 64 #define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */ 65 66 #define CCR1 0xc1 /* configuration control register 1 */ 67 #define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */ 68 /* the remaining 7 bits of this register are reserved */ 69 70 /* 71 * bits in the %cr4 control register: 72 */ 73 #define CR4_VME 0x00000001 /* virtual 8086 mode extension enable */ 74 #define CR4_PVI 0x00000002 /* protected mode virtual interrupt enable */ 75 #define CR4_TSD 0x00000004 /* restrict RDTSC instruction to cpl 0 */ 76 #define CR4_DE 0x00000008 /* debugging extension */ 77 #define CR4_PSE 0x00000010 /* large (4MB) page size enable */ 78 #define CR4_PAE 0x00000020 /* physical address extension enable */ 79 #define CR4_MCE 0x00000040 /* machine check enable */ 80 #define CR4_PGE 0x00000080 /* page global enable */ 81 #define CR4_PCE 0x00000100 /* enable RDPMC instruction for all cpls */ 82 #define CR4_OSFXSR 0x00000200 /* enable fxsave/fxrestor and SSE */ 83 #define CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */ 84 #define CR4_UMIP 0x00000800 /* user-mode instruction prevention */ 85 #define CR4_VMXE 0x00002000 /* enable VMX operations */ 86 #define CR4_SMXE 0x00004000 /* enable SMX operations */ 87 #define CR4_FSGSBASE 0x00010000 /* enable *FSBASE and *GSBASE instructions */ 88 #define CR4_PCIDE 0x00020000 /* enable Process Context IDentifiers */ 89 #define CR4_OSXSAVE 0x00040000 /* enable xsave and xrestore */ 90 #define CR4_SMEP 0x00100000 /* enable SMEP support */ 91 #define CR4_SMAP 0x00200000 /* enable SMAP support */ 92 #define CR4_PKE 0x00400000 /* protection key enable */ 93 94 /* 95 * Extended Control Register XCR0 96 */ 97 #define XCR0_X87 0x00000001 /* x87 FPU/MMX state */ 98 #define XCR0_SSE 0x00000002 /* SSE state */ 99 #define XCR0_YMM_Hi128 0x00000004 /* AVX-256 (ymmn registers) */ 100 #define XCR0_BNDREGS 0x00000008 /* Memory protection ext bounds */ 101 #define XCR0_BNDCSR 0x00000010 /* Memory protection ext state */ 102 #define XCR0_Opmask 0x00000020 /* AVX-512 Opmask */ 103 #define XCR0_ZMM_Hi256 0x00000040 /* AVX-512 upper 256 bits low regs */ 104 #define XCR0_Hi16_ZMM 0x00000080 /* AVX-512 512 bits upper registers */ 105 106 /* 107 * Known fpu bits - only these get enabled. The save area is sized for all the 108 * fields below (max 2680 bytes). 109 */ 110 #define XCR0_FPU (XCR0_X87 | XCR0_SSE | XCR0_YMM_Hi128 | \ 111 XCR0_Opmask | XCR0_ZMM_Hi256 | XCR0_Hi16_ZMM) 112 113 #define XCR0_BND (XCR0_BNDREGS | XCR0_BNDCSR) 114 115 #define XCR0_FLAGS1 "\20" \ 116 "\1" "x87" "\2" "SSE" "\3" "AVX" \ 117 "\4" "BNDREGS" "\5" "BNDCSR" \ 118 "\6" "Opmask" "\7" "ZMM_Hi256" "\10" "Hi16_ZMM" 119 120 121 /* 122 * CPUID "features" bits 123 */ 124 125 /* Fn00000001 %edx features */ 126 #define CPUID_FPU 0x00000001 /* processor has an FPU? */ 127 #define CPUID_VME 0x00000002 /* has virtual mode (%cr4's VME/PVI) */ 128 #define CPUID_DE 0x00000004 /* has debugging extension */ 129 #define CPUID_PSE 0x00000008 /* has 4MB page size extension */ 130 #define CPUID_TSC 0x00000010 /* has time stamp counter */ 131 #define CPUID_MSR 0x00000020 /* has model specific registers */ 132 #define CPUID_PAE 0x00000040 /* has phys address extension */ 133 #define CPUID_MCE 0x00000080 /* has machine check exception */ 134 #define CPUID_CX8 0x00000100 /* has CMPXCHG8B instruction */ 135 #define CPUID_APIC 0x00000200 /* has enabled APIC */ 136 #define CPUID_B10 0x00000400 /* reserved, MTRR */ 137 #define CPUID_SEP 0x00000800 /* has SYSENTER/SYSEXIT extension */ 138 #define CPUID_MTRR 0x00001000 /* has memory type range register */ 139 #define CPUID_PGE 0x00002000 /* has page global extension */ 140 #define CPUID_MCA 0x00004000 /* has machine check architecture */ 141 #define CPUID_CMOV 0x00008000 /* has CMOVcc instruction */ 142 #define CPUID_PAT 0x00010000 /* Page Attribute Table */ 143 #define CPUID_PSE36 0x00020000 /* 36-bit PSE */ 144 #define CPUID_PN 0x00040000 /* processor serial number */ 145 #define CPUID_CFLUSH 0x00080000 /* CLFLUSH insn supported */ 146 #define CPUID_B20 0x00100000 /* reserved */ 147 #define CPUID_DS 0x00200000 /* Debug Store */ 148 #define CPUID_ACPI 0x00400000 /* ACPI performance modulation regs */ 149 #define CPUID_MMX 0x00800000 /* MMX supported */ 150 #define CPUID_FXSR 0x01000000 /* fast FP/MMX save/restore */ 151 #define CPUID_SSE 0x02000000 /* streaming SIMD extensions */ 152 #define CPUID_SSE2 0x04000000 /* streaming SIMD extensions #2 */ 153 #define CPUID_SS 0x08000000 /* self-snoop */ 154 #define CPUID_HTT 0x10000000 /* Hyper-Threading Technology */ 155 #define CPUID_TM 0x20000000 /* thermal monitor (TCC) */ 156 #define CPUID_IA64 0x40000000 /* IA-64 architecture */ 157 #define CPUID_SBF 0x80000000 /* signal break on FERR */ 158 159 #define CPUID_FLAGS1 "\20" \ 160 "\1" "FPU" "\2" "VME" "\3" "DE" "\4" "PSE" \ 161 "\5" "TSC" "\6" "MSR" "\7" "PAE" "\10" "MCE" \ 162 "\11" "CX8" "\12" "APIC" "\13" "B10" "\14" "SEP" \ 163 "\15" "MTRR" "\16" "PGE" "\17" "MCA" "\20" "CMOV" \ 164 "\21" "PAT" "\22" "PSE36" "\23" "PN" "\24" "CLFLUSH" \ 165 "\25" "B20" "\26" "DS" "\27" "ACPI" "\30" "MMX" \ 166 "\31" "FXSR" "\32" "SSE" "\33" "SSE2" "\34" "SS" \ 167 "\35" "HTT" "\36" "TM" "\37" "IA64" "\40" "SBF" 168 169 /* Blacklists of CPUID flags - used to mask certain features */ 170 #ifdef XEN 171 /* Not on Xen */ 172 #define CPUID_FEAT_BLACKLIST (CPUID_PGE|CPUID_PSE|CPUID_MTRR) 173 #else 174 #define CPUID_FEAT_BLACKLIST 0 175 #endif /* XEN */ 176 177 /* 178 * CPUID "features" bits in Fn00000001 %ecx 179 */ 180 181 #define CPUID2_SSE3 0x00000001 /* Streaming SIMD Extensions 3 */ 182 #define CPUID2_PCLMUL 0x00000002 /* PCLMULQDQ instructions */ 183 #define CPUID2_DTES64 0x00000004 /* 64-bit Debug Trace */ 184 #define CPUID2_MONITOR 0x00000008 /* MONITOR/MWAIT instructions */ 185 #define CPUID2_DS_CPL 0x00000010 /* CPL Qualified Debug Store */ 186 #define CPUID2_VMX 0x00000020 /* Virtual Machine Extensions */ 187 #define CPUID2_SMX 0x00000040 /* Safer Mode Extensions */ 188 #define CPUID2_EST 0x00000080 /* Enhanced SpeedStep Technology */ 189 #define CPUID2_TM2 0x00000100 /* Thermal Monitor 2 */ 190 #define CPUID2_SSSE3 0x00000200 /* Supplemental SSE3 */ 191 #define CPUID2_CID 0x00000400 /* Context ID */ 192 #define CPUID2_SDBG 0x00000800 /* Silicon Debug */ 193 #define CPUID2_FMA 0x00001000 /* has Fused Multiply Add */ 194 #define CPUID2_CX16 0x00002000 /* has CMPXCHG16B instruction */ 195 #define CPUID2_xTPR 0x00004000 /* Task Priority Messages disabled? */ 196 #define CPUID2_PDCM 0x00008000 /* Perf/Debug Capability MSR */ 197 /* bit 16 unused 0x00010000 */ 198 #define CPUID2_PCID 0x00020000 /* Process Context ID */ 199 #define CPUID2_DCA 0x00040000 /* Direct Cache Access */ 200 #define CPUID2_SSE41 0x00080000 /* Streaming SIMD Extensions 4.1 */ 201 #define CPUID2_SSE42 0x00100000 /* Streaming SIMD Extensions 4.2 */ 202 #define CPUID2_X2APIC 0x00200000 /* xAPIC Extensions */ 203 #define CPUID2_MOVBE 0x00400000 /* MOVBE (move after byteswap) */ 204 #define CPUID2_POPCNT 0x00800000 /* popcount instruction available */ 205 #define CPUID2_DEADLINE 0x01000000 /* APIC Timer supports TSC Deadline */ 206 #define CPUID2_AES 0x02000000 /* AES instructions */ 207 #define CPUID2_XSAVE 0x04000000 /* XSAVE instructions */ 208 #define CPUID2_OSXSAVE 0x08000000 /* XGETBV/XSETBV instructions */ 209 #define CPUID2_AVX 0x10000000 /* AVX instructions */ 210 #define CPUID2_F16C 0x20000000 /* half precision conversion */ 211 #define CPUID2_RDRAND 0x40000000 /* RDRAND (hardware random number) */ 212 #define CPUID2_RAZ 0x80000000 /* RAZ. Indicates guest state. */ 213 214 #define CPUID2_FLAGS1 "\20" \ 215 "\1" "SSE3" "\2" "PCLMULQDQ" "\3" "DTES64" "\4" "MONITOR" \ 216 "\5" "DS-CPL" "\6" "VMX" "\7" "SMX" "\10" "EST" \ 217 "\11" "TM2" "\12" "SSSE3" "\13" "CID" "\14" "SDBG" \ 218 "\15" "FMA" "\16" "CX16" "\17" "xTPR" "\20" "PDCM" \ 219 "\21" "B16" "\22" "PCID" "\23" "DCA" "\24" "SSE41" \ 220 "\25" "SSE42" "\26" "X2APIC" "\27" "MOVBE" "\30" "POPCNT" \ 221 "\31" "DEADLINE" "\32" "AES" "\33" "XSAVE" "\34" "OSXSAVE" \ 222 "\35" "AVX" "\36" "F16C" "\37" "RDRAND" "\40" "RAZ" 223 224 /* CPUID Fn00000001 %eax */ 225 226 #define CPUID_TO_BASEFAMILY(cpuid) (((cpuid) >> 8) & 0xf) 227 #define CPUID_TO_BASEMODEL(cpuid) (((cpuid) >> 4) & 0xf) 228 #define CPUID_TO_STEPPING(cpuid) ((cpuid) & 0xf) 229 230 /* 231 * The Extended family bits should only be inspected when CPUID_TO_BASEFAMILY() 232 * returns 15. They are use to encode family value 16 to 270 (add 15). 233 * The Extended model bits are the high 4 bits of the model. 234 * They are only valid for family >= 15 or family 6 (intel, but all amd 235 * family 6 are documented to return zero bits for them). 236 */ 237 #define CPUID_TO_EXTFAMILY(cpuid) (((cpuid) >> 20) & 0xff) 238 #define CPUID_TO_EXTMODEL(cpuid) (((cpuid) >> 16) & 0xf) 239 240 /* The macros for the Display Family and the Display Model */ 241 #define CPUID_TO_FAMILY(cpuid) (CPUID_TO_BASEFAMILY(cpuid) \ 242 + ((CPUID_TO_BASEFAMILY(cpuid) != 0x0f) \ 243 ? 0 : CPUID_TO_EXTFAMILY(cpuid))) 244 #define CPUID_TO_MODEL(cpuid) (CPUID_TO_BASEMODEL(cpuid) \ 245 | ((CPUID_TO_BASEFAMILY(cpuid) != 0x0f) \ 246 && (CPUID_TO_BASEFAMILY(cpuid) != 0x06) \ 247 ? 0 : (CPUID_TO_EXTMODEL(cpuid) << 4))) 248 249 /* CPUID Fn00000001 %ebx */ 250 #define CPUID_BRAND_INDEX __BITS(7,0) 251 #define CPUID_CLFLUSH_SIZE __BITS(15,8) 252 #define CPUID_HTT_CORES __BITS(23,16) 253 #define CPUID_LOCAL_APIC_ID __BITS(31,24) 254 255 /* 256 * Intel Deterministic Cache Parameter Leaf 257 * Fn0000_0004 258 */ 259 260 /* %eax */ 261 #define CPUID_DCP_CACHETYPE __BITS(4, 0) /* Cache type */ 262 #define CPUID_DCP_CACHETYPE_N 0 /* NULL */ 263 #define CPUID_DCP_CACHETYPE_D 1 /* Data cache */ 264 #define CPUID_DCP_CACHETYPE_I 2 /* Instruction cache */ 265 #define CPUID_DCP_CACHETYPE_U 3 /* Unified cache */ 266 #define CPUID_DCP_CACHELEVEL __BITS(7, 5) /* Cache level (start at 1) */ 267 #define CPUID_DCP_SELFINITCL __BIT(8) /* Self initializing cachelvl*/ 268 #define CPUID_DCP_FULLASSOC __BIT(9) /* Full associative */ 269 #define CPUID_DCP_SHAREING __BITS(25, 14) /* shareing */ 270 #define CPUID_DCP_CORE_P_PKG __BITS(31, 26) /* Cores/package */ 271 272 /* %ebx */ 273 #define CPUID_DCP_LINESIZE __BITS(11, 0) /* System coherency linesize */ 274 #define CPUID_DCP_PARTITIONS __BITS(21, 12) /* Physical line partitions */ 275 #define CPUID_DCP_WAYS __BITS(31, 22) /* Ways of associativity */ 276 277 /* Number of sets: %ecx */ 278 279 /* %edx */ 280 #define CPUID_DCP_INVALIDATE __BIT(0) /* WB invalidate/invalidate */ 281 #define CPUID_DCP_INCLUSIVE __BIT(1) /* Cache inclusiveness */ 282 #define CPUID_DCP_COMPLEX __BIT(2) /* Complex cache indexing */ 283 284 /* 285 * Intel Digital Thermal Sensor and 286 * Power Management, Fn0000_0006 - %eax. 287 */ 288 #define CPUID_DSPM_DTS __BIT(0) /* Digital Thermal Sensor */ 289 #define CPUID_DSPM_IDA __BIT(1) /* Intel Dynamic Acceleration */ 290 #define CPUID_DSPM_ARAT __BIT(2) /* Always Running APIC Timer */ 291 #define CPUID_DSPM_PLN __BIT(4) /* Power Limit Notification */ 292 #define CPUID_DSPM_ECMD __BIT(5) /* Clock Modulation Extension */ 293 #define CPUID_DSPM_PTM __BIT(6) /* Package Level Thermal Management */ 294 #define CPUID_DSPM_HWP __BIT(7) /* HWP */ 295 #define CPUID_DSPM_HWP_NOTIFY __BIT(8) /* HWP Notification */ 296 #define CPUID_DSPM_HWP_ACTWIN __BIT(9) /* HWP Activity Window */ 297 #define CPUID_DSPM_HWP_EPP __BIT(10) /* HWP Energy Performance Preference */ 298 #define CPUID_DSPM_HWP_PLR __BIT(11) /* HWP Package Level Request */ 299 #define CPUID_DSPM_HDC __BIT(13) /* Hardware Duty Cycling */ 300 #define CPUID_DSPM_TBMT3 __BIT(14) /* Turbo Boost Max Technology 3.0 */ 301 #define CPUID_DSPM_HWP_CAP __BIT(15) /* HWP Capabilities */ 302 #define CPUID_DSPM_HWP_PECI __BIT(16) /* HWP PECI override */ 303 #define CPUID_DSPM_HWP_FLEX __BIT(17) /* Flexible HWP */ 304 #define CPUID_DSPM_HWP_FAST __BIT(18) /* Fast access for IA32_HWP_REQUEST */ 305 #define CPUID_DSPM_HWP_IGNIDL __BIT(20) /* Ignore Idle Logical Processor HWP */ 306 307 #define CPUID_DSPM_FLAGS "\20" \ 308 "\1" "DTS" "\2" "IDA" "\3" "ARAT" \ 309 "\5" "PLN" "\6" "ECMD" "\7" "PTM" "\10" "HWP" \ 310 "\11" "HWP_NOTIFY" "\12" "HWP_ACTWIN" "\13" "HWP_EPP" "\14" "HWP_PLR" \ 311 "\16" "HDC" "\17" "TBM3" "\20" "HWP_CAP" \ 312 "\21" "HWP_PECI" "\22" "HWP_FLEX" "\23" "HWP_FAST" \ 313 "25" "HWP_IGNIDL" 314 315 /* 316 * Intel Digital Thermal Sensor and 317 * Power Management, Fn0000_0006 - %ecx. 318 */ 319 #define CPUID_DSPM_HWF 0x00000001 /* MSR_APERF/MSR_MPERF available */ 320 #define CPUID_DSPM_EPB 0x00000008 /* Energy Performance Bias */ 321 322 #define CPUID_DSPM_FLAGS1 "\20" "\1" "HWF" "\4" "EPB" 323 324 /* 325 * Intel Structured Extended Feature leaf Fn0000_0007 326 * %eax == 0: Subleaf 0 327 * %eax: The Maximum input value for supported subleaf. 328 * %ebx: Feature bits. 329 * %ecx: Feature bits. 330 * %edx: Feature bits. 331 */ 332 333 /* %ebx */ 334 #define CPUID_SEF_FSGSBASE __BIT(0) /* {RD,WR}{FS,GS}BASE */ 335 #define CPUID_SEF_TSC_ADJUST __BIT(1) /* IA32_TSC_ADJUST MSR support */ 336 #define CPUID_SEF_SGX __BIT(2) /* Software Guard Extentions */ 337 #define CPUID_SEF_BMI1 __BIT(3) /* advanced bit manipulation ext. 1st grp */ 338 #define CPUID_SEF_HLE __BIT(4) /* Hardware Lock Elision */ 339 #define CPUID_SEF_AVX2 __BIT(5) /* Advanced Vector Extensions 2 */ 340 #define CPUID_SEF_FDPEXONLY __BIT(6) /* x87FPU Data ptr updated only on x87exp */ 341 #define CPUID_SEF_SMEP __BIT(7) /* Supervisor-Mode Excecution Prevention */ 342 #define CPUID_SEF_BMI2 __BIT(8) /* advanced bit manipulation ext. 2nd grp */ 343 #define CPUID_SEF_ERMS __BIT(9) /* Enhanced REP MOVSB/STOSB */ 344 #define CPUID_SEF_INVPCID __BIT(10) /* INVPCID instruction */ 345 #define CPUID_SEF_RTM __BIT(11) /* Restricted Transactional Memory */ 346 #define CPUID_SEF_QM __BIT(12) /* Resource Director Technology Monitoring */ 347 #define CPUID_SEF_FPUCSDS __BIT(13) /* Deprecate FPU CS and FPU DS values */ 348 #define CPUID_SEF_MPX __BIT(14) /* Memory Protection Extensions */ 349 #define CPUID_SEF_PQE __BIT(15) /* Resource Director Technology Allocation */ 350 #define CPUID_SEF_AVX512F __BIT(16) /* AVX-512 Foundation */ 351 #define CPUID_SEF_AVX512DQ __BIT(17) /* AVX-512 Double/Quadword */ 352 #define CPUID_SEF_RDSEED __BIT(18) /* RDSEED instruction */ 353 #define CPUID_SEF_ADX __BIT(19) /* ADCX/ADOX instructions */ 354 #define CPUID_SEF_SMAP __BIT(20) /* Supervisor-Mode Access Prevention */ 355 #define CPUID_SEF_AVX512_IFMA __BIT(21) /* AVX-512 Integer Fused Multiply Add */ 356 #define CPUID_SEF_CLFLUSHOPT __BIT(23) /* Cache Line FLUSH OPTimized */ 357 #define CPUID_SEF_CLWB __BIT(24) /* Cache Line Write Back */ 358 #define CPUID_SEF_PT __BIT(25) /* Processor Trace */ 359 #define CPUID_SEF_AVX512PF __BIT(26) /* AVX-512 PreFetch */ 360 #define CPUID_SEF_AVX512ER __BIT(27) /* AVX-512 Exponential and Reciprocal */ 361 #define CPUID_SEF_AVX512CD __BIT(28) /* AVX-512 Conflict Detection */ 362 #define CPUID_SEF_SHA __BIT(29) /* SHA Extensions */ 363 #define CPUID_SEF_AVX512BW __BIT(30) /* AVX-512 Byte and Word */ 364 #define CPUID_SEF_AVX512VL __BIT(31) /* AVX-512 Vector Length */ 365 366 #define CPUID_SEF_FLAGS "\20" \ 367 "\1" "FSGSBASE" "\2" "TSCADJUST" "\3" "SGX" "\4" "BMI1" \ 368 "\5" "HLE" "\6" "AVX2" "\7" "FDPEXONLY" "\10" "SMEP" \ 369 "\11" "BMI2" "\12" "ERMS" "\13" "INVPCID" "\14" "RTM" \ 370 "\15" "QM" "\16" "FPUCSDS" "\17" "MPX" "\20" "PQE" \ 371 "\21" "AVX512F" "\22" "AVX512DQ" "\23" "RDSEED" "\24" "ADX" \ 372 "\25" "SMAP" "\26" "AVX512_IFMA" "\30" "CLFLUSHOPT" \ 373 "\31" "CLWB" "\32" "PT" "\33" "AVX512PF" "\34" "AVX512ER" \ 374 "\35" "AVX512CD""\36" "SHA" "\37" "AVX512BW" "\40" "AVX512VL" 375 376 /* %ecx */ 377 #define CPUID_SEF_PREFETCHWT1 __BIT(0) /* PREFETCHWT1 instruction */ 378 #define CPUID_SEF_AVX512_VBMI __BIT(1) /* AVX-512 Vector Byte Manipulation */ 379 #define CPUID_SEF_UMIP __BIT(2) /* User-Mode Instruction prevention */ 380 #define CPUID_SEF_PKU __BIT(3) /* Protection Keys for User-mode pages */ 381 #define CPUID_SEF_OSPKE __BIT(4) /* OS has set CR4.PKE to ena. protec. keys */ 382 #define CPUID_SEF_AVX512_VBMI2 __BIT(6) /* AVX-512 Vector Byte Manipulation 2 */ 383 #define CPUID_SEF_GFNI __BIT(8) 384 #define CPUID_SEF_VAES __BIT(9) 385 #define CPUID_SEF_VPCLMULQDQ __BIT(10) 386 #define CPUID_SEF_AVX512_VNNI __BIT(11) /* Vector neural Network Instruction */ 387 #define CPUID_SEF_AVX512_BITALG __BIT(12) 388 #define CPUID_SEF_AVX512_VPOPCNTDQ __BIT(14) 389 #define CPUID_SEF_RDPID __BIT(22) /* RDPID and IA32_TSC_AUX */ 390 #define CPUID_SEF_SGXLC __BIT(30) /* SGX Launch Configuration */ 391 392 #define CPUID_SEF_FLAGS1 "\20" \ 393 "\1" "PREFETCHWT1" "\2" "AVX512_VBMI" "\3" "UMIP" "\4" "PKU" \ 394 "\5" "OSPKE" "\7" "AVX512_VBMI2" \ 395 "\11" "GFNI" "\12" "VAES" "\13" "VPCLMULQDQ" "\14" "AVX512_VNNI"\ 396 "\15" "AVX512_BITALG" "\17" "AVX512_VPOPCNTDQ" \ 397 "\27" "RDPID" \ 398 "\37" "SGXLC" 399 400 /* %edx */ 401 #define CPUID_SEF_AVX512_4VNNIW __BIT(2) 402 #define CPUID_SEF_AVX512_4FMAPS __BIT(3) 403 #define CPUID_SEF_IBRS __BIT(26) /* IBRS / IBPB Speculation Control */ 404 #define CPUID_SEF_STIBP __BIT(27) /* STIBP Speculation Control */ 405 #define CPUID_SEF_ARCH_CAP __BIT(29) /* IA32_ARCH_CAPABILITIES */ 406 #define CPUID_SEF_SSBD __BIT(31) /* Speculative Store Bypass Disable */ 407 408 #define CPUID_SEF_FLAGS2 "\20" \ 409 "\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS" \ 410 "\33" "IBRS" "\34" "STIBP" \ 411 "\36" "ARCH_CAP" "\40" "SSBD" 412 413 /* 414 * CPUID Processor extended state Enumeration Fn0000000d 415 * 416 * %ecx == 0: supported features info: 417 * %eax: Valid bits of lower 32bits of XCR0 418 * %ebx: Maximum save area size for features enabled in XCR0 419 * %ecx: Maximum save area size for all cpu features 420 * %edx: Valid bits of upper 32bits of XCR0 421 * 422 * %ecx == 1: 423 * %eax: Bit 0 => xsaveopt instruction available (sandy bridge onwards) 424 * %ebx: Save area size for features enabled by XCR0 | IA32_XSS 425 * %ecx: Valid bits of lower 32bits of IA32_XSS 426 * %edx: Valid bits of upper 32bits of IA32_XSS 427 * 428 * %ecx >= 2: Save area details for XCR0 bit n 429 * %eax: size of save area for this feature 430 * %ebx: offset of save area for this feature 431 * %ecx, %edx: reserved 432 * All of %eax, %ebx, %ecx and %edx are zero for unsupported features. 433 */ 434 435 /* %ecx=1 %eax */ 436 #define CPUID_PES1_XSAVEOPT 0x00000001 /* xsaveopt instruction */ 437 #define CPUID_PES1_XSAVEC 0x00000002 /* xsavec & compacted XRSTOR */ 438 #define CPUID_PES1_XGETBV 0x00000004 /* xgetbv with ECX = 1 */ 439 #define CPUID_PES1_XSAVES 0x00000008 /* xsaves/xrstors, IA32_XSS */ 440 441 #define CPUID_PES1_FLAGS "\20" \ 442 "\1" "XSAVEOPT" "\2" "XSAVEC" "\3" "XGETBV" "\4" "XSAVES" 443 444 /* 445 * Intel Deterministic Address Translation Parameter Leaf 446 * Fn0000_0018 447 */ 448 449 /* %ecx=0 %eax __BITS(31, 0): the maximum input value of supported sub-leaf */ 450 451 /* %ebx */ 452 #define CPUID_DATP_PGSIZE __BITS(3, 0) /* page size */ 453 #define CPUID_DATP_PGSIZE_4KB __BIT(0) /* 4KB page support */ 454 #define CPUID_DATP_PGSIZE_2MB __BIT(1) /* 2MB page support */ 455 #define CPUID_DATP_PGSIZE_4MB __BIT(2) /* 4MB page support */ 456 #define CPUID_DATP_PGSIZE_1GB __BIT(3) /* 1GB page support */ 457 #define CPUID_DATP_PARTITIONING __BITS(10, 8) /* Partitioning */ 458 #define CPUID_DATP_WAYS __BITS(31, 16) /* Ways of associativity */ 459 460 /* Number of sets: %ecx */ 461 462 /* %edx */ 463 #define CPUID_DATP_TCTYPE __BITS(4, 0) /* Translation Cache type */ 464 #define CPUID_DATP_TCTYPE_N 0 /* NULL (not valid) */ 465 #define CPUID_DATP_TCTYPE_D 1 /* Data TLB */ 466 #define CPUID_DATP_TCTYPE_I 2 /* Instruction TLB */ 467 #define CPUID_DATP_TCTYPE_U 3 /* Unified TLB */ 468 #define CPUID_DATP_TCLEVEL __BITS(7, 5) /* TLB level (start at 1) */ 469 #define CPUID_DATP_FULLASSOC __BIT(8) /* Full associative */ 470 #define CPUID_DATP_SHAREING __BITS(25, 14) /* shareing */ 471 472 473 /* Intel Fn80000001 extended features - %edx */ 474 #define CPUID_SYSCALL 0x00000800 /* SYSCALL/SYSRET */ 475 #define CPUID_XD 0x00100000 /* Execute Disable (like CPUID_NOX) */ 476 #define CPUID_P1GB 0x04000000 /* 1GB Large Page Support */ 477 #define CPUID_RDTSCP 0x08000000 /* Read TSC Pair Instruction */ 478 #define CPUID_EM64T 0x20000000 /* Intel EM64T */ 479 480 #define CPUID_INTEL_EXT_FLAGS "\20" \ 481 "\14" "SYSCALL/SYSRET" "\25" "XD" "\33" "P1GB" \ 482 "\34" "RDTSCP" "\36" "EM64T" 483 484 /* Intel Fn80000001 extended features - %ecx */ 485 #define CPUID_LAHF 0x00000001 /* LAHF/SAHF in IA-32e mode, 64bit sub*/ 486 /* 0x00000020 */ /* LZCNT. Same as AMD's CPUID_LZCNT */ 487 #define CPUID_PREFETCHW 0x00000100 /* PREFETCHW */ 488 489 #define CPUID_INTEL_FLAGS4 "\20" \ 490 "\1" "LAHF" "\02" "B01" "\03" "B02" \ 491 "\06" "LZCNT" \ 492 "\11" "PREFETCHW" 493 494 495 /* AMD/VIA Fn80000001 extended features - %edx */ 496 /* CPUID_SYSCALL SYSCALL/SYSRET */ 497 #define CPUID_MPC 0x00080000 /* Multiprocessing Capable */ 498 #define CPUID_NOX 0x00100000 /* No Execute Page Protection */ 499 #define CPUID_MMXX 0x00400000 /* AMD MMX Extensions */ 500 /* CPUID_MMX MMX supported */ 501 /* CPUID_FXSR fast FP/MMX save/restore */ 502 #define CPUID_FFXSR 0x02000000 /* FXSAVE/FXSTOR Extensions */ 503 /* CPUID_P1GB 1GB Large Page Support */ 504 /* CPUID_RDTSCP Read TSC Pair Instruction */ 505 /* CPUID_EM64T Long mode */ 506 #define CPUID_3DNOW2 0x40000000 /* 3DNow! Instruction Extension */ 507 #define CPUID_3DNOW 0x80000000 /* 3DNow! Instructions */ 508 509 #define CPUID_EXT_FLAGS "\20" \ 510 "\14" "SYSCALL/SYSRET" \ 511 "\24" "MPC" \ 512 "\25" "NOX" "\27" "MMXX" "\30" "MMX" \ 513 "\31" "FXSR" "\32" "FFXSR" "\33" "P1GB" "\34" "RDTSCP" \ 514 "\36" "LONG" "\37" "3DNOW2" "\40" "3DNOW" 515 516 /* AMD Fn80000001 extended features - %ecx */ 517 /* CPUID_LAHF LAHF/SAHF instruction */ 518 #define CPUID_CMPLEGACY 0x00000002 /* Compare Legacy */ 519 #define CPUID_SVM 0x00000004 /* Secure Virtual Machine */ 520 #define CPUID_EAPIC 0x00000008 /* Extended APIC space */ 521 #define CPUID_ALTMOVCR0 0x00000010 /* Lock Mov Cr0 */ 522 #define CPUID_LZCNT 0x00000020 /* LZCNT instruction */ 523 #define CPUID_SSE4A 0x00000040 /* SSE4A instruction set */ 524 #define CPUID_MISALIGNSSE 0x00000080 /* Misaligned SSE */ 525 #define CPUID_3DNOWPF 0x00000100 /* 3DNow Prefetch */ 526 #define CPUID_OSVW 0x00000200 /* OS visible workarounds */ 527 #define CPUID_IBS 0x00000400 /* Instruction Based Sampling */ 528 #define CPUID_XOP 0x00000800 /* XOP instruction set */ 529 #define CPUID_SKINIT 0x00001000 /* SKINIT */ 530 #define CPUID_WDT 0x00002000 /* watchdog timer support */ 531 #define CPUID_LWP 0x00008000 /* Light Weight Profiling */ 532 #define CPUID_FMA4 0x00010000 /* FMA4 instructions */ 533 #define CPUID_TCE 0x00020000 /* Translation cache Extension */ 534 #define CPUID_NODEID 0x00080000 /* NodeID MSR available*/ 535 #define CPUID_TBM 0x00200000 /* TBM instructions */ 536 #define CPUID_TOPOEXT 0x00400000 /* cpuid Topology Extension */ 537 #define CPUID_PCEC 0x00800000 /* Perf Ctr Ext Core */ 538 #define CPUID_PCENB 0x01000000 /* Perf Ctr Ext NB */ 539 #define CPUID_SPM 0x02000000 /* Stream Perf Mon */ 540 #define CPUID_DBE 0x04000000 /* Data Breakpoint Extension */ 541 #define CPUID_PTSC 0x08000000 /* PerfTsc */ 542 #define CPUID_L2IPERFC 0x10000000 /* L2I performance counter Extension */ 543 #define CPUID_MWAITX 0x20000000 /* MWAITX/MONITORX support */ 544 545 #define CPUID_AMD_FLAGS4 "\20" \ 546 "\1" "LAHF" "\2" "CMPLEGACY" "\3" "SVM" "\4" "EAPIC" \ 547 "\5" "ALTMOVCR0" "\6" "LZCNT" "\7" "SSE4A" "\10" "MISALIGNSSE" \ 548 "\11" "3DNOWPREFETCH" \ 549 "\12" "OSVW" "\13" "IBS" "\14" "XOP" \ 550 "\15" "SKINIT" "\16" "WDT" "\17" "B14" "\20" "LWP" \ 551 "\21" "FMA4" "\22" "TCE" "\23" "B18" "\24" "NodeID" \ 552 "\25" "B20" "\26" "TBM" "\27" "TopoExt" "\30" "PCExtC" \ 553 "\31" "PCExtNB" "\32" "StrmPM" "\33" "DBExt" "\34" "PerfTsc" \ 554 "\35" "L2IPERFC" "\36" "MWAITX" "\37" "B30" "\40" "B31" 555 556 /* 557 * AMD Advanced Power Management 558 * CPUID Fn8000_0007 %edx 559 */ 560 #define CPUID_APM_TS 0x00000001 /* Temperature Sensor */ 561 #define CPUID_APM_FID 0x00000002 /* Frequency ID control */ 562 #define CPUID_APM_VID 0x00000004 /* Voltage ID control */ 563 #define CPUID_APM_TTP 0x00000008 /* THERMTRIP (PCI F3xE4 register) */ 564 #define CPUID_APM_HTC 0x00000010 /* Hardware thermal control (HTC) */ 565 #define CPUID_APM_STC 0x00000020 /* Software thermal control (STC) */ 566 #define CPUID_APM_100 0x00000040 /* 100MHz multiplier control */ 567 #define CPUID_APM_HWP 0x00000080 /* HW P-State control */ 568 #define CPUID_APM_TSC 0x00000100 /* TSC invariant */ 569 #define CPUID_APM_CPB 0x00000200 /* Core performance boost */ 570 #define CPUID_APM_EFF 0x00000400 /* Effective Frequency (read-only) */ 571 572 #define CPUID_APM_FLAGS "\20" \ 573 "\1" "TS" "\2" "FID" "\3" "VID" "\4" "TTP" \ 574 "\5" "HTC" "\6" "STC" "\7" "100" "\10" "HWP" \ 575 "\11" "TSC" "\12" "CPB" "\13" "EffFreq" "\14" "B11" \ 576 "\15" "B12" 577 578 /* AMD Fn8000000a %edx features (SVM features) */ 579 #define CPUID_AMD_SVM_NP 0x00000001 580 #define CPUID_AMD_SVM_LbrVirt 0x00000002 581 #define CPUID_AMD_SVM_SVML 0x00000004 582 #define CPUID_AMD_SVM_NRIPS 0x00000008 583 #define CPUID_AMD_SVM_TSCRateCtrl 0x00000010 584 #define CPUID_AMD_SVM_VMCBCleanBits 0x00000020 585 #define CPUID_AMD_SVM_FlushByASID 0x00000040 586 #define CPUID_AMD_SVM_DecodeAssist 0x00000080 587 #define CPUID_AMD_SVM_PauseFilter 0x00000400 588 #define CPUID_AMD_SVM_PFThreshold 0x0x001000 /* PAUSE filter threshold */ 589 #define CPUID_AMD_SVM_AVIC 0x00002000 /* AMD Virtual intr. ctrl */ 590 #define CPUID_AMD_SVM_V_VMSAVE_VMLOAD 0x00008000 /* Virtual VM{SAVE/LOAD} */ 591 #define CPUID_AMD_SVM_vGIF 0x00010000 /* Virtualized GIF */ 592 #define CPUID_AMD_SVM_FLAGS "\20" \ 593 "\1" "NP" "\2" "LbrVirt" "\3" "SVML" "\4" "NRIPS" \ 594 "\5" "TSCRate" "\6" "VMCBCleanBits" \ 595 "\7" "FlushByASID" "\10" "DecodeAssist" \ 596 "\11" "B08" "\12" "B09" "\13" "PauseFilter" "\14" "B11" \ 597 "\15" "PFThreshold" "\16" "AVIC" "\17" "B14" \ 598 "\20" "V_VMSAVE_VMLOAD" \ 599 "\21" "VGIF" 600 601 /* 602 * Centaur Extended Feature flags 603 */ 604 #define CPUID_VIA_HAS_RNG 0x00000004 /* Random number generator */ 605 #define CPUID_VIA_DO_RNG 0x00000008 606 #define CPUID_VIA_HAS_ACE 0x00000040 /* AES Encryption */ 607 #define CPUID_VIA_DO_ACE 0x00000080 608 #define CPUID_VIA_HAS_ACE2 0x00000100 /* AES+CTR instructions */ 609 #define CPUID_VIA_DO_ACE2 0x00000200 610 #define CPUID_VIA_HAS_PHE 0x00000400 /* SHA1+SHA256 HMAC */ 611 #define CPUID_VIA_DO_PHE 0x00000800 612 #define CPUID_VIA_HAS_PMM 0x00001000 /* RSA Instructions */ 613 #define CPUID_VIA_DO_PMM 0x00002000 614 615 #define CPUID_FLAGS_PADLOCK "\20" \ 616 "\3" "RNG" "\7" "AES" "\11" "AES/CTR" "\13" "SHA1/SHA256" \ 617 "\15" "RSA" 618 619 /* 620 * Model-specific registers for the i386 family 621 */ 622 #define MSR_P5_MC_ADDR 0x000 /* P5 only */ 623 #define MSR_P5_MC_TYPE 0x001 /* P5 only */ 624 #define MSR_TSC 0x010 625 #define MSR_CESR 0x011 /* P5 only (trap on P6) */ 626 #define MSR_CTR0 0x012 /* P5 only (trap on P6) */ 627 #define MSR_CTR1 0x013 /* P5 only (trap on P6) */ 628 #define MSR_IA32_PLATFORM_ID 0x017 629 #define MSR_APICBASE 0x01b 630 #define APICBASE_BSP 0x00000100 /* boot processor */ 631 #define APICBASE_EXTD 0x00000400 /* x2APIC mode */ 632 #define APICBASE_EN 0x00000800 /* software enable */ 633 /* 634 * APICBASE_PHYSADDR is actually variable-sized on some CPUs. But we're 635 * only interested in the initial value, which is guaranteed to fit the 636 * first 32 bits. So this macro is fine. 637 */ 638 #define APICBASE_PHYSADDR 0xfffff000 /* physical address */ 639 #define MSR_EBL_CR_POWERON 0x02a 640 #define MSR_EBC_FREQUENCY_ID 0x02c /* PIV only */ 641 #define MSR_TEST_CTL 0x033 642 #define MSR_IA32_SPEC_CTRL 0x048 643 #define IA32_SPEC_CTRL_IBRS 0x01 644 #define IA32_SPEC_CTRL_STIBP 0x02 645 #define IA32_SPEC_CTRL_SSBD 0x04 646 #define MSR_IA32_PRED_CMD 0x049 647 #define IA32_PRED_CMD_IBPB 0x01 648 #define MSR_BIOS_UPDT_TRIG 0x079 649 #define MSR_BBL_CR_D0 0x088 /* PII+ only */ 650 #define MSR_BBL_CR_D1 0x089 /* PII+ only */ 651 #define MSR_BBL_CR_D2 0x08a /* PII+ only */ 652 #define MSR_BIOS_SIGN 0x08b 653 #define MSR_PERFCTR0 0x0c1 654 #define MSR_PERFCTR1 0x0c2 655 #define MSR_FSB_FREQ 0x0cd /* Core Duo/Solo only */ 656 #define MSR_MPERF 0x0e7 657 #define MSR_APERF 0x0e8 658 #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ 659 #define MSR_MTRRcap 0x0fe 660 #define MSR_IA32_ARCH_CAPABILITIES 0x10a 661 #define IA32_ARCH_RDCL_NO 0x01 662 #define IA32_ARCH_IBRS_ALL 0x02 663 #define IA32_ARCH_RSBA 0x04 664 #define IA32_ARCH_SSB_NO 0x10 665 #define MSR_BBL_CR_ADDR 0x116 /* PII+ only */ 666 #define MSR_BBL_CR_DECC 0x118 /* PII+ only */ 667 #define MSR_BBL_CR_CTL 0x119 /* PII+ only */ 668 #define MSR_BBL_CR_TRIG 0x11a /* PII+ only */ 669 #define MSR_BBL_CR_BUSY 0x11b /* PII+ only */ 670 #define MSR_BBL_CR_CTR3 0x11e /* PII+ only */ 671 #define MSR_SYSENTER_CS 0x174 /* PII+ only */ 672 #define MSR_SYSENTER_ESP 0x175 /* PII+ only */ 673 #define MSR_SYSENTER_EIP 0x176 /* PII+ only */ 674 #define MSR_MCG_CAP 0x179 675 #define MSR_MCG_STATUS 0x17a 676 #define MSR_MCG_CTL 0x17b 677 #define MSR_EVNTSEL0 0x186 678 #define MSR_EVNTSEL1 0x187 679 #define MSR_PERF_STATUS 0x198 /* Pentium M */ 680 #define MSR_PERF_CTL 0x199 /* Pentium M */ 681 #define MSR_THERM_CONTROL 0x19a 682 #define MSR_THERM_INTERRUPT 0x19b 683 #define MSR_THERM_STATUS 0x19c 684 #define MSR_THERM2_CTL 0x19d /* Pentium M */ 685 #define MSR_MISC_ENABLE 0x1a0 686 #define MSR_TEMPERATURE_TARGET 0x1a2 687 #define MSR_DEBUGCTLMSR 0x1d9 688 #define MSR_LASTBRANCHFROMIP 0x1db 689 #define MSR_LASTBRANCHTOIP 0x1dc 690 #define MSR_LASTINTFROMIP 0x1dd 691 #define MSR_LASTINTTOIP 0x1de 692 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 693 #define MSR_MTRRphysBase0 0x200 694 #define MSR_MTRRphysMask0 0x201 695 #define MSR_MTRRphysBase1 0x202 696 #define MSR_MTRRphysMask1 0x203 697 #define MSR_MTRRphysBase2 0x204 698 #define MSR_MTRRphysMask2 0x205 699 #define MSR_MTRRphysBase3 0x206 700 #define MSR_MTRRphysMask3 0x207 701 #define MSR_MTRRphysBase4 0x208 702 #define MSR_MTRRphysMask4 0x209 703 #define MSR_MTRRphysBase5 0x20a 704 #define MSR_MTRRphysMask5 0x20b 705 #define MSR_MTRRphysBase6 0x20c 706 #define MSR_MTRRphysMask6 0x20d 707 #define MSR_MTRRphysBase7 0x20e 708 #define MSR_MTRRphysMask7 0x20f 709 #define MSR_MTRRphysBase8 0x210 710 #define MSR_MTRRphysMask8 0x211 711 #define MSR_MTRRphysBase9 0x212 712 #define MSR_MTRRphysMask9 0x213 713 #define MSR_MTRRphysBase10 0x214 714 #define MSR_MTRRphysMask10 0x215 715 #define MSR_MTRRphysBase11 0x216 716 #define MSR_MTRRphysMask11 0x217 717 #define MSR_MTRRphysBase12 0x218 718 #define MSR_MTRRphysMask12 0x219 719 #define MSR_MTRRphysBase13 0x21a 720 #define MSR_MTRRphysMask13 0x21b 721 #define MSR_MTRRphysBase14 0x21c 722 #define MSR_MTRRphysMask14 0x21d 723 #define MSR_MTRRphysBase15 0x21e 724 #define MSR_MTRRphysMask15 0x21f 725 #define MSR_MTRRfix64K_00000 0x250 726 #define MSR_MTRRfix16K_80000 0x258 727 #define MSR_MTRRfix16K_A0000 0x259 728 #define MSR_MTRRfix4K_C0000 0x268 729 #define MSR_MTRRfix4K_C8000 0x269 730 #define MSR_MTRRfix4K_D0000 0x26a 731 #define MSR_MTRRfix4K_D8000 0x26b 732 #define MSR_MTRRfix4K_E0000 0x26c 733 #define MSR_MTRRfix4K_E8000 0x26d 734 #define MSR_MTRRfix4K_F0000 0x26e 735 #define MSR_MTRRfix4K_F8000 0x26f 736 #define MSR_CR_PAT 0x277 737 #define MSR_MTRRdefType 0x2ff 738 #define MSR_MC0_CTL 0x400 739 #define MSR_MC0_STATUS 0x401 740 #define MSR_MC0_ADDR 0x402 741 #define MSR_MC0_MISC 0x403 742 #define MSR_MC1_CTL 0x404 743 #define MSR_MC1_STATUS 0x405 744 #define MSR_MC1_ADDR 0x406 745 #define MSR_MC1_MISC 0x407 746 #define MSR_MC2_CTL 0x408 747 #define MSR_MC2_STATUS 0x409 748 #define MSR_MC2_ADDR 0x40a 749 #define MSR_MC2_MISC 0x40b 750 #define MSR_MC3_CTL 0x40c 751 #define MSR_MC3_STATUS 0x40d 752 #define MSR_MC3_ADDR 0x40e 753 #define MSR_MC3_MISC 0x40f 754 #define MSR_MC4_CTL 0x410 755 #define MSR_MC4_STATUS 0x411 756 #define MSR_MC4_ADDR 0x412 757 #define MSR_MC4_MISC 0x413 758 /* 0x480 - 0x490 VMX */ 759 #define MSR_X2APIC_BASE 0x800 /* 0x800 - 0xBFF */ 760 #define MSR_X2APIC_ID 0x002 /* x2APIC ID. (RO) */ 761 #define MSR_X2APIC_VERS 0x003 /* Version. (RO) */ 762 #define MSR_X2APIC_TPRI 0x008 /* Task Prio. (RW) */ 763 #define MSR_X2APIC_PPRI 0x00a /* Processor prio. (RO) */ 764 #define MSR_X2APIC_EOI 0x00b /* End Int. (W) */ 765 #define MSR_X2APIC_LDR 0x00d /* Logical dest. (RO) */ 766 #define MSR_X2APIC_SVR 0x00f /* Spurious intvec (RW) */ 767 #define MSR_X2APIC_ISR 0x010 /* In-Service Status (RO) */ 768 #define MSR_X2APIC_TMR 0x018 /* Trigger Mode (RO) */ 769 #define MSR_X2APIC_IRR 0x020 /* Interrupt Req (RO) */ 770 #define MSR_X2APIC_ESR 0x028 /* Err status. (RW) */ 771 #define MSR_X2APIC_LVT_CMCI 0x02f /* LVT CMCI (RW) */ 772 #define MSR_X2APIC_ICRLO 0x030 /* Int. cmd. (RW64) */ 773 #define MSR_X2APIC_LVTT 0x032 /* Loc.vec.(timer) (RW) */ 774 #define MSR_X2APIC_TMINT 0x033 /* Loc.vec (Thermal) (RW) */ 775 #define MSR_X2APIC_PCINT 0x034 /* Loc.vec (Perf Mon) (RW) */ 776 #define MSR_X2APIC_LVINT0 0x035 /* Loc.vec (LINT0) (RW) */ 777 #define MSR_X2APIC_LVINT1 0x036 /* Loc.vec (LINT1) (RW) */ 778 #define MSR_X2APIC_LVERR 0x037 /* Loc.vec (ERROR) (RW) */ 779 #define MSR_X2APIC_ICR_TIMER 0x038 /* Initial count (RW) */ 780 #define MSR_X2APIC_CCR_TIMER 0x039 /* Current count (RO) */ 781 #define MSR_X2APIC_DCR_TIMER 0x03e /* Divisor config (RW) */ 782 #define MSR_X2APIC_SELF_IPI 0x03f /* SELF IPI (W) */ 783 784 /* 785 * VIA "Nehemiah" MSRs 786 */ 787 #define MSR_VIA_RNG 0x0000110b 788 #define MSR_VIA_RNG_ENABLE 0x00000040 789 #define MSR_VIA_RNG_NOISE_MASK 0x00000300 790 #define MSR_VIA_RNG_NOISE_A 0x00000000 791 #define MSR_VIA_RNG_NOISE_B 0x00000100 792 #define MSR_VIA_RNG_2NOISE 0x00000300 793 #define MSR_VIA_ACE 0x00001107 794 #define MSR_VIA_ACE_ENABLE 0x10000000 795 796 /* 797 * VIA "Eden" MSRs 798 */ 799 #define MSR_VIA_FCR MSR_VIA_ACE 800 801 /* 802 * AMD K6/K7 MSRs. 803 */ 804 #define MSR_K6_UWCCR 0xc0000085 805 #define MSR_K7_EVNTSEL0 0xc0010000 806 #define MSR_K7_EVNTSEL1 0xc0010001 807 #define MSR_K7_EVNTSEL2 0xc0010002 808 #define MSR_K7_EVNTSEL3 0xc0010003 809 #define MSR_K7_PERFCTR0 0xc0010004 810 #define MSR_K7_PERFCTR1 0xc0010005 811 #define MSR_K7_PERFCTR2 0xc0010006 812 #define MSR_K7_PERFCTR3 0xc0010007 813 814 /* 815 * AMD K8 (Opteron) MSRs. 816 */ 817 #define MSR_SYSCFG 0xc0010010 818 819 #define MSR_EFER 0xc0000080 /* Extended feature enable */ 820 #define EFER_SCE 0x00000001 /* SYSCALL extension */ 821 #define EFER_LME 0x00000100 /* Long Mode Enable */ 822 #define EFER_LMA 0x00000400 /* Long Mode Active */ 823 #define EFER_NXE 0x00000800 /* No-Execute Enabled */ 824 #define EFER_SVME 0x00001000 /* Secure Virtual Machine En. */ 825 #define EFER_LMSLE 0x00002000 /* Long Mode Segment Limit E. */ 826 #define EFER_FFXSR 0x00004000 /* Fast FXSAVE/FXRSTOR En. */ 827 #define EFER_TCE 0x00008000 /* Translation Cache Ext. */ 828 829 #define MSR_STAR 0xc0000081 /* 32 bit syscall gate addr */ 830 #define MSR_LSTAR 0xc0000082 /* 64 bit syscall gate addr */ 831 #define MSR_CSTAR 0xc0000083 /* compat syscall gate addr */ 832 #define MSR_SFMASK 0xc0000084 /* flags to clear on syscall */ 833 834 #define MSR_FSBASE 0xc0000100 /* 64bit offset for fs: */ 835 #define MSR_GSBASE 0xc0000101 /* 64bit offset for gs: */ 836 #define MSR_KERNELGSBASE 0xc0000102 /* storage for swapgs ins */ 837 838 #define MSR_VMCR 0xc0010114 /* Virtual Machine Control Register */ 839 #define VMCR_DPD 0x00000001 /* Debug port disable */ 840 #define VMCR_RINIT 0x00000002 /* intercept init */ 841 #define VMCR_DISA20 0x00000004 /* Disable A20 masking */ 842 #define VMCR_LOCK 0x00000008 /* SVM Lock */ 843 #define VMCR_SVMED 0x00000010 /* SVME Disable */ 844 #define MSR_SVMLOCK 0xc0010118 /* SVM Lock key */ 845 846 /* 847 * These require a 'passcode' for access. See cpufunc.h. 848 */ 849 #define MSR_HWCR 0xc0010015 850 #define HWCR_TLBCACHEDIS 0x00000008 851 #define HWCR_FFDIS 0x00000040 852 853 #define MSR_NB_CFG 0xc001001f 854 #define NB_CFG_DISIOREQLOCK 0x0000000000000008ULL 855 #define NB_CFG_DISDATMSK 0x0000001000000000ULL 856 #define NB_CFG_INITAPICCPUIDLO (1ULL << 54) 857 858 #define MSR_LS_CFG 0xc0011020 859 #define LS_CFG_DIS_LS2_SQUISH 0x02000000 860 #define LS_CFG_DIS_SSB_F15H 0x0040000000000000ULL 861 #define LS_CFG_DIS_SSB_F16H 0x0000000200000000ULL 862 #define LS_CFG_DIS_SSB_F17H 0x0000000000000400ULL 863 864 #define MSR_IC_CFG 0xc0011021 865 #define IC_CFG_DIS_SEQ_PREFETCH 0x00000800 866 #define IC_CFG_DIS_IND 0x00004000 867 868 #define MSR_DC_CFG 0xc0011022 869 #define DC_CFG_DIS_CNV_WC_SSO 0x00000008 870 #define DC_CFG_DIS_SMC_CHK_BUF 0x00000400 871 #define DC_CFG_ERRATA_261 0x01000000 872 873 #define MSR_BU_CFG 0xc0011023 874 #define BU_CFG_ERRATA_298 0x0000000000000002ULL 875 #define BU_CFG_ERRATA_254 0x0000000000200000ULL 876 #define BU_CFG_ERRATA_309 0x0000000000800000ULL 877 #define BU_CFG_THRL2IDXCMPDIS 0x0000080000000000ULL 878 #define BU_CFG_WBPFSMCCHKDIS 0x0000200000000000ULL 879 #define BU_CFG_WBENHWSBDIS 0x0001000000000000ULL 880 881 #define MSR_DE_CFG 0xc0011029 882 #define DE_CFG_ERRATA_721 0x00000001 883 884 /* AMD Family10h MSRs */ 885 #define MSR_OSVW_ID_LENGTH 0xc0010140 886 #define MSR_OSVW_STATUS 0xc0010141 887 #define MSR_UCODE_AMD_PATCHLEVEL 0x0000008b 888 #define MSR_UCODE_AMD_PATCHLOADER 0xc0010020 889 890 /* X86 MSRs */ 891 #define MSR_RDTSCP_AUX 0xc0000103 892 893 /* 894 * Constants related to MTRRs 895 */ 896 #define MTRR_N64K 8 /* numbers of fixed-size entries */ 897 #define MTRR_N16K 16 898 #define MTRR_N4K 64 899 900 /* 901 * the following four 3-byte registers control the non-cacheable regions. 902 * These registers must be written as three separate bytes. 903 * 904 * NCRx+0: A31-A24 of starting address 905 * NCRx+1: A23-A16 of starting address 906 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 907 * 908 * The non-cacheable region's starting address must be aligned to the 909 * size indicated by the NCR_SIZE_xx field. 910 */ 911 #define NCR1 0xc4 912 #define NCR2 0xc7 913 #define NCR3 0xca 914 #define NCR4 0xcd 915 916 #define NCR_SIZE_0K 0 917 #define NCR_SIZE_4K 1 918 #define NCR_SIZE_8K 2 919 #define NCR_SIZE_16K 3 920 #define NCR_SIZE_32K 4 921 #define NCR_SIZE_64K 5 922 #define NCR_SIZE_128K 6 923 #define NCR_SIZE_256K 7 924 #define NCR_SIZE_512K 8 925 #define NCR_SIZE_1M 9 926 #define NCR_SIZE_2M 10 927 #define NCR_SIZE_4M 11 928 #define NCR_SIZE_8M 12 929 #define NCR_SIZE_16M 13 930 #define NCR_SIZE_32M 14 931 #define NCR_SIZE_4G 15 932 933 /* 934 * Performance monitor events. 935 * 936 * Note that 586-class and 686-class CPUs have different performance 937 * monitors available, and they are accessed differently: 938 * 939 * 686-class: `rdpmc' instruction 940 * 586-class: `rdmsr' instruction, CESR MSR 941 * 942 * The descriptions of these events are too lengthy to include here. 943 * See Appendix A of "Intel Architecture Software Developer's 944 * Manual, Volume 3: System Programming" for more information. 945 */ 946 947 /* 948 * 586-class CESR MSR format. Lower 16 bits is CTR0, upper 16 bits 949 * is CTR1. 950 */ 951 952 #define PMC5_CESR_EVENT 0x003f 953 #define PMC5_CESR_OS 0x0040 954 #define PMC5_CESR_USR 0x0080 955 #define PMC5_CESR_E 0x0100 956 #define PMC5_CESR_P 0x0200 957 958 #define PMC5_DATA_READ 0x00 959 #define PMC5_DATA_WRITE 0x01 960 #define PMC5_DATA_TLB_MISS 0x02 961 #define PMC5_DATA_READ_MISS 0x03 962 #define PMC5_DATA_WRITE_MISS 0x04 963 #define PMC5_WRITE_M_E 0x05 964 #define PMC5_DATA_LINES_WBACK 0x06 965 #define PMC5_DATA_CACHE_SNOOP 0x07 966 #define PMC5_DATA_CACHE_SNOOP_HIT 0x08 967 #define PMC5_MEM_ACCESS_BOTH_PIPES 0x09 968 #define PMC5_BANK_CONFLICTS 0x0a 969 #define PMC5_MISALIGNED_DATA 0x0b 970 #define PMC5_INST_READ 0x0c 971 #define PMC5_INST_TLB_MISS 0x0d 972 #define PMC5_INST_CACHE_MISS 0x0e 973 #define PMC5_SEGMENT_REG_LOAD 0x0f 974 #define PMC5_BRANCHES 0x12 975 #define PMC5_BTB_HITS 0x13 976 #define PMC5_BRANCH_TAKEN 0x14 977 #define PMC5_PIPELINE_FLUSH 0x15 978 #define PMC5_INST_EXECUTED 0x16 979 #define PMC5_INST_EXECUTED_V_PIPE 0x17 980 #define PMC5_BUS_UTILIZATION 0x18 981 #define PMC5_WRITE_BACKUP_STALL 0x19 982 #define PMC5_DATA_READ_STALL 0x1a 983 #define PMC5_WRITE_E_M_STALL 0x1b 984 #define PMC5_LOCKED_BUS 0x1c 985 #define PMC5_IO_CYCLE 0x1d 986 #define PMC5_NONCACHE_MEM_READ 0x1e 987 #define PMC5_AGI_STALL 0x1f 988 #define PMC5_FLOPS 0x22 989 #define PMC5_BP0_MATCH 0x23 990 #define PMC5_BP1_MATCH 0x24 991 #define PMC5_BP2_MATCH 0x25 992 #define PMC5_BP3_MATCH 0x26 993 #define PMC5_HARDWARE_INTR 0x27 994 #define PMC5_DATA_RW 0x28 995 #define PMC5_DATA_RW_MISS 0x29 996 997 /* 998 * 686-class Event Selector MSR format. 999 */ 1000 1001 #define PMC6_EVTSEL_EVENT 0x000000ff 1002 #define PMC6_EVTSEL_UNIT 0x0000ff00 1003 #define PMC6_EVTSEL_UNIT_SHIFT 8 1004 #define PMC6_EVTSEL_USR (1 << 16) 1005 #define PMC6_EVTSEL_OS (1 << 17) 1006 #define PMC6_EVTSEL_E (1 << 18) 1007 #define PMC6_EVTSEL_PC (1 << 19) 1008 #define PMC6_EVTSEL_INT (1 << 20) 1009 #define PMC6_EVTSEL_EN (1 << 22) /* PerfEvtSel0 only */ 1010 #define PMC6_EVTSEL_INV (1 << 23) 1011 #define PMC6_EVTSEL_COUNTER_MASK 0xff000000 1012 #define PMC6_EVTSEL_COUNTER_MASK_SHIFT 24 1013 1014 /* Data Cache Unit */ 1015 #define PMC6_DATA_MEM_REFS 0x43 1016 #define PMC6_DCU_LINES_IN 0x45 1017 #define PMC6_DCU_M_LINES_IN 0x46 1018 #define PMC6_DCU_M_LINES_OUT 0x47 1019 #define PMC6_DCU_MISS_OUTSTANDING 0x48 1020 1021 /* Instruction Fetch Unit */ 1022 #define PMC6_IFU_IFETCH 0x80 1023 #define PMC6_IFU_IFETCH_MISS 0x81 1024 #define PMC6_ITLB_MISS 0x85 1025 #define PMC6_IFU_MEM_STALL 0x86 1026 #define PMC6_ILD_STALL 0x87 1027 1028 /* L2 Cache */ 1029 #define PMC6_L2_IFETCH 0x28 1030 #define PMC6_L2_LD 0x29 1031 #define PMC6_L2_ST 0x2a 1032 #define PMC6_L2_LINES_IN 0x24 1033 #define PMC6_L2_LINES_OUT 0x26 1034 #define PMC6_L2_M_LINES_INM 0x25 1035 #define PMC6_L2_M_LINES_OUTM 0x27 1036 #define PMC6_L2_RQSTS 0x2e 1037 #define PMC6_L2_ADS 0x21 1038 #define PMC6_L2_DBUS_BUSY 0x22 1039 #define PMC6_L2_DBUS_BUSY_RD 0x23 1040 1041 /* External Bus Logic */ 1042 #define PMC6_BUS_DRDY_CLOCKS 0x62 1043 #define PMC6_BUS_LOCK_CLOCKS 0x63 1044 #define PMC6_BUS_REQ_OUTSTANDING 0x60 1045 #define PMC6_BUS_TRAN_BRD 0x65 1046 #define PMC6_BUS_TRAN_RFO 0x66 1047 #define PMC6_BUS_TRANS_WB 0x67 1048 #define PMC6_BUS_TRAN_IFETCH 0x68 1049 #define PMC6_BUS_TRAN_INVAL 0x69 1050 #define PMC6_BUS_TRAN_PWR 0x6a 1051 #define PMC6_BUS_TRANS_P 0x6b 1052 #define PMC6_BUS_TRANS_IO 0x6c 1053 #define PMC6_BUS_TRAN_DEF 0x6d 1054 #define PMC6_BUS_TRAN_BURST 0x6e 1055 #define PMC6_BUS_TRAN_ANY 0x70 1056 #define PMC6_BUS_TRAN_MEM 0x6f 1057 #define PMC6_BUS_DATA_RCV 0x64 1058 #define PMC6_BUS_BNR_DRV 0x61 1059 #define PMC6_BUS_HIT_DRV 0x7a 1060 #define PMC6_BUS_HITM_DRDV 0x7b 1061 #define PMC6_BUS_SNOOP_STALL 0x7e 1062 1063 /* Floating Point Unit */ 1064 #define PMC6_FLOPS 0xc1 1065 #define PMC6_FP_COMP_OPS_EXE 0x10 1066 #define PMC6_FP_ASSIST 0x11 1067 #define PMC6_MUL 0x12 1068 #define PMC6_DIV 0x12 1069 #define PMC6_CYCLES_DIV_BUSY 0x14 1070 1071 /* Memory Ordering */ 1072 #define PMC6_LD_BLOCKS 0x03 1073 #define PMC6_SB_DRAINS 0x04 1074 #define PMC6_MISALIGN_MEM_REF 0x05 1075 #define PMC6_EMON_KNI_PREF_DISPATCHED 0x07 /* P-III only */ 1076 #define PMC6_EMON_KNI_PREF_MISS 0x4b /* P-III only */ 1077 1078 /* Instruction Decoding and Retirement */ 1079 #define PMC6_INST_RETIRED 0xc0 1080 #define PMC6_UOPS_RETIRED 0xc2 1081 #define PMC6_INST_DECODED 0xd0 1082 #define PMC6_EMON_KNI_INST_RETIRED 0xd8 1083 #define PMC6_EMON_KNI_COMP_INST_RET 0xd9 1084 1085 /* Interrupts */ 1086 #define PMC6_HW_INT_RX 0xc8 1087 #define PMC6_CYCLES_INT_MASKED 0xc6 1088 #define PMC6_CYCLES_INT_PENDING_AND_MASKED 0xc7 1089 1090 /* Branches */ 1091 #define PMC6_BR_INST_RETIRED 0xc4 1092 #define PMC6_BR_MISS_PRED_RETIRED 0xc5 1093 #define PMC6_BR_TAKEN_RETIRED 0xc9 1094 #define PMC6_BR_MISS_PRED_TAKEN_RET 0xca 1095 #define PMC6_BR_INST_DECODED 0xe0 1096 #define PMC6_BTB_MISSES 0xe2 1097 #define PMC6_BR_BOGUS 0xe4 1098 #define PMC6_BACLEARS 0xe6 1099 1100 /* Stalls */ 1101 #define PMC6_RESOURCE_STALLS 0xa2 1102 #define PMC6_PARTIAL_RAT_STALLS 0xd2 1103 1104 /* Segment Register Loads */ 1105 #define PMC6_SEGMENT_REG_LOADS 0x06 1106 1107 /* Clocks */ 1108 #define PMC6_CPU_CLK_UNHALTED 0x79 1109 1110 /* MMX Unit */ 1111 #define PMC6_MMX_INSTR_EXEC 0xb0 /* Celeron, P-II, P-IIX only */ 1112 #define PMC6_MMX_SAT_INSTR_EXEC 0xb1 /* P-II and P-III only */ 1113 #define PMC6_MMX_UOPS_EXEC 0xb2 /* P-II and P-III only */ 1114 #define PMC6_MMX_INSTR_TYPE_EXEC 0xb3 /* P-II and P-III only */ 1115 #define PMC6_FP_MMX_TRANS 0xcc /* P-II and P-III only */ 1116 #define PMC6_MMX_ASSIST 0xcd /* P-II and P-III only */ 1117 #define PMC6_MMX_INSTR_RET 0xc3 /* P-II only */ 1118 1119 /* Segment Register Renaming */ 1120 #define PMC6_SEG_RENAME_STALLS 0xd4 /* P-II and P-III only */ 1121 #define PMC6_SEG_REG_RENAMES 0xd5 /* P-II and P-III only */ 1122 #define PMC6_RET_SEG_RENAMES 0xd6 /* P-II and P-III only */ 1123 1124 /* 1125 * AMD K7. [Doc: 22007K.pdf, Feb 2002] 1126 */ 1127 /* Event Selector MSR format */ 1128 #define K7_EVTSEL_EVENT 0x000000ff 1129 #define K7_EVTSEL_UNIT 0x0000ff00 1130 #define K7_EVTSEL_UNIT_SHIFT 8 1131 #define K7_EVTSEL_USR __BIT(16) 1132 #define K7_EVTSEL_OS __BIT(17) 1133 #define K7_EVTSEL_E __BIT(18) 1134 #define K7_EVTSEL_PC __BIT(19) 1135 #define K7_EVTSEL_INT __BIT(20) 1136 #define K7_EVTSEL_EN __BIT(22) 1137 #define K7_EVTSEL_INV __BIT(23) 1138 #define K7_EVTSEL_COUNTER_MASK 0xff000000 1139 #define K7_EVTSEL_COUNTER_MASK_SHIFT 24 1140 /* Data Cache Unit */ 1141 #define K7_DATA_CACHE_ACCESS 0x40 1142 #define K7_DATA_CACHE_MISS 0x41 1143 #define K7_DATA_CACHE_REFILL 0x42 1144 #define K7_DATA_CACHE_REFILL_SYSTEM 0x43 1145 #define K7_DATA_CACHE_WBACK 0x44 1146 #define K7_L1_DTLB_MISS 0x45 1147 #define K7_L2_DTLB_MISS 0x46 1148 #define K7_MISALIGNED_DATA_REF 0x47 1149 /* Instruction Fetch Unit */ 1150 #define K7_IFU_IFETCH 0x80 1151 #define K7_IFU_IFETCH_MISS 0x81 1152 #define K7_IFU_REFILL_FROM_L2 0x82 1153 #define K7_IFU_REFILL_FROM_SYSTEM 0x83 1154 #define K7_L1_ITLB_MISS 0x84 1155 #define K7_L2_ITLB_MISS 0x85 1156 /* Retired */ 1157 #define K7_RETIRED_INST 0xc0 1158 #define K7_RETIRED_OPS 0xc1 1159 #define K7_RETIRED_BRANCH 0xc2 1160 #define K7_RETIRED_BRANCH_MISPREDICTED 0xc3 1161 #define K7_RETIRED_TAKEN_BRANCH 0xc4 1162 #define K7_RETIRED_TAKEN_BRANCH_MISPREDICTED 0xc5 1163 #define K7_RETIRED_FAR_CONTROL_TRANSFER 0xc6 1164 #define K7_RETIRED_RESYNC_BRANCH 0xc7 1165 /* Interrupts */ 1166 #define K7_CYCLES_INT_MASKED 0xcd 1167 #define K7_CYCLES_INT_PENDING_AND_MASKED 0xce 1168 #define K7_HW_INTR_RECV 0xcf 1169 1170 /* 1171 * AMD 10h family PMCs. [Doc: 31116.pdf, Jan 2013] 1172 */ 1173 /* Register MSRs */ 1174 #define MSR_F10H_EVNTSEL0 0xc0010000 1175 #define MSR_F10H_EVNTSEL1 0xc0010001 1176 #define MSR_F10H_EVNTSEL2 0xc0010002 1177 #define MSR_F10H_EVNTSEL3 0xc0010003 1178 #define MSR_F10H_PERFCTR0 0xc0010004 1179 #define MSR_F10H_PERFCTR1 0xc0010005 1180 #define MSR_F10H_PERFCTR2 0xc0010006 1181 #define MSR_F10H_PERFCTR3 0xc0010007 1182 /* Event Selector MSR format */ 1183 #define F10H_EVTSEL_EVENT_MASK 0x000F000000FF 1184 #define F10H_EVTSEL_EVENT_SHIFT_LOW 0 1185 #define F10H_EVTSEL_EVENT_SHIFT_HIGH 32 1186 #define F10H_EVTSEL_UNIT_MASK 0x0000FF00 1187 #define F10H_EVTSEL_UNIT_SHIFT 8 1188 #define F10H_EVTSEL_USR __BIT(16) 1189 #define F10H_EVTSEL_OS __BIT(17) 1190 #define F10H_EVTSEL_EDGE __BIT(18) 1191 #define F10H_EVTSEL_RSVD1 __BIT(19) 1192 #define F10H_EVTSEL_INT __BIT(20) 1193 #define F10H_EVTSEL_RSVD2 __BIT(21) 1194 #define F10H_EVTSEL_EN __BIT(22) 1195 #define F10H_EVTSEL_INV __BIT(23) 1196 #define F10H_EVTSEL_COUNTER_MASK 0xFF000000 1197 #define F10H_EVTSEL_COUNTER_MASK_SHIFT 24 1198 /* Floating Point Events */ 1199 #define F10H_FP_DISPATCHED_FPU_OPS 0x00 1200 #define F10H_FP_CYCLES_EMPTY_FPU_OPS 0x01 1201 #define F10H_FP_DISPATCHED_FASTFLAG_OPS 0x02 1202 #define F10H_FP_RETIRED_SSE_OPS 0x03 1203 #define F10H_FP_RETIRED_MOVE_OPS 0x04 1204 #define F10H_FP_RETIRED_SERIALIZING_OPS 0x05 1205 #define F10H_FP_CYCLES_SERIALIZING_OP_SCHEDULER 0x06 1206 /* Load/Store and TLB Events */ 1207 #define F10H_SEGMENT_REG_LOADS 0x20 1208 #define F10H_PIPELINE_RESTART_SELFMOD_CODE 0x21 1209 #define F10H_PIPELINE_RESTART_PROBE_HIT 0x22 1210 #define F10H_LS_BUFFER_2_FILL 0x23 1211 #define F10H_LOCKED_OPERATIONS 0x24 1212 #define F10H_RETIRED_CLFLUSH_INSTRUCTIONS 0x26 1213 #define F10H_RETIRED_CPUID_INSTRUCTIONS 0x27 1214 #define F10H_CANCELLED_STORE_LOAD_FORWARD_OPS 0x2A 1215 #define F10H_SMI_RECEIVED 0x2B 1216 /* Data Cache Events */ 1217 #define F10H_DATA_CACHE_ACCESS 0x40 1218 #define F10H_DATA_CACHE_MISS 0x41 1219 #define F10H_DATA_CACHE_REFILL_FROM_L2 0x42 1220 #define F10H_DATA_CACHE_REFILL_FROM_NORTHBRIDGE 0x43 1221 #define F10H_CACHE_LINES_EVICTED 0x44 1222 #define F10H_L1_DTLB_MISS 0x45 1223 #define F10H_L2_DTLB_MISS 0x46 1224 #define F10H_MISALIGNED_ACCESS 0x47 1225 #define F10H_MICROARCH_LATE_CANCEL_OF_ACCESS 0x48 1226 #define F10H_MICROARCH_EARLY_CANCEL_OF_ACCESS 0x49 1227 #define F10H_SINGLE_BIT_ECC_ERRORS_RECORDED 0x4A 1228 #define F10H_PREFETCH_INSTRUCTIONS_DISPATCHED 0x4B 1229 #define F10H_DCACHE_MISSES_LOCKED_INSTRUCTIONS 0x4C 1230 #define F10H_L1_DTLB_HIT 0x4D 1231 #define F10H_INEFFECTIVE_SOFTWARE_PREFETCHS 0x52 1232 #define F10H_GLOBAL_TLB_FLUSHES 0x54 1233 #define F10H_MEMORY_REQUESTS_BY_TYPE 0x65 1234 #define F10H_DATA_PREFETCHER 0x67 1235 #define F10H_MAB_REQUESTS 0x68 1236 #define F10H_MAB_WAIT_CYCLES 0x69 1237 #define F10H_NORTHBRIDGE_READ_RESP_BY_COH_STATE 0x6C 1238 #define F10H_OCTWORDS_WRITTEN_TO_SYSTEM 0x6D 1239 #define F10H_CPU_CLOCKS_NOT_HALTED 0x76 1240 #define F10H_REQUESTS_TO_L2_CACHE 0x7D 1241 #define F10H_L2_CACHE_MISSES 0x7E 1242 #define F10H_L2_FILL 0x7F 1243 /* F10H_PAGE_SIZE_MISMATCHES (0x01C0): reserved on some revisions */ 1244 /* Instruction Cache Events */ 1245 #define F10H_INSTRUCTION_CACHE_FETCH 0x80 1246 #define F10H_INSTRUCTION_CACHE_MISS 0x81 1247 #define F10H_INSTRUCTION_CACHE_REFILL_FROM_L2 0x82 1248 #define F10H_INSTRUCTION_CACHE_REFILL_FROM_SYS 0x83 1249 #define F10H_L1_ITLB_MISS 0x84 1250 #define F10H_L2_ITLB_MISS 0x85 1251 #define F10H_PIPELINE_RESTART_INSTR_STREAM_PROBE 0x86 1252 #define F10H_INSTRUCTION_FETCH_STALL 0x87 1253 #define F10H_RETURN_STACK_HITS 0x88 1254 #define F10H_RETURN_STACK_OVERFLOWS 0x89 1255 #define F10H_INSTRUCTION_CACHE_VICTIMS 0x8B 1256 #define F10H_INSTRUCTION_CACHE_LINES_INVALIDATED 0x8C 1257 #define F10H_ITLD_RELOADS 0x99 1258 #define F10H_ITLD_RELOADS_ABORTED 0x9A 1259 /* Execution Unit Events */ 1260 #define F10H_RETIRED_INSTRUCTIONS 0xC0 1261 #define F10H_RETIRED_UOPS 0xC1 1262 #define F10H_RETIRED_BRANCH 0xC2 1263 #define F10H_RETIRED_MISPREDICTED_BRANCH 0xC3 1264 #define F10H_RETIRED_TAKEN_BRANCH 0xC4 1265 #define F10H_RETIRED_TAKEN_BRANCH_MISPREDICTED 0xC5 1266 #define F10H_RETIRED_FAR_CONTROL_TRANSFER 0xC6 1267 #define F10H_RETIRED_BRANCH_RESYNC 0xC7 1268 #define F10H_RETIRED_NEAR_RETURNS 0xC8 1269 #define F10H_RETIRED_NEAR_RETURNS_MISPREDICTED 0xC9 1270 #define F10H_RETIRED_INDIRECT_BRANCH_MISPREDICTED 0xCA 1271 #define F10H_RETIRED_MMX_FP_INSTRUCTIONS 0xCB 1272 #define F10H_RETIRED_FASTPATH_DOUBLE_OP_INSTR 0xCC 1273 #define F10H_INTERRUPTS_MASKED_CYCLES 0xCD 1274 #define F10H_INTERRUPTS_MASKED_CYCLES_INTERRUPT_PENDING 0xCE 1275 #define F10H_INTERRUPTS_TAKEN 0xCF 1276 #define F10H_DECODER_EMPTY 0xD0 1277 #define F10H_DISPATCH_STALLS 0xD1 1278 #define F10H_DISPATCH_STALLS_BRANCH_ABORT_RETIRE 0xD2 1279 #define F10H_DISPATCH_STALLS_SERIALIZATION 0xD3 1280 #define F10H_DISPATCH_STALLS_SEGMENT_LOAD 0xD4 1281 #define F10H_DISPATCH_STALLS_REORDER_BUF_FULL 0xD5 1282 #define F10H_DISPATCH_STALLS_RSV_STATION_FULL 0xD6 1283 #define F10H_DISPATCH_STALLS_FPU_FULL 0xD7 1284 #define F10H_DISPATCH_STALLS_LS_FULL 0xD8 1285 #define F10H_DISPATCH_STALLS_WAITING_ALL_QUITE 0xD9 1286 #define F10H_DISPATCH_STALLS_FAR_TRANSFER 0xDA 1287 #define F10H_FPU_EXCEPTIONS 0xDB 1288 #define F10H_DR0_BREAKPOINT_MATCHES 0xDC 1289 #define F10H_DR1_BREAKPOINT_MATCHES 0xDD 1290 #define F10H_DR2_BREAKPOINT_MATCHES 0xDE 1291 #define F10H_DR3_BREAKPOINT_MATCHES 0xDF 1292 /* F10H_RETIRED_X87_FP_OPERATIONS (0x01C0): reserved on some revisions */ 1293 /* F10H_IBS_OPS_TAGGED (0x1CF): reserved on some revisions */ 1294 /* F10H_LFENCE_INSTRUCTIONS_RETIRED (0x01D3): reserved on some revisions */ 1295 /* F10H_SFENCE_INSTRUCTIONS_RETIRED (0x01D4): reserved on some revisions */ 1296 /* F10H_MFENCE_INSTRUCTIONS_RETIRED (0x01D5): reserved on some revisions */ 1297 /* Memory Controller Events */ 1298 #define F10H_DRAM_ACCESSES 0xE0 1299 #define F10H_DRAM_CONTROLLER_PT_OVERFLOWS 0xE1 1300 #define F10H_MEM_CONTROLLER_DRAM_COMMAND_SLOTS_MISSED 0xE2 1301 #define F10H_MEM_CONTROLLER_TURNAROUNDS 0xE3 1302 #define F10H_MEM_CONTROLLER_BYPASS_COUNTER_SATURATION 0xE4 1303 #define F10H_THERMAL_STATUS 0xE8 1304 #define F10H_CPU_IO_REQUESTS_TO_MEMORY_IO 0xE9 1305 #define F10H_CACHE_BLOCK_COMMANDS 0xEA 1306 #define F10H_SIZED_COMMANDS 0xEB 1307 #define F10H_PROBE_RESPONSES_AND_UPSTREAM_REQUESTS 0xEC 1308 #define F10H_GART_EVENTS 0xEE 1309 #define F10H_MEMORY_CONTROLLER_REQUESTS 0x01F0 1310 #define F10H_CPU_TO_DRAM_REQUESTS_TO_TARGET_NODE 0x01E0 1311 #define F10H_IO_TO_DRAM_REQUESTS_TO_TARGET_NODE 0x01E1 1312 #define F10H_CPU_READ_CMD_LATENCY_TARGET_NODE_03 0x01E2 1313 #define F10H_CPU_READ_CMD_REQUESTS_TARGET_NODE_03 0x01E3 1314 #define F10H_CPU_READ_CMD_LATENCY_TARGET_NODE_47 0x01E4 1315 #define F10H_CPU_READ_CMD_REQUESTS_TARGET_NODE_47 0x01E5 1316 #define F10H_CPU_CMD_LATENCY_TO_TARGET_NODE_0347 0x01E6 1317 #define F10H_CPU_REQUESTS_TO_TARGET_NODE_0347 0x01E7 1318 /* Link Events */ 1319 #define F10H_HYPERTRANSPORT_LINK0_TRANSMIT_BANDWIDTH 0xF6 1320 #define F10H_HYPERTRANSPORT_LINK1_TRANSMIT_BANDWIDTH 0xF7 1321 #define F10H_HYPERTRANSPORT_LINK2_TRANSMIT_BANDWIDTH 0xF8 1322 #define F10H_HYPERTRANSPORT_LINK3_TRANSMIT_BANDWIDTH 0x01F9 1323 /* L3 Cache Events */ 1324 /* F10H_READ_READ_REQUEST_TO_L3_CACHE (0x04E0): depends on the revision */ 1325 /* F10H_L3_CACHE_MISSES (0x04E1): depends on the revision */ 1326 /* F10H_L3_FILLS_FROM_L2_EVICTIONS (0x04E2): depends on the revision */ 1327 #define F10H_L3_EVICTIONS 0x04E3 1328 /* F10H_NONCANCELLED_L3_READ_REQUESTS (0x04ED): depends on the revision */ 1329 1330
Indexes created Mon Sep 29 21:09:56 GMT 2025