specialreg.h revision 1.135
1 /* $NetBSD: specialreg.h,v 1.135 2018/11/22 06:14:35 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1991 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of the University nor the names of its contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * @(#)specialreg.h 7.1 (Berkeley) 5/9/91 32 */ 33 34 /* 35 * Bits in 386 special registers: 36 */ 37 #define CR0_PE 0x00000001 /* Protected mode Enable */ 38 #define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */ 39 #define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */ 40 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 41 #define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */ 42 #define CR0_PG 0x80000000 /* PaGing enable */ 43 44 /* 45 * Bits in 486 special registers: 46 */ 47 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 48 #define CR0_WP 0x00010000 /* Write Protect (honor PG_RW in all modes) */ 49 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 50 #define CR0_NW 0x20000000 /* Not Write-through */ 51 #define CR0_CD 0x40000000 /* Cache Disable */ 52 53 /* 54 * Cyrix 486 DLC special registers, accessible as IO ports. 55 */ 56 #define CCR0 0xc0 /* configuration control register 0 */ 57 #define CCR0_NC0 0x01 /* first 64K of each 1M memory region is non-cacheable */ 58 #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 59 #define CCR0_A20M 0x04 /* enables A20M# input pin */ 60 #define CCR0_KEN 0x08 /* enables KEN# input pin */ 61 #define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */ 62 #define CCR0_BARB 0x20 /* flushes internal cache when entering hold state */ 63 #define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */ 64 #define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */ 65 66 #define CCR1 0xc1 /* configuration control register 1 */ 67 #define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */ 68 /* the remaining 7 bits of this register are reserved */ 69 70 /* 71 * bits in the %cr4 control register: 72 */ 73 #define CR4_VME 0x00000001 /* virtual 8086 mode extension enable */ 74 #define CR4_PVI 0x00000002 /* protected mode virtual interrupt enable */ 75 #define CR4_TSD 0x00000004 /* restrict RDTSC instruction to cpl 0 */ 76 #define CR4_DE 0x00000008 /* debugging extension */ 77 #define CR4_PSE 0x00000010 /* large (4MB) page size enable */ 78 #define CR4_PAE 0x00000020 /* physical address extension enable */ 79 #define CR4_MCE 0x00000040 /* machine check enable */ 80 #define CR4_PGE 0x00000080 /* page global enable */ 81 #define CR4_PCE 0x00000100 /* enable RDPMC instruction for all cpls */ 82 #define CR4_OSFXSR 0x00000200 /* enable fxsave/fxrestor and SSE */ 83 #define CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */ 84 #define CR4_UMIP 0x00000800 /* user-mode instruction prevention */ 85 #define CR4_VMXE 0x00002000 /* enable VMX operations */ 86 #define CR4_SMXE 0x00004000 /* enable SMX operations */ 87 #define CR4_FSGSBASE 0x00010000 /* enable *FSBASE and *GSBASE instructions */ 88 #define CR4_PCIDE 0x00020000 /* enable Process Context IDentifiers */ 89 #define CR4_OSXSAVE 0x00040000 /* enable xsave and xrestore */ 90 #define CR4_SMEP 0x00100000 /* enable SMEP support */ 91 #define CR4_SMAP 0x00200000 /* enable SMAP support */ 92 #define CR4_PKE 0x00400000 /* protection key enable */ 93 94 /* 95 * Extended Control Register XCR0 96 */ 97 #define XCR0_X87 0x00000001 /* x87 FPU/MMX state */ 98 #define XCR0_SSE 0x00000002 /* SSE state */ 99 #define XCR0_YMM_Hi128 0x00000004 /* AVX-256 (ymmn registers) */ 100 #define XCR0_BNDREGS 0x00000008 /* Memory protection ext bounds */ 101 #define XCR0_BNDCSR 0x00000010 /* Memory protection ext state */ 102 #define XCR0_Opmask 0x00000020 /* AVX-512 Opmask */ 103 #define XCR0_ZMM_Hi256 0x00000040 /* AVX-512 upper 256 bits low regs */ 104 #define XCR0_Hi16_ZMM 0x00000080 /* AVX-512 512 bits upper registers */ 105 106 /* 107 * Known fpu bits - only these get enabled. The save area is sized for all the 108 * fields below (max 2680 bytes). 109 */ 110 #define XCR0_FPU (XCR0_X87 | XCR0_SSE | XCR0_YMM_Hi128 | \ 111 XCR0_Opmask | XCR0_ZMM_Hi256 | XCR0_Hi16_ZMM) 112 113 #define XCR0_BND (XCR0_BNDREGS | XCR0_BNDCSR) 114 115 #define XCR0_FLAGS1 "\20" \ 116 "\1" "x87" "\2" "SSE" "\3" "AVX" \ 117 "\4" "BNDREGS" "\5" "BNDCSR" \ 118 "\6" "Opmask" "\7" "ZMM_Hi256" "\10" "Hi16_ZMM" 119 120 121 /* 122 * CPUID "features" bits 123 */ 124 125 /* Fn00000001 %edx features */ 126 #define CPUID_FPU 0x00000001 /* processor has an FPU? */ 127 #define CPUID_VME 0x00000002 /* has virtual mode (%cr4's VME/PVI) */ 128 #define CPUID_DE 0x00000004 /* has debugging extension */ 129 #define CPUID_PSE 0x00000008 /* has 4MB page size extension */ 130 #define CPUID_TSC 0x00000010 /* has time stamp counter */ 131 #define CPUID_MSR 0x00000020 /* has model specific registers */ 132 #define CPUID_PAE 0x00000040 /* has phys address extension */ 133 #define CPUID_MCE 0x00000080 /* has machine check exception */ 134 #define CPUID_CX8 0x00000100 /* has CMPXCHG8B instruction */ 135 #define CPUID_APIC 0x00000200 /* has enabled APIC */ 136 #define CPUID_B10 0x00000400 /* reserved, MTRR */ 137 #define CPUID_SEP 0x00000800 /* has SYSENTER/SYSEXIT extension */ 138 #define CPUID_MTRR 0x00001000 /* has memory type range register */ 139 #define CPUID_PGE 0x00002000 /* has page global extension */ 140 #define CPUID_MCA 0x00004000 /* has machine check architecture */ 141 #define CPUID_CMOV 0x00008000 /* has CMOVcc instruction */ 142 #define CPUID_PAT 0x00010000 /* Page Attribute Table */ 143 #define CPUID_PSE36 0x00020000 /* 36-bit PSE */ 144 #define CPUID_PN 0x00040000 /* processor serial number */ 145 #define CPUID_CFLUSH 0x00080000 /* CLFLUSH insn supported */ 146 #define CPUID_B20 0x00100000 /* reserved */ 147 #define CPUID_DS 0x00200000 /* Debug Store */ 148 #define CPUID_ACPI 0x00400000 /* ACPI performance modulation regs */ 149 #define CPUID_MMX 0x00800000 /* MMX supported */ 150 #define CPUID_FXSR 0x01000000 /* fast FP/MMX save/restore */ 151 #define CPUID_SSE 0x02000000 /* streaming SIMD extensions */ 152 #define CPUID_SSE2 0x04000000 /* streaming SIMD extensions #2 */ 153 #define CPUID_SS 0x08000000 /* self-snoop */ 154 #define CPUID_HTT 0x10000000 /* Hyper-Threading Technology */ 155 #define CPUID_TM 0x20000000 /* thermal monitor (TCC) */ 156 #define CPUID_IA64 0x40000000 /* IA-64 architecture */ 157 #define CPUID_SBF 0x80000000 /* signal break on FERR */ 158 159 #define CPUID_FLAGS1 "\20" \ 160 "\1" "FPU" "\2" "VME" "\3" "DE" "\4" "PSE" \ 161 "\5" "TSC" "\6" "MSR" "\7" "PAE" "\10" "MCE" \ 162 "\11" "CX8" "\12" "APIC" "\13" "B10" "\14" "SEP" \ 163 "\15" "MTRR" "\16" "PGE" "\17" "MCA" "\20" "CMOV" \ 164 "\21" "PAT" "\22" "PSE36" "\23" "PN" "\24" "CLFLUSH" \ 165 "\25" "B20" "\26" "DS" "\27" "ACPI" "\30" "MMX" \ 166 "\31" "FXSR" "\32" "SSE" "\33" "SSE2" "\34" "SS" \ 167 "\35" "HTT" "\36" "TM" "\37" "IA64" "\40" "SBF" 168 169 /* Blacklists of CPUID flags - used to mask certain features */ 170 #ifdef XEN 171 /* Not on Xen */ 172 #define CPUID_FEAT_BLACKLIST (CPUID_PGE|CPUID_PSE|CPUID_MTRR) 173 #else 174 #define CPUID_FEAT_BLACKLIST 0 175 #endif /* XEN */ 176 177 /* 178 * CPUID "features" bits in Fn00000001 %ecx 179 */ 180 181 #define CPUID2_SSE3 0x00000001 /* Streaming SIMD Extensions 3 */ 182 #define CPUID2_PCLMUL 0x00000002 /* PCLMULQDQ instructions */ 183 #define CPUID2_DTES64 0x00000004 /* 64-bit Debug Trace */ 184 #define CPUID2_MONITOR 0x00000008 /* MONITOR/MWAIT instructions */ 185 #define CPUID2_DS_CPL 0x00000010 /* CPL Qualified Debug Store */ 186 #define CPUID2_VMX 0x00000020 /* Virtual Machine Extensions */ 187 #define CPUID2_SMX 0x00000040 /* Safer Mode Extensions */ 188 #define CPUID2_EST 0x00000080 /* Enhanced SpeedStep Technology */ 189 #define CPUID2_TM2 0x00000100 /* Thermal Monitor 2 */ 190 #define CPUID2_SSSE3 0x00000200 /* Supplemental SSE3 */ 191 #define CPUID2_CID 0x00000400 /* Context ID */ 192 #define CPUID2_SDBG 0x00000800 /* Silicon Debug */ 193 #define CPUID2_FMA 0x00001000 /* has Fused Multiply Add */ 194 #define CPUID2_CX16 0x00002000 /* has CMPXCHG16B instruction */ 195 #define CPUID2_xTPR 0x00004000 /* Task Priority Messages disabled? */ 196 #define CPUID2_PDCM 0x00008000 /* Perf/Debug Capability MSR */ 197 /* bit 16 unused 0x00010000 */ 198 #define CPUID2_PCID 0x00020000 /* Process Context ID */ 199 #define CPUID2_DCA 0x00040000 /* Direct Cache Access */ 200 #define CPUID2_SSE41 0x00080000 /* Streaming SIMD Extensions 4.1 */ 201 #define CPUID2_SSE42 0x00100000 /* Streaming SIMD Extensions 4.2 */ 202 #define CPUID2_X2APIC 0x00200000 /* xAPIC Extensions */ 203 #define CPUID2_MOVBE 0x00400000 /* MOVBE (move after byteswap) */ 204 #define CPUID2_POPCNT 0x00800000 /* popcount instruction available */ 205 #define CPUID2_DEADLINE 0x01000000 /* APIC Timer supports TSC Deadline */ 206 #define CPUID2_AES 0x02000000 /* AES instructions */ 207 #define CPUID2_XSAVE 0x04000000 /* XSAVE instructions */ 208 #define CPUID2_OSXSAVE 0x08000000 /* XGETBV/XSETBV instructions */ 209 #define CPUID2_AVX 0x10000000 /* AVX instructions */ 210 #define CPUID2_F16C 0x20000000 /* half precision conversion */ 211 #define CPUID2_RDRAND 0x40000000 /* RDRAND (hardware random number) */ 212 #define CPUID2_RAZ 0x80000000 /* RAZ. Indicates guest state. */ 213 214 #define CPUID2_FLAGS1 "\20" \ 215 "\1" "SSE3" "\2" "PCLMULQDQ" "\3" "DTES64" "\4" "MONITOR" \ 216 "\5" "DS-CPL" "\6" "VMX" "\7" "SMX" "\10" "EST" \ 217 "\11" "TM2" "\12" "SSSE3" "\13" "CID" "\14" "SDBG" \ 218 "\15" "FMA" "\16" "CX16" "\17" "xTPR" "\20" "PDCM" \ 219 "\21" "B16" "\22" "PCID" "\23" "DCA" "\24" "SSE41" \ 220 "\25" "SSE42" "\26" "X2APIC" "\27" "MOVBE" "\30" "POPCNT" \ 221 "\31" "DEADLINE" "\32" "AES" "\33" "XSAVE" "\34" "OSXSAVE" \ 222 "\35" "AVX" "\36" "F16C" "\37" "RDRAND" "\40" "RAZ" 223 224 /* CPUID Fn00000001 %eax */ 225 226 #define CPUID_TO_BASEFAMILY(cpuid) (((cpuid) >> 8) & 0xf) 227 #define CPUID_TO_BASEMODEL(cpuid) (((cpuid) >> 4) & 0xf) 228 #define CPUID_TO_STEPPING(cpuid) ((cpuid) & 0xf) 229 230 /* 231 * The Extended family bits should only be inspected when CPUID_TO_BASEFAMILY() 232 * returns 15. They are use to encode family value 16 to 270 (add 15). 233 * The Extended model bits are the high 4 bits of the model. 234 * They are only valid for family >= 15 or family 6 (intel, but all amd 235 * family 6 are documented to return zero bits for them). 236 */ 237 #define CPUID_TO_EXTFAMILY(cpuid) (((cpuid) >> 20) & 0xff) 238 #define CPUID_TO_EXTMODEL(cpuid) (((cpuid) >> 16) & 0xf) 239 240 /* The macros for the Display Family and the Display Model */ 241 #define CPUID_TO_FAMILY(cpuid) (CPUID_TO_BASEFAMILY(cpuid) \ 242 + ((CPUID_TO_BASEFAMILY(cpuid) != 0x0f) \ 243 ? 0 : CPUID_TO_EXTFAMILY(cpuid))) 244 #define CPUID_TO_MODEL(cpuid) (CPUID_TO_BASEMODEL(cpuid) \ 245 | ((CPUID_TO_BASEFAMILY(cpuid) != 0x0f) \ 246 && (CPUID_TO_BASEFAMILY(cpuid) != 0x06) \ 247 ? 0 : (CPUID_TO_EXTMODEL(cpuid) << 4))) 248 249 /* CPUID Fn00000001 %ebx */ 250 #define CPUID_BRAND_INDEX __BITS(7,0) 251 #define CPUID_CLFLUSH_SIZE __BITS(15,8) 252 #define CPUID_HTT_CORES __BITS(23,16) 253 #define CPUID_LOCAL_APIC_ID __BITS(31,24) 254 255 /* 256 * Intel Deterministic Cache Parameter Leaf 257 * Fn0000_0004 258 */ 259 260 /* %eax */ 261 #define CPUID_DCP_CACHETYPE __BITS(4, 0) /* Cache type */ 262 #define CPUID_DCP_CACHETYPE_N 0 /* NULL */ 263 #define CPUID_DCP_CACHETYPE_D 1 /* Data cache */ 264 #define CPUID_DCP_CACHETYPE_I 2 /* Instruction cache */ 265 #define CPUID_DCP_CACHETYPE_U 3 /* Unified cache */ 266 #define CPUID_DCP_CACHELEVEL __BITS(7, 5) /* Cache level (start at 1) */ 267 #define CPUID_DCP_SELFINITCL __BIT(8) /* Self initializing cachelvl*/ 268 #define CPUID_DCP_FULLASSOC __BIT(9) /* Full associative */ 269 #define CPUID_DCP_SHAREING __BITS(25, 14) /* shareing */ 270 #define CPUID_DCP_CORE_P_PKG __BITS(31, 26) /* Cores/package */ 271 272 /* %ebx */ 273 #define CPUID_DCP_LINESIZE __BITS(11, 0) /* System coherency linesize */ 274 #define CPUID_DCP_PARTITIONS __BITS(21, 12) /* Physical line partitions */ 275 #define CPUID_DCP_WAYS __BITS(31, 22) /* Ways of associativity */ 276 277 /* Number of sets: %ecx */ 278 279 /* %edx */ 280 #define CPUID_DCP_INVALIDATE __BIT(0) /* WB invalidate/invalidate */ 281 #define CPUID_DCP_INCLUSIVE __BIT(1) /* Cache inclusiveness */ 282 #define CPUID_DCP_COMPLEX __BIT(2) /* Complex cache indexing */ 283 284 /* 285 * Intel/AMD MONITOR/MWAIT 286 * Fn0000_0005 287 */ 288 /* %eax */ 289 #define CPUID_MON_MINSIZE __BITS(15, 0) /* Smallest monitor-line size */ 290 /* %ebx */ 291 #define CPUID_MON_MAXSIZE __BITS(15, 0) /* Largest monitor-line size */ 292 /* %ecx */ 293 #define CPUID_MON_EMX __BIT(0) /* MONITOR/MWAIT Extensions */ 294 #define CPUID_MON_IBE __BIT(1) /* Interrupt as Break Event */ 295 296 #define CPUID_MON_FLAGS "\20" \ 297 "\1" "EMX" "\2" "IBE" 298 299 /* %edx: number of substates for specific C-state */ 300 #define CPUID_MON_SUBSTATE(edx, cstate) (((edx) >> (cstate * 4)) & 0x0000000f) 301 302 /* 303 * Intel/AMD Digital Thermal Sensor and 304 * Power Management, Fn0000_0006 - %eax. 305 */ 306 #define CPUID_DSPM_DTS __BIT(0) /* Digital Thermal Sensor */ 307 #define CPUID_DSPM_IDA __BIT(1) /* Intel Dynamic Acceleration */ 308 #define CPUID_DSPM_ARAT __BIT(2) /* Always Running APIC Timer */ 309 #define CPUID_DSPM_PLN __BIT(4) /* Power Limit Notification */ 310 #define CPUID_DSPM_ECMD __BIT(5) /* Clock Modulation Extension */ 311 #define CPUID_DSPM_PTM __BIT(6) /* Package Level Thermal Management */ 312 #define CPUID_DSPM_HWP __BIT(7) /* HWP */ 313 #define CPUID_DSPM_HWP_NOTIFY __BIT(8) /* HWP Notification */ 314 #define CPUID_DSPM_HWP_ACTWIN __BIT(9) /* HWP Activity Window */ 315 #define CPUID_DSPM_HWP_EPP __BIT(10) /* HWP Energy Performance Preference */ 316 #define CPUID_DSPM_HWP_PLR __BIT(11) /* HWP Package Level Request */ 317 #define CPUID_DSPM_HDC __BIT(13) /* Hardware Duty Cycling */ 318 #define CPUID_DSPM_TBMT3 __BIT(14) /* Turbo Boost Max Technology 3.0 */ 319 #define CPUID_DSPM_HWP_CAP __BIT(15) /* HWP Capabilities */ 320 #define CPUID_DSPM_HWP_PECI __BIT(16) /* HWP PECI override */ 321 #define CPUID_DSPM_HWP_FLEX __BIT(17) /* Flexible HWP */ 322 #define CPUID_DSPM_HWP_FAST __BIT(18) /* Fast access for IA32_HWP_REQUEST */ 323 #define CPUID_DSPM_HWP_IGNIDL __BIT(20) /* Ignore Idle Logical Processor HWP */ 324 325 #define CPUID_DSPM_FLAGS "\20" \ 326 "\1" "DTS" "\2" "IDA" "\3" "ARAT" \ 327 "\5" "PLN" "\6" "ECMD" "\7" "PTM" "\10" "HWP" \ 328 "\11" "HWP_NOTIFY" "\12" "HWP_ACTWIN" "\13" "HWP_EPP" "\14" "HWP_PLR" \ 329 "\16" "HDC" "\17" "TBM3" "\20" "HWP_CAP" \ 330 "\21" "HWP_PECI" "\22" "HWP_FLEX" "\23" "HWP_FAST" \ 331 "25" "HWP_IGNIDL" 332 333 /* 334 * Intel/AMD Digital Thermal Sensor and 335 * Power Management, Fn0000_0006 - %ecx. 336 */ 337 #define CPUID_DSPM_HWF 0x00000001 /* MSR_APERF/MSR_MPERF available */ 338 #define CPUID_DSPM_EPB 0x00000008 /* Energy Performance Bias */ 339 340 #define CPUID_DSPM_FLAGS1 "\20" "\1" "HWF" "\4" "EPB" 341 342 /* 343 * Intel/AMD Structured Extended Feature leaf Fn0000_0007 344 * %eax == 0: Subleaf 0 345 * %eax: The Maximum input value for supported subleaf. 346 * %ebx: Feature bits. 347 * %ecx: Feature bits. 348 * %edx: Feature bits. 349 */ 350 351 /* %ebx */ 352 #define CPUID_SEF_FSGSBASE __BIT(0) /* {RD,WR}{FS,GS}BASE */ 353 #define CPUID_SEF_TSC_ADJUST __BIT(1) /* IA32_TSC_ADJUST MSR support */ 354 #define CPUID_SEF_SGX __BIT(2) /* Software Guard Extentions */ 355 #define CPUID_SEF_BMI1 __BIT(3) /* advanced bit manipulation ext. 1st grp */ 356 #define CPUID_SEF_HLE __BIT(4) /* Hardware Lock Elision */ 357 #define CPUID_SEF_AVX2 __BIT(5) /* Advanced Vector Extensions 2 */ 358 #define CPUID_SEF_FDPEXONLY __BIT(6) /* x87FPU Data ptr updated only on x87exp */ 359 #define CPUID_SEF_SMEP __BIT(7) /* Supervisor-Mode Excecution Prevention */ 360 #define CPUID_SEF_BMI2 __BIT(8) /* advanced bit manipulation ext. 2nd grp */ 361 #define CPUID_SEF_ERMS __BIT(9) /* Enhanced REP MOVSB/STOSB */ 362 #define CPUID_SEF_INVPCID __BIT(10) /* INVPCID instruction */ 363 #define CPUID_SEF_RTM __BIT(11) /* Restricted Transactional Memory */ 364 #define CPUID_SEF_QM __BIT(12) /* Resource Director Technology Monitoring */ 365 #define CPUID_SEF_FPUCSDS __BIT(13) /* Deprecate FPU CS and FPU DS values */ 366 #define CPUID_SEF_MPX __BIT(14) /* Memory Protection Extensions */ 367 #define CPUID_SEF_PQE __BIT(15) /* Resource Director Technology Allocation */ 368 #define CPUID_SEF_AVX512F __BIT(16) /* AVX-512 Foundation */ 369 #define CPUID_SEF_AVX512DQ __BIT(17) /* AVX-512 Double/Quadword */ 370 #define CPUID_SEF_RDSEED __BIT(18) /* RDSEED instruction */ 371 #define CPUID_SEF_ADX __BIT(19) /* ADCX/ADOX instructions */ 372 #define CPUID_SEF_SMAP __BIT(20) /* Supervisor-Mode Access Prevention */ 373 #define CPUID_SEF_AVX512_IFMA __BIT(21) /* AVX-512 Integer Fused Multiply Add */ 374 /* Bit 22 was PCOMMIT */ 375 #define CPUID_SEF_CLFLUSHOPT __BIT(23) /* Cache Line FLUSH OPTimized */ 376 #define CPUID_SEF_CLWB __BIT(24) /* Cache Line Write Back */ 377 #define CPUID_SEF_PT __BIT(25) /* Processor Trace */ 378 #define CPUID_SEF_AVX512PF __BIT(26) /* AVX-512 PreFetch */ 379 #define CPUID_SEF_AVX512ER __BIT(27) /* AVX-512 Exponential and Reciprocal */ 380 #define CPUID_SEF_AVX512CD __BIT(28) /* AVX-512 Conflict Detection */ 381 #define CPUID_SEF_SHA __BIT(29) /* SHA Extensions */ 382 #define CPUID_SEF_AVX512BW __BIT(30) /* AVX-512 Byte and Word */ 383 #define CPUID_SEF_AVX512VL __BIT(31) /* AVX-512 Vector Length */ 384 385 #define CPUID_SEF_FLAGS "\20" \ 386 "\1" "FSGSBASE" "\2" "TSCADJUST" "\3" "SGX" "\4" "BMI1" \ 387 "\5" "HLE" "\6" "AVX2" "\7" "FDPEXONLY" "\10" "SMEP" \ 388 "\11" "BMI2" "\12" "ERMS" "\13" "INVPCID" "\14" "RTM" \ 389 "\15" "QM" "\16" "FPUCSDS" "\17" "MPX" "\20" "PQE" \ 390 "\21" "AVX512F" "\22" "AVX512DQ" "\23" "RDSEED" "\24" "ADX" \ 391 "\25" "SMAP" "\26" "AVX512_IFMA" "\30" "CLFLUSHOPT" \ 392 "\31" "CLWB" "\32" "PT" "\33" "AVX512PF" "\34" "AVX512ER" \ 393 "\35" "AVX512CD""\36" "SHA" "\37" "AVX512BW" "\40" "AVX512VL" 394 395 /* %ecx */ 396 #define CPUID_SEF_PREFETCHWT1 __BIT(0) /* PREFETCHWT1 instruction */ 397 #define CPUID_SEF_AVX512_VBMI __BIT(1) /* AVX-512 Vector Byte Manipulation */ 398 #define CPUID_SEF_UMIP __BIT(2) /* User-Mode Instruction prevention */ 399 #define CPUID_SEF_PKU __BIT(3) /* Protection Keys for User-mode pages */ 400 #define CPUID_SEF_OSPKE __BIT(4) /* OS has set CR4.PKE to ena. protec. keys */ 401 #define CPUID_SEF_AVX512_VBMI2 __BIT(6) /* AVX-512 Vector Byte Manipulation 2 */ 402 #define CPUID_SEF_GFNI __BIT(8) 403 #define CPUID_SEF_VAES __BIT(9) 404 #define CPUID_SEF_VPCLMULQDQ __BIT(10) 405 #define CPUID_SEF_AVX512_VNNI __BIT(11) /* Vector neural Network Instruction */ 406 #define CPUID_SEF_AVX512_BITALG __BIT(12) 407 #define CPUID_SEF_AVX512_VPOPCNTDQ __BIT(14) 408 #define CPUID_SEF_MAWAU __BITS(21, 17) /* MAWAU for BND{LD,ST}X */ 409 #define CPUID_SEF_RDPID __BIT(22) /* RDPID and IA32_TSC_AUX */ 410 #define CPUID_SEF_SGXLC __BIT(30) /* SGX Launch Configuration */ 411 412 #define CPUID_SEF_FLAGS1 "\177\20" \ 413 "b\0PREFETCHWT1\0" "b\1AVX512_VBMI\0" "b\2UMIP\0" "b\3PKU\0" \ 414 "b\4OSPKE\0" "b\6AVX512_VBMI2\0" \ 415 "b\10GFNI\0" "b\11VAES\0" "b\12VPCLMULQDQ\0" "b\13AVX512_VNNI\0"\ 416 "b\14AVX512_BITALG\0" "b\16AVX512_VPOPCNTDQ\0" \ 417 "f\21\5MAWAU\0" \ 418 "b\26RDPID\0" \ 419 "b\36SGXLC\0" 420 421 /* %edx */ 422 #define CPUID_SEF_AVX512_4VNNIW __BIT(2) 423 #define CPUID_SEF_AVX512_4FMAPS __BIT(3) 424 #define CPUID_SEF_IBRS __BIT(26) /* IBRS / IBPB Speculation Control */ 425 #define CPUID_SEF_STIBP __BIT(27) /* STIBP Speculation Control */ 426 #define CPUID_SEF_L1D_FLUSH __BIT(28) /* IA32_FLUSH_CMD MSR */ 427 #define CPUID_SEF_ARCH_CAP __BIT(29) /* IA32_ARCH_CAPABILITIES */ 428 #define CPUID_SEF_SSBD __BIT(31) /* Speculative Store Bypass Disable */ 429 430 #define CPUID_SEF_FLAGS2 "\20" \ 431 "\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS" \ 432 "\33" "IBRS" "\34" "STIBP" \ 433 "\35" "L1D_FLUSH" "\36" "ARCH_CAP" "\40" "SSBD" 434 435 /* 436 * Intel CPUID Extended Topology Enumeration Fn0000000b 437 * %ecx == level number 438 * %eax: See below. 439 * %ebx: Number of logical processors at this level. 440 * %ecx: See below. 441 * %edx: x2APIC ID of the current logical processor. 442 */ 443 /* %eax */ 444 #define CPUID_TOP_SHIFTNUM __BITS(4, 0) /* Topology ID shift value */ 445 /* %ecx */ 446 #define CPUID_TOP_LVLNUM __BITS(7, 0) /* Level number */ 447 #define CPUID_TOP_LVLTYPE __BITS(15, 8) /* Level type */ 448 #define CPUID_TOP_LVLTYPE_INVAL 0 /* Invalid */ 449 #define CPUID_TOP_LVLTYPE_SMT 1 /* SMT */ 450 #define CPUID_TOP_LVLTYPE_CORE 2 /* Core */ 451 452 /* 453 * Intel/AMD CPUID Processor extended state Enumeration Fn0000000d 454 * 455 * %ecx == 0: supported features info: 456 * %eax: Valid bits of lower 32bits of XCR0 457 * %ebx: Maximum save area size for features enabled in XCR0 458 * %ecx: Maximum save area size for all cpu features 459 * %edx: Valid bits of upper 32bits of XCR0 460 * 461 * %ecx == 1: 462 * %eax: Bit 0 => xsaveopt instruction available (sandy bridge onwards) 463 * %ebx: Save area size for features enabled by XCR0 | IA32_XSS 464 * %ecx: Valid bits of lower 32bits of IA32_XSS 465 * %edx: Valid bits of upper 32bits of IA32_XSS 466 * 467 * %ecx >= 2: Save area details for XCR0 bit n 468 * %eax: size of save area for this feature 469 * %ebx: offset of save area for this feature 470 * %ecx, %edx: reserved 471 * All of %eax, %ebx, %ecx and %edx are zero for unsupported features. 472 */ 473 474 /* %ecx=1 %eax */ 475 #define CPUID_PES1_XSAVEOPT 0x00000001 /* xsaveopt instruction */ 476 #define CPUID_PES1_XSAVEC 0x00000002 /* xsavec & compacted XRSTOR */ 477 #define CPUID_PES1_XGETBV 0x00000004 /* xgetbv with ECX = 1 */ 478 #define CPUID_PES1_XSAVES 0x00000008 /* xsaves/xrstors, IA32_XSS */ 479 480 #define CPUID_PES1_FLAGS "\20" \ 481 "\1" "XSAVEOPT" "\2" "XSAVEC" "\3" "XGETBV" "\4" "XSAVES" 482 483 /* 484 * Intel Deterministic Address Translation Parameter Leaf 485 * Fn0000_0018 486 */ 487 488 /* %ecx=0 %eax __BITS(31, 0): the maximum input value of supported sub-leaf */ 489 490 /* %ebx */ 491 #define CPUID_DATP_PGSIZE __BITS(3, 0) /* page size */ 492 #define CPUID_DATP_PGSIZE_4KB __BIT(0) /* 4KB page support */ 493 #define CPUID_DATP_PGSIZE_2MB __BIT(1) /* 2MB page support */ 494 #define CPUID_DATP_PGSIZE_4MB __BIT(2) /* 4MB page support */ 495 #define CPUID_DATP_PGSIZE_1GB __BIT(3) /* 1GB page support */ 496 #define CPUID_DATP_PARTITIONING __BITS(10, 8) /* Partitioning */ 497 #define CPUID_DATP_WAYS __BITS(31, 16) /* Ways of associativity */ 498 499 /* Number of sets: %ecx */ 500 501 /* %edx */ 502 #define CPUID_DATP_TCTYPE __BITS(4, 0) /* Translation Cache type */ 503 #define CPUID_DATP_TCTYPE_N 0 /* NULL (not valid) */ 504 #define CPUID_DATP_TCTYPE_D 1 /* Data TLB */ 505 #define CPUID_DATP_TCTYPE_I 2 /* Instruction TLB */ 506 #define CPUID_DATP_TCTYPE_U 3 /* Unified TLB */ 507 #define CPUID_DATP_TCLEVEL __BITS(7, 5) /* TLB level (start at 1) */ 508 #define CPUID_DATP_FULLASSOC __BIT(8) /* Full associative */ 509 #define CPUID_DATP_SHAREING __BITS(25, 14) /* shareing */ 510 511 512 /* Intel Fn80000001 extended features - %edx */ 513 #define CPUID_SYSCALL 0x00000800 /* SYSCALL/SYSRET */ 514 #define CPUID_XD 0x00100000 /* Execute Disable (like CPUID_NOX) */ 515 #define CPUID_P1GB 0x04000000 /* 1GB Large Page Support */ 516 #define CPUID_RDTSCP 0x08000000 /* Read TSC Pair Instruction */ 517 #define CPUID_EM64T 0x20000000 /* Intel EM64T */ 518 519 #define CPUID_INTEL_EXT_FLAGS "\20" \ 520 "\14" "SYSCALL/SYSRET" "\25" "XD" "\33" "P1GB" \ 521 "\34" "RDTSCP" "\36" "EM64T" 522 523 /* Intel Fn80000001 extended features - %ecx */ 524 #define CPUID_LAHF 0x00000001 /* LAHF/SAHF in IA-32e mode, 64bit sub*/ 525 /* 0x00000020 */ /* LZCNT. Same as AMD's CPUID_LZCNT */ 526 #define CPUID_PREFETCHW 0x00000100 /* PREFETCHW */ 527 528 #define CPUID_INTEL_FLAGS4 "\20" \ 529 "\1" "LAHF" "\02" "B01" "\03" "B02" \ 530 "\06" "LZCNT" \ 531 "\11" "PREFETCHW" 532 533 534 /* AMD/VIA Fn80000001 extended features - %edx */ 535 /* CPUID_SYSCALL SYSCALL/SYSRET */ 536 #define CPUID_MPC 0x00080000 /* Multiprocessing Capable */ 537 #define CPUID_NOX 0x00100000 /* No Execute Page Protection */ 538 #define CPUID_MMXX 0x00400000 /* AMD MMX Extensions */ 539 /* CPUID_MMX MMX supported */ 540 /* CPUID_FXSR fast FP/MMX save/restore */ 541 #define CPUID_FFXSR 0x02000000 /* FXSAVE/FXSTOR Extensions */ 542 /* CPUID_P1GB 1GB Large Page Support */ 543 /* CPUID_RDTSCP Read TSC Pair Instruction */ 544 /* CPUID_EM64T Long mode */ 545 #define CPUID_3DNOW2 0x40000000 /* 3DNow! Instruction Extension */ 546 #define CPUID_3DNOW 0x80000000 /* 3DNow! Instructions */ 547 548 #define CPUID_EXT_FLAGS "\20" \ 549 "\14" "SYSCALL/SYSRET" \ 550 "\24" "MPC" \ 551 "\25" "NOX" "\27" "MMXX" "\30" "MMX" \ 552 "\31" "FXSR" "\32" "FFXSR" "\33" "P1GB" "\34" "RDTSCP" \ 553 "\36" "LONG" "\37" "3DNOW2" "\40" "3DNOW" 554 555 /* AMD Fn80000001 extended features - %ecx */ 556 /* CPUID_LAHF LAHF/SAHF instruction */ 557 #define CPUID_CMPLEGACY 0x00000002 /* Compare Legacy */ 558 #define CPUID_SVM 0x00000004 /* Secure Virtual Machine */ 559 #define CPUID_EAPIC 0x00000008 /* Extended APIC space */ 560 #define CPUID_ALTMOVCR0 0x00000010 /* Lock Mov Cr0 */ 561 #define CPUID_LZCNT 0x00000020 /* LZCNT instruction */ 562 #define CPUID_SSE4A 0x00000040 /* SSE4A instruction set */ 563 #define CPUID_MISALIGNSSE 0x00000080 /* Misaligned SSE */ 564 #define CPUID_3DNOWPF 0x00000100 /* 3DNow Prefetch */ 565 #define CPUID_OSVW 0x00000200 /* OS visible workarounds */ 566 #define CPUID_IBS 0x00000400 /* Instruction Based Sampling */ 567 #define CPUID_XOP 0x00000800 /* XOP instruction set */ 568 #define CPUID_SKINIT 0x00001000 /* SKINIT */ 569 #define CPUID_WDT 0x00002000 /* watchdog timer support */ 570 #define CPUID_LWP 0x00008000 /* Light Weight Profiling */ 571 #define CPUID_FMA4 0x00010000 /* FMA4 instructions */ 572 #define CPUID_TCE 0x00020000 /* Translation cache Extension */ 573 #define CPUID_NODEID 0x00080000 /* NodeID MSR available*/ 574 #define CPUID_TBM 0x00200000 /* TBM instructions */ 575 #define CPUID_TOPOEXT 0x00400000 /* cpuid Topology Extension */ 576 #define CPUID_PCEC 0x00800000 /* Perf Ctr Ext Core */ 577 #define CPUID_PCENB 0x01000000 /* Perf Ctr Ext NB */ 578 #define CPUID_SPM 0x02000000 /* Stream Perf Mon */ 579 #define CPUID_DBE 0x04000000 /* Data Breakpoint Extension */ 580 #define CPUID_PTSC 0x08000000 /* PerfTsc */ 581 #define CPUID_L2IPERFC 0x10000000 /* L2I performance counter Extension */ 582 #define CPUID_MWAITX 0x20000000 /* MWAITX/MONITORX support */ 583 584 #define CPUID_AMD_FLAGS4 "\20" \ 585 "\1" "LAHF" "\2" "CMPLEGACY" "\3" "SVM" "\4" "EAPIC" \ 586 "\5" "ALTMOVCR0" "\6" "LZCNT" "\7" "SSE4A" "\10" "MISALIGNSSE" \ 587 "\11" "3DNOWPREFETCH" \ 588 "\12" "OSVW" "\13" "IBS" "\14" "XOP" \ 589 "\15" "SKINIT" "\16" "WDT" "\17" "B14" "\20" "LWP" \ 590 "\21" "FMA4" "\22" "TCE" "\23" "B18" "\24" "NodeID" \ 591 "\25" "B20" "\26" "TBM" "\27" "TopoExt" "\30" "PCExtC" \ 592 "\31" "PCExtNB" "\32" "StrmPM" "\33" "DBExt" "\34" "PerfTsc" \ 593 "\35" "L2IPERFC" "\36" "MWAITX" "\37" "B30" "\40" "B31" 594 595 /* 596 * AMD Advanced Power Management 597 * CPUID Fn8000_0007 %edx 598 */ 599 #define CPUID_APM_TS 0x00000001 /* Temperature Sensor */ 600 #define CPUID_APM_FID 0x00000002 /* Frequency ID control */ 601 #define CPUID_APM_VID 0x00000004 /* Voltage ID control */ 602 #define CPUID_APM_TTP 0x00000008 /* THERMTRIP (PCI F3xE4 register) */ 603 #define CPUID_APM_HTC 0x00000010 /* Hardware thermal control (HTC) */ 604 #define CPUID_APM_STC 0x00000020 /* Software thermal control (STC) */ 605 #define CPUID_APM_100 0x00000040 /* 100MHz multiplier control */ 606 #define CPUID_APM_HWP 0x00000080 /* HW P-State control */ 607 #define CPUID_APM_TSC 0x00000100 /* TSC invariant */ 608 #define CPUID_APM_CPB 0x00000200 /* Core performance boost */ 609 #define CPUID_APM_EFF 0x00000400 /* Effective Frequency (read-only) */ 610 611 #define CPUID_APM_FLAGS "\20" \ 612 "\1" "TS" "\2" "FID" "\3" "VID" "\4" "TTP" \ 613 "\5" "HTC" "\6" "STC" "\7" "100" "\10" "HWP" \ 614 "\11" "TSC" "\12" "CPB" "\13" "EffFreq" "\14" "B11" \ 615 "\15" "B12" 616 617 /* AMD Fn8000000a %edx features (SVM features) */ 618 #define CPUID_AMD_SVM_NP 0x00000001 619 #define CPUID_AMD_SVM_LbrVirt 0x00000002 620 #define CPUID_AMD_SVM_SVML 0x00000004 621 #define CPUID_AMD_SVM_NRIPS 0x00000008 622 #define CPUID_AMD_SVM_TSCRateCtrl 0x00000010 623 #define CPUID_AMD_SVM_VMCBCleanBits 0x00000020 624 #define CPUID_AMD_SVM_FlushByASID 0x00000040 625 #define CPUID_AMD_SVM_DecodeAssist 0x00000080 626 #define CPUID_AMD_SVM_PauseFilter 0x00000400 627 #define CPUID_AMD_SVM_PFThreshold 0x0x001000 /* PAUSE filter threshold */ 628 #define CPUID_AMD_SVM_AVIC 0x00002000 /* AMD Virtual intr. ctrl */ 629 #define CPUID_AMD_SVM_V_VMSAVE_VMLOAD 0x00008000 /* Virtual VM{SAVE/LOAD} */ 630 #define CPUID_AMD_SVM_vGIF 0x00010000 /* Virtualized GIF */ 631 #define CPUID_AMD_SVM_FLAGS "\20" \ 632 "\1" "NP" "\2" "LbrVirt" "\3" "SVML" "\4" "NRIPS" \ 633 "\5" "TSCRate" "\6" "VMCBCleanBits" \ 634 "\7" "FlushByASID" "\10" "DecodeAssist" \ 635 "\11" "B08" "\12" "B09" "\13" "PauseFilter" "\14" "B11" \ 636 "\15" "PFThreshold" "\16" "AVIC" "\17" "B14" \ 637 "\20" "V_VMSAVE_VMLOAD" \ 638 "\21" "VGIF" 639 640 /* 641 * Centaur Extended Feature flags 642 */ 643 #define CPUID_VIA_HAS_RNG 0x00000004 /* Random number generator */ 644 #define CPUID_VIA_DO_RNG 0x00000008 645 #define CPUID_VIA_HAS_ACE 0x00000040 /* AES Encryption */ 646 #define CPUID_VIA_DO_ACE 0x00000080 647 #define CPUID_VIA_HAS_ACE2 0x00000100 /* AES+CTR instructions */ 648 #define CPUID_VIA_DO_ACE2 0x00000200 649 #define CPUID_VIA_HAS_PHE 0x00000400 /* SHA1+SHA256 HMAC */ 650 #define CPUID_VIA_DO_PHE 0x00000800 651 #define CPUID_VIA_HAS_PMM 0x00001000 /* RSA Instructions */ 652 #define CPUID_VIA_DO_PMM 0x00002000 653 654 #define CPUID_FLAGS_PADLOCK "\20" \ 655 "\3" "RNG" "\7" "AES" "\11" "AES/CTR" "\13" "SHA1/SHA256" \ 656 "\15" "RSA" 657 658 /* 659 * Model-specific registers for the i386 family 660 */ 661 #define MSR_P5_MC_ADDR 0x000 /* P5 only */ 662 #define MSR_P5_MC_TYPE 0x001 /* P5 only */ 663 #define MSR_TSC 0x010 664 #define MSR_CESR 0x011 /* P5 only (trap on P6) */ 665 #define MSR_CTR0 0x012 /* P5 only (trap on P6) */ 666 #define MSR_CTR1 0x013 /* P5 only (trap on P6) */ 667 #define MSR_IA32_PLATFORM_ID 0x017 668 #define MSR_APICBASE 0x01b 669 #define APICBASE_BSP 0x00000100 /* boot processor */ 670 #define APICBASE_EXTD 0x00000400 /* x2APIC mode */ 671 #define APICBASE_EN 0x00000800 /* software enable */ 672 /* 673 * APICBASE_PHYSADDR is actually variable-sized on some CPUs. But we're 674 * only interested in the initial value, which is guaranteed to fit the 675 * first 32 bits. So this macro is fine. 676 */ 677 #define APICBASE_PHYSADDR 0xfffff000 /* physical address */ 678 #define MSR_EBL_CR_POWERON 0x02a 679 #define MSR_EBC_FREQUENCY_ID 0x02c /* PIV only */ 680 #define MSR_TEST_CTL 0x033 681 #define MSR_IA32_SPEC_CTRL 0x048 682 #define IA32_SPEC_CTRL_IBRS 0x01 683 #define IA32_SPEC_CTRL_STIBP 0x02 684 #define IA32_SPEC_CTRL_SSBD 0x04 685 #define MSR_IA32_PRED_CMD 0x049 686 #define IA32_PRED_CMD_IBPB 0x01 687 #define MSR_BIOS_UPDT_TRIG 0x079 688 #define MSR_BBL_CR_D0 0x088 /* PII+ only */ 689 #define MSR_BBL_CR_D1 0x089 /* PII+ only */ 690 #define MSR_BBL_CR_D2 0x08a /* PII+ only */ 691 #define MSR_BIOS_SIGN 0x08b 692 #define MSR_PERFCTR0 0x0c1 693 #define MSR_PERFCTR1 0x0c2 694 #define MSR_FSB_FREQ 0x0cd /* Core Duo/Solo only */ 695 #define MSR_MPERF 0x0e7 696 #define MSR_APERF 0x0e8 697 #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ 698 #define MSR_MTRRcap 0x0fe 699 #define MSR_IA32_ARCH_CAPABILITIES 0x10a 700 #define IA32_ARCH_RDCL_NO 0x01 701 #define IA32_ARCH_IBRS_ALL 0x02 702 #define IA32_ARCH_RSBA 0x04 703 #define IA32_ARCH_SKIP_L1DFL_VMENTRY 0x08 704 #define IA32_ARCH_SSB_NO 0x10 705 #define MSR_IA32_FLUSH_CMD 0x10b 706 #define IA32_FLUSH_CMD_L1D_FLUSH 0x01 707 #define MSR_BBL_CR_ADDR 0x116 /* PII+ only */ 708 #define MSR_BBL_CR_DECC 0x118 /* PII+ only */ 709 #define MSR_BBL_CR_CTL 0x119 /* PII+ only */ 710 #define MSR_BBL_CR_TRIG 0x11a /* PII+ only */ 711 #define MSR_BBL_CR_BUSY 0x11b /* PII+ only */ 712 #define MSR_BBL_CR_CTR3 0x11e /* PII+ only */ 713 #define MSR_SYSENTER_CS 0x174 /* PII+ only */ 714 #define MSR_SYSENTER_ESP 0x175 /* PII+ only */ 715 #define MSR_SYSENTER_EIP 0x176 /* PII+ only */ 716 #define MSR_MCG_CAP 0x179 717 #define MSR_MCG_STATUS 0x17a 718 #define MSR_MCG_CTL 0x17b 719 #define MSR_EVNTSEL0 0x186 720 #define MSR_EVNTSEL1 0x187 721 #define MSR_PERF_STATUS 0x198 /* Pentium M */ 722 #define MSR_PERF_CTL 0x199 /* Pentium M */ 723 #define MSR_THERM_CONTROL 0x19a 724 #define MSR_THERM_INTERRUPT 0x19b 725 #define MSR_THERM_STATUS 0x19c 726 #define MSR_THERM2_CTL 0x19d /* Pentium M */ 727 #define MSR_MISC_ENABLE 0x1a0 728 #define IA32_MISC_MWAIT_EN 0x40000 729 #define MSR_TEMPERATURE_TARGET 0x1a2 730 #define MSR_DEBUGCTLMSR 0x1d9 731 #define MSR_LASTBRANCHFROMIP 0x1db 732 #define MSR_LASTBRANCHTOIP 0x1dc 733 #define MSR_LASTINTFROMIP 0x1dd 734 #define MSR_LASTINTTOIP 0x1de 735 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 736 #define MSR_MTRRphysBase0 0x200 737 #define MSR_MTRRphysMask0 0x201 738 #define MSR_MTRRphysBase1 0x202 739 #define MSR_MTRRphysMask1 0x203 740 #define MSR_MTRRphysBase2 0x204 741 #define MSR_MTRRphysMask2 0x205 742 #define MSR_MTRRphysBase3 0x206 743 #define MSR_MTRRphysMask3 0x207 744 #define MSR_MTRRphysBase4 0x208 745 #define MSR_MTRRphysMask4 0x209 746 #define MSR_MTRRphysBase5 0x20a 747 #define MSR_MTRRphysMask5 0x20b 748 #define MSR_MTRRphysBase6 0x20c 749 #define MSR_MTRRphysMask6 0x20d 750 #define MSR_MTRRphysBase7 0x20e 751 #define MSR_MTRRphysMask7 0x20f 752 #define MSR_MTRRphysBase8 0x210 753 #define MSR_MTRRphysMask8 0x211 754 #define MSR_MTRRphysBase9 0x212 755 #define MSR_MTRRphysMask9 0x213 756 #define MSR_MTRRphysBase10 0x214 757 #define MSR_MTRRphysMask10 0x215 758 #define MSR_MTRRphysBase11 0x216 759 #define MSR_MTRRphysMask11 0x217 760 #define MSR_MTRRphysBase12 0x218 761 #define MSR_MTRRphysMask12 0x219 762 #define MSR_MTRRphysBase13 0x21a 763 #define MSR_MTRRphysMask13 0x21b 764 #define MSR_MTRRphysBase14 0x21c 765 #define MSR_MTRRphysMask14 0x21d 766 #define MSR_MTRRphysBase15 0x21e 767 #define MSR_MTRRphysMask15 0x21f 768 #define MSR_MTRRfix64K_00000 0x250 769 #define MSR_MTRRfix16K_80000 0x258 770 #define MSR_MTRRfix16K_A0000 0x259 771 #define MSR_MTRRfix4K_C0000 0x268 772 #define MSR_MTRRfix4K_C8000 0x269 773 #define MSR_MTRRfix4K_D0000 0x26a 774 #define MSR_MTRRfix4K_D8000 0x26b 775 #define MSR_MTRRfix4K_E0000 0x26c 776 #define MSR_MTRRfix4K_E8000 0x26d 777 #define MSR_MTRRfix4K_F0000 0x26e 778 #define MSR_MTRRfix4K_F8000 0x26f 779 #define MSR_CR_PAT 0x277 780 #define MSR_MTRRdefType 0x2ff 781 #define MSR_MC0_CTL 0x400 782 #define MSR_MC0_STATUS 0x401 783 #define MSR_MC0_ADDR 0x402 784 #define MSR_MC0_MISC 0x403 785 #define MSR_MC1_CTL 0x404 786 #define MSR_MC1_STATUS 0x405 787 #define MSR_MC1_ADDR 0x406 788 #define MSR_MC1_MISC 0x407 789 #define MSR_MC2_CTL 0x408 790 #define MSR_MC2_STATUS 0x409 791 #define MSR_MC2_ADDR 0x40a 792 #define MSR_MC2_MISC 0x40b 793 #define MSR_MC3_CTL 0x40c 794 #define MSR_MC3_STATUS 0x40d 795 #define MSR_MC3_ADDR 0x40e 796 #define MSR_MC3_MISC 0x40f 797 #define MSR_MC4_CTL 0x410 798 #define MSR_MC4_STATUS 0x411 799 #define MSR_MC4_ADDR 0x412 800 #define MSR_MC4_MISC 0x413 801 /* 0x480 - 0x490 VMX */ 802 #define MSR_X2APIC_BASE 0x800 /* 0x800 - 0xBFF */ 803 #define MSR_X2APIC_ID 0x002 /* x2APIC ID. (RO) */ 804 #define MSR_X2APIC_VERS 0x003 /* Version. (RO) */ 805 #define MSR_X2APIC_TPRI 0x008 /* Task Prio. (RW) */ 806 #define MSR_X2APIC_PPRI 0x00a /* Processor prio. (RO) */ 807 #define MSR_X2APIC_EOI 0x00b /* End Int. (W) */ 808 #define MSR_X2APIC_LDR 0x00d /* Logical dest. (RO) */ 809 #define MSR_X2APIC_SVR 0x00f /* Spurious intvec (RW) */ 810 #define MSR_X2APIC_ISR 0x010 /* In-Service Status (RO) */ 811 #define MSR_X2APIC_TMR 0x018 /* Trigger Mode (RO) */ 812 #define MSR_X2APIC_IRR 0x020 /* Interrupt Req (RO) */ 813 #define MSR_X2APIC_ESR 0x028 /* Err status. (RW) */ 814 #define MSR_X2APIC_LVT_CMCI 0x02f /* LVT CMCI (RW) */ 815 #define MSR_X2APIC_ICRLO 0x030 /* Int. cmd. (RW64) */ 816 #define MSR_X2APIC_LVTT 0x032 /* Loc.vec.(timer) (RW) */ 817 #define MSR_X2APIC_TMINT 0x033 /* Loc.vec (Thermal) (RW) */ 818 #define MSR_X2APIC_PCINT 0x034 /* Loc.vec (Perf Mon) (RW) */ 819 #define MSR_X2APIC_LVINT0 0x035 /* Loc.vec (LINT0) (RW) */ 820 #define MSR_X2APIC_LVINT1 0x036 /* Loc.vec (LINT1) (RW) */ 821 #define MSR_X2APIC_LVERR 0x037 /* Loc.vec (ERROR) (RW) */ 822 #define MSR_X2APIC_ICR_TIMER 0x038 /* Initial count (RW) */ 823 #define MSR_X2APIC_CCR_TIMER 0x039 /* Current count (RO) */ 824 #define MSR_X2APIC_DCR_TIMER 0x03e /* Divisor config (RW) */ 825 #define MSR_X2APIC_SELF_IPI 0x03f /* SELF IPI (W) */ 826 827 /* 828 * VIA "Nehemiah" MSRs 829 */ 830 #define MSR_VIA_RNG 0x0000110b 831 #define MSR_VIA_RNG_ENABLE 0x00000040 832 #define MSR_VIA_RNG_NOISE_MASK 0x00000300 833 #define MSR_VIA_RNG_NOISE_A 0x00000000 834 #define MSR_VIA_RNG_NOISE_B 0x00000100 835 #define MSR_VIA_RNG_2NOISE 0x00000300 836 #define MSR_VIA_ACE 0x00001107 837 #define VIA_ACE_ALTINST 0x00000001 838 #define VIA_ACE_ECX8 0x00000002 839 #define VIA_ACE_ENABLE 0x10000000 840 841 /* 842 * VIA "Eden" MSRs 843 */ 844 #define MSR_VIA_FCR MSR_VIA_ACE 845 846 /* 847 * AMD K6/K7 MSRs. 848 */ 849 #define MSR_K6_UWCCR 0xc0000085 850 #define MSR_K7_EVNTSEL0 0xc0010000 851 #define MSR_K7_EVNTSEL1 0xc0010001 852 #define MSR_K7_EVNTSEL2 0xc0010002 853 #define MSR_K7_EVNTSEL3 0xc0010003 854 #define MSR_K7_PERFCTR0 0xc0010004 855 #define MSR_K7_PERFCTR1 0xc0010005 856 #define MSR_K7_PERFCTR2 0xc0010006 857 #define MSR_K7_PERFCTR3 0xc0010007 858 859 /* 860 * AMD K8 (Opteron) MSRs. 861 */ 862 #define MSR_SYSCFG 0xc0010010 863 864 #define MSR_EFER 0xc0000080 /* Extended feature enable */ 865 #define EFER_SCE 0x00000001 /* SYSCALL extension */ 866 #define EFER_LME 0x00000100 /* Long Mode Enable */ 867 #define EFER_LMA 0x00000400 /* Long Mode Active */ 868 #define EFER_NXE 0x00000800 /* No-Execute Enabled */ 869 #define EFER_SVME 0x00001000 /* Secure Virtual Machine En. */ 870 #define EFER_LMSLE 0x00002000 /* Long Mode Segment Limit E. */ 871 #define EFER_FFXSR 0x00004000 /* Fast FXSAVE/FXRSTOR En. */ 872 #define EFER_TCE 0x00008000 /* Translation Cache Ext. */ 873 874 #define MSR_STAR 0xc0000081 /* 32 bit syscall gate addr */ 875 #define MSR_LSTAR 0xc0000082 /* 64 bit syscall gate addr */ 876 #define MSR_CSTAR 0xc0000083 /* compat syscall gate addr */ 877 #define MSR_SFMASK 0xc0000084 /* flags to clear on syscall */ 878 879 #define MSR_FSBASE 0xc0000100 /* 64bit offset for fs: */ 880 #define MSR_GSBASE 0xc0000101 /* 64bit offset for gs: */ 881 #define MSR_KERNELGSBASE 0xc0000102 /* storage for swapgs ins */ 882 883 #define MSR_VMCR 0xc0010114 /* Virtual Machine Control Register */ 884 #define VMCR_DPD 0x00000001 /* Debug port disable */ 885 #define VMCR_RINIT 0x00000002 /* intercept init */ 886 #define VMCR_DISA20 0x00000004 /* Disable A20 masking */ 887 #define VMCR_LOCK 0x00000008 /* SVM Lock */ 888 #define VMCR_SVMED 0x00000010 /* SVME Disable */ 889 #define MSR_SVMLOCK 0xc0010118 /* SVM Lock key */ 890 891 /* 892 * These require a 'passcode' for access. See cpufunc.h. 893 */ 894 #define MSR_HWCR 0xc0010015 895 #define HWCR_TLBCACHEDIS 0x00000008 896 #define HWCR_FFDIS 0x00000040 897 898 #define MSR_NB_CFG 0xc001001f 899 #define NB_CFG_DISIOREQLOCK 0x0000000000000008ULL 900 #define NB_CFG_DISDATMSK 0x0000001000000000ULL 901 #define NB_CFG_INITAPICCPUIDLO (1ULL << 54) 902 903 #define MSR_LS_CFG 0xc0011020 904 #define LS_CFG_ERRATA_1033 __BIT(4) 905 #define LS_CFG_ERRATA_793 __BIT(15) 906 #define LS_CFG_ERRATA_1095 __BIT(57) 907 #define LS_CFG_DIS_LS2_SQUISH 0x02000000 908 #define LS_CFG_DIS_SSB_F15H 0x0040000000000000ULL 909 #define LS_CFG_DIS_SSB_F16H 0x0000000200000000ULL 910 #define LS_CFG_DIS_SSB_F17H 0x0000000000000400ULL 911 912 #define MSR_IC_CFG 0xc0011021 913 #define IC_CFG_DIS_SEQ_PREFETCH 0x00000800 914 #define IC_CFG_DIS_IND 0x00004000 915 #define IC_CFG_ERRATA_776 __BIT(26) 916 917 #define MSR_DC_CFG 0xc0011022 918 #define DC_CFG_DIS_CNV_WC_SSO 0x00000008 919 #define DC_CFG_DIS_SMC_CHK_BUF 0x00000400 920 #define DC_CFG_ERRATA_261 0x01000000 921 922 #define MSR_BU_CFG 0xc0011023 923 #define BU_CFG_ERRATA_298 0x0000000000000002ULL 924 #define BU_CFG_ERRATA_254 0x0000000000200000ULL 925 #define BU_CFG_ERRATA_309 0x0000000000800000ULL 926 #define BU_CFG_THRL2IDXCMPDIS 0x0000080000000000ULL 927 #define BU_CFG_WBPFSMCCHKDIS 0x0000200000000000ULL 928 #define BU_CFG_WBENHWSBDIS 0x0001000000000000ULL 929 930 #define MSR_FP_CFG 0xc0011028 931 #define FP_CFG_ERRATA_1049 __BIT(4) 932 933 #define MSR_DE_CFG 0xc0011029 934 #define DE_CFG_ERRATA_721 0x00000001 935 #define DE_CFG_ERRATA_1021 __BIT(13) 936 937 #define MSR_LS_CFG2 0xc001102d 938 #define LS_CFG2_ERRATA_1091 __BIT(34) 939 940 /* AMD Family10h MSRs */ 941 #define MSR_OSVW_ID_LENGTH 0xc0010140 942 #define MSR_OSVW_STATUS 0xc0010141 943 #define MSR_UCODE_AMD_PATCHLEVEL 0x0000008b 944 #define MSR_UCODE_AMD_PATCHLOADER 0xc0010020 945 946 /* X86 MSRs */ 947 #define MSR_RDTSCP_AUX 0xc0000103 948 949 /* 950 * Constants related to MTRRs 951 */ 952 #define MTRR_N64K 8 /* numbers of fixed-size entries */ 953 #define MTRR_N16K 16 954 #define MTRR_N4K 64 955 956 /* 957 * the following four 3-byte registers control the non-cacheable regions. 958 * These registers must be written as three separate bytes. 959 * 960 * NCRx+0: A31-A24 of starting address 961 * NCRx+1: A23-A16 of starting address 962 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 963 * 964 * The non-cacheable region's starting address must be aligned to the 965 * size indicated by the NCR_SIZE_xx field. 966 */ 967 #define NCR1 0xc4 968 #define NCR2 0xc7 969 #define NCR3 0xca 970 #define NCR4 0xcd 971 972 #define NCR_SIZE_0K 0 973 #define NCR_SIZE_4K 1 974 #define NCR_SIZE_8K 2 975 #define NCR_SIZE_16K 3 976 #define NCR_SIZE_32K 4 977 #define NCR_SIZE_64K 5 978 #define NCR_SIZE_128K 6 979 #define NCR_SIZE_256K 7 980 #define NCR_SIZE_512K 8 981 #define NCR_SIZE_1M 9 982 #define NCR_SIZE_2M 10 983 #define NCR_SIZE_4M 11 984 #define NCR_SIZE_8M 12 985 #define NCR_SIZE_16M 13 986 #define NCR_SIZE_32M 14 987 #define NCR_SIZE_4G 15 988
Indexes created Mon Sep 29 21:09:56 GMT 2025