specialreg.h revision 1.162
1 /* $NetBSD: specialreg.h,v 1.162 2020/04/24 09:49:05 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2014-2019 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * Copyright (c) 1991 The Regents of the University of California. 31 * All rights reserved. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 1. Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * 2. Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in the 40 * documentation and/or other materials provided with the distribution. 41 * 3. Neither the name of the University nor the names of its contributors 42 * may be used to endorse or promote products derived from this software 43 * without specific prior written permission. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 * 57 * @(#)specialreg.h 7.1 (Berkeley) 5/9/91 58 */ 59 60 /* 61 * CR0 62 */ 63 #define CR0_PE 0x00000001 /* Protected mode Enable */ 64 #define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */ 65 #define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */ 66 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 67 #define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */ 68 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 69 #define CR0_WP 0x00010000 /* Write Protect (honor PTE_W in all modes) */ 70 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 71 #define CR0_NW 0x20000000 /* Not Write-through */ 72 #define CR0_CD 0x40000000 /* Cache Disable */ 73 #define CR0_PG 0x80000000 /* PaGing enable */ 74 75 /* 76 * Cyrix 486 DLC special registers, accessible as IO ports 77 */ 78 #define CCR0 0xc0 /* configuration control register 0 */ 79 #define CCR0_NC0 0x01 /* first 64K of each 1M memory region is non-cacheable */ 80 #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 81 #define CCR0_A20M 0x04 /* enables A20M# input pin */ 82 #define CCR0_KEN 0x08 /* enables KEN# input pin */ 83 #define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */ 84 #define CCR0_BARB 0x20 /* flushes internal cache when entering hold state */ 85 #define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */ 86 #define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */ 87 #define CCR1 0xc1 /* configuration control register 1 */ 88 #define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */ 89 90 /* 91 * CR3 92 */ 93 #define CR3_PCID __BITS(11,0) 94 #define CR3_PA __BITS(62,12) 95 #define CR3_NO_TLB_FLUSH __BIT(63) 96 97 /* 98 * CR4 99 */ 100 #define CR4_VME 0x00000001 /* virtual 8086 mode extension enable */ 101 #define CR4_PVI 0x00000002 /* protected mode virtual interrupt enable */ 102 #define CR4_TSD 0x00000004 /* restrict RDTSC instruction to cpl 0 */ 103 #define CR4_DE 0x00000008 /* debugging extension */ 104 #define CR4_PSE 0x00000010 /* large (4MB) page size enable */ 105 #define CR4_PAE 0x00000020 /* physical address extension enable */ 106 #define CR4_MCE 0x00000040 /* machine check enable */ 107 #define CR4_PGE 0x00000080 /* page global enable */ 108 #define CR4_PCE 0x00000100 /* enable RDPMC instruction for all cpls */ 109 #define CR4_OSFXSR 0x00000200 /* enable fxsave/fxrestor and SSE */ 110 #define CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */ 111 #define CR4_UMIP 0x00000800 /* user-mode instruction prevention */ 112 #define CR4_VMXE 0x00002000 /* enable VMX operations */ 113 #define CR4_SMXE 0x00004000 /* enable SMX operations */ 114 #define CR4_FSGSBASE 0x00010000 /* enable *FSBASE and *GSBASE instructions */ 115 #define CR4_PCIDE 0x00020000 /* enable Process Context IDentifiers */ 116 #define CR4_OSXSAVE 0x00040000 /* enable xsave and xrestore */ 117 #define CR4_SMEP 0x00100000 /* enable SMEP support */ 118 #define CR4_SMAP 0x00200000 /* enable SMAP support */ 119 #define CR4_PKE 0x00400000 /* protection key enable */ 120 121 /* 122 * Extended Control Register XCR0 123 */ 124 #define XCR0_X87 0x00000001 /* x87 FPU/MMX state */ 125 #define XCR0_SSE 0x00000002 /* SSE state */ 126 #define XCR0_YMM_Hi128 0x00000004 /* AVX-256 (ymmn registers) */ 127 #define XCR0_BNDREGS 0x00000008 /* Memory protection ext bounds */ 128 #define XCR0_BNDCSR 0x00000010 /* Memory protection ext state */ 129 #define XCR0_Opmask 0x00000020 /* AVX-512 Opmask */ 130 #define XCR0_ZMM_Hi256 0x00000040 /* AVX-512 upper 256 bits low regs */ 131 #define XCR0_Hi16_ZMM 0x00000080 /* AVX-512 512 bits upper registers */ 132 #define XCR0_PT 0x00000100 /* Processor Trace state */ 133 #define XCR0_PKRU 0x00000200 /* Protection Key state */ 134 #define XCR0_HDC 0x00002000 /* Hardware Duty Cycle state */ 135 136 #define XCR0_FLAGS1 "\20" \ 137 "\1" "x87" "\2" "SSE" "\3" "AVX" \ 138 "\4" "BNDREGS" "\5" "BNDCSR" "\6" "Opmask" \ 139 "\7" "ZMM_Hi256" "\10" "Hi16_ZMM" "\11" "PT" \ 140 "\12" "PKRU" "\16" "HDC" 141 142 /* 143 * Known FPU bits, only these get enabled. The save area is sized for all the 144 * fields below. 145 */ 146 #define XCR0_FPU (XCR0_X87 | XCR0_SSE | XCR0_YMM_Hi128 | \ 147 XCR0_Opmask | XCR0_ZMM_Hi256 | XCR0_Hi16_ZMM) 148 149 /* 150 * XSAVE component indices. 151 */ 152 #define XSAVE_X87 0 153 #define XSAVE_SSE 1 154 #define XSAVE_YMM_Hi128 2 155 #define XSAVE_BNDREGS 3 156 #define XSAVE_BNDCSR 4 157 #define XSAVE_Opmask 5 158 #define XSAVE_ZMM_Hi256 6 159 #define XSAVE_Hi16_ZMM 7 160 #define XSAVE_PT 8 161 #define XSAVE_PKRU 9 162 #define XSAVE_HDC 10 163 164 /* 165 * Highest XSAVE component enabled by XCR0_FPU. 166 */ 167 #define XSAVE_MAX_COMPONENT XSAVE_Hi16_ZMM 168 169 /* 170 * CPUID "features" bits 171 */ 172 173 /* Fn00000001 %edx features */ 174 #define CPUID_FPU 0x00000001 /* processor has an FPU? */ 175 #define CPUID_VME 0x00000002 /* has virtual mode (%cr4's VME/PVI) */ 176 #define CPUID_DE 0x00000004 /* has debugging extension */ 177 #define CPUID_PSE 0x00000008 /* has 4MB page size extension */ 178 #define CPUID_TSC 0x00000010 /* has time stamp counter */ 179 #define CPUID_MSR 0x00000020 /* has model specific registers */ 180 #define CPUID_PAE 0x00000040 /* has phys address extension */ 181 #define CPUID_MCE 0x00000080 /* has machine check exception */ 182 #define CPUID_CX8 0x00000100 /* has CMPXCHG8B instruction */ 183 #define CPUID_APIC 0x00000200 /* has enabled APIC */ 184 #define CPUID_B10 0x00000400 /* reserved, MTRR */ 185 #define CPUID_SEP 0x00000800 /* has SYSENTER/SYSEXIT extension */ 186 #define CPUID_MTRR 0x00001000 /* has memory type range register */ 187 #define CPUID_PGE 0x00002000 /* has page global extension */ 188 #define CPUID_MCA 0x00004000 /* has machine check architecture */ 189 #define CPUID_CMOV 0x00008000 /* has CMOVcc instruction */ 190 #define CPUID_PAT 0x00010000 /* Page Attribute Table */ 191 #define CPUID_PSE36 0x00020000 /* 36-bit PSE */ 192 #define CPUID_PN 0x00040000 /* processor serial number */ 193 #define CPUID_CFLUSH 0x00080000 /* CLFLUSH insn supported */ 194 #define CPUID_B20 0x00100000 /* reserved */ 195 #define CPUID_DS 0x00200000 /* Debug Store */ 196 #define CPUID_ACPI 0x00400000 /* ACPI performance modulation regs */ 197 #define CPUID_MMX 0x00800000 /* MMX supported */ 198 #define CPUID_FXSR 0x01000000 /* fast FP/MMX save/restore */ 199 #define CPUID_SSE 0x02000000 /* streaming SIMD extensions */ 200 #define CPUID_SSE2 0x04000000 /* streaming SIMD extensions #2 */ 201 #define CPUID_SS 0x08000000 /* self-snoop */ 202 #define CPUID_HTT 0x10000000 /* Hyper-Threading Technology */ 203 #define CPUID_TM 0x20000000 /* thermal monitor (TCC) */ 204 #define CPUID_IA64 0x40000000 /* IA-64 architecture */ 205 #define CPUID_SBF 0x80000000 /* signal break on FERR */ 206 207 #define CPUID_FLAGS1 "\20" \ 208 "\1" "FPU" "\2" "VME" "\3" "DE" "\4" "PSE" \ 209 "\5" "TSC" "\6" "MSR" "\7" "PAE" "\10" "MCE" \ 210 "\11" "CX8" "\12" "APIC" "\13" "B10" "\14" "SEP" \ 211 "\15" "MTRR" "\16" "PGE" "\17" "MCA" "\20" "CMOV" \ 212 "\21" "PAT" "\22" "PSE36" "\23" "PN" "\24" "CLFLUSH" \ 213 "\25" "B20" "\26" "DS" "\27" "ACPI" "\30" "MMX" \ 214 "\31" "FXSR" "\32" "SSE" "\33" "SSE2" "\34" "SS" \ 215 "\35" "HTT" "\36" "TM" "\37" "IA64" "\40" "SBF" 216 217 /* Blacklists of CPUID flags - used to mask certain features */ 218 #ifdef XENPV 219 #define CPUID_FEAT_BLACKLIST (CPUID_PGE|CPUID_PSE|CPUID_MTRR) 220 #else 221 #define CPUID_FEAT_BLACKLIST 0 222 #endif 223 224 /* 225 * CPUID "features" bits in Fn00000001 %ecx 226 */ 227 228 #define CPUID2_SSE3 0x00000001 /* Streaming SIMD Extensions 3 */ 229 #define CPUID2_PCLMUL 0x00000002 /* PCLMULQDQ instructions */ 230 #define CPUID2_DTES64 0x00000004 /* 64-bit Debug Trace */ 231 #define CPUID2_MONITOR 0x00000008 /* MONITOR/MWAIT instructions */ 232 #define CPUID2_DS_CPL 0x00000010 /* CPL Qualified Debug Store */ 233 #define CPUID2_VMX 0x00000020 /* Virtual Machine Extensions */ 234 #define CPUID2_SMX 0x00000040 /* Safer Mode Extensions */ 235 #define CPUID2_EST 0x00000080 /* Enhanced SpeedStep Technology */ 236 #define CPUID2_TM2 0x00000100 /* Thermal Monitor 2 */ 237 #define CPUID2_SSSE3 0x00000200 /* Supplemental SSE3 */ 238 #define CPUID2_CID 0x00000400 /* Context ID */ 239 #define CPUID2_SDBG 0x00000800 /* Silicon Debug */ 240 #define CPUID2_FMA 0x00001000 /* has Fused Multiply Add */ 241 #define CPUID2_CX16 0x00002000 /* has CMPXCHG16B instruction */ 242 #define CPUID2_xTPR 0x00004000 /* Task Priority Messages disabled? */ 243 #define CPUID2_PDCM 0x00008000 /* Perf/Debug Capability MSR */ 244 /* bit 16 unused 0x00010000 */ 245 #define CPUID2_PCID 0x00020000 /* Process Context ID */ 246 #define CPUID2_DCA 0x00040000 /* Direct Cache Access */ 247 #define CPUID2_SSE41 0x00080000 /* Streaming SIMD Extensions 4.1 */ 248 #define CPUID2_SSE42 0x00100000 /* Streaming SIMD Extensions 4.2 */ 249 #define CPUID2_X2APIC 0x00200000 /* xAPIC Extensions */ 250 #define CPUID2_MOVBE 0x00400000 /* MOVBE (move after byteswap) */ 251 #define CPUID2_POPCNT 0x00800000 /* popcount instruction available */ 252 #define CPUID2_DEADLINE 0x01000000 /* APIC Timer supports TSC Deadline */ 253 #define CPUID2_AES 0x02000000 /* AES instructions */ 254 #define CPUID2_XSAVE 0x04000000 /* XSAVE instructions */ 255 #define CPUID2_OSXSAVE 0x08000000 /* XGETBV/XSETBV instructions */ 256 #define CPUID2_AVX 0x10000000 /* AVX instructions */ 257 #define CPUID2_F16C 0x20000000 /* half precision conversion */ 258 #define CPUID2_RDRAND 0x40000000 /* RDRAND (hardware random number) */ 259 #define CPUID2_RAZ 0x80000000 /* RAZ. Indicates guest state. */ 260 261 #define CPUID2_FLAGS1 "\20" \ 262 "\1" "SSE3" "\2" "PCLMULQDQ" "\3" "DTES64" "\4" "MONITOR" \ 263 "\5" "DS-CPL" "\6" "VMX" "\7" "SMX" "\10" "EST" \ 264 "\11" "TM2" "\12" "SSSE3" "\13" "CID" "\14" "SDBG" \ 265 "\15" "FMA" "\16" "CX16" "\17" "xTPR" "\20" "PDCM" \ 266 "\21" "B16" "\22" "PCID" "\23" "DCA" "\24" "SSE41" \ 267 "\25" "SSE42" "\26" "X2APIC" "\27" "MOVBE" "\30" "POPCNT" \ 268 "\31" "DEADLINE" "\32" "AES" "\33" "XSAVE" "\34" "OSXSAVE" \ 269 "\35" "AVX" "\36" "F16C" "\37" "RDRAND" "\40" "RAZ" 270 271 /* CPUID Fn00000001 %eax */ 272 273 #define CPUID_TO_BASEFAMILY(cpuid) (((cpuid) >> 8) & 0xf) 274 #define CPUID_TO_BASEMODEL(cpuid) (((cpuid) >> 4) & 0xf) 275 #define CPUID_TO_STEPPING(cpuid) ((cpuid) & 0xf) 276 277 /* 278 * The Extended family bits should only be inspected when CPUID_TO_BASEFAMILY() 279 * returns 15. They are use to encode family value 16 to 270 (add 15). 280 * The Extended model bits are the high 4 bits of the model. 281 * They are only valid for family >= 15 or family 6 (intel, but all amd 282 * family 6 are documented to return zero bits for them). 283 */ 284 #define CPUID_TO_EXTFAMILY(cpuid) (((cpuid) >> 20) & 0xff) 285 #define CPUID_TO_EXTMODEL(cpuid) (((cpuid) >> 16) & 0xf) 286 287 /* The macros for the Display Family and the Display Model */ 288 #define CPUID_TO_FAMILY(cpuid) (CPUID_TO_BASEFAMILY(cpuid) \ 289 + ((CPUID_TO_BASEFAMILY(cpuid) != 0x0f) \ 290 ? 0 : CPUID_TO_EXTFAMILY(cpuid))) 291 #define CPUID_TO_MODEL(cpuid) (CPUID_TO_BASEMODEL(cpuid) \ 292 | ((CPUID_TO_BASEFAMILY(cpuid) != 0x0f) \ 293 && (CPUID_TO_BASEFAMILY(cpuid) != 0x06) \ 294 ? 0 : (CPUID_TO_EXTMODEL(cpuid) << 4))) 295 296 /* CPUID Fn00000001 %ebx */ 297 #define CPUID_BRAND_INDEX __BITS(7,0) 298 #define CPUID_CLFLUSH_SIZE __BITS(15,8) 299 #define CPUID_HTT_CORES __BITS(23,16) 300 #define CPUID_LOCAL_APIC_ID __BITS(31,24) 301 302 /* 303 * Intel Deterministic Cache Parameter Leaf 304 * Fn0000_0004 305 */ 306 307 /* %eax */ 308 #define CPUID_DCP_CACHETYPE __BITS(4, 0) /* Cache type */ 309 #define CPUID_DCP_CACHETYPE_N 0 /* NULL */ 310 #define CPUID_DCP_CACHETYPE_D 1 /* Data cache */ 311 #define CPUID_DCP_CACHETYPE_I 2 /* Instruction cache */ 312 #define CPUID_DCP_CACHETYPE_U 3 /* Unified cache */ 313 #define CPUID_DCP_CACHELEVEL __BITS(7, 5) /* Cache level (start at 1) */ 314 #define CPUID_DCP_SELFINITCL __BIT(8) /* Self initializing cachelvl*/ 315 #define CPUID_DCP_FULLASSOC __BIT(9) /* Full associative */ 316 #define CPUID_DCP_SHAREING __BITS(25, 14) /* shareing */ 317 #define CPUID_DCP_CORE_P_PKG __BITS(31, 26) /* Cores/package */ 318 319 /* %ebx */ 320 #define CPUID_DCP_LINESIZE __BITS(11, 0) /* System coherency linesize */ 321 #define CPUID_DCP_PARTITIONS __BITS(21, 12) /* Physical line partitions */ 322 #define CPUID_DCP_WAYS __BITS(31, 22) /* Ways of associativity */ 323 324 /* Number of sets: %ecx */ 325 326 /* %edx */ 327 #define CPUID_DCP_INVALIDATE __BIT(0) /* WB invalidate/invalidate */ 328 #define CPUID_DCP_INCLUSIVE __BIT(1) /* Cache inclusiveness */ 329 #define CPUID_DCP_COMPLEX __BIT(2) /* Complex cache indexing */ 330 331 /* 332 * Intel/AMD MONITOR/MWAIT 333 * Fn0000_0005 334 */ 335 /* %eax */ 336 #define CPUID_MON_MINSIZE __BITS(15, 0) /* Smallest monitor-line size */ 337 /* %ebx */ 338 #define CPUID_MON_MAXSIZE __BITS(15, 0) /* Largest monitor-line size */ 339 /* %ecx */ 340 #define CPUID_MON_EMX __BIT(0) /* MONITOR/MWAIT Extensions */ 341 #define CPUID_MON_IBE __BIT(1) /* Interrupt as Break Event */ 342 343 #define CPUID_MON_FLAGS "\20" \ 344 "\1" "EMX" "\2" "IBE" 345 346 /* %edx: number of substates for specific C-state */ 347 #define CPUID_MON_SUBSTATE(edx, cstate) (((edx) >> (cstate * 4)) & 0x0000000f) 348 349 /* 350 * Intel/AMD Digital Thermal Sensor and 351 * Power Management, Fn0000_0006 - %eax. 352 */ 353 #define CPUID_DSPM_DTS __BIT(0) /* Digital Thermal Sensor */ 354 #define CPUID_DSPM_IDA __BIT(1) /* Intel Dynamic Acceleration */ 355 #define CPUID_DSPM_ARAT __BIT(2) /* Always Running APIC Timer */ 356 #define CPUID_DSPM_PLN __BIT(4) /* Power Limit Notification */ 357 #define CPUID_DSPM_ECMD __BIT(5) /* Clock Modulation Extension */ 358 #define CPUID_DSPM_PTM __BIT(6) /* Package Level Thermal Management */ 359 #define CPUID_DSPM_HWP __BIT(7) /* HWP */ 360 #define CPUID_DSPM_HWP_NOTIFY __BIT(8) /* HWP Notification */ 361 #define CPUID_DSPM_HWP_ACTWIN __BIT(9) /* HWP Activity Window */ 362 #define CPUID_DSPM_HWP_EPP __BIT(10) /* HWP Energy Performance Preference */ 363 #define CPUID_DSPM_HWP_PLR __BIT(11) /* HWP Package Level Request */ 364 #define CPUID_DSPM_HDC __BIT(13) /* Hardware Duty Cycling */ 365 #define CPUID_DSPM_TBMT3 __BIT(14) /* Turbo Boost Max Technology 3.0 */ 366 #define CPUID_DSPM_HWP_CAP __BIT(15) /* HWP Capabilities */ 367 #define CPUID_DSPM_HWP_PECI __BIT(16) /* HWP PECI override */ 368 #define CPUID_DSPM_HWP_FLEX __BIT(17) /* Flexible HWP */ 369 #define CPUID_DSPM_HWP_FAST __BIT(18) /* Fast access for IA32_HWP_REQUEST */ 370 #define CPUID_DSPM_HWP_IGNIDL __BIT(20) /* Ignore Idle Logical Processor HWP */ 371 372 #define CPUID_DSPM_FLAGS "\20" \ 373 "\1" "DTS" "\2" "IDA" "\3" "ARAT" \ 374 "\5" "PLN" "\6" "ECMD" "\7" "PTM" "\10" "HWP" \ 375 "\11" "HWP_NOTIFY" "\12" "HWP_ACTWIN" "\13" "HWP_EPP" "\14" "HWP_PLR" \ 376 "\16" "HDC" "\17" "TBM3" "\20" "HWP_CAP" \ 377 "\21" "HWP_PECI" "\22" "HWP_FLEX" "\23" "HWP_FAST" \ 378 "25" "HWP_IGNIDL" 379 380 /* 381 * Intel/AMD Digital Thermal Sensor and 382 * Power Management, Fn0000_0006 - %ecx. 383 */ 384 #define CPUID_DSPM_HWF 0x00000001 /* MSR_APERF/MSR_MPERF available */ 385 #define CPUID_DSPM_EPB 0x00000008 /* Energy Performance Bias */ 386 387 #define CPUID_DSPM_FLAGS1 "\20" "\1" "HWF" "\4" "EPB" 388 389 /* 390 * Intel/AMD Structured Extended Feature leaf Fn0000_0007 391 * %eax == 0: Subleaf 0 392 * %eax: The Maximum input value for supported subleaf. 393 * %ebx: Feature bits. 394 * %ecx: Feature bits. 395 * %edx: Feature bits. 396 */ 397 398 /* %ebx */ 399 #define CPUID_SEF_FSGSBASE __BIT(0) /* {RD,WR}{FS,GS}BASE */ 400 #define CPUID_SEF_TSC_ADJUST __BIT(1) /* IA32_TSC_ADJUST MSR support */ 401 #define CPUID_SEF_SGX __BIT(2) /* Software Guard Extensions */ 402 #define CPUID_SEF_BMI1 __BIT(3) /* advanced bit manipulation ext. 1st grp */ 403 #define CPUID_SEF_HLE __BIT(4) /* Hardware Lock Elision */ 404 #define CPUID_SEF_AVX2 __BIT(5) /* Advanced Vector Extensions 2 */ 405 #define CPUID_SEF_FDPEXONLY __BIT(6) /* x87FPU Data ptr updated only on x87exp */ 406 #define CPUID_SEF_SMEP __BIT(7) /* Supervisor-Mode Execution Prevention */ 407 #define CPUID_SEF_BMI2 __BIT(8) /* advanced bit manipulation ext. 2nd grp */ 408 #define CPUID_SEF_ERMS __BIT(9) /* Enhanced REP MOVSB/STOSB */ 409 #define CPUID_SEF_INVPCID __BIT(10) /* INVPCID instruction */ 410 #define CPUID_SEF_RTM __BIT(11) /* Restricted Transactional Memory */ 411 #define CPUID_SEF_QM __BIT(12) /* Resource Director Technology Monitoring */ 412 #define CPUID_SEF_FPUCSDS __BIT(13) /* Deprecate FPU CS and FPU DS values */ 413 #define CPUID_SEF_MPX __BIT(14) /* Memory Protection Extensions */ 414 #define CPUID_SEF_PQE __BIT(15) /* Resource Director Technology Allocation */ 415 #define CPUID_SEF_AVX512F __BIT(16) /* AVX-512 Foundation */ 416 #define CPUID_SEF_AVX512DQ __BIT(17) /* AVX-512 Double/Quadword */ 417 #define CPUID_SEF_RDSEED __BIT(18) /* RDSEED instruction */ 418 #define CPUID_SEF_ADX __BIT(19) /* ADCX/ADOX instructions */ 419 #define CPUID_SEF_SMAP __BIT(20) /* Supervisor-Mode Access Prevention */ 420 #define CPUID_SEF_AVX512_IFMA __BIT(21) /* AVX-512 Integer Fused Multiply Add */ 421 /* Bit 22 was PCOMMIT */ 422 #define CPUID_SEF_CLFLUSHOPT __BIT(23) /* Cache Line FLUSH OPTimized */ 423 #define CPUID_SEF_CLWB __BIT(24) /* Cache Line Write Back */ 424 #define CPUID_SEF_PT __BIT(25) /* Processor Trace */ 425 #define CPUID_SEF_AVX512PF __BIT(26) /* AVX-512 PreFetch */ 426 #define CPUID_SEF_AVX512ER __BIT(27) /* AVX-512 Exponential and Reciprocal */ 427 #define CPUID_SEF_AVX512CD __BIT(28) /* AVX-512 Conflict Detection */ 428 #define CPUID_SEF_SHA __BIT(29) /* SHA Extensions */ 429 #define CPUID_SEF_AVX512BW __BIT(30) /* AVX-512 Byte and Word */ 430 #define CPUID_SEF_AVX512VL __BIT(31) /* AVX-512 Vector Length */ 431 432 #define CPUID_SEF_FLAGS "\20" \ 433 "\1" "FSGSBASE" "\2" "TSCADJUST" "\3" "SGX" "\4" "BMI1" \ 434 "\5" "HLE" "\6" "AVX2" "\7" "FDPEXONLY" "\10" "SMEP" \ 435 "\11" "BMI2" "\12" "ERMS" "\13" "INVPCID" "\14" "RTM" \ 436 "\15" "QM" "\16" "FPUCSDS" "\17" "MPX" "\20" "PQE" \ 437 "\21" "AVX512F" "\22" "AVX512DQ" "\23" "RDSEED" "\24" "ADX" \ 438 "\25" "SMAP" "\26" "AVX512_IFMA" "\30" "CLFLUSHOPT" \ 439 "\31" "CLWB" "\32" "PT" "\33" "AVX512PF" "\34" "AVX512ER" \ 440 "\35" "AVX512CD""\36" "SHA" "\37" "AVX512BW" "\40" "AVX512VL" 441 442 /* %ecx */ 443 #define CPUID_SEF_PREFETCHWT1 __BIT(0) /* PREFETCHWT1 instruction */ 444 #define CPUID_SEF_AVX512_VBMI __BIT(1) /* AVX-512 Vector Byte Manipulation */ 445 #define CPUID_SEF_UMIP __BIT(2) /* User-Mode Instruction prevention */ 446 #define CPUID_SEF_PKU __BIT(3) /* Protection Keys for User-mode pages */ 447 #define CPUID_SEF_OSPKE __BIT(4) /* OS has set CR4.PKE to ena. protec. keys */ 448 #define CPUID_SEF_WAITPKG __BIT(5) /* TPAUSE,UMONITOR,UMWAIT */ 449 #define CPUID_SEF_AVX512_VBMI2 __BIT(6) /* AVX-512 Vector Byte Manipulation 2 */ 450 #define CPUID_SEF_CET_SS __BIT(7) /* CET shadow stack */ 451 #define CPUID_SEF_GFNI __BIT(8) 452 #define CPUID_SEF_VAES __BIT(9) 453 #define CPUID_SEF_VPCLMULQDQ __BIT(10) 454 #define CPUID_SEF_AVX512_VNNI __BIT(11) /* Vector neural Network Instruction */ 455 #define CPUID_SEF_AVX512_BITALG __BIT(12) 456 #define CPUID_SEF_AVX512_VPOPCNTDQ __BIT(14) 457 #define CPUID_SEF_MAWAU __BITS(21, 17) /* MAWAU for BND{LD,ST}X */ 458 #define CPUID_SEF_RDPID __BIT(22) /* RDPID and IA32_TSC_AUX */ 459 #define CPUID_SEF_CLDEMOTE __BIT(25) /* Cache line demote */ 460 #define CPUID_SEF_MOVDIRI __BIT(27) /* MOVDIRI instruction */ 461 #define CPUID_SEF_MOVDIR64B __BIT(28) /* MOVDIR64B instruction */ 462 #define CPUID_SEF_SGXLC __BIT(30) /* SGX Launch Configuration */ 463 464 #define CPUID_SEF_FLAGS1 "\177\20" \ 465 "b\0PREFETCHWT1\0" "b\1AVX512_VBMI\0" "b\2UMIP\0" "b\3PKU\0" \ 466 "b\4OSPKE\0" "b\5WAITPKG\0" "b\6AVX512_VBMI2\0" "b\7CET_SS\0" \ 467 "b\10GFNI\0" "b\11VAES\0" "b\12VPCLMULQDQ\0" "b\13AVX512_VNNI\0"\ 468 "b\14AVX512_BITALG\0" "b\16AVX512_VPOPCNTDQ\0" \ 469 "f\21\5MAWAU\0" \ 470 "b\26RDPID\0" \ 471 "b\31CLDEMOTE\0" "b\33MOVDIRI\0" \ 472 "b\34MOVDIR64B\0" "b\36SGXLC\0" 473 474 /* %edx */ 475 #define CPUID_SEF_AVX512_4VNNIW __BIT(2) 476 #define CPUID_SEF_AVX512_4FMAPS __BIT(3) 477 #define CPUID_SEF_FSREP_MOV __BIT(4) /* Fast Short REP MOV */ 478 #define CPUID_SEF_AVX512_VP2INTERSECT __BIT(8) 479 #define CPUID_SEF_MD_CLEAR __BIT(10) 480 #define CPUID_SEF_TSX_FORCE_ABORT __BIT(13) /* MSR_TSX_FORCE_ABORT bit 0 */ 481 #define CPUID_SEF_SERIALIZE __BIT(14) 482 #define CPUID_SEF_HYBRID __BIT(15) /* Hybrid part */ 483 #define CPUID_SEF_TSXLDTRK __BIT(16) /* TSX suspend load addr tracking */ 484 #define CPUID_SEF_CET_IBT __BIT(20) /* CET Indirect Branch Tracking */ 485 #define CPUID_SEF_IBRS __BIT(26) /* IBRS / IBPB Speculation Control */ 486 #define CPUID_SEF_STIBP __BIT(27) /* STIBP Speculation Control */ 487 #define CPUID_SEF_L1D_FLUSH __BIT(28) /* IA32_FLUSH_CMD MSR */ 488 #define CPUID_SEF_ARCH_CAP __BIT(29) /* IA32_ARCH_CAPABILITIES */ 489 #define CPUID_SEF_CORE_CAP __BIT(30) /* IA32_CORE_CAPABILITIES */ 490 #define CPUID_SEF_SSBD __BIT(31) /* Speculative Store Bypass Disable */ 491 492 #define CPUID_SEF_FLAGS2 "\20" \ 493 "\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS" \ 494 "\5" "FSREP_MOV" \ 495 "\11" "VP2INTERSECT" "\13" "MD_CLEAR" \ 496 "\16TSX_FORCE_ABORT" "\17SERIALIZE" "\20HYBRID" \ 497 "\21" "TSXLDTRK" \ 498 "\25" "CET_IBT" \ 499 "\33" "IBRS" "\34" "STIBP" \ 500 "\35" "L1D_FLUSH" "\36" "ARCH_CAP" "\37CORE_CAP" "\40" "SSBD" 501 502 /* 503 * Intel CPUID Architectural Performance Monitoring Fn0000000a 504 * 505 * See also src/usr.sbin/tprof/arch/tprof_x86.c 506 */ 507 508 /* %eax */ 509 #define CPUID_PERF_VERSION __BITS(7, 0) /* Version ID */ 510 #define CPUID_PERF_NGPPC __BITS(15, 8) /* Num of G.P. perf counter */ 511 #define CPUID_PERF_NBWGPPC __BITS(23, 16) /* Bit width of G.P. perfcnt */ 512 #define CPUID_PERF_BVECLEN __BITS(31, 24) /* Length of EBX bit vector */ 513 514 #define CPUID_PERF_FLAGS0 "\177\20" \ 515 "f\0\10VERSION\0" "f\10\10GPCounter\0" \ 516 "f\20\10GPBitwidth\0" "f\30\10Vectorlen\0" 517 518 /* %ebx */ 519 #define CPUID_PERF_CORECYCL __BIT(0) /* No core cycle */ 520 #define CPUID_PERF_INSTRETRY __BIT(1) /* No instruction retried */ 521 #define CPUID_PERF_REFCYCL __BIT(2) /* No reference cycles */ 522 #define CPUID_PERF_LLCREF __BIT(3) /* No LLCache reference */ 523 #define CPUID_PERF_LLCMISS __BIT(4) /* No LLCache miss */ 524 #define CPUID_PERF_BRINSRETR __BIT(5) /* No branch inst. retried */ 525 #define CPUID_PERF_BRMISPRRETR __BIT(6) /* No branch mispredict retry */ 526 527 #define CPUID_PERF_FLAGS1 "\177\20" \ 528 "b\0CORECYCL\0" "b\1INSTRETRY\0" "b\2REFCYCL\0" "b\3LLCREF\0" \ 529 "b\4LLCMISS\0" "b\5BRINSRETR\0" "b\6BRMISPRRETR\0" 530 531 /* %edx */ 532 #define CPUID_PERF_NFFPC __BITS(4, 0) /* Num of fixed-funct perfcnt */ 533 #define CPUID_PERF_NBWFFPC __BITS(12, 5) /* Bit width of fixed-func pc */ 534 #define CPUID_PERF_ANYTHREADDEPR __BIT(15) /* Any Thread deprecation */ 535 536 #define CPUID_PERF_FLAGS3 "\177\20" \ 537 "f\0\5FixedFunc\0" "f\5\10FFBitwidth\0" "b\17ANYTHREADDEPR\0" 538 539 /* 540 * Intel CPUID Extended Topology Enumeration Fn0000000b 541 * %ecx == level number 542 * %eax: See below. 543 * %ebx: Number of logical processors at this level. 544 * %ecx: See below. 545 * %edx: x2APIC ID of the current logical processor. 546 */ 547 /* %eax */ 548 #define CPUID_TOP_SHIFTNUM __BITS(4, 0) /* Topology ID shift value */ 549 /* %ecx */ 550 #define CPUID_TOP_LVLNUM __BITS(7, 0) /* Level number */ 551 #define CPUID_TOP_LVLTYPE __BITS(15, 8) /* Level type */ 552 #define CPUID_TOP_LVLTYPE_INVAL 0 /* Invalid */ 553 #define CPUID_TOP_LVLTYPE_SMT 1 /* SMT */ 554 #define CPUID_TOP_LVLTYPE_CORE 2 /* Core */ 555 556 /* 557 * Intel/AMD CPUID Processor extended state Enumeration Fn0000000d 558 * 559 * %ecx == 0: supported features info: 560 * %eax: Valid bits of lower 32bits of XCR0 561 * %ebx: Maximum save area size for features enabled in XCR0 562 * %ecx: Maximum save area size for all cpu features 563 * %edx: Valid bits of upper 32bits of XCR0 564 * 565 * %ecx == 1: 566 * %eax: Bit 0 => xsaveopt instruction available (sandy bridge onwards) 567 * %ebx: Save area size for features enabled by XCR0 | IA32_XSS 568 * %ecx: Valid bits of lower 32bits of IA32_XSS 569 * %edx: Valid bits of upper 32bits of IA32_XSS 570 * 571 * %ecx >= 2: Save area details for XCR0 bit n 572 * %eax: size of save area for this feature 573 * %ebx: offset of save area for this feature 574 * %ecx, %edx: reserved 575 * All of %eax, %ebx, %ecx and %edx are zero for unsupported features. 576 */ 577 578 /* %ecx=1 %eax */ 579 #define CPUID_PES1_XSAVEOPT 0x00000001 /* xsaveopt instruction */ 580 #define CPUID_PES1_XSAVEC 0x00000002 /* xsavec & compacted XRSTOR */ 581 #define CPUID_PES1_XGETBV 0x00000004 /* xgetbv with ECX = 1 */ 582 #define CPUID_PES1_XSAVES 0x00000008 /* xsaves/xrstors, IA32_XSS */ 583 584 #define CPUID_PES1_FLAGS "\20" \ 585 "\1" "XSAVEOPT" "\2" "XSAVEC" "\3" "XGETBV" "\4" "XSAVES" 586 587 /* 588 * Intel Deterministic Address Translation Parameter Leaf 589 * Fn0000_0018 590 */ 591 592 /* %ecx=0 %eax __BITS(31, 0): the maximum input value of supported sub-leaf */ 593 594 /* %ebx */ 595 #define CPUID_DATP_PGSIZE __BITS(3, 0) /* page size */ 596 #define CPUID_DATP_PGSIZE_4KB __BIT(0) /* 4KB page support */ 597 #define CPUID_DATP_PGSIZE_2MB __BIT(1) /* 2MB page support */ 598 #define CPUID_DATP_PGSIZE_4MB __BIT(2) /* 4MB page support */ 599 #define CPUID_DATP_PGSIZE_1GB __BIT(3) /* 1GB page support */ 600 #define CPUID_DATP_PARTITIONING __BITS(10, 8) /* Partitioning */ 601 #define CPUID_DATP_WAYS __BITS(31, 16) /* Ways of associativity */ 602 603 /* Number of sets: %ecx */ 604 605 /* %edx */ 606 #define CPUID_DATP_TCTYPE __BITS(4, 0) /* Translation Cache type */ 607 #define CPUID_DATP_TCTYPE_N 0 /* NULL (not valid) */ 608 #define CPUID_DATP_TCTYPE_D 1 /* Data TLB */ 609 #define CPUID_DATP_TCTYPE_I 2 /* Instruction TLB */ 610 #define CPUID_DATP_TCTYPE_U 3 /* Unified TLB */ 611 #define CPUID_DATP_TCLEVEL __BITS(7, 5) /* TLB level (start at 1) */ 612 #define CPUID_DATP_FULLASSOC __BIT(8) /* Full associative */ 613 #define CPUID_DATP_SHAREING __BITS(25, 14) /* shareing */ 614 615 616 /* Intel Fn80000001 extended features - %edx */ 617 #define CPUID_SYSCALL 0x00000800 /* SYSCALL/SYSRET */ 618 #define CPUID_XD 0x00100000 /* Execute Disable (like CPUID_NOX) */ 619 #define CPUID_P1GB 0x04000000 /* 1GB Large Page Support */ 620 #define CPUID_RDTSCP 0x08000000 /* Read TSC Pair Instruction */ 621 #define CPUID_EM64T 0x20000000 /* Intel EM64T */ 622 623 #define CPUID_INTEL_EXT_FLAGS "\20" \ 624 "\14" "SYSCALL/SYSRET" "\25" "XD" "\33" "P1GB" \ 625 "\34" "RDTSCP" "\36" "EM64T" 626 627 /* Intel Fn80000001 extended features - %ecx */ 628 #define CPUID_LAHF 0x00000001 /* LAHF/SAHF in IA-32e mode, 64bit sub*/ 629 /* 0x00000020 */ /* LZCNT. Same as AMD's CPUID_LZCNT */ 630 #define CPUID_PREFETCHW 0x00000100 /* PREFETCHW */ 631 632 #define CPUID_INTEL_FLAGS4 "\20" \ 633 "\1" "LAHF" "\02" "B01" "\03" "B02" \ 634 "\06" "LZCNT" \ 635 "\11" "PREFETCHW" 636 637 638 /* AMD/VIA Fn80000001 extended features - %edx */ 639 /* CPUID_SYSCALL SYSCALL/SYSRET */ 640 #define CPUID_MPC 0x00080000 /* Multiprocessing Capable */ 641 #define CPUID_NOX 0x00100000 /* No Execute Page Protection */ 642 #define CPUID_MMXX 0x00400000 /* AMD MMX Extensions */ 643 /* CPUID_MMX MMX supported */ 644 /* CPUID_FXSR fast FP/MMX save/restore */ 645 #define CPUID_FFXSR 0x02000000 /* FXSAVE/FXSTOR Extensions */ 646 /* CPUID_P1GB 1GB Large Page Support */ 647 /* CPUID_RDTSCP Read TSC Pair Instruction */ 648 /* CPUID_EM64T Long mode */ 649 #define CPUID_3DNOW2 0x40000000 /* 3DNow! Instruction Extension */ 650 #define CPUID_3DNOW 0x80000000 /* 3DNow! Instructions */ 651 652 #define CPUID_EXT_FLAGS "\20" \ 653 "\14" "SYSCALL/SYSRET" \ 654 "\24" "MPC" \ 655 "\25" "NOX" "\27" "MMXX" "\30" "MMX" \ 656 "\31" "FXSR" "\32" "FFXSR" "\33" "P1GB" "\34" "RDTSCP" \ 657 "\36" "LONG" "\37" "3DNOW2" "\40" "3DNOW" 658 659 /* AMD Fn8000_0001 extended features - %ecx */ 660 /* CPUID_LAHF LAHF/SAHF instruction */ 661 #define CPUID_CMPLEGACY 0x00000002 /* Compare Legacy */ 662 #define CPUID_SVM 0x00000004 /* Secure Virtual Machine */ 663 #define CPUID_EAPIC 0x00000008 /* Extended APIC space */ 664 #define CPUID_ALTMOVCR0 0x00000010 /* Lock Mov Cr0 */ 665 #define CPUID_LZCNT 0x00000020 /* LZCNT instruction */ 666 #define CPUID_SSE4A 0x00000040 /* SSE4A instruction set */ 667 #define CPUID_MISALIGNSSE 0x00000080 /* Misaligned SSE */ 668 #define CPUID_3DNOWPF 0x00000100 /* 3DNow Prefetch */ 669 #define CPUID_OSVW 0x00000200 /* OS visible workarounds */ 670 #define CPUID_IBS 0x00000400 /* Instruction Based Sampling */ 671 #define CPUID_XOP 0x00000800 /* XOP instruction set */ 672 #define CPUID_SKINIT 0x00001000 /* SKINIT */ 673 #define CPUID_WDT 0x00002000 /* watchdog timer support */ 674 #define CPUID_LWP 0x00008000 /* Light Weight Profiling */ 675 #define CPUID_FMA4 0x00010000 /* FMA4 instructions */ 676 #define CPUID_TCE 0x00020000 /* Translation cache Extension */ 677 #define CPUID_NODEID 0x00080000 /* NodeID MSR available*/ 678 #define CPUID_TBM 0x00200000 /* TBM instructions */ 679 #define CPUID_TOPOEXT 0x00400000 /* cpuid Topology Extension */ 680 #define CPUID_PCEC 0x00800000 /* Perf Ctr Ext Core */ 681 #define CPUID_PCENB 0x01000000 /* Perf Ctr Ext NB */ 682 #define CPUID_SPM 0x02000000 /* Stream Perf Mon */ 683 #define CPUID_DBE 0x04000000 /* Data Breakpoint Extension */ 684 #define CPUID_PTSC 0x08000000 /* PerfTsc */ 685 #define CPUID_L2IPERFC 0x10000000 /* L2I performance counter Extension */ 686 #define CPUID_MWAITX 0x20000000 /* MWAITX/MONITORX support */ 687 688 #define CPUID_AMD_FLAGS4 "\20" \ 689 "\1" "LAHF" "\2" "CMPLEGACY" "\3" "SVM" "\4" "EAPIC" \ 690 "\5" "ALTMOVCR0" "\6" "LZCNT" "\7" "SSE4A" "\10" "MISALIGNSSE" \ 691 "\11" "3DNOWPREFETCH" \ 692 "\12" "OSVW" "\13" "IBS" "\14" "XOP" \ 693 "\15" "SKINIT" "\16" "WDT" "\17" "B14" "\20" "LWP" \ 694 "\21" "FMA4" "\22" "TCE" "\23" "B18" "\24" "NodeID" \ 695 "\25" "B20" "\26" "TBM" "\27" "TopoExt" "\30" "PCExtC" \ 696 "\31" "PCExtNB" "\32" "StrmPM" "\33" "DBExt" "\34" "PerfTsc" \ 697 "\35" "L2IPERFC" "\36" "MWAITX" "\37" "B30" "\40" "B31" 698 699 /* 700 * Advanced Power Management 701 * CPUID Fn8000_0007 %edx 702 * 703 * Only ITSC is for both Intel and AMD. Others are only for AMD. 704 */ 705 #define CPUID_APM_TS 0x00000001 /* Temperature Sensor */ 706 #define CPUID_APM_FID 0x00000002 /* Frequency ID control */ 707 #define CPUID_APM_VID 0x00000004 /* Voltage ID control */ 708 #define CPUID_APM_TTP 0x00000008 /* THERMTRIP (PCI F3xE4 register) */ 709 #define CPUID_APM_HTC 0x00000010 /* Hardware thermal control (HTC) */ 710 #define CPUID_APM_STC 0x00000020 /* Software thermal control (STC) */ 711 #define CPUID_APM_100 0x00000040 /* 100MHz multiplier control */ 712 #define CPUID_APM_HWP 0x00000080 /* HW P-State control */ 713 #define CPUID_APM_ITSC 0x00000100 /* invariant TSC */ 714 #define CPUID_APM_CPB 0x00000200 /* Core performance boost */ 715 #define CPUID_APM_EFF 0x00000400 /* Effective Frequency (read-only) */ 716 #define CPUID_APM_PROCFI 0x00000800 /* Proc Feedback Interface */ 717 #define CPUID_APM_PROCPR 0x00001000 /* Proc Power Reporting */ 718 #define CPUID_APM_CONNSTBY 0x00002000 /* Connected Standby */ 719 #define CPUID_APM_RAPL 0x00004000 /* Running Average Power Limit */ 720 721 #define CPUID_APM_FLAGS "\20" \ 722 "\1" "TS" "\2" "FID" "\3" "VID" "\4" "TTP" \ 723 "\5" "HTC" "\6" "STC" "\7" "100" "\10" "HWP" \ 724 "\11" "ITSC" "\12" "CPB" "\13" "EffFreq" "\14" "PROCFI" \ 725 "\15" "PROCPR" "\16" "CONNSTBY" "\17" "RAPL" 726 727 /* 728 * AMD Processor Capacity Parameters and Extended Features 729 * CPUID Fn8000_0008 730 * %eax: Long Mode Size Identifiers 731 * %ebx: Extended Feature Identifiers 732 * %ecx: Size Identifiers 733 */ 734 735 /* %ebx */ 736 #define CPUID_CAPEX_CLZERO __BIT(0) /* CLZERO instruction */ 737 #define CPUID_CAPEX_IRPERF __BIT(1) /* InstRetCntMsr */ 738 #define CPUID_CAPEX_XSAVEERPTR __BIT(2) /* RstrFpErrPtrs by XRSTOR */ 739 #define CPUID_CAPEX_RDPRU __BIT(4) /* RDPRU instruction */ 740 #define CPUID_CAPEX_MCOMMIT __BIT(8) /* MCOMMIT instruction */ 741 #define CPUID_CAPEX_WBNOINVD __BIT(9) /* WBNOINVD instruction */ 742 #define CPUID_CAPEX_IBPB __BIT(12) /* Speculation Control IBPB */ 743 #define CPUID_CAPEX_IBRS __BIT(14) /* Speculation Control IBRS */ 744 #define CPUID_CAPEX_STIBP __BIT(15) /* Speculation Control STIBP */ 745 #define CPUID_CAPEX_IBRS_ALWAYSON __BIT(16) /* IBRS always on mode */ 746 #define CPUID_CAPEX_STIBP_ALWAYSON __BIT(17) /* STIBP always on mode */ 747 #define CPUID_CAPEX_PREFER_IBRS __BIT(18) /* IBRS preferred */ 748 #define CPUID_CAPEX_SSBD __BIT(24) /* Speculation Control SSBD */ 749 #define CPUID_CAPEX_VIRT_SSBD __BIT(25) /* Virt Spec Control SSBD */ 750 #define CPUID_CAPEX_SSB_NO __BIT(26) /* SSBD not required */ 751 752 #define CPUID_CAPEX_FLAGS "\20" \ 753 "\1CLZERO" "\2IRPERF" "\3XSAVEERPTR" \ 754 "\5RDPRU" "\7B6" \ 755 "\11MCOMMIT" "\12WBNOINVD" "\13B10" \ 756 "\15IBPB" "\16B13" "\17IBRS" "\20STIBP" \ 757 "\21IBRS_ALWAYSON" "\22STIBP_ALWAYSON" "\23PREFER_IBRS" "\24B19" \ 758 "\31SSBD" "\32VIRT_SSBD" "\33SSB_NO" 759 760 /* AMD Fn8000_000a %edx features (SVM features) */ 761 #define CPUID_AMD_SVM_NP 0x00000001 762 #define CPUID_AMD_SVM_LbrVirt 0x00000002 763 #define CPUID_AMD_SVM_SVML 0x00000004 764 #define CPUID_AMD_SVM_NRIPS 0x00000008 765 #define CPUID_AMD_SVM_TSCRateCtrl 0x00000010 766 #define CPUID_AMD_SVM_VMCBCleanBits 0x00000020 767 #define CPUID_AMD_SVM_FlushByASID 0x00000040 768 #define CPUID_AMD_SVM_DecodeAssist 0x00000080 769 #define CPUID_AMD_SVM_PauseFilter 0x00000400 770 #define CPUID_AMD_SVM_PFThreshold 0x00001000 /* PAUSE filter threshold */ 771 #define CPUID_AMD_SVM_AVIC 0x00002000 /* AMD Virtual intr. ctrl */ 772 #define CPUID_AMD_SVM_V_VMSAVE_VMLOAD 0x00008000 /* Virtual VM{SAVE/LOAD} */ 773 #define CPUID_AMD_SVM_vGIF 0x00010000 /* Virtualized GIF */ 774 #define CPUID_AMD_SVM_GMET 0x00020000 775 #define CPUID_AMD_SVM_SPEC_CTRL __BIT(20) 776 777 #define CPUID_AMD_SVM_FLAGS "\20" \ 778 "\1" "NP" "\2" "LbrVirt" "\3" "SVML" "\4" "NRIPS" \ 779 "\5" "TSCRate" "\6" "VMCBCleanBits" \ 780 "\7" "FlushByASID" "\10" "DecodeAssist" \ 781 "\11" "B08" "\12" "B09" "\13" "PauseFilter" "\14" "B11" \ 782 "\15" "PFThreshold" "\16" "AVIC" "\17" "B14" \ 783 "\20" "V_VMSAVE_VMLOAD" \ 784 "\21" "VGIF" "\22" "GMET" \ 785 "\25" "SPEC_CTRL" 786 787 /* 788 * AMD Fn8000_0001d Cache Topology Information. 789 * It's almost the same as Intel Deterministic Cache Parameter Leaf(0x04) 790 * except the following: 791 * No Cores/package (%eax bit 31..26) 792 * No Complex cache indexing (%edx bit 2) 793 */ 794 795 /* 796 * AMD Fn8000_0001f Encrypted Memory Capabilities. 797 * %eax: flags 798 * %ebx: 5-0: Cbit Position 799 * 11-6: PhysAddrReduction 800 * 15-12: NumVMPL 801 * %ecx: 31-0: NumEncryptedGuests 802 * %edx: 31-0: MinSevNoEsAsid 803 */ 804 #define CPUID_AMD_ENCMEM_SME __BIT(0) /* Secure Memory Encryption */ 805 #define CPUID_AMD_ENCMEM_SEV __BIT(1) /* Secure Encrypted Virtualiz. */ 806 #define CPUID_AMD_ENCMEM_PGFLMSR __BIT(2) /* Page Flush MSR */ 807 #define CPUID_AMD_ENCMEM_SEVES __BIT(3) /* SEV Encrypted State */ 808 #define CPUID_AMD_ENCMEM_SEV_SNP __BIT(4) /* Secure Nested Paging */ 809 #define CPUID_AMD_ENCMEM_VMPL __BIT(5) /* Virtual Machine Privilege Lvl */ 810 #define CPUID_AMD_ENCMEM_HECC __BIT(10) /* HW Enf Cache Coh across enc dom */ 811 #define CPUID_AMD_ENCMEM_64BH __BIT(11) /* 64Bit Host */ 812 #define CPUID_AMD_ENCMEM_RSTRINJ __BIT(12) /* Restricted Injection */ 813 #define CPUID_AMD_ENCMEM_ALTINJ __BIT(13) /* Alternate Injection */ 814 #define CPUID_AMD_ENCMEM_DBGSWAP __BIT(14) /* Debug Swap */ 815 #define CPUID_AMD_ENCMEM_PREVHOSTIBS __BIT(15) /* Prevent Host IBS */ 816 #define CPUID_AMD_ENCMEM_VTE __BIT(16) /* Virtual Transparent Encryption */ 817 818 #define CPUID_AMD_ENCMEM_FLAGS "\20" \ 819 "\1" "SME" "\2" "SEV" "\3" "PageFlushMsr" "\4" "SEV-ES" \ 820 "\5" "SEV-SNP" "\6" "VMPL" \ 821 "\13HwEnfCacheCoh" "\14" "64BitHost" \ 822 "\15" "RSTRINJ" "\16" "ALTINJ" "\17" "DebugSwap" "\20PreventHostlbs" \ 823 "\21" "VTE" 824 825 /* 826 * Centaur Extended Feature flags 827 */ 828 #define CPUID_VIA_HAS_RNG 0x00000004 /* Random number generator */ 829 #define CPUID_VIA_DO_RNG 0x00000008 830 #define CPUID_VIA_HAS_ACE 0x00000040 /* AES Encryption */ 831 #define CPUID_VIA_DO_ACE 0x00000080 832 #define CPUID_VIA_HAS_ACE2 0x00000100 /* AES+CTR instructions */ 833 #define CPUID_VIA_DO_ACE2 0x00000200 834 #define CPUID_VIA_HAS_PHE 0x00000400 /* SHA1+SHA256 HMAC */ 835 #define CPUID_VIA_DO_PHE 0x00000800 836 #define CPUID_VIA_HAS_PMM 0x00001000 /* RSA Instructions */ 837 #define CPUID_VIA_DO_PMM 0x00002000 838 839 #define CPUID_FLAGS_PADLOCK "\20" \ 840 "\3" "RNG" "\7" "AES" "\11" "AES/CTR" "\13" "SHA1/SHA256" \ 841 "\15" "RSA" 842 843 /* 844 * Model-Specific Registers 845 */ 846 #define MSR_TSC 0x010 847 #define MSR_IA32_PLATFORM_ID 0x017 848 #define MSR_APICBASE 0x01b 849 #define APICBASE_BSP 0x00000100 /* boot processor */ 850 #define APICBASE_EXTD 0x00000400 /* x2APIC mode */ 851 #define APICBASE_EN 0x00000800 /* software enable */ 852 /* 853 * APICBASE_PHYSADDR is actually variable-sized on some CPUs. But we're 854 * only interested in the initial value, which is guaranteed to fit the 855 * first 32 bits. So this macro is fine. 856 */ 857 #define APICBASE_PHYSADDR 0xfffff000 /* physical address */ 858 #define MSR_EBL_CR_POWERON 0x02a 859 #define MSR_EBC_FREQUENCY_ID 0x02c /* PIV only */ 860 #define MSR_IA32_SPEC_CTRL 0x048 861 #define IA32_SPEC_CTRL_IBRS 0x01 862 #define IA32_SPEC_CTRL_STIBP 0x02 863 #define IA32_SPEC_CTRL_SSBD 0x04 864 #define MSR_IA32_PRED_CMD 0x049 865 #define IA32_PRED_CMD_IBPB 0x01 866 #define MSR_BIOS_UPDT_TRIG 0x079 867 #define MSR_BIOS_SIGN 0x08b 868 #define MSR_PERFCTR0 0x0c1 869 #define MSR_PERFCTR1 0x0c2 870 #define MSR_FSB_FREQ 0x0cd /* Core Duo/Solo only */ 871 #define MSR_MPERF 0x0e7 872 #define MSR_APERF 0x0e8 873 #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ 874 #define MSR_MTRRcap 0x0fe 875 #define MSR_IA32_ARCH_CAPABILITIES 0x10a 876 #define IA32_ARCH_RDCL_NO 0x01 877 #define IA32_ARCH_IBRS_ALL 0x02 878 #define IA32_ARCH_RSBA 0x04 879 #define IA32_ARCH_SKIP_L1DFL_VMENTRY 0x08 880 #define IA32_ARCH_SSB_NO 0x10 881 #define IA32_ARCH_MDS_NO 0x20 882 #define IA32_ARCH_TSX_CTRL 0x80 883 #define IA32_ARCH_TAA_NO 0x100 884 #define MSR_IA32_FLUSH_CMD 0x10b 885 #define IA32_FLUSH_CMD_L1D_FLUSH 0x01 886 #define MSR_TSX_FORCE_ABORT 0x10f 887 #define MSR_IA32_TSX_CTRL 0x122 888 #define IA32_TSX_CTRL_RTM_DISABLE __BIT(0) 889 #define IA32_TSX_CTRL_TSX_CPUID_CLEAR __BIT(1) 890 #define MSR_SYSENTER_CS 0x174 /* PII+ only */ 891 #define MSR_SYSENTER_ESP 0x175 /* PII+ only */ 892 #define MSR_SYSENTER_EIP 0x176 /* PII+ only */ 893 #define MSR_MCG_CAP 0x179 894 #define MSR_MCG_STATUS 0x17a 895 #define MSR_MCG_CTL 0x17b 896 #define MSR_EVNTSEL0 0x186 897 #define MSR_EVNTSEL1 0x187 898 #define MSR_PERF_STATUS 0x198 /* Pentium M */ 899 #define MSR_PERF_CTL 0x199 /* Pentium M */ 900 #define MSR_THERM_CONTROL 0x19a 901 #define MSR_THERM_INTERRUPT 0x19b 902 #define MSR_THERM_STATUS 0x19c 903 #define MSR_THERM2_CTL 0x19d /* Pentium M */ 904 #define MSR_MISC_ENABLE 0x1a0 905 #define IA32_MISC_FAST_STR_EN __BIT(0) 906 #define IA32_MISC_ATCC_EN __BIT(3) 907 #define IA32_MISC_PERFMON_EN __BIT(7) 908 #define IA32_MISC_BTS_UNAVAIL __BIT(11) 909 #define IA32_MISC_PEBS_UNAVAIL __BIT(12) 910 #define IA32_MISC_EISST_EN __BIT(16) 911 #define IA32_MISC_MWAIT_EN __BIT(18) 912 #define IA32_MISC_LIMIT_CPUID __BIT(22) 913 #define IA32_MISC_XTPR_DIS __BIT(23) 914 #define IA32_MISC_XD_DIS __BIT(34) 915 #define MSR_TEMPERATURE_TARGET 0x1a2 916 #define MSR_DEBUGCTLMSR 0x1d9 917 #define MSR_LASTBRANCHFROMIP 0x1db 918 #define MSR_LASTBRANCHTOIP 0x1dc 919 #define MSR_LASTINTFROMIP 0x1dd 920 #define MSR_LASTINTTOIP 0x1de 921 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 922 #define MSR_MTRRphysBase0 0x200 923 #define MSR_MTRRphysMask0 0x201 924 #define MSR_MTRRphysBase1 0x202 925 #define MSR_MTRRphysMask1 0x203 926 #define MSR_MTRRphysBase2 0x204 927 #define MSR_MTRRphysMask2 0x205 928 #define MSR_MTRRphysBase3 0x206 929 #define MSR_MTRRphysMask3 0x207 930 #define MSR_MTRRphysBase4 0x208 931 #define MSR_MTRRphysMask4 0x209 932 #define MSR_MTRRphysBase5 0x20a 933 #define MSR_MTRRphysMask5 0x20b 934 #define MSR_MTRRphysBase6 0x20c 935 #define MSR_MTRRphysMask6 0x20d 936 #define MSR_MTRRphysBase7 0x20e 937 #define MSR_MTRRphysMask7 0x20f 938 #define MSR_MTRRphysBase8 0x210 939 #define MSR_MTRRphysMask8 0x211 940 #define MSR_MTRRphysBase9 0x212 941 #define MSR_MTRRphysMask9 0x213 942 #define MSR_MTRRphysBase10 0x214 943 #define MSR_MTRRphysMask10 0x215 944 #define MSR_MTRRphysBase11 0x216 945 #define MSR_MTRRphysMask11 0x217 946 #define MSR_MTRRphysBase12 0x218 947 #define MSR_MTRRphysMask12 0x219 948 #define MSR_MTRRphysBase13 0x21a 949 #define MSR_MTRRphysMask13 0x21b 950 #define MSR_MTRRphysBase14 0x21c 951 #define MSR_MTRRphysMask14 0x21d 952 #define MSR_MTRRphysBase15 0x21e 953 #define MSR_MTRRphysMask15 0x21f 954 #define MSR_MTRRfix64K_00000 0x250 955 #define MSR_MTRRfix16K_80000 0x258 956 #define MSR_MTRRfix16K_A0000 0x259 957 #define MSR_MTRRfix4K_C0000 0x268 958 #define MSR_MTRRfix4K_C8000 0x269 959 #define MSR_MTRRfix4K_D0000 0x26a 960 #define MSR_MTRRfix4K_D8000 0x26b 961 #define MSR_MTRRfix4K_E0000 0x26c 962 #define MSR_MTRRfix4K_E8000 0x26d 963 #define MSR_MTRRfix4K_F0000 0x26e 964 #define MSR_MTRRfix4K_F8000 0x26f 965 #define MSR_CR_PAT 0x277 966 #define MSR_MTRRdefType 0x2ff 967 #define MSR_MC0_CTL 0x400 968 #define MSR_MC0_STATUS 0x401 969 #define MSR_MC0_ADDR 0x402 970 #define MSR_MC0_MISC 0x403 971 #define MSR_MC1_CTL 0x404 972 #define MSR_MC1_STATUS 0x405 973 #define MSR_MC1_ADDR 0x406 974 #define MSR_MC1_MISC 0x407 975 #define MSR_MC2_CTL 0x408 976 #define MSR_MC2_STATUS 0x409 977 #define MSR_MC2_ADDR 0x40a 978 #define MSR_MC2_MISC 0x40b 979 #define MSR_MC3_CTL 0x40c 980 #define MSR_MC3_STATUS 0x40d 981 #define MSR_MC3_ADDR 0x40e 982 #define MSR_MC3_MISC 0x40f 983 #define MSR_MC4_CTL 0x410 984 #define MSR_MC4_STATUS 0x411 985 #define MSR_MC4_ADDR 0x412 986 #define MSR_MC4_MISC 0x413 987 /* 0x480 - 0x490 VMX */ 988 #define MSR_X2APIC_BASE 0x800 /* 0x800 - 0xBFF */ 989 #define MSR_X2APIC_ID 0x002 /* x2APIC ID. (RO) */ 990 #define MSR_X2APIC_VERS 0x003 /* Version. (RO) */ 991 #define MSR_X2APIC_TPRI 0x008 /* Task Prio. (RW) */ 992 #define MSR_X2APIC_PPRI 0x00a /* Processor prio. (RO) */ 993 #define MSR_X2APIC_EOI 0x00b /* End Int. (W) */ 994 #define MSR_X2APIC_LDR 0x00d /* Logical dest. (RO) */ 995 #define MSR_X2APIC_SVR 0x00f /* Spurious intvec (RW) */ 996 #define MSR_X2APIC_ISR 0x010 /* In-Service Status (RO) */ 997 #define MSR_X2APIC_TMR 0x018 /* Trigger Mode (RO) */ 998 #define MSR_X2APIC_IRR 0x020 /* Interrupt Req (RO) */ 999 #define MSR_X2APIC_ESR 0x028 /* Err status. (RW) */ 1000 #define MSR_X2APIC_LVT_CMCI 0x02f /* LVT CMCI (RW) */ 1001 #define MSR_X2APIC_ICRLO 0x030 /* Int. cmd. (RW64) */ 1002 #define MSR_X2APIC_LVTT 0x032 /* Loc.vec.(timer) (RW) */ 1003 #define MSR_X2APIC_TMINT 0x033 /* Loc.vec (Thermal) (RW) */ 1004 #define MSR_X2APIC_PCINT 0x034 /* Loc.vec (Perf Mon) (RW) */ 1005 #define MSR_X2APIC_LVINT0 0x035 /* Loc.vec (LINT0) (RW) */ 1006 #define MSR_X2APIC_LVINT1 0x036 /* Loc.vec (LINT1) (RW) */ 1007 #define MSR_X2APIC_LVERR 0x037 /* Loc.vec (ERROR) (RW) */ 1008 #define MSR_X2APIC_ICR_TIMER 0x038 /* Initial count (RW) */ 1009 #define MSR_X2APIC_CCR_TIMER 0x039 /* Current count (RO) */ 1010 #define MSR_X2APIC_DCR_TIMER 0x03e /* Divisor config (RW) */ 1011 #define MSR_X2APIC_SELF_IPI 0x03f /* SELF IPI (W) */ 1012 1013 /* 1014 * VIA "Nehemiah" MSRs 1015 */ 1016 #define MSR_VIA_RNG 0x0000110b 1017 #define MSR_VIA_RNG_ENABLE 0x00000040 1018 #define MSR_VIA_RNG_NOISE_MASK 0x00000300 1019 #define MSR_VIA_RNG_NOISE_A 0x00000000 1020 #define MSR_VIA_RNG_NOISE_B 0x00000100 1021 #define MSR_VIA_RNG_2NOISE 0x00000300 1022 #define MSR_VIA_ACE 0x00001107 1023 #define VIA_ACE_ALTINST 0x00000001 1024 #define VIA_ACE_ECX8 0x00000002 1025 #define VIA_ACE_ENABLE 0x10000000 1026 1027 /* 1028 * VIA "Eden" MSRs 1029 */ 1030 #define MSR_VIA_FCR MSR_VIA_ACE 1031 1032 /* 1033 * AMD K6/K7 MSRs. 1034 */ 1035 #define MSR_K6_UWCCR 0xc0000085 1036 #define MSR_K7_EVNTSEL0 0xc0010000 1037 #define MSR_K7_EVNTSEL1 0xc0010001 1038 #define MSR_K7_EVNTSEL2 0xc0010002 1039 #define MSR_K7_EVNTSEL3 0xc0010003 1040 #define MSR_K7_PERFCTR0 0xc0010004 1041 #define MSR_K7_PERFCTR1 0xc0010005 1042 #define MSR_K7_PERFCTR2 0xc0010006 1043 #define MSR_K7_PERFCTR3 0xc0010007 1044 1045 /* 1046 * AMD K8 (Opteron) MSRs. 1047 */ 1048 #define MSR_SYSCFG 0xc0010010 1049 1050 #define MSR_EFER 0xc0000080 /* Extended feature enable */ 1051 #define EFER_SCE 0x00000001 /* SYSCALL extension */ 1052 #define EFER_LME 0x00000100 /* Long Mode Enable */ 1053 #define EFER_LMA 0x00000400 /* Long Mode Active */ 1054 #define EFER_NXE 0x00000800 /* No-Execute Enabled */ 1055 #define EFER_SVME 0x00001000 /* Secure Virtual Machine En. */ 1056 #define EFER_LMSLE 0x00002000 /* Long Mode Segment Limit E. */ 1057 #define EFER_FFXSR 0x00004000 /* Fast FXSAVE/FXRSTOR En. */ 1058 #define EFER_TCE 0x00008000 /* Translation Cache Ext. */ 1059 1060 #define MSR_STAR 0xc0000081 /* 32 bit syscall gate addr */ 1061 #define MSR_LSTAR 0xc0000082 /* 64 bit syscall gate addr */ 1062 #define MSR_CSTAR 0xc0000083 /* compat syscall gate addr */ 1063 #define MSR_SFMASK 0xc0000084 /* flags to clear on syscall */ 1064 1065 #define MSR_FSBASE 0xc0000100 /* 64bit offset for fs: */ 1066 #define MSR_GSBASE 0xc0000101 /* 64bit offset for gs: */ 1067 #define MSR_KERNELGSBASE 0xc0000102 /* storage for swapgs ins */ 1068 1069 #define MSR_VMCR 0xc0010114 /* Virtual Machine Control Register */ 1070 #define VMCR_DPD 0x00000001 /* Debug port disable */ 1071 #define VMCR_RINIT 0x00000002 /* intercept init */ 1072 #define VMCR_DISA20 0x00000004 /* Disable A20 masking */ 1073 #define VMCR_LOCK 0x00000008 /* SVM Lock */ 1074 #define VMCR_SVMED 0x00000010 /* SVME Disable */ 1075 #define MSR_SVMLOCK 0xc0010118 /* SVM Lock key */ 1076 1077 /* 1078 * These require a 'passcode' for access. See cpufunc.h. 1079 */ 1080 #define MSR_HWCR 0xc0010015 1081 #define HWCR_TLBCACHEDIS 0x00000008 1082 #define HWCR_FFDIS 0x00000040 1083 1084 #define MSR_NB_CFG 0xc001001f 1085 #define NB_CFG_DISIOREQLOCK 0x0000000000000008ULL 1086 #define NB_CFG_DISDATMSK 0x0000001000000000ULL 1087 #define NB_CFG_INITAPICCPUIDLO (1ULL << 54) 1088 1089 #define MSR_LS_CFG 0xc0011020 1090 #define LS_CFG_ERRATA_1033 __BIT(4) 1091 #define LS_CFG_ERRATA_793 __BIT(15) 1092 #define LS_CFG_ERRATA_1095 __BIT(57) 1093 #define LS_CFG_DIS_LS2_SQUISH 0x02000000 1094 #define LS_CFG_DIS_SSB_F15H 0x0040000000000000ULL 1095 #define LS_CFG_DIS_SSB_F16H 0x0000000200000000ULL 1096 #define LS_CFG_DIS_SSB_F17H 0x0000000000000400ULL 1097 1098 #define MSR_IC_CFG 0xc0011021 1099 #define IC_CFG_DIS_SEQ_PREFETCH 0x00000800 1100 #define IC_CFG_DIS_IND 0x00004000 1101 #define IC_CFG_ERRATA_776 __BIT(26) 1102 1103 #define MSR_DC_CFG 0xc0011022 1104 #define DC_CFG_DIS_CNV_WC_SSO 0x00000008 1105 #define DC_CFG_DIS_SMC_CHK_BUF 0x00000400 1106 #define DC_CFG_ERRATA_261 0x01000000 1107 1108 #define MSR_BU_CFG 0xc0011023 1109 #define BU_CFG_ERRATA_298 0x0000000000000002ULL 1110 #define BU_CFG_ERRATA_254 0x0000000000200000ULL 1111 #define BU_CFG_ERRATA_309 0x0000000000800000ULL 1112 #define BU_CFG_THRL2IDXCMPDIS 0x0000080000000000ULL 1113 #define BU_CFG_WBPFSMCCHKDIS 0x0000200000000000ULL 1114 #define BU_CFG_WBENHWSBDIS 0x0001000000000000ULL 1115 1116 #define MSR_FP_CFG 0xc0011028 1117 #define FP_CFG_ERRATA_1049 __BIT(4) 1118 1119 #define MSR_DE_CFG 0xc0011029 1120 #define DE_CFG_ERRATA_721 0x00000001 1121 #define DE_CFG_ERRATA_1021 __BIT(13) 1122 1123 #define MSR_BU_CFG2 0xc001102a 1124 #define BU_CFG2_CWPLUS_DIS __BIT(24) 1125 1126 #define MSR_LS_CFG2 0xc001102d 1127 #define LS_CFG2_ERRATA_1091 __BIT(34) 1128 1129 /* AMD Family10h MSRs */ 1130 #define MSR_OSVW_ID_LENGTH 0xc0010140 1131 #define MSR_OSVW_STATUS 0xc0010141 1132 #define MSR_UCODE_AMD_PATCHLEVEL 0x0000008b 1133 #define MSR_UCODE_AMD_PATCHLOADER 0xc0010020 1134 1135 /* X86 MSRs */ 1136 #define MSR_RDTSCP_AUX 0xc0000103 1137 1138 /* 1139 * Constants related to MTRRs 1140 */ 1141 #define MTRR_N64K 8 /* numbers of fixed-size entries */ 1142 #define MTRR_N16K 16 1143 #define MTRR_N4K 64 1144 1145 /* 1146 * the following four 3-byte registers control the non-cacheable regions. 1147 * These registers must be written as three separate bytes. 1148 * 1149 * NCRx+0: A31-A24 of starting address 1150 * NCRx+1: A23-A16 of starting address 1151 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 1152 * 1153 * The non-cacheable region's starting address must be aligned to the 1154 * size indicated by the NCR_SIZE_xx field. 1155 */ 1156 #define NCR1 0xc4 1157 #define NCR2 0xc7 1158 #define NCR3 0xca 1159 #define NCR4 0xcd 1160 1161 #define NCR_SIZE_0K 0 1162 #define NCR_SIZE_4K 1 1163 #define NCR_SIZE_8K 2 1164 #define NCR_SIZE_16K 3 1165 #define NCR_SIZE_32K 4 1166 #define NCR_SIZE_64K 5 1167 #define NCR_SIZE_128K 6 1168 #define NCR_SIZE_256K 7 1169 #define NCR_SIZE_512K 8 1170 #define NCR_SIZE_1M 9 1171 #define NCR_SIZE_2M 10 1172 #define NCR_SIZE_4M 11 1173 #define NCR_SIZE_8M 12 1174 #define NCR_SIZE_16M 13 1175 #define NCR_SIZE_32M 14 1176 #define NCR_SIZE_4G 15 1177
Indexes created Mon Sep 29 21:09:56 GMT 2025