specialreg.h revision 1.186
1 /* $NetBSD: specialreg.h,v 1.186 2022/01/15 10:59:40 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2014-2020 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * Copyright (c) 1991 The Regents of the University of California. 31 * All rights reserved. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 1. Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * 2. Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in the 40 * documentation and/or other materials provided with the distribution. 41 * 3. Neither the name of the University nor the names of its contributors 42 * may be used to endorse or promote products derived from this software 43 * without specific prior written permission. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 * 57 * @(#)specialreg.h 7.1 (Berkeley) 5/9/91 58 */ 59 60 /* 61 * CR0 62 */ 63 #define CR0_PE 0x00000001 /* Protected mode Enable */ 64 #define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */ 65 #define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */ 66 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 67 #define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */ 68 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 69 #define CR0_WP 0x00010000 /* Write Protect (honor PTE_W in all modes) */ 70 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 71 #define CR0_NW 0x20000000 /* Not Write-through */ 72 #define CR0_CD 0x40000000 /* Cache Disable */ 73 #define CR0_PG 0x80000000 /* PaGing enable */ 74 75 /* 76 * Cyrix 486 DLC special registers, accessible as IO ports 77 */ 78 #define CCR0 0xc0 /* configuration control register 0 */ 79 #define CCR0_NC0 0x01 /* first 64K of each 1M memory region is non-cacheable */ 80 #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 81 #define CCR0_A20M 0x04 /* enables A20M# input pin */ 82 #define CCR0_KEN 0x08 /* enables KEN# input pin */ 83 #define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */ 84 #define CCR0_BARB 0x20 /* flushes internal cache when entering hold state */ 85 #define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */ 86 #define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */ 87 #define CCR1 0xc1 /* configuration control register 1 */ 88 #define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */ 89 90 /* 91 * CR3 92 */ 93 #define CR3_PCID __BITS(11,0) 94 #define CR3_PA __BITS(62,12) 95 #define CR3_NO_TLB_FLUSH __BIT(63) 96 97 /* 98 * CR4 99 */ 100 #define CR4_VME 0x00000001 /* Virtual 8086 mode extension enable */ 101 #define CR4_PVI 0x00000002 /* Protected mode virtual interrupt enable */ 102 #define CR4_TSD 0x00000004 /* Restrict RDTSC instruction to cpl 0 */ 103 #define CR4_DE 0x00000008 /* Debugging extension */ 104 #define CR4_PSE 0x00000010 /* Large (4MB) page size enable */ 105 #define CR4_PAE 0x00000020 /* Physical address extension enable */ 106 #define CR4_MCE 0x00000040 /* Machine check enable */ 107 #define CR4_PGE 0x00000080 /* Page global enable */ 108 #define CR4_PCE 0x00000100 /* Enable RDPMC instruction for all cpls */ 109 #define CR4_OSFXSR 0x00000200 /* Enable fxsave/fxrestor and SSE */ 110 #define CR4_OSXMMEXCPT 0x00000400 /* Enable unmasked SSE exceptions */ 111 #define CR4_UMIP 0x00000800 /* User Mode Instruction Prevention */ 112 #define CR4_LA57 0x00001000 /* 57-bit linear addresses */ 113 #define CR4_VMXE 0x00002000 /* Enable VMX operations */ 114 #define CR4_SMXE 0x00004000 /* Enable SMX operations */ 115 #define CR4_FSGSBASE 0x00010000 /* Enable *FSBASE and *GSBASE instructions */ 116 #define CR4_PCIDE 0x00020000 /* Enable Process Context IDentifiers */ 117 #define CR4_OSXSAVE 0x00040000 /* Enable xsave and xrestore */ 118 #define CR4_SMEP 0x00100000 /* Enable SMEP support */ 119 #define CR4_SMAP 0x00200000 /* Enable SMAP support */ 120 #define CR4_PKE 0x00400000 /* Enable Protection Keys for user pages */ 121 #define CR4_CET 0x00800000 /* Enable CET */ 122 #define CR4_PKS 0x01000000 /* Enable Protection Keys for kern pages */ 123 124 /* 125 * Extended Control Register XCR0 126 */ 127 #define XCR0_X87 0x00000001 /* x87 FPU/MMX state */ 128 #define XCR0_SSE 0x00000002 /* SSE state */ 129 #define XCR0_YMM_Hi128 0x00000004 /* AVX-256 (ymmn registers) */ 130 #define XCR0_BNDREGS 0x00000008 /* Memory protection ext bounds */ 131 #define XCR0_BNDCSR 0x00000010 /* Memory protection ext state */ 132 #define XCR0_Opmask 0x00000020 /* AVX-512 Opmask */ 133 #define XCR0_ZMM_Hi256 0x00000040 /* AVX-512 upper 256 bits low regs */ 134 #define XCR0_Hi16_ZMM 0x00000080 /* AVX-512 512 bits upper registers */ 135 #define XCR0_PT 0x00000100 /* Processor Trace state */ 136 #define XCR0_PKRU 0x00000200 /* Protection Key state */ 137 #define XCR0_CET_U 0x00000800 /* User CET state */ 138 #define XCR0_CET_S 0x00001000 /* Kern CET state */ 139 #define XCR0_HDC 0x00002000 /* Hardware Duty Cycle state */ 140 #define XCR0_LBR 0x00008000 /* Last Branch Record */ 141 #define XCR0_HWP 0x00010000 /* Hardware P-states */ 142 143 #define XCR0_FLAGS1 "\20" \ 144 "\1" "x87" "\2" "SSE" "\3" "AVX" "\4" "BNDREGS" \ 145 "\5" "BNDCSR" "\6" "Opmask" "\7" "ZMM_Hi256" "\10" "Hi16_ZMM" \ 146 "\11" "PT" "\12" "PKRU" "\14" "CET_U" \ 147 "\15" "CET_S" "\16" "HDC" "\20" "LBR" \ 148 "\21" "HWP" 149 150 /* 151 * Known FPU bits, only these get enabled. The save area is sized for all the 152 * fields below. 153 */ 154 #define XCR0_FPU (XCR0_X87 | XCR0_SSE | XCR0_YMM_Hi128 | \ 155 XCR0_Opmask | XCR0_ZMM_Hi256 | XCR0_Hi16_ZMM) 156 157 /* 158 * XSAVE component indices, internal to NetBSD. 159 */ 160 #define XSAVE_X87 0 161 #define XSAVE_SSE 1 162 #define XSAVE_YMM_Hi128 2 163 #define XSAVE_BNDREGS 3 164 #define XSAVE_BNDCSR 4 165 #define XSAVE_Opmask 5 166 #define XSAVE_ZMM_Hi256 6 167 #define XSAVE_Hi16_ZMM 7 168 169 /* 170 * Highest XSAVE component enabled by XCR0_FPU. 171 */ 172 #define XSAVE_MAX_COMPONENT XSAVE_Hi16_ZMM 173 174 /* 175 * "features" bits. 176 * CPUID Fn00000001 177 */ 178 /* %edx */ 179 #define CPUID_FPU 0x00000001 /* processor has an FPU? */ 180 #define CPUID_VME 0x00000002 /* has virtual mode (%cr4's VME/PVI) */ 181 #define CPUID_DE 0x00000004 /* has debugging extension */ 182 #define CPUID_PSE 0x00000008 /* has 4MB page size extension */ 183 #define CPUID_TSC 0x00000010 /* has time stamp counter */ 184 #define CPUID_MSR 0x00000020 /* has model specific registers */ 185 #define CPUID_PAE 0x00000040 /* has physical address extension */ 186 #define CPUID_MCE 0x00000080 /* has machine check exception */ 187 #define CPUID_CX8 0x00000100 /* has CMPXCHG8B instruction */ 188 #define CPUID_APIC 0x00000200 /* has enabled APIC */ 189 #define CPUID_SEP 0x00000800 /* has SYSENTER/SYSEXIT extension */ 190 #define CPUID_MTRR 0x00001000 /* has memory type range register */ 191 #define CPUID_PGE 0x00002000 /* has page global extension */ 192 #define CPUID_MCA 0x00004000 /* has machine check architecture */ 193 #define CPUID_CMOV 0x00008000 /* has CMOVcc instruction */ 194 #define CPUID_PAT 0x00010000 /* Page Attribute Table */ 195 #define CPUID_PSE36 0x00020000 /* 36-bit PSE */ 196 #define CPUID_PSN 0x00040000 /* Processor Serial Number */ 197 #define CPUID_CLFSH 0x00080000 /* CLFLUSH instruction supported */ 198 #define CPUID_DS 0x00200000 /* Debug Store */ 199 #define CPUID_ACPI 0x00400000 /* ACPI performance modulation regs */ 200 #define CPUID_MMX 0x00800000 /* MMX supported */ 201 #define CPUID_FXSR 0x01000000 /* Fast FP/MMX Save/Restore */ 202 #define CPUID_SSE 0x02000000 /* Streaming SIMD Extensions */ 203 #define CPUID_SSE2 0x04000000 /* Streaming SIMD Extensions #2 */ 204 #define CPUID_SS 0x08000000 /* Self-Snoop */ 205 #define CPUID_HTT 0x10000000 /* Hyper-Threading Technology */ 206 #define CPUID_TM 0x20000000 /* Thermal Monitor (TCC) */ 207 #define CPUID_PBE 0x80000000 /* Pending Break Enable */ 208 209 #define CPUID_FLAGS1 "\20" \ 210 "\1" "FPU" "\2" "VME" "\3" "DE" "\4" "PSE" \ 211 "\5" "TSC" "\6" "MSR" "\7" "PAE" "\10" "MCE" \ 212 "\11" "CX8" "\12" "APIC" "\13" "B10" "\14" "SEP" \ 213 "\15" "MTRR" "\16" "PGE" "\17" "MCA" "\20" "CMOV" \ 214 "\21" "PAT" "\22" "PSE36" "\23" "PN" "\24" "CLFSH" \ 215 "\25" "B20" "\26" "DS" "\27" "ACPI" "\30" "MMX" \ 216 "\31" "FXSR" "\32" "SSE" "\33" "SSE2" "\34" "SS" \ 217 "\35" "HTT" "\36" "TM" "\37" "IA64" "\40" "PBE" 218 219 /* Blacklists of CPUID flags - used to mask certain features */ 220 #ifdef XENPV 221 #define CPUID_FEAT_BLACKLIST (CPUID_PGE|CPUID_PSE|CPUID_MTRR) 222 #else 223 #define CPUID_FEAT_BLACKLIST 0 224 #endif 225 226 /* %ecx */ 227 #define CPUID2_SSE3 0x00000001 /* Streaming SIMD Extensions 3 */ 228 #define CPUID2_PCLMULQDQ 0x00000002 /* PCLMULQDQ instructions */ 229 #define CPUID2_DTES64 0x00000004 /* 64-bit Debug Trace */ 230 #define CPUID2_MONITOR 0x00000008 /* MONITOR/MWAIT instructions */ 231 #define CPUID2_DS_CPL 0x00000010 /* CPL Qualified Debug Store */ 232 #define CPUID2_VMX 0x00000020 /* Virtual Machine eXtensions */ 233 #define CPUID2_SMX 0x00000040 /* Safer Mode eXtensions */ 234 #define CPUID2_EST 0x00000080 /* Enhanced SpeedStep Technology */ 235 #define CPUID2_TM2 0x00000100 /* Thermal Monitor 2 */ 236 #define CPUID2_SSSE3 0x00000200 /* Supplemental SSE3 */ 237 #define CPUID2_CNXTID 0x00000400 /* Context ID */ 238 #define CPUID2_SDBG 0x00000800 /* Silicon Debug */ 239 #define CPUID2_FMA 0x00001000 /* Fused Multiply Add */ 240 #define CPUID2_CX16 0x00002000 /* CMPXCHG16B instruction */ 241 #define CPUID2_XTPR 0x00004000 /* Task Priority Messages disabled? */ 242 #define CPUID2_PDCM 0x00008000 /* Perf/Debug Capability MSR */ 243 /* bit 16 unused 0x00010000 */ 244 #define CPUID2_PCID 0x00020000 /* Process Context ID */ 245 #define CPUID2_DCA 0x00040000 /* Direct Cache Access */ 246 #define CPUID2_SSE41 0x00080000 /* Streaming SIMD Extensions 4.1 */ 247 #define CPUID2_SSE42 0x00100000 /* Streaming SIMD Extensions 4.2 */ 248 #define CPUID2_X2APIC 0x00200000 /* xAPIC Extensions */ 249 #define CPUID2_MOVBE 0x00400000 /* MOVBE (move after byteswap) */ 250 #define CPUID2_POPCNT 0x00800000 /* POPCNT instruction available */ 251 #define CPUID2_DEADLINE 0x01000000 /* APIC Timer supports TSC Deadline */ 252 #define CPUID2_AESNI 0x02000000 /* AES instructions */ 253 #define CPUID2_XSAVE 0x04000000 /* XSAVE instructions */ 254 #define CPUID2_OSXSAVE 0x08000000 /* XGETBV/XSETBV instructions */ 255 #define CPUID2_AVX 0x10000000 /* AVX instructions */ 256 #define CPUID2_F16C 0x20000000 /* half precision conversion */ 257 #define CPUID2_RDRAND 0x40000000 /* RDRAND (hardware random number) */ 258 #define CPUID2_RAZ 0x80000000 /* RAZ. Indicates guest state. */ 259 260 #define CPUID2_FLAGS1 "\20" \ 261 "\1" "SSE3" "\2" "PCLMULQDQ" "\3" "DTES64" "\4" "MONITOR" \ 262 "\5" "DS-CPL" "\6" "VMX" "\7" "SMX" "\10" "EST" \ 263 "\11" "TM2" "\12" "SSSE3" "\13" "CID" "\14" "SDBG" \ 264 "\15" "FMA" "\16" "CX16" "\17" "xTPR" "\20" "PDCM" \ 265 "\21" "B16" "\22" "PCID" "\23" "DCA" "\24" "SSE41" \ 266 "\25" "SSE42" "\26" "X2APIC" "\27" "MOVBE" "\30" "POPCNT" \ 267 "\31" "DEADLINE" "\32" "AES" "\33" "XSAVE" "\34" "OSXSAVE" \ 268 "\35" "AVX" "\36" "F16C" "\37" "RDRAND" "\40" "RAZ" 269 270 /* %eax */ 271 #define CPUID_TO_BASEFAMILY(cpuid) (((cpuid) >> 8) & 0xf) 272 #define CPUID_TO_BASEMODEL(cpuid) (((cpuid) >> 4) & 0xf) 273 #define CPUID_TO_STEPPING(cpuid) ((cpuid) & 0xf) 274 275 /* 276 * The Extended family bits should only be inspected when CPUID_TO_BASEFAMILY() 277 * returns 15. They are use to encode family value 16 to 270 (add 15). 278 * The Extended model bits are the high 4 bits of the model. 279 * They are only valid for family >= 15 or family 6 (intel, but all amd 280 * family 6 are documented to return zero bits for them). 281 */ 282 #define CPUID_TO_EXTFAMILY(cpuid) (((cpuid) >> 20) & 0xff) 283 #define CPUID_TO_EXTMODEL(cpuid) (((cpuid) >> 16) & 0xf) 284 285 /* The macros for the Display Family and the Display Model */ 286 #define CPUID_TO_FAMILY(cpuid) (CPUID_TO_BASEFAMILY(cpuid) \ 287 + ((CPUID_TO_BASEFAMILY(cpuid) != 0x0f) \ 288 ? 0 : CPUID_TO_EXTFAMILY(cpuid))) 289 #define CPUID_TO_MODEL(cpuid) (CPUID_TO_BASEMODEL(cpuid) \ 290 | ((CPUID_TO_BASEFAMILY(cpuid) != 0x0f) \ 291 && (CPUID_TO_BASEFAMILY(cpuid) != 0x06) \ 292 ? 0 : (CPUID_TO_EXTMODEL(cpuid) << 4))) 293 294 /* %ebx */ 295 #define CPUID_BRAND_INDEX __BITS(7,0) 296 #define CPUID_CLFLUSH_SIZE __BITS(15,8) 297 #define CPUID_HTT_CORES __BITS(23,16) 298 #define CPUID_LOCAL_APIC_ID __BITS(31,24) 299 300 /* 301 * Intel Deterministic Cache Parameter. 302 * CPUID Fn0000_0004 303 */ 304 305 /* %eax */ 306 #define CPUID_DCP_CACHETYPE __BITS(4, 0) /* Cache type */ 307 #define CPUID_DCP_CACHETYPE_N 0 /* NULL */ 308 #define CPUID_DCP_CACHETYPE_D 1 /* Data cache */ 309 #define CPUID_DCP_CACHETYPE_I 2 /* Instruction cache */ 310 #define CPUID_DCP_CACHETYPE_U 3 /* Unified cache */ 311 #define CPUID_DCP_CACHELEVEL __BITS(7, 5) /* Cache level (start at 1) */ 312 #define CPUID_DCP_SELFINITCL __BIT(8) /* Self initializing cachelvl*/ 313 #define CPUID_DCP_FULLASSOC __BIT(9) /* Full associative */ 314 #define CPUID_DCP_SHAREING __BITS(25, 14) /* shareing */ 315 #define CPUID_DCP_CORE_P_PKG __BITS(31, 26) /* Cores/package */ 316 317 /* %ebx */ 318 #define CPUID_DCP_LINESIZE __BITS(11, 0) /* System coherency linesize */ 319 #define CPUID_DCP_PARTITIONS __BITS(21, 12) /* Physical line partitions */ 320 #define CPUID_DCP_WAYS __BITS(31, 22) /* Ways of associativity */ 321 322 /* %ecx: Number of sets */ 323 324 /* %edx */ 325 #define CPUID_DCP_INVALIDATE __BIT(0) /* WB invalidate/invalidate */ 326 #define CPUID_DCP_INCLUSIVE __BIT(1) /* Cache inclusiveness */ 327 #define CPUID_DCP_COMPLEX __BIT(2) /* Complex cache indexing */ 328 329 /* 330 * Intel/AMD MONITOR/MWAIT. 331 * CPUID Fn0000_0005 332 */ 333 /* %eax */ 334 #define CPUID_MON_MINSIZE __BITS(15, 0) /* Smallest monitor-line size */ 335 /* %ebx */ 336 #define CPUID_MON_MAXSIZE __BITS(15, 0) /* Largest monitor-line size */ 337 /* %ecx */ 338 #define CPUID_MON_EMX __BIT(0) /* MONITOR/MWAIT Extensions */ 339 #define CPUID_MON_IBE __BIT(1) /* Interrupt as Break Event */ 340 341 #define CPUID_MON_FLAGS "\20" \ 342 "\1" "EMX" "\2" "IBE" 343 344 /* %edx: number of substates for specific C-state */ 345 #define CPUID_MON_SUBSTATE(edx, cstate) (((edx) >> (cstate * 4)) & 0x0000000f) 346 347 /* 348 * Intel/AMD Digital Thermal Sensor and Power Management. 349 * CPUID Fn0000_0006 350 */ 351 /* %eax */ 352 #define CPUID_DSPM_DTS __BIT(0) /* Digital Thermal Sensor */ 353 #define CPUID_DSPM_IDA __BIT(1) /* Intel Dynamic Acceleration */ 354 #define CPUID_DSPM_ARAT __BIT(2) /* Always Running APIC Timer */ 355 #define CPUID_DSPM_PLN __BIT(4) /* Power Limit Notification */ 356 #define CPUID_DSPM_ECMD __BIT(5) /* Clock Modulation Extension */ 357 #define CPUID_DSPM_PTM __BIT(6) /* Package Level Thermal Management */ 358 #define CPUID_DSPM_HWP __BIT(7) /* HWP */ 359 #define CPUID_DSPM_HWP_NOTIFY __BIT(8) /* HWP Notification */ 360 #define CPUID_DSPM_HWP_ACTWIN __BIT(9) /* HWP Activity Window */ 361 #define CPUID_DSPM_HWP_EPP __BIT(10) /* HWP Energy Performance Preference */ 362 #define CPUID_DSPM_HWP_PLR __BIT(11) /* HWP Package Level Request */ 363 #define CPUID_DSPM_HDC __BIT(13) /* Hardware Duty Cycling */ 364 #define CPUID_DSPM_TBMT3 __BIT(14) /* Turbo Boost Max Technology 3.0 */ 365 #define CPUID_DSPM_HWP_CAP __BIT(15) /* HWP Capabilities */ 366 #define CPUID_DSPM_HWP_PECI __BIT(16) /* HWP PECI override */ 367 #define CPUID_DSPM_HWP_FLEX __BIT(17) /* Flexible HWP */ 368 #define CPUID_DSPM_HWP_FAST __BIT(18) /* Fast access for IA32_HWP_REQUEST */ 369 #define CPUID_DSPM_HW_FEEDBACK __BIT(19) /* HW_FEEDBACK*, IA32_PACKAGE_TERM* */ 370 #define CPUID_DSPM_HWP_IGNIDL __BIT(20) /* Ignore Idle Logical Processor HWP */ 371 #define CPUID_DSPM_TD __BIT(23) /* Thread Director */ 372 373 #define CPUID_DSPM_FLAGS "\20" \ 374 "\1" "DTS" "\2" "IDA" "\3" "ARAT" \ 375 "\5" "PLN" "\6" "ECMD" "\7" "PTM" "\10" "HWP" \ 376 "\11" "HWP_NOTIFY" "\12" "HWP_ACTWIN" "\13" "HWP_EPP" "\14" "HWP_PLR" \ 377 "\16" "HDC" "\17" "TBM3" "\20" "HWP_CAP" \ 378 "\21" "HWP_PECI" "\22" "HWP_FLEX" "\23" "HWP_FAST" "\24HW_FEEDBACK" \ 379 "\25" "HWP_IGNIDL" "\30" "TD" 380 381 /* %ecx */ 382 #define CPUID_DSPM_HWF __BIT(0) /* MSR_APERF/MSR_MPERF available */ 383 #define CPUID_DSPM_EPB __BIT(3) /* Energy Performance Bias */ 384 #define CPUID_DSPM_NTDC __BITS(15, 8) /* Number of Thread Director Classes */ 385 386 #define CPUID_DSPM_FLAGS1 "\177\20" \ 387 "b\0HWF\0" "b\3EPB\0" \ 388 "f\10\10NTDC\0" 389 390 /* 391 * Intel/AMD Structured Extended Feature. 392 * CPUID Fn0000_0007 393 * %ecx == 0: Subleaf 0 394 * %eax: The Maximum input value for supported subleaf. 395 * %ebx: Feature bits. 396 * %ecx: Feature bits. 397 * %edx: Feature bits. 398 * 399 * %ecx == 1: Structure Extendede Feature Enumeration Sub-leaf 400 * %eax: See below. 401 */ 402 403 /* %ecx = 0, %ebx */ 404 #define CPUID_SEF_FSGSBASE __BIT(0) /* {RD,WR}{FS,GS}BASE */ 405 #define CPUID_SEF_TSC_ADJUST __BIT(1) /* IA32_TSC_ADJUST MSR support */ 406 #define CPUID_SEF_SGX __BIT(2) /* Software Guard Extensions */ 407 #define CPUID_SEF_BMI1 __BIT(3) /* Advanced bit manipulation ext. 1st grp */ 408 #define CPUID_SEF_HLE __BIT(4) /* Hardware Lock Elision */ 409 #define CPUID_SEF_AVX2 __BIT(5) /* Advanced Vector Extensions 2 */ 410 #define CPUID_SEF_FDPEXONLY __BIT(6) /* x87FPU Data ptr updated only on x87exp */ 411 #define CPUID_SEF_SMEP __BIT(7) /* Supervisor-Mode Execution Prevention */ 412 #define CPUID_SEF_BMI2 __BIT(8) /* Advanced bit manipulation ext. 2nd grp */ 413 #define CPUID_SEF_ERMS __BIT(9) /* Enhanced REP MOVSB/STOSB */ 414 #define CPUID_SEF_INVPCID __BIT(10) /* INVPCID instruction */ 415 #define CPUID_SEF_RTM __BIT(11) /* Restricted Transactional Memory */ 416 #define CPUID_SEF_QM __BIT(12) /* Resource Director Technology Monitoring */ 417 #define CPUID_SEF_FPUCSDS __BIT(13) /* Deprecate FPU CS and FPU DS values */ 418 #define CPUID_SEF_MPX __BIT(14) /* Memory Protection Extensions */ 419 #define CPUID_SEF_PQE __BIT(15) /* Resource Director Technology Allocation */ 420 #define CPUID_SEF_AVX512F __BIT(16) /* AVX-512 Foundation */ 421 #define CPUID_SEF_AVX512DQ __BIT(17) /* AVX-512 Double/Quadword */ 422 #define CPUID_SEF_RDSEED __BIT(18) /* RDSEED instruction */ 423 #define CPUID_SEF_ADX __BIT(19) /* ADCX/ADOX instructions */ 424 #define CPUID_SEF_SMAP __BIT(20) /* Supervisor-Mode Access Prevention */ 425 #define CPUID_SEF_AVX512_IFMA __BIT(21) /* AVX-512 Integer Fused Multiply Add */ 426 /* Bit 22 was PCOMMIT */ 427 #define CPUID_SEF_CLFLUSHOPT __BIT(23) /* Cache Line FLUSH OPTimized */ 428 #define CPUID_SEF_CLWB __BIT(24) /* Cache Line Write Back */ 429 #define CPUID_SEF_PT __BIT(25) /* Processor Trace */ 430 #define CPUID_SEF_AVX512PF __BIT(26) /* AVX-512 PreFetch */ 431 #define CPUID_SEF_AVX512ER __BIT(27) /* AVX-512 Exponential and Reciprocal */ 432 #define CPUID_SEF_AVX512CD __BIT(28) /* AVX-512 Conflict Detection */ 433 #define CPUID_SEF_SHA __BIT(29) /* SHA Extensions */ 434 #define CPUID_SEF_AVX512BW __BIT(30) /* AVX-512 Byte and Word */ 435 #define CPUID_SEF_AVX512VL __BIT(31) /* AVX-512 Vector Length */ 436 437 #define CPUID_SEF_FLAGS "\20" \ 438 "\1" "FSGSBASE" "\2" "TSCADJUST" "\3" "SGX" "\4" "BMI1" \ 439 "\5" "HLE" "\6" "AVX2" "\7" "FDPEXONLY" "\10" "SMEP" \ 440 "\11" "BMI2" "\12" "ERMS" "\13" "INVPCID" "\14" "RTM" \ 441 "\15" "QM" "\16" "FPUCSDS" "\17" "MPX" "\20" "PQE" \ 442 "\21" "AVX512F" "\22" "AVX512DQ" "\23" "RDSEED" "\24" "ADX" \ 443 "\25" "SMAP" "\26" "AVX512_IFMA" "\30" "CLFLUSHOPT" \ 444 "\31" "CLWB" "\32" "PT" "\33" "AVX512PF" "\34" "AVX512ER" \ 445 "\35" "AVX512CD""\36" "SHA" "\37" "AVX512BW" "\40" "AVX512VL" 446 447 /* %ecx = 0, %ecx */ 448 #define CPUID_SEF_PREFETCHWT1 __BIT(0) /* PREFETCHWT1 instruction */ 449 #define CPUID_SEF_AVX512_VBMI __BIT(1) /* AVX-512 Vector Byte Manipulation */ 450 #define CPUID_SEF_UMIP __BIT(2) /* User-Mode Instruction prevention */ 451 #define CPUID_SEF_PKU __BIT(3) /* Protection Keys for User-mode pages */ 452 #define CPUID_SEF_OSPKE __BIT(4) /* OS has set CR4.PKE to ena. protec. keys */ 453 #define CPUID_SEF_WAITPKG __BIT(5) /* TPAUSE,UMONITOR,UMWAIT */ 454 #define CPUID_SEF_AVX512_VBMI2 __BIT(6) /* AVX-512 Vector Byte Manipulation 2 */ 455 #define CPUID_SEF_CET_SS __BIT(7) /* CET Shadow Stack */ 456 #define CPUID_SEF_GFNI __BIT(8) /* Galois Field instructions */ 457 #define CPUID_SEF_VAES __BIT(9) /* Vector AES instruction set */ 458 #define CPUID_SEF_VPCLMULQDQ __BIT(10) /* CLMUL instruction set */ 459 #define CPUID_SEF_AVX512_VNNI __BIT(11) /* Vector Neural Network Instruction */ 460 #define CPUID_SEF_AVX512_BITALG __BIT(12) /* BITALG instructions */ 461 #define CPUID_SEF_TME_EN __BIT(13) /* Total Memory Encryption */ 462 #define CPUID_SEF_AVX512_VPOPCNTDQ __BIT(14) /* Vector Population Count D/Q */ 463 #define CPUID_SEF_LA57 __BIT(16) /* 57bit linear addr & 5LVL paging */ 464 #define CPUID_SEF_MAWAU __BITS(21, 17) /* MAWAU for BND{LD,ST}X */ 465 #define CPUID_SEF_RDPID __BIT(22) /* RDPID and IA32_TSC_AUX */ 466 #define CPUID_SEF_KL __BIT(23) /* Key Locker */ 467 #define CPUID_SEF_CLDEMOTE __BIT(25) /* Cache line demote */ 468 #define CPUID_SEF_MOVDIRI __BIT(27) /* MOVDIRI instruction */ 469 #define CPUID_SEF_MOVDIR64B __BIT(28) /* MOVDIR64B instruction */ 470 #define CPUID_SEF_SGXLC __BIT(30) /* SGX Launch Configuration */ 471 #define CPUID_SEF_PKS __BIT(31) /* Protection Keys for kern-mode pages */ 472 473 #define CPUID_SEF_FLAGS1 "\177\20" \ 474 "b\0PREFETCHWT1\0" "b\1AVX512_VBMI\0" "b\2UMIP\0" "b\3PKU\0" \ 475 "b\4OSPKE\0" "b\5WAITPKG\0" "b\6AVX512_VBMI2\0" "b\7CET_SS\0" \ 476 "b\10GFNI\0" "b\11VAES\0" "b\12VPCLMULQDQ\0" "b\13AVX512_VNNI\0"\ 477 "b\14AVX512_BITALG\0" "b\15TME_EN\0" "b\16AVX512_VPOPCNTDQ\0" \ 478 "b\20LA57\0" \ 479 "f\21\5MAWAU\0" "b\26RDPID\0" "b\27KL\0" \ 480 "b\31CLDEMOTE\0" "b\33MOVDIRI\0" \ 481 "b\34MOVDIR64B\0" "b\36SGXLC\0" "b\37PKS\0" 482 483 /* %ecx = 0, %edx */ 484 #define CPUID_SEF_AVX512_4VNNIW __BIT(2) /* AVX512 4-reg Neural Network ins */ 485 #define CPUID_SEF_AVX512_4FMAPS __BIT(3) /* AVX512 4-reg Mult Accum Single precision */ 486 #define CPUID_SEF_FSREP_MOV __BIT(4) /* Fast Short REP MOVE */ 487 #define CPUID_SEF_AVX512_VP2INTERSECT __BIT(8) /* AVX512 VP2INTERSECT */ 488 #define CPUID_SEF_SRBDS_CTRL __BIT(9) /* IA32_MCU_OPT_CTRL */ 489 #define CPUID_SEF_MD_CLEAR __BIT(10) /* VERW clears CPU buffers */ 490 #define CPUID_SEF_TSX_FORCE_ABORT __BIT(13) /* MSR_TSX_FORCE_ABORT bit 0 */ 491 #define CPUID_SEF_SERIALIZE __BIT(14) /* SERIALIZE instruction */ 492 #define CPUID_SEF_HYBRID __BIT(15) /* Hybrid part */ 493 #define CPUID_SEF_TSXLDTRK __BIT(16) /* TSX suspend load addr tracking */ 494 #define CPUID_SEF_PCONFIG __BIT(18) /* Platform CONFIGuration */ 495 #define CPUID_SEF_ARCH_LBR __BIT(19) /* Architectural LBR */ 496 #define CPUID_SEF_CET_IBT __BIT(20) /* CET Indirect Branch Tracking */ 497 #define CPUID_SEF_IBRS __BIT(26) /* IBRS / IBPB Speculation Control */ 498 #define CPUID_SEF_STIBP __BIT(27) /* STIBP Speculation Control */ 499 #define CPUID_SEF_L1D_FLUSH __BIT(28) /* IA32_FLUSH_CMD MSR */ 500 #define CPUID_SEF_ARCH_CAP __BIT(29) /* IA32_ARCH_CAPABILITIES */ 501 #define CPUID_SEF_CORE_CAP __BIT(30) /* IA32_CORE_CAPABILITIES */ 502 #define CPUID_SEF_SSBD __BIT(31) /* Speculative Store Bypass Disable */ 503 504 #define CPUID_SEF_FLAGS2 "\20" \ 505 "\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS" \ 506 "\5" "FSREP_MOV" \ 507 "\11VP2INTERSECT" "\12SRBDS_CTRL" "\13MD_CLEAR" \ 508 "\16TSX_FORCE_ABORT" "\17SERIALIZE" "\20HYBRID" \ 509 "\21" "TSXLDTRK" "\23" "PCONFIG" "\24" "ARCH_LBR" \ 510 "\25" "CET_IBT" \ 511 "\33" "IBRS" "\34" "STIBP" \ 512 "\35" "L1D_FLUSH" "\36" "ARCH_CAP" "\37CORE_CAP" "\40" "SSBD" 513 514 /* %ecx = 1, %eax */ 515 #define CPUID_SEF_AVXVNNI __BIT(4) /* AVX version of VNNI */ 516 #define CPUID_SEF_AVX512_BF16 __BIT(5) 517 #define CPUID_SEF_FZLRMS __BIT(10) /* fast zero-length REP MOVSB */ 518 #define CPUID_SEF_FSRSB __BIT(11) /* fast short REP STOSB */ 519 #define CPUID_SEF_FSRCS __BIT(12) /* fast short REP CMPSB, REP SCASB */ 520 #define CPUID_SEF_HRESET __BIT(22) /* HREST & IA32_HRESET_ENABLE MSR */ 521 #define CPUID_SEF_LAM __BIT(26) /* Linear Address Masking */ 522 523 #define CPUID_SEF1_FLAGS_A "\20" \ 524 "\5" "AVXVNNI" "\6" "AVX512_BF16" \ 525 "\13" "FZLRMS" "\14" "FSRSB" \ 526 "\15" "FSRCS" "\27" "HRESET" \ 527 "\31" "LAM" 528 529 /* %ecx = 1, %ebx */ 530 #define CPUID_SEF_PPIN __BIT(0) /* IA32_PPIN & IA32_PPIN_CTL MSRs */ 531 532 #define CPUID_SEF1_FLAGS_B "\20" \ 533 "\1" "PPIN" 534 535 /* 536 * Intel CPUID Architectural Performance Monitoring. 537 * CPUID Fn0000000a 538 * 539 * See also src/usr.sbin/tprof/arch/tprof_x86.c 540 */ 541 542 /* %eax */ 543 #define CPUID_PERF_VERSION __BITS(7, 0) /* Version ID */ 544 #define CPUID_PERF_NGPPC __BITS(15, 8) /* Num of G.P. perf counter */ 545 #define CPUID_PERF_NBWGPPC __BITS(23, 16) /* Bit width of G.P. perfcnt */ 546 #define CPUID_PERF_BVECLEN __BITS(31, 24) /* Length of EBX bit vector */ 547 548 #define CPUID_PERF_FLAGS0 "\177\20" \ 549 "f\0\10VERSION\0" "f\10\10GPCounter\0" \ 550 "f\20\10GPBitwidth\0" "f\30\10Vectorlen\0" 551 552 /* %ebx */ 553 #define CPUID_PERF_CORECYCL __BIT(0) /* No core cycle */ 554 #define CPUID_PERF_INSTRETRY __BIT(1) /* No instruction retried */ 555 #define CPUID_PERF_REFCYCL __BIT(2) /* No reference cycles */ 556 #define CPUID_PERF_LLCREF __BIT(3) /* No LLCache reference */ 557 #define CPUID_PERF_LLCMISS __BIT(4) /* No LLCache miss */ 558 #define CPUID_PERF_BRINSRETR __BIT(5) /* No branch inst. retried */ 559 #define CPUID_PERF_BRMISPRRETR __BIT(6) /* No branch mispredict retry */ 560 561 #define CPUID_PERF_FLAGS1 "\177\20" \ 562 "b\0CORECYCL\0" "b\1INSTRETRY\0" "b\2REFCYCL\0" "b\3LLCREF\0" \ 563 "b\4LLCMISS\0" "b\5BRINSRETR\0" "b\6BRMISPRRETR\0" 564 565 /* %edx */ 566 #define CPUID_PERF_NFFPC __BITS(4, 0) /* Num of fixed-funct perfcnt */ 567 #define CPUID_PERF_NBWFFPC __BITS(12, 5) /* Bit width of fixed-func pc */ 568 #define CPUID_PERF_ANYTHREADDEPR __BIT(15) /* Any Thread deprecation */ 569 570 #define CPUID_PERF_FLAGS3 "\177\20" \ 571 "f\0\5FixedFunc\0" "f\5\10FFBitwidth\0" "b\17ANYTHREADDEPR\0" 572 573 /* 574 * Intel CPUID Extended Topology Enumeration. 575 * CPUID Fn0000000b 576 * %ecx == level number 577 * %eax: See below. 578 * %ebx: Number of logical processors at this level. 579 * %ecx: See below. 580 * %edx: x2APIC ID of the current logical processor. 581 */ 582 /* %eax */ 583 #define CPUID_TOP_SHIFTNUM __BITS(4, 0) /* Topology ID shift value */ 584 /* %ecx */ 585 #define CPUID_TOP_LVLNUM __BITS(7, 0) /* Level number */ 586 #define CPUID_TOP_LVLTYPE __BITS(15, 8) /* Level type */ 587 #define CPUID_TOP_LVLTYPE_INVAL 0 /* Invalid */ 588 #define CPUID_TOP_LVLTYPE_SMT 1 /* SMT */ 589 #define CPUID_TOP_LVLTYPE_CORE 2 /* Core */ 590 591 /* 592 * Intel/AMD CPUID Processor extended state Enumeration. 593 * CPUID Fn0000000d 594 * 595 * %ecx == 0: supported features info: 596 * %eax: Valid bits of lower 32bits of XCR0 597 * %ebx: Maximum save area size for features enabled in XCR0 598 * %ecx: Maximum save area size for all cpu features 599 * %edx: Valid bits of upper 32bits of XCR0 600 * 601 * %ecx == 1: 602 * %eax: Bit 0 => xsaveopt instruction available (sandy bridge onwards) 603 * %ebx: Save area size for features enabled by XCR0 | IA32_XSS 604 * %ecx: Valid bits of lower 32bits of IA32_XSS 605 * %edx: Valid bits of upper 32bits of IA32_XSS 606 * 607 * %ecx >= 2: Save area details for XCR0 bit n 608 * %eax: size of save area for this feature 609 * %ebx: offset of save area for this feature 610 * %ecx, %edx: reserved 611 * All of %eax, %ebx, %ecx and %edx are zero for unsupported features. 612 */ 613 614 /* %ecx = 1, %eax */ 615 #define CPUID_PES1_XSAVEOPT 0x00000001 /* xsaveopt instruction */ 616 #define CPUID_PES1_XSAVEC 0x00000002 /* xsavec & compacted XRSTOR */ 617 #define CPUID_PES1_XGETBV 0x00000004 /* xgetbv with ECX = 1 */ 618 #define CPUID_PES1_XSAVES 0x00000008 /* xsaves/xrstors, IA32_XSS */ 619 620 #define CPUID_PES1_FLAGS "\20" \ 621 "\1" "XSAVEOPT" "\2" "XSAVEC" "\3" "XGETBV" "\4" "XSAVES" 622 623 /* 624 * Intel Deterministic Address Translation Parameter. 625 * CPUID Fn0000_0018 626 */ 627 628 /* %ecx=0 %eax __BITS(31, 0): the maximum input value of supported sub-leaf */ 629 630 /* %ebx */ 631 #define CPUID_DATP_PGSIZE __BITS(3, 0) /* page size */ 632 #define CPUID_DATP_PGSIZE_4KB __BIT(0) /* 4KB page support */ 633 #define CPUID_DATP_PGSIZE_2MB __BIT(1) /* 2MB page support */ 634 #define CPUID_DATP_PGSIZE_4MB __BIT(2) /* 4MB page support */ 635 #define CPUID_DATP_PGSIZE_1GB __BIT(3) /* 1GB page support */ 636 #define CPUID_DATP_PARTITIONING __BITS(10, 8) /* Partitioning */ 637 #define CPUID_DATP_WAYS __BITS(31, 16) /* Ways of associativity */ 638 639 /* Number of sets: %ecx */ 640 641 /* %edx */ 642 #define CPUID_DATP_TCTYPE __BITS(4, 0) /* Translation Cache type */ 643 #define CPUID_DATP_TCTYPE_N 0 /* NULL (not valid) */ 644 #define CPUID_DATP_TCTYPE_D 1 /* Data TLB */ 645 #define CPUID_DATP_TCTYPE_I 2 /* Instruction TLB */ 646 #define CPUID_DATP_TCTYPE_U 3 /* Unified TLB */ 647 #define CPUID_DATP_TCTYPE_L 4 /* Load only TLB */ 648 #define CPUID_DATP_TCTYPE_S 5 /* Store only TLB */ 649 #define CPUID_DATP_TCLEVEL __BITS(7, 5) /* TLB level (start at 1) */ 650 #define CPUID_DATP_FULLASSOC __BIT(8) /* Full associative */ 651 #define CPUID_DATP_SHAREING __BITS(25, 14) /* shareing */ 652 653 654 /* 655 * Intel extended features. 656 * CPUID Fn80000001 657 */ 658 /* %edx */ 659 #define CPUID_SYSCALL 0x00000800 /* SYSCALL/SYSRET */ 660 #define CPUID_XD 0x00100000 /* Execute Disable (like CPUID_NOX) */ 661 #define CPUID_PAGE1GB 0x04000000 /* 1GB Large Page Support */ 662 #define CPUID_RDTSCP 0x08000000 /* Read TSC Pair Instruction */ 663 #define CPUID_EM64T 0x20000000 /* Intel EM64T */ 664 665 #define CPUID_INTEL_EXT_FLAGS "\20" \ 666 "\14" "SYSCALL/SYSRET" "\25" "XD" "\33" "P1GB" \ 667 "\34" "RDTSCP" "\36" "EM64T" 668 669 /* %ecx */ 670 #define CPUID_LAHF __BIT(0) /* LAHF/SAHF in IA-32e mode, 64bit sub*/ 671 /* __BIT(5) */ /* LZCNT. Same as AMD's CPUID_ABM */ 672 #define CPUID_PREFETCHW __BIT(8) /* PREFETCHW */ 673 674 #define CPUID_INTEL_FLAGS4 "\20" \ 675 "\1" "LAHF" "\02" "B01" "\03" "B02" \ 676 "\06" "LZCNT" \ 677 "\11" "PREFETCHW" 678 679 680 /* 681 * AMD/VIA extended features. 682 * CPUID Fn80000001 683 */ 684 /* %edx */ 685 /* CPUID_SYSCALL SYSCALL/SYSRET */ 686 #define CPUID_MPC 0x00080000 /* Multiprocessing Capable */ 687 #define CPUID_NOX 0x00100000 /* No Execute Page Protection */ 688 #define CPUID_MMXX 0x00400000 /* AMD MMX Extensions */ 689 /* CPUID_MMX MMX supported */ 690 /* CPUID_FXSR fast FP/MMX save/restore */ 691 #define CPUID_FFXSR 0x02000000 /* FXSAVE/FXSTOR Extensions */ 692 /* CPUID_PAGE1GB 1GB Large Page Support */ 693 /* CPUID_RDTSCP Read TSC Pair Instruction */ 694 /* CPUID_EM64T Long mode */ 695 #define CPUID_3DNOW2 0x40000000 /* 3DNow! Instruction Extension */ 696 #define CPUID_3DNOW 0x80000000 /* 3DNow! Instructions */ 697 698 #define CPUID_EXT_FLAGS "\20" \ 699 "\14" "SYSCALL/SYSRET" \ 700 "\24" "MPC" \ 701 "\25" "NOX" "\27" "MMXX" "\30" "MMX" \ 702 "\31" "FXSR" "\32" "FFXSR" "\33" "P1GB" "\34" "RDTSCP" \ 703 "\36" "LONG" "\37" "3DNOW2" "\40" "3DNOW" 704 705 /* %ecx (AMD) */ 706 /* CPUID_LAHF LAHF/SAHF instruction */ 707 #define CPUID_CMPLEGACY __BIT(1) /* Compare Legacy */ 708 #define CPUID_SVM __BIT(2) /* Secure Virtual Machine */ 709 #define CPUID_EAPIC __BIT(3) /* Extended APIC space */ 710 #define CPUID_ALTMOVCR0 __BIT(4) /* Lock Mov Cr0 */ 711 #define CPUID_ABM __BIT(5) /* LZCNT instruction */ 712 #define CPUID_SSE4A __BIT(6) /* SSE4A instruction set */ 713 #define CPUID_MISALIGNSSE __BIT(7) /* Misaligned SSE */ 714 #define CPUID_3DNOWPF __BIT(8) /* 3DNow Prefetch */ 715 #define CPUID_OSVW __BIT(9) /* OS visible workarounds */ 716 #define CPUID_IBS __BIT(10) /* Instruction Based Sampling */ 717 #define CPUID_XOP __BIT(11) /* XOP instruction set */ 718 #define CPUID_SKINIT __BIT(12) /* SKINIT */ 719 #define CPUID_WDT __BIT(13) /* watchdog timer support */ 720 #define CPUID_LWP __BIT(15) /* Light Weight Profiling */ 721 #define CPUID_FMA4 __BIT(16) /* FMA4 instructions */ 722 #define CPUID_TCE __BIT(17) /* Translation cache Extension */ 723 #define CPUID_NODEID __BIT(19) /* NodeID MSR available */ 724 #define CPUID_TBM __BIT(21) /* TBM instructions */ 725 #define CPUID_TOPOEXT __BIT(22) /* cpuid Topology Extension */ 726 #define CPUID_PCEC __BIT(23) /* Perf Ctr Ext Core */ 727 #define CPUID_PCENB __BIT(24) /* Perf Ctr Ext NB */ 728 #define CPUID_SPM __BIT(25) /* Stream Perf Mon */ 729 #define CPUID_DBE __BIT(26) /* Data Breakpoint Extension */ 730 #define CPUID_PTSC __BIT(27) /* PerfTsc */ 731 #define CPUID_L2IPERFC __BIT(28) /* L2I performance counter Extension */ 732 #define CPUID_MWAITX __BIT(29) /* MWAITX/MONITORX support */ 733 #define CPUID_ADDRMASKEXT __BIT(30) /* Breakpoint Addressing Mask ext. */ 734 735 #define CPUID_AMD_FLAGS4 "\20" \ 736 "\1" "LAHF" "\2" "CMPLEGACY" "\3" "SVM" "\4" "EAPIC" \ 737 "\5" "ALTMOVCR0" "\6" "LZCNT" "\7" "SSE4A" "\10" "MISALIGNSSE" \ 738 "\11" "3DNOWPREFETCH" \ 739 "\12" "OSVW" "\13" "IBS" "\14" "XOP" \ 740 "\15" "SKINIT" "\16" "WDT" "\17" "B14" "\20" "LWP" \ 741 "\21" "FMA4" "\22" "TCE" "\23" "B18" "\24" "NodeID" \ 742 "\25" "B20" "\26" "TBM" "\27" "TopoExt" "\30" "PCExtC" \ 743 "\31" "PCExtNB" "\32" "StrmPM" "\33" "DBExt" "\34" "PerfTsc" \ 744 "\35" "L2IPERFC" "\36" "MWAITX" "\37" "AddrMaskExt" "\40" "B31" 745 746 /* 747 * Advanced Power Management. 748 * CPUID Fn8000_0007 749 * 750 * Only ITSC is for both Intel and AMD. Others are only for AMD. 751 */ 752 /* %edx */ 753 #define CPUID_APM_TS __BIT(0) /* Temperature Sensor */ 754 #define CPUID_APM_FID __BIT(1) /* Frequency ID control */ 755 #define CPUID_APM_VID __BIT(2) /* Voltage ID control */ 756 #define CPUID_APM_TTP __BIT(3) /* THERMTRIP (PCI F3xE4 register) */ 757 #define CPUID_APM_HTC __BIT(4) /* Hardware thermal control (HTC) */ 758 #define CPUID_APM_STC __BIT(5) /* Software thermal control (STC) */ 759 #define CPUID_APM_100 __BIT(6) /* 100MHz multiplier control */ 760 #define CPUID_APM_HWP __BIT(7) /* HW P-State control */ 761 #define CPUID_APM_ITSC __BIT(8) /* Invariant TSC */ 762 #define CPUID_APM_CPB __BIT(9) /* Core Performance Boost */ 763 #define CPUID_APM_EFF __BIT(10) /* Effective Frequency (read-only) */ 764 #define CPUID_APM_PROCFI __BIT(11) /* Processor Feedback Interface */ 765 #define CPUID_APM_PROCPR __BIT(12) /* Processor Power Reporting */ 766 #define CPUID_APM_CONNSTBY __BIT(13) /* Connected Standby */ 767 #define CPUID_APM_RAPL __BIT(14) /* Running Average Power Limit */ 768 769 #define CPUID_APM_FLAGS "\20" \ 770 "\1" "TS" "\2" "FID" "\3" "VID" "\4" "TTP" \ 771 "\5" "HTC" "\6" "STC" "\7" "100" "\10" "HWP" \ 772 "\11" "ITSC" "\12" "CPB" "\13" "EffFreq" "\14" "PROCFI" \ 773 "\15" "PROCPR" "\16" "CONNSTBY" "\17" "RAPL" 774 775 /* 776 * AMD Processor Capacity Parameters and Extended Features. 777 * CPUID Fn8000_0008 778 * %eax: Long Mode Size Identifiers 779 * %ebx: Extended Feature Identifiers 780 * %ecx: Size Identifiers 781 * %edx: RDPRU Register Identifier Range 782 */ 783 784 /* %ebx */ 785 #define CPUID_CAPEX_CLZERO __BIT(0) /* CLZERO instruction */ 786 #define CPUID_CAPEX_IRPERF __BIT(1) /* InstRetCntMsr */ 787 #define CPUID_CAPEX_XSAVEERPTR __BIT(2) /* RstrFpErrPtrs by XRSTOR */ 788 #define CPUID_CAPEX_RDPRU __BIT(4) /* RDPRU instruction */ 789 #define CPUID_CAPEX_MCOMMIT __BIT(8) /* MCOMMIT instruction */ 790 #define CPUID_CAPEX_WBNOINVD __BIT(9) /* WBNOINVD instruction */ 791 #define CPUID_CAPEX_IBPB __BIT(12) /* Speculation Control IBPB */ 792 #define CPUID_CAPEX_INT_WBINVD __BIT(13) /* Interruptable WB[NO]INVD */ 793 #define CPUID_CAPEX_IBRS __BIT(14) /* Speculation Control IBRS */ 794 #define CPUID_CAPEX_STIBP __BIT(15) /* Speculation Control STIBP */ 795 #define CPUID_CAPEX_IBRS_ALWAYSON __BIT(16) /* IBRS always on mode */ 796 #define CPUID_CAPEX_STIBP_ALWAYSON __BIT(17) /* STIBP always on mode */ 797 #define CPUID_CAPEX_PREFER_IBRS __BIT(18) /* IBRS preferred */ 798 #define CPUID_CAPEX_IBRS_SAMEMODE __BIT(19) /* IBRS same speculation limits */ 799 #define CPUID_CAPEX_EFER_LSMSLE_UN __BIT(20) /* EFER.LMSLE is unsupported */ 800 #define CPUID_CAPEX_SSBD __BIT(24) /* Speculation Control SSBD */ 801 #define CPUID_CAPEX_VIRT_SSBD __BIT(25) /* Virt Spec Control SSBD */ 802 #define CPUID_CAPEX_SSB_NO __BIT(26) /* SSBD not required */ 803 #define CPUID_CAPEX_PSFD __BIT(28) /* Predictive Store Froward Dis */ 804 805 #define CPUID_CAPEX_FLAGS "\20" \ 806 "\1CLZERO" "\2IRPERF" "\3XSAVEERPTR" \ 807 "\5RDPRU" "\7B6" \ 808 "\11MCOMMIT" "\12WBNOINVD" "\13B10" \ 809 "\15IBPB" "\16INT_WBINVD" "\17IBRS" "\20STIBP" \ 810 "\21IBRS_ALWAYSON" "\22STIBP_ALWAYSON" "\23PREFER_IBRS" \ 811 "\24IBRS_SAMEMODE" \ 812 "\25EFER_LSMSLE_UN" \ 813 "\31SSBD" "\32VIRT_SSBD" "\33SSB_NO" \ 814 "\35PSFD" 815 816 /* %ecx */ 817 #define CPUID_CAPEX_PerfTscSize __BITS(17,16) 818 #define CPUID_CAPEX_ApicIdSize __BITS(15,12) 819 #define CPUID_CAPEX_NC __BITS(7,0) 820 821 /* 822 * AMD SVM Revision and Feature. 823 * CPUID Fn8000_000a 824 */ 825 826 /* %eax: SVM revision */ 827 #define CPUID_AMD_SVM_REV __BITS(7,0) 828 829 /* %edx: SVM features */ 830 #define CPUID_AMD_SVM_NP __BIT(0) /* Nested Paging */ 831 #define CPUID_AMD_SVM_LbrVirt __BIT(1) /* LBR virtualization */ 832 #define CPUID_AMD_SVM_SVML __BIT(2) /* SVM Lock */ 833 #define CPUID_AMD_SVM_NRIPS __BIT(3) /* NRIP Save on #VMEXIT */ 834 #define CPUID_AMD_SVM_TSCRateCtrl __BIT(4) /* MSR-based TSC rate ctrl */ 835 #define CPUID_AMD_SVM_VMCBCleanBits __BIT(5) /* VMCB Clean Bits support */ 836 #define CPUID_AMD_SVM_FlushByASID __BIT(6) /* Flush by ASID */ 837 #define CPUID_AMD_SVM_DecodeAssist __BIT(7) /* Decode Assists support */ 838 #define CPUID_AMD_SVM_PauseFilter __BIT(10) /* PAUSE intercept filter */ 839 #define CPUID_AMD_SVM_PFThreshold __BIT(12) /* PAUSE filter threshold */ 840 #define CPUID_AMD_SVM_AVIC __BIT(13) /* Advanced Virt. Intr. Ctrl */ 841 #define CPUID_AMD_SVM_V_VMSAVE_VMLOAD __BIT(15) /* Virtual VM{SAVE/LOAD} */ 842 #define CPUID_AMD_SVM_vGIF __BIT(16) /* Virtualized GIF */ 843 #define CPUID_AMD_SVM_GMET __BIT(17) /* Guest Mode Execution Trap */ 844 #define CPUID_AMD_SVM_SSSCHECK __BIT(19) /* Shadow Stack restrictions */ 845 #define CPUID_AMD_SVM_SPEC_CTRL __BIT(20) /* SPEC_CTRL virtualization */ 846 #define CPUID_AMD_SVM_TLBICTL __BIT(24) /* TLB Intercept Control */ 847 848 #define CPUID_AMD_SVM_FLAGS "\20" \ 849 "\1" "NP" "\2" "LbrVirt" "\3" "SVML" "\4" "NRIPS" \ 850 "\5" "TSCRate" "\6" "VMCBCleanBits" \ 851 "\7" "FlushByASID" "\10" "DecodeAssist" \ 852 "\11" "B08" "\12" "B09" "\13" "PauseFilter" "\14" "B11" \ 853 "\15" "PFThreshold" "\16" "AVIC" "\17" "B14" \ 854 "\20" "V_VMSAVE_VMLOAD" \ 855 "\21" "VGIF" "\22" "GMET" "\24SSSCHECK" \ 856 "\25" "SPEC_CTRL" \ 857 "\31" "TLBICTL" \ 858 "\35B28" 859 860 /* 861 * AMD Cache Topology Information. 862 * CPUID Fn8000_001d 863 * It's almost the same as Intel Deterministic Cache Parameter Leaf(0x04) 864 * except the following: 865 * No Cores/package (%eax bit 31..26) 866 * No Complex cache indexing (%edx bit 2) 867 */ 868 869 /* 870 * AMD Encrypted Memory Capabilities. 871 * CPUID Fn8000_001f 872 * %eax: flags 873 * %ebx: 5-0: Cbit Position 874 * 11-6: PhysAddrReduction 875 * 15-12: NumVMPL 876 * %ecx: 31-0: NumEncryptedGuests 877 * %edx: 31-0: MinSevNoEsAsid 878 */ 879 #define CPUID_AMD_ENCMEM_SME __BIT(0) /* Secure Memory Encryption */ 880 #define CPUID_AMD_ENCMEM_SEV __BIT(1) /* Secure Encrypted Virtualiz. */ 881 #define CPUID_AMD_ENCMEM_PGFLMSR __BIT(2) /* Page Flush MSR */ 882 #define CPUID_AMD_ENCMEM_SEVES __BIT(3) /* SEV Encrypted State */ 883 #define CPUID_AMD_ENCMEM_SEV_SNP __BIT(4) /* Secure Nested Paging */ 884 #define CPUID_AMD_ENCMEM_VMPL __BIT(5) /* Virtual Machine Privilege Lvl */ 885 #define CPUID_AMD_ENCMEM_SECTSC __BIT(8) /* Secure TSC */ 886 #define CPUID_AMD_ENCMEM_HECC __BIT(10) /* HW Enf Cache Coh across enc dom */ 887 #define CPUID_AMD_ENCMEM_64BH __BIT(11) /* 64Bit Host */ 888 #define CPUID_AMD_ENCMEM_RSTRINJ __BIT(12) /* Restricted Injection */ 889 #define CPUID_AMD_ENCMEM_ALTINJ __BIT(13) /* Alternate Injection */ 890 #define CPUID_AMD_ENCMEM_DBGSWAP __BIT(14) /* Debug Swap */ 891 #define CPUID_AMD_ENCMEM_PREVHOSTIBS __BIT(15) /* Prevent Host IBS */ 892 #define CPUID_AMD_ENCMEM_VTE __BIT(16) /* Virtual Transparent Encryption */ 893 #define CPUID_AMD_ENCMEM_VMSA_REGPROT __BIT(24) /* VmsaRegProt */ 894 895 #define CPUID_AMD_ENCMEM_FLAGS "\20" \ 896 "\1" "SME" "\2" "SEV" "\3" "PageFlushMsr" "\4" "SEV-ES" \ 897 "\5" "SEV-SNP" "\6" "VMPL" \ 898 "\11SecureTSC" "\13HwEnfCacheCoh" "\14" "64BitHost" \ 899 "\15" "RSTRINJ" "\16" "ALTINJ" "\17" "DebugSwap" "\20PreventHostlbs" \ 900 "\21" "VTE" \ 901 "\31" "VmsaRegProt" 902 903 /* 904 * Centaur Extended Feature flags. 905 */ 906 #define CPUID_VIA_HAS_RNG 0x00000004 /* Random number generator */ 907 #define CPUID_VIA_DO_RNG 0x00000008 908 #define CPUID_VIA_HAS_ACE 0x00000040 /* AES Encryption */ 909 #define CPUID_VIA_DO_ACE 0x00000080 910 #define CPUID_VIA_HAS_ACE2 0x00000100 /* AES+CTR instructions */ 911 #define CPUID_VIA_DO_ACE2 0x00000200 912 #define CPUID_VIA_HAS_PHE 0x00000400 /* SHA1+SHA256 HMAC */ 913 #define CPUID_VIA_DO_PHE 0x00000800 914 #define CPUID_VIA_HAS_PMM 0x00001000 /* RSA Instructions */ 915 #define CPUID_VIA_DO_PMM 0x00002000 916 917 #define CPUID_FLAGS_PADLOCK "\20" \ 918 "\3" "RNG" "\7" "AES" "\11" "AES/CTR" "\13" "SHA1/SHA256" \ 919 "\15" "RSA" 920 921 /* 922 * Model-Specific Registers 923 */ 924 #define MSR_TSC 0x010 925 #define MSR_IA32_PLATFORM_ID 0x017 926 #define MSR_APICBASE 0x01b 927 #define APICBASE_BSP 0x00000100 /* boot processor */ 928 #define APICBASE_EXTD 0x00000400 /* x2APIC mode */ 929 #define APICBASE_EN 0x00000800 /* software enable */ 930 /* 931 * APICBASE_PHYSADDR is actually variable-sized on some CPUs. But we're 932 * only interested in the initial value, which is guaranteed to fit the 933 * first 32 bits. So this macro is fine. 934 */ 935 #define APICBASE_PHYSADDR 0xfffff000 /* physical address */ 936 #define MSR_EBL_CR_POWERON 0x02a 937 #define MSR_EBC_FREQUENCY_ID 0x02c /* PIV only */ 938 #define MSR_IA32_SPEC_CTRL 0x048 939 #define IA32_SPEC_CTRL_IBRS 0x01 940 #define IA32_SPEC_CTRL_STIBP 0x02 941 #define IA32_SPEC_CTRL_SSBD 0x04 942 #define MSR_IA32_PRED_CMD 0x049 943 #define IA32_PRED_CMD_IBPB 0x01 944 #define MSR_BIOS_UPDT_TRIG 0x079 945 #define MSR_BIOS_SIGN 0x08b 946 #define MSR_PERFCTR0 0x0c1 947 #define MSR_PERFCTR1 0x0c2 948 #define MSR_FSB_FREQ 0x0cd /* Core Duo/Solo only */ 949 #define MSR_MPERF 0x0e7 950 #define MSR_APERF 0x0e8 951 #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ 952 #define MSR_MTRRcap 0x0fe 953 #define MSR_IA32_ARCH_CAPABILITIES 0x10a 954 #define IA32_ARCH_RDCL_NO 0x01 955 #define IA32_ARCH_IBRS_ALL 0x02 956 #define IA32_ARCH_RSBA 0x04 957 #define IA32_ARCH_SKIP_L1DFL_VMENTRY 0x08 958 #define IA32_ARCH_SSB_NO 0x10 959 #define IA32_ARCH_MDS_NO 0x20 960 #define IA32_ARCH_IF_PSCHANGE_MC_NO 0x40 961 #define IA32_ARCH_TSX_CTRL 0x80 962 #define IA32_ARCH_TAA_NO 0x100 963 #define MSR_IA32_FLUSH_CMD 0x10b 964 #define IA32_FLUSH_CMD_L1D_FLUSH 0x01 965 #define MSR_TSX_FORCE_ABORT 0x10f 966 #define MSR_IA32_TSX_CTRL 0x122 967 #define IA32_TSX_CTRL_RTM_DISABLE __BIT(0) 968 #define IA32_TSX_CTRL_TSX_CPUID_CLEAR __BIT(1) 969 #define MSR_SYSENTER_CS 0x174 /* PII+ only */ 970 #define MSR_SYSENTER_ESP 0x175 /* PII+ only */ 971 #define MSR_SYSENTER_EIP 0x176 /* PII+ only */ 972 #define MSR_MCG_CAP 0x179 973 #define MSR_MCG_STATUS 0x17a 974 #define MSR_MCG_CTL 0x17b 975 #define MSR_EVNTSEL0 0x186 976 #define MSR_EVNTSEL1 0x187 977 #define MSR_PERF_STATUS 0x198 /* Pentium M */ 978 #define MSR_PERF_CTL 0x199 /* Pentium M */ 979 #define MSR_THERM_CONTROL 0x19a 980 #define MSR_THERM_INTERRUPT 0x19b 981 #define MSR_THERM_STATUS 0x19c 982 #define MSR_THERM2_CTL 0x19d /* Pentium M */ 983 #define MSR_MISC_ENABLE 0x1a0 984 #define IA32_MISC_FAST_STR_EN __BIT(0) 985 #define IA32_MISC_ATCC_EN __BIT(3) 986 #define IA32_MISC_PERFMON_EN __BIT(7) 987 #define IA32_MISC_BTS_UNAVAIL __BIT(11) 988 #define IA32_MISC_PEBS_UNAVAIL __BIT(12) 989 #define IA32_MISC_EISST_EN __BIT(16) 990 #define IA32_MISC_MWAIT_EN __BIT(18) 991 #define IA32_MISC_LIMIT_CPUID __BIT(22) 992 #define IA32_MISC_XTPR_DIS __BIT(23) 993 #define IA32_MISC_XD_DIS __BIT(34) 994 #define MSR_TEMPERATURE_TARGET 0x1a2 995 #define MSR_DEBUGCTLMSR 0x1d9 996 #define MSR_LASTBRANCHFROMIP 0x1db 997 #define MSR_LASTBRANCHTOIP 0x1dc 998 #define MSR_LASTINTFROMIP 0x1dd 999 #define MSR_LASTINTTOIP 0x1de 1000 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 1001 #define MSR_MTRRphysBase0 0x200 1002 #define MSR_MTRRphysMask0 0x201 1003 #define MSR_MTRRphysBase1 0x202 1004 #define MSR_MTRRphysMask1 0x203 1005 #define MSR_MTRRphysBase2 0x204 1006 #define MSR_MTRRphysMask2 0x205 1007 #define MSR_MTRRphysBase3 0x206 1008 #define MSR_MTRRphysMask3 0x207 1009 #define MSR_MTRRphysBase4 0x208 1010 #define MSR_MTRRphysMask4 0x209 1011 #define MSR_MTRRphysBase5 0x20a 1012 #define MSR_MTRRphysMask5 0x20b 1013 #define MSR_MTRRphysBase6 0x20c 1014 #define MSR_MTRRphysMask6 0x20d 1015 #define MSR_MTRRphysBase7 0x20e 1016 #define MSR_MTRRphysMask7 0x20f 1017 #define MSR_MTRRphysBase8 0x210 1018 #define MSR_MTRRphysMask8 0x211 1019 #define MSR_MTRRphysBase9 0x212 1020 #define MSR_MTRRphysMask9 0x213 1021 #define MSR_MTRRphysBase10 0x214 1022 #define MSR_MTRRphysMask10 0x215 1023 #define MSR_MTRRphysBase11 0x216 1024 #define MSR_MTRRphysMask11 0x217 1025 #define MSR_MTRRphysBase12 0x218 1026 #define MSR_MTRRphysMask12 0x219 1027 #define MSR_MTRRphysBase13 0x21a 1028 #define MSR_MTRRphysMask13 0x21b 1029 #define MSR_MTRRphysBase14 0x21c 1030 #define MSR_MTRRphysMask14 0x21d 1031 #define MSR_MTRRphysBase15 0x21e 1032 #define MSR_MTRRphysMask15 0x21f 1033 #define MSR_MTRRfix64K_00000 0x250 1034 #define MSR_MTRRfix16K_80000 0x258 1035 #define MSR_MTRRfix16K_A0000 0x259 1036 #define MSR_MTRRfix4K_C0000 0x268 1037 #define MSR_MTRRfix4K_C8000 0x269 1038 #define MSR_MTRRfix4K_D0000 0x26a 1039 #define MSR_MTRRfix4K_D8000 0x26b 1040 #define MSR_MTRRfix4K_E0000 0x26c 1041 #define MSR_MTRRfix4K_E8000 0x26d 1042 #define MSR_MTRRfix4K_F0000 0x26e 1043 #define MSR_MTRRfix4K_F8000 0x26f 1044 #define MSR_CR_PAT 0x277 1045 #define MSR_MTRRdefType 0x2ff 1046 #define MSR_MC0_CTL 0x400 1047 #define MSR_MC0_STATUS 0x401 1048 #define MSR_MC0_ADDR 0x402 1049 #define MSR_MC0_MISC 0x403 1050 #define MSR_MC1_CTL 0x404 1051 #define MSR_MC1_STATUS 0x405 1052 #define MSR_MC1_ADDR 0x406 1053 #define MSR_MC1_MISC 0x407 1054 #define MSR_MC2_CTL 0x408 1055 #define MSR_MC2_STATUS 0x409 1056 #define MSR_MC2_ADDR 0x40a 1057 #define MSR_MC2_MISC 0x40b 1058 #define MSR_MC3_CTL 0x40c 1059 #define MSR_MC3_STATUS 0x40d 1060 #define MSR_MC3_ADDR 0x40e 1061 #define MSR_MC3_MISC 0x40f 1062 #define MSR_MC4_CTL 0x410 1063 #define MSR_MC4_STATUS 0x411 1064 #define MSR_MC4_ADDR 0x412 1065 #define MSR_MC4_MISC 0x413 1066 /* 0x480 - 0x490 VMX */ 1067 #define MSR_X2APIC_BASE 0x800 /* 0x800 - 0xBFF */ 1068 #define MSR_X2APIC_ID 0x002 /* x2APIC ID. (RO) */ 1069 #define MSR_X2APIC_VERS 0x003 /* Version. (RO) */ 1070 #define MSR_X2APIC_TPRI 0x008 /* Task Prio. (RW) */ 1071 #define MSR_X2APIC_PPRI 0x00a /* Processor prio. (RO) */ 1072 #define MSR_X2APIC_EOI 0x00b /* End Int. (W) */ 1073 #define MSR_X2APIC_LDR 0x00d /* Logical dest. (RO) */ 1074 #define MSR_X2APIC_SVR 0x00f /* Spurious intvec (RW) */ 1075 #define MSR_X2APIC_ISR 0x010 /* In-Service Status (RO) */ 1076 #define MSR_X2APIC_TMR 0x018 /* Trigger Mode (RO) */ 1077 #define MSR_X2APIC_IRR 0x020 /* Interrupt Req (RO) */ 1078 #define MSR_X2APIC_ESR 0x028 /* Err status. (RW) */ 1079 #define MSR_X2APIC_LVT_CMCI 0x02f /* LVT CMCI (RW) */ 1080 #define MSR_X2APIC_ICRLO 0x030 /* Int. cmd. (RW64) */ 1081 #define MSR_X2APIC_LVTT 0x032 /* Loc.vec.(timer) (RW) */ 1082 #define MSR_X2APIC_TMINT 0x033 /* Loc.vec (Thermal) (RW) */ 1083 #define MSR_X2APIC_PCINT 0x034 /* Loc.vec (Perf Mon) (RW) */ 1084 #define MSR_X2APIC_LVINT0 0x035 /* Loc.vec (LINT0) (RW) */ 1085 #define MSR_X2APIC_LVINT1 0x036 /* Loc.vec (LINT1) (RW) */ 1086 #define MSR_X2APIC_LVERR 0x037 /* Loc.vec (ERROR) (RW) */ 1087 #define MSR_X2APIC_ICR_TIMER 0x038 /* Initial count (RW) */ 1088 #define MSR_X2APIC_CCR_TIMER 0x039 /* Current count (RO) */ 1089 #define MSR_X2APIC_DCR_TIMER 0x03e /* Divisor config (RW) */ 1090 #define MSR_X2APIC_SELF_IPI 0x03f /* SELF IPI (W) */ 1091 1092 /* 1093 * VIA "Nehemiah" MSRs 1094 */ 1095 #define MSR_VIA_RNG 0x0000110b 1096 #define MSR_VIA_RNG_ENABLE 0x00000040 1097 #define MSR_VIA_RNG_NOISE_MASK 0x00000300 1098 #define MSR_VIA_RNG_NOISE_A 0x00000000 1099 #define MSR_VIA_RNG_NOISE_B 0x00000100 1100 #define MSR_VIA_RNG_2NOISE 0x00000300 1101 #define MSR_VIA_ACE 0x00001107 1102 #define VIA_ACE_ALTINST 0x00000001 1103 #define VIA_ACE_ECX8 0x00000002 1104 #define VIA_ACE_ENABLE 0x10000000 1105 1106 /* 1107 * VIA "Eden" MSRs 1108 */ 1109 #define MSR_VIA_FCR MSR_VIA_ACE 1110 1111 /* 1112 * AMD K6/K7 MSRs. 1113 */ 1114 #define MSR_K6_UWCCR 0xc0000085 1115 #define MSR_K7_EVNTSEL0 0xc0010000 1116 #define MSR_K7_EVNTSEL1 0xc0010001 1117 #define MSR_K7_EVNTSEL2 0xc0010002 1118 #define MSR_K7_EVNTSEL3 0xc0010003 1119 #define MSR_K7_PERFCTR0 0xc0010004 1120 #define MSR_K7_PERFCTR1 0xc0010005 1121 #define MSR_K7_PERFCTR2 0xc0010006 1122 #define MSR_K7_PERFCTR3 0xc0010007 1123 1124 /* 1125 * AMD K8 (Opteron) MSRs. 1126 */ 1127 #define MSR_SYSCFG 0xc0010010 1128 1129 #define MSR_EFER 0xc0000080 /* Extended feature enable */ 1130 #define EFER_SCE 0x00000001 /* SYSCALL extension */ 1131 #define EFER_LME 0x00000100 /* Long Mode Enable */ 1132 #define EFER_LMA 0x00000400 /* Long Mode Active */ 1133 #define EFER_NXE 0x00000800 /* No-Execute Enabled */ 1134 #define EFER_SVME 0x00001000 /* Secure Virtual Machine En. */ 1135 #define EFER_LMSLE 0x00002000 /* Long Mode Segment Limit E. */ 1136 #define EFER_FFXSR 0x00004000 /* Fast FXSAVE/FXRSTOR En. */ 1137 #define EFER_TCE 0x00008000 /* Translation Cache Ext. */ 1138 1139 #define MSR_STAR 0xc0000081 /* 32 bit syscall gate addr */ 1140 #define MSR_LSTAR 0xc0000082 /* 64 bit syscall gate addr */ 1141 #define MSR_CSTAR 0xc0000083 /* compat syscall gate addr */ 1142 #define MSR_SFMASK 0xc0000084 /* flags to clear on syscall */ 1143 1144 #define MSR_FSBASE 0xc0000100 /* 64bit offset for fs: */ 1145 #define MSR_GSBASE 0xc0000101 /* 64bit offset for gs: */ 1146 #define MSR_KERNELGSBASE 0xc0000102 /* storage for swapgs ins */ 1147 1148 #define MSR_VMCR 0xc0010114 /* Virtual Machine Control Register */ 1149 #define VMCR_DPD 0x00000001 /* Debug port disable */ 1150 #define VMCR_RINIT 0x00000002 /* intercept init */ 1151 #define VMCR_DISA20 0x00000004 /* Disable A20 masking */ 1152 #define VMCR_LOCK 0x00000008 /* SVM Lock */ 1153 #define VMCR_SVMED 0x00000010 /* SVME Disable */ 1154 #define MSR_SVMLOCK 0xc0010118 /* SVM Lock key */ 1155 1156 /* 1157 * These require a 'passcode' for access. See cpufunc.h. 1158 */ 1159 #define MSR_HWCR 0xc0010015 1160 #define HWCR_TLBCACHEDIS 0x00000008 1161 #define HWCR_FFDIS 0x00000040 1162 1163 #define MSR_NB_CFG 0xc001001f 1164 #define NB_CFG_DISIOREQLOCK 0x0000000000000008ULL 1165 #define NB_CFG_DISDATMSK 0x0000001000000000ULL 1166 #define NB_CFG_INITAPICCPUIDLO (1ULL << 54) 1167 1168 #define MSR_LS_CFG 0xc0011020 1169 #define LS_CFG_ERRATA_1033 __BIT(4) 1170 #define LS_CFG_ERRATA_793 __BIT(15) 1171 #define LS_CFG_ERRATA_1095 __BIT(57) 1172 #define LS_CFG_DIS_LS2_SQUISH 0x02000000 1173 #define LS_CFG_DIS_SSB_F15H 0x0040000000000000ULL 1174 #define LS_CFG_DIS_SSB_F16H 0x0000000200000000ULL 1175 #define LS_CFG_DIS_SSB_F17H 0x0000000000000400ULL 1176 1177 #define MSR_IC_CFG 0xc0011021 1178 #define IC_CFG_DIS_SEQ_PREFETCH 0x00000800 1179 #define IC_CFG_DIS_IND 0x00004000 1180 #define IC_CFG_ERRATA_776 __BIT(26) 1181 1182 #define MSR_DC_CFG 0xc0011022 1183 #define DC_CFG_DIS_CNV_WC_SSO 0x00000008 1184 #define DC_CFG_DIS_SMC_CHK_BUF 0x00000400 1185 #define DC_CFG_ERRATA_261 0x01000000 1186 1187 #define MSR_BU_CFG 0xc0011023 1188 #define BU_CFG_ERRATA_298 0x0000000000000002ULL 1189 #define BU_CFG_ERRATA_254 0x0000000000200000ULL 1190 #define BU_CFG_ERRATA_309 0x0000000000800000ULL 1191 #define BU_CFG_THRL2IDXCMPDIS 0x0000080000000000ULL 1192 #define BU_CFG_WBPFSMCCHKDIS 0x0000200000000000ULL 1193 #define BU_CFG_WBENHWSBDIS 0x0001000000000000ULL 1194 1195 #define MSR_FP_CFG 0xc0011028 1196 #define FP_CFG_ERRATA_1049 __BIT(4) 1197 1198 #define MSR_DE_CFG 0xc0011029 1199 #define DE_CFG_ERRATA_721 0x00000001 1200 #define DE_CFG_LFENCE_SERIALIZE __BIT(1) 1201 #define DE_CFG_ERRATA_1021 __BIT(13) 1202 1203 #define MSR_BU_CFG2 0xc001102a 1204 #define BU_CFG2_CWPLUS_DIS __BIT(24) 1205 1206 #define MSR_LS_CFG2 0xc001102d 1207 #define LS_CFG2_ERRATA_1091 __BIT(34) 1208 1209 /* AMD Family10h MSRs */ 1210 #define MSR_OSVW_ID_LENGTH 0xc0010140 1211 #define MSR_OSVW_STATUS 0xc0010141 1212 #define MSR_UCODE_AMD_PATCHLEVEL 0x0000008b 1213 #define MSR_UCODE_AMD_PATCHLOADER 0xc0010020 1214 1215 /* X86 MSRs */ 1216 #define MSR_RDTSCP_AUX 0xc0000103 1217 1218 /* 1219 * Constants related to MTRRs 1220 */ 1221 #define MTRR_N64K 8 /* numbers of fixed-size entries */ 1222 #define MTRR_N16K 16 1223 #define MTRR_N4K 64 1224 1225 /* 1226 * the following four 3-byte registers control the non-cacheable regions. 1227 * These registers must be written as three separate bytes. 1228 * 1229 * NCRx+0: A31-A24 of starting address 1230 * NCRx+1: A23-A16 of starting address 1231 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 1232 * 1233 * The non-cacheable region's starting address must be aligned to the 1234 * size indicated by the NCR_SIZE_xx field. 1235 */ 1236 #define NCR1 0xc4 1237 #define NCR2 0xc7 1238 #define NCR3 0xca 1239 #define NCR4 0xcd 1240 1241 #define NCR_SIZE_0K 0 1242 #define NCR_SIZE_4K 1 1243 #define NCR_SIZE_8K 2 1244 #define NCR_SIZE_16K 3 1245 #define NCR_SIZE_32K 4 1246 #define NCR_SIZE_64K 5 1247 #define NCR_SIZE_128K 6 1248 #define NCR_SIZE_256K 7 1249 #define NCR_SIZE_512K 8 1250 #define NCR_SIZE_1M 9 1251 #define NCR_SIZE_2M 10 1252 #define NCR_SIZE_4M 11 1253 #define NCR_SIZE_8M 12 1254 #define NCR_SIZE_16M 13 1255 #define NCR_SIZE_32M 14 1256 #define NCR_SIZE_4G 15 1257
Indexes created Tue Sep 30 17:09:57 GMT 2025