specialreg.h revision 1.23
1 /* $NetBSD: specialreg.h,v 1.23 2008/02/03 06:19:06 xtraeme Exp $ */ 2 3 /*- 4 * Copyright (c) 1991 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of the University nor the names of its contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * @(#)specialreg.h 7.1 (Berkeley) 5/9/91 32 */ 33 34 /* 35 * Bits in 386 special registers: 36 */ 37 #define CR0_PE 0x00000001 /* Protected mode Enable */ 38 #define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */ 39 #define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */ 40 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 41 #define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */ 42 #define CR0_PG 0x80000000 /* PaGing enable */ 43 44 /* 45 * Bits in 486 special registers: 46 */ 47 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 48 #define CR0_WP 0x00010000 /* Write Protect (honor PG_RW in all modes) */ 49 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 50 #define CR0_NW 0x20000000 /* Not Write-through */ 51 #define CR0_CD 0x40000000 /* Cache Disable */ 52 53 /* 54 * Cyrix 486 DLC special registers, accessible as IO ports. 55 */ 56 #define CCR0 0xc0 /* configuration control register 0 */ 57 #define CCR0_NC0 0x01 /* first 64K of each 1M memory region is non-cacheable */ 58 #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 59 #define CCR0_A20M 0x04 /* enables A20M# input pin */ 60 #define CCR0_KEN 0x08 /* enables KEN# input pin */ 61 #define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */ 62 #define CCR0_BARB 0x20 /* flushes internal cache when entering hold state */ 63 #define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */ 64 #define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */ 65 66 #define CCR1 0xc1 /* configuration control register 1 */ 67 #define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */ 68 /* the remaining 7 bits of this register are reserved */ 69 70 /* 71 * bits in the pentiums %cr4 register: 72 */ 73 74 #define CR4_VME 0x00000001 /* virtual 8086 mode extension enable */ 75 #define CR4_PVI 0x00000002 /* protected mode virtual interrupt enable */ 76 #define CR4_TSD 0x00000004 /* restrict RDTSC instruction to cpl 0 only */ 77 #define CR4_DE 0x00000008 /* debugging extension */ 78 #define CR4_PSE 0x00000010 /* large (4MB) page size enable */ 79 #define CR4_PAE 0x00000020 /* physical address extension enable */ 80 #define CR4_MCE 0x00000040 /* machine check enable */ 81 #define CR4_PGE 0x00000080 /* page global enable */ 82 #define CR4_PCE 0x00000100 /* enable RDPMC instruction for all cpls */ 83 #define CR4_OSFXSR 0x00000200 /* enable fxsave/fxrestor and SSE */ 84 #define CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */ 85 86 /* 87 * CPUID "features" bits in %edx 88 */ 89 90 #define CPUID_FPU 0x00000001 /* processor has an FPU? */ 91 #define CPUID_VME 0x00000002 /* has virtual mode (%cr4's VME/PVI) */ 92 #define CPUID_DE 0x00000004 /* has debugging extension */ 93 #define CPUID_PSE 0x00000008 /* has page 4MB page size extension */ 94 #define CPUID_TSC 0x00000010 /* has time stamp counter */ 95 #define CPUID_MSR 0x00000020 /* has mode specific registers */ 96 #define CPUID_PAE 0x00000040 /* has phys address extension */ 97 #define CPUID_MCE 0x00000080 /* has machine check exception */ 98 #define CPUID_CX8 0x00000100 /* has CMPXCHG8B instruction */ 99 #define CPUID_APIC 0x00000200 /* has enabled APIC */ 100 #define CPUID_B10 0x00000400 /* reserved, MTRR */ 101 #define CPUID_SEP 0x00000800 /* has SYSENTER/SYSEXIT extension */ 102 #define CPUID_MTRR 0x00001000 /* has memory type range register */ 103 #define CPUID_PGE 0x00002000 /* has page global extension */ 104 #define CPUID_MCA 0x00004000 /* has machine check architecture */ 105 #define CPUID_CMOV 0x00008000 /* has CMOVcc instruction */ 106 #define CPUID_PAT 0x00010000 /* Page Attribute Table */ 107 #define CPUID_PSE36 0x00020000 /* 36-bit PSE */ 108 #define CPUID_PN 0x00040000 /* processor serial number */ 109 #define CPUID_CFLUSH 0x00080000 /* CFLUSH insn supported */ 110 #define CPUID_B20 0x00100000 /* reserved */ 111 #define CPUID_DS 0x00200000 /* Debug Store */ 112 #define CPUID_ACPI 0x00400000 /* ACPI performance modulation regs */ 113 #define CPUID_MMX 0x00800000 /* MMX supported */ 114 #define CPUID_FXSR 0x01000000 /* fast FP/MMX save/restore */ 115 #define CPUID_SSE 0x02000000 /* streaming SIMD extensions */ 116 #define CPUID_SSE2 0x04000000 /* streaming SIMD extensions #2 */ 117 #define CPUID_SS 0x08000000 /* self-snoop */ 118 #define CPUID_HTT 0x10000000 /* Hyper-Threading Technology */ 119 #define CPUID_TM 0x20000000 /* thermal monitor (TCC) */ 120 #define CPUID_IA64 0x40000000 /* IA-64 architecture */ 121 #define CPUID_SBF 0x80000000 /* signal break on FERR */ 122 123 #define CPUID_FLAGS1 "\20\1FPU\2VME\3DE\4PSE\5TSC\6MSR\7PAE" \ 124 "\10MCE\11CX8\12APIC\13B10\14SEP\15MTRR" 125 #define CPUID_MASK1 0x00001fff 126 #define CPUID_FLAGS2 "\20\16PGE\17MCA\20CMOV\21PAT\22PSE36\23PN\24CFLUSH" \ 127 "\25B20\26DS\27ACPI\30MMX" 128 #define CPUID_MASK2 0x00ffe000 129 #define CPUID_FLAGS3 "\20\31FXSR\32SSE\33SSE2\34SS\35HTT\36TM\37IA64\40SBF" 130 #define CPUID_MASK3 0xff000000 131 132 /* 133 * CPUID Intel extended features 134 */ 135 #define CPUID_SYSCALL 0x00000800 /* SYSCALL/SYSRET */ 136 #define CPUID_XD 0x00100000 /* Execute Disable */ 137 #define CPUID_EM64T 0x20000000 /* Intel EM64T */ 138 139 #define CPUID_MASK4 0x20100800 140 #define CPUID_FLAGS4 "\20\14SYSCALL/SYSRET\25XD\36EM64T" 141 142 /* 143 * AMD/VIA processor specific flags. 144 */ 145 146 #define CPUID_MPC 0x00080000 /* Multiprocessing Capable */ 147 #define CPUID_NOX 0x00100000 /* No Execute Page Protection */ 148 #define CPUID_MMXX 0x00400000 /* AMD MMX Extensions */ 149 #define CPUID_RDTSCP 0x08000000 /* Read TSC Pair Instruction */ 150 #define CPUID_3DNOW2 0x40000000 /* 3DNow! Instruction Extension */ 151 #define CPUID_3DNOW 0x80000000 /* 3DNow! Instructions */ 152 153 #define CPUID_EXT_FLAGS2 "\20\16PGE\17MCA\20CMOV\21PAT\22PSE36\23PN" \ 154 "\24MPC\25NOX\26B21\27MMXX\30MMX" 155 #define CPUID_EXT_FLAGS3 "\20\31FXSR\32SSE\33SSE2\34RDTSCP\35HTT" \ 156 "\36LONG\0373DNOW2\0403DNOW" 157 158 /* 159 * Centaur Extended Feature flags 160 */ 161 #define CPUID_VIA_HAS_RNG 0x00000004 /* Random number generator */ 162 #define CPUID_VIA_DO_RNG 0x00000008 163 #define CPUID_VIA_HAS_ACE 0x00000040 /* AES Encryption */ 164 #define CPUID_VIA_DO_ACE 0x00000080 165 #define CPUID_VIA_HAS_ACE2 0x00000100 /* AES+CTR instructions */ 166 #define CPUID_VIA_DO_ACE2 0x00000200 167 #define CPUID_VIA_HAS_PHE 0x00000400 /* SHA1+SHA256 HMAC */ 168 #define CPUID_VIA_DO_PHE 0x00000800 169 #define CPUID_VIA_HAS_PMM 0x00001000 /* RSA Instructions */ 170 #define CPUID_VIA_DO_PMM 0x00002000 171 172 #define CPUID_FLAGS_PADLOCK "\20\3RNG\7AES\11AES/CTR\13SHA1/SHA256\15RSA" 173 174 /* 175 * CPUID "features" bits in %ecx 176 */ 177 178 #define CPUID2_SSE3 0x00000001 /* Streaming SIMD Extensions 3 */ 179 #define CPUID2_DTES64 0x00000004 /* 64-bit Debug Trace */ 180 #define CPUID2_MONITOR 0x00000008 /* MONITOR/MWAIT instructions */ 181 #define CPUID2_DS_CPL 0x00000010 /* CPL Qualified Debug Store */ 182 #define CPUID2_VMX 0x00000020 /* Virtual Machine Extensions */ 183 #define CPUID2_SMX 0x00000040 /* Safer Mode Extensions */ 184 #define CPUID2_EST 0x00000080 /* Enhanced SpeedStep Technology */ 185 #define CPUID2_TM2 0x00000100 /* Thermal Monitor 2 */ 186 #define CPUID2_SSSE3 0x00000200 /* Supplemental SSE3 */ 187 #define CPUID2_CID 0x00000400 /* Context ID */ 188 #define CPUID2_CX16 0x00002000 /* has CMPXCHG16B instruction */ 189 #define CPUID2_xTPR 0x00004000 /* Task Priority Messages disabled? */ 190 #define CPUID2_PDCM 0x00008000 /* Perf/Debug Capability MSR */ 191 #define CPUID2_DCA 0x00040000 /* Direct Cache Access */ 192 #define CPUID2_SSE41 0x00080000 /* Streaming SIMD Extensions 4.1 */ 193 #define CPUID2_SSE42 0x00100000 /* Streaming SIMD Extensions 4.2 */ 194 #define CPUID2_X2APIC 0x00200000 /* xAPIC Extensions */ 195 #define CPUID2_POPCNT 0x00800000 196 197 #define CPUID2_FLAGS "\20\1SSE3\3DTES64\4MONITOR\5DS-CPL\6VMX\7SMX\10EST" \ 198 "\11TM2\12SSSE3\13CID\16CX16\17xTPR\20PDCM\23DCA" \ 199 "\24SSE41\25SSE42\26X2APIC\30POPCNT" 200 201 #define CPUID2FAMILY(cpuid) (((cpuid) >> 8) & 0xf) 202 #define CPUID2MODEL(cpuid) (((cpuid) >> 4) & 0xf) 203 #define CPUID2STEPPING(cpuid) ((cpuid) & 0xf) 204 205 /* Extended family and model are defined on amd64 processors */ 206 #define CPUID2EXTFAMILY(cpuid) (((cpuid) >> 20) & 0xff) 207 #define CPUID2EXTMODEL(cpuid) (((cpuid) >> 16) & 0xf) 208 209 /* 210 * Model-specific registers for the i386 family 211 */ 212 #define MSR_P5_MC_ADDR 0x000 /* P5 only */ 213 #define MSR_P5_MC_TYPE 0x001 /* P5 only */ 214 #define MSR_TSC 0x010 215 #define MSR_CESR 0x011 /* P5 only (trap on P6) */ 216 #define MSR_CTR0 0x012 /* P5 only (trap on P6) */ 217 #define MSR_CTR1 0x013 /* P5 only (trap on P6) */ 218 #define MSR_APICBASE 0x01b 219 #define MSR_EBL_CR_POWERON 0x02a 220 #define MSR_EBC_FREQUENCY_ID 0x02c /* PIV only */ 221 #define MSR_TEST_CTL 0x033 222 #define MSR_BIOS_UPDT_TRIG 0x079 223 #define MSR_BBL_CR_D0 0x088 /* PII+ only */ 224 #define MSR_BBL_CR_D1 0x089 /* PII+ only */ 225 #define MSR_BBL_CR_D2 0x08a /* PII+ only */ 226 #define MSR_BIOS_SIGN 0x08b 227 #define MSR_PERFCTR0 0x0c1 228 #define MSR_PERFCTR1 0x0c2 229 #define MSR_FSB_FREQ 0x0cd /* Core Duo/Solo only */ 230 #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ 231 #define MSR_MTRRcap 0x0fe 232 #define MSR_BBL_CR_ADDR 0x116 /* PII+ only */ 233 #define MSR_BBL_CR_DECC 0x118 /* PII+ only */ 234 #define MSR_BBL_CR_CTL 0x119 /* PII+ only */ 235 #define MSR_BBL_CR_TRIG 0x11a /* PII+ only */ 236 #define MSR_BBL_CR_BUSY 0x11b /* PII+ only */ 237 #define MSR_BBL_CR_CTR3 0x11e /* PII+ only */ 238 #define MSR_SYSENTER_CS 0x174 /* PII+ only */ 239 #define MSR_SYSENTER_ESP 0x175 /* PII+ only */ 240 #define MSR_SYSENTER_EIP 0x176 /* PII+ only */ 241 #define MSR_MCG_CAP 0x179 242 #define MSR_MCG_STATUS 0x17a 243 #define MSR_MCG_CTL 0x17b 244 #define MSR_EVNTSEL0 0x186 245 #define MSR_EVNTSEL1 0x187 246 #define MSR_PERF_STATUS 0x198 /* Pentium M */ 247 #define MSR_PERF_CTL 0x199 /* Pentium M */ 248 #define MSR_THERM_CONTROL 0x19a 249 #define MSR_THERM_INTERRUPT 0x19b 250 #define MSR_THERM_STATUS 0x19c 251 #define MSR_THERM2_CTL 0x19d /* Pentium M */ 252 #define MSR_MISC_ENABLE 0x1a0 253 #define MSR_DEBUGCTLMSR 0x1d9 254 #define MSR_LASTBRANCHFROMIP 0x1db 255 #define MSR_LASTBRANCHTOIP 0x1dc 256 #define MSR_LASTINTFROMIP 0x1dd 257 #define MSR_LASTINTTOIP 0x1de 258 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 259 #define MSR_MTRRphysBase0 0x200 260 #define MSR_MTRRphysMask0 0x201 261 #define MSR_MTRRphysBase1 0x202 262 #define MSR_MTRRphysMask1 0x203 263 #define MSR_MTRRphysBase2 0x204 264 #define MSR_MTRRphysMask2 0x205 265 #define MSR_MTRRphysBase3 0x206 266 #define MSR_MTRRphysMask3 0x207 267 #define MSR_MTRRphysBase4 0x208 268 #define MSR_MTRRphysMask4 0x209 269 #define MSR_MTRRphysBase5 0x20a 270 #define MSR_MTRRphysMask5 0x20b 271 #define MSR_MTRRphysBase6 0x20c 272 #define MSR_MTRRphysMask6 0x20d 273 #define MSR_MTRRphysBase7 0x20e 274 #define MSR_MTRRphysMask7 0x20f 275 #define MSR_MTRRfix64K_00000 0x250 276 #define MSR_MTRRfix16K_80000 0x258 277 #define MSR_MTRRfix16K_A0000 0x259 278 #define MSR_MTRRfix4K_C0000 0x268 279 #define MSR_MTRRfix4K_C8000 0x269 280 #define MSR_MTRRfix4K_D0000 0x26a 281 #define MSR_MTRRfix4K_D8000 0x26b 282 #define MSR_MTRRfix4K_E0000 0x26c 283 #define MSR_MTRRfix4K_E8000 0x26d 284 #define MSR_MTRRfix4K_F0000 0x26e 285 #define MSR_MTRRfix4K_F8000 0x26f 286 #define MSR_MTRRdefType 0x2ff 287 #define MSR_MC0_CTL 0x400 288 #define MSR_MC0_STATUS 0x401 289 #define MSR_MC0_ADDR 0x402 290 #define MSR_MC0_MISC 0x403 291 #define MSR_MC1_CTL 0x404 292 #define MSR_MC1_STATUS 0x405 293 #define MSR_MC1_ADDR 0x406 294 #define MSR_MC1_MISC 0x407 295 #define MSR_MC2_CTL 0x408 296 #define MSR_MC2_STATUS 0x409 297 #define MSR_MC2_ADDR 0x40a 298 #define MSR_MC2_MISC 0x40b 299 #define MSR_MC4_CTL 0x40c 300 #define MSR_MC4_STATUS 0x40d 301 #define MSR_MC4_ADDR 0x40e 302 #define MSR_MC4_MISC 0x40f 303 #define MSR_MC3_CTL 0x410 304 #define MSR_MC3_STATUS 0x411 305 #define MSR_MC3_ADDR 0x412 306 #define MSR_MC3_MISC 0x413 307 308 /* 309 * VIA "Nehemiah" MSRs 310 */ 311 #define MSR_VIA_RNG 0x0000110b 312 #define MSR_VIA_RNG_ENABLE 0x00000040 313 #define MSR_VIA_RNG_NOISE_MASK 0x00000300 314 #define MSR_VIA_RNG_NOISE_A 0x00000000 315 #define MSR_VIA_RNG_NOISE_B 0x00000100 316 #define MSR_VIA_RNG_2NOISE 0x00000300 317 #define MSR_VIA_ACE 0x00001107 318 #define MSR_VIA_ACE_ENABLE 0x10000000 319 320 /* 321 * AMD K6/K7 MSRs. 322 */ 323 #define MSR_K6_UWCCR 0xc0000085 324 #define MSR_K7_EVNTSEL0 0xc0010000 325 #define MSR_K7_EVNTSEL1 0xc0010001 326 #define MSR_K7_EVNTSEL2 0xc0010002 327 #define MSR_K7_EVNTSEL3 0xc0010003 328 #define MSR_K7_PERFCTR0 0xc0010004 329 #define MSR_K7_PERFCTR1 0xc0010005 330 #define MSR_K7_PERFCTR2 0xc0010006 331 #define MSR_K7_PERFCTR3 0xc0010007 332 333 /* 334 * AMD K8 (Opteron) MSRs. 335 */ 336 #define MSR_SYSCFG 0xc0000010 337 338 #define MSR_EFER 0xc0000080 /* Extended feature enable */ 339 #define EFER_SCE 0x00000001 /* SYSCALL extension */ 340 #define EFER_LME 0x00000100 /* Long Mode Active */ 341 #define EFER_LMA 0x00000400 /* Long Mode Enabled */ 342 #define EFER_NXE 0x00000800 /* No-Execute Enabled */ 343 344 #define MSR_STAR 0xc0000081 /* 32 bit syscall gate addr */ 345 #define MSR_LSTAR 0xc0000082 /* 64 bit syscall gate addr */ 346 #define MSR_CSTAR 0xc0000083 /* compat syscall gate addr */ 347 #define MSR_SFMASK 0xc0000084 /* flags to clear on syscall */ 348 349 #define MSR_FSBASE 0xc0000100 /* 64bit offset for fs: */ 350 #define MSR_GSBASE 0xc0000101 /* 64bit offset for gs: */ 351 #define MSR_KERNELGSBASE 0xc0000102 /* storage for swapgs ins */ 352 353 /* 354 * These require a 'passcode' for access. See cpufunc.h. 355 */ 356 #define MSR_HWCR 0xc0010015 357 #define HWCR_FFDIS 0x00000040 358 359 #define MSR_NB_CFG 0xc001001f 360 #define NB_CFG_DISIOREQLOCK 0x0000000000000004ULL 361 #define NB_CFG_DISDATMSK 0x0000001000000000ULL 362 363 #define MSR_LS_CFG 0xc0011020 364 #define LS_CFG_DIS_LS2_SQUISH 0x02000000 365 366 #define MSR_IC_CFG 0xc0011021 367 #define IC_CFG_DIS_SEQ_PREFETCH 0x00000800 368 369 #define MSR_DC_CFG 0xc0011022 370 #define DC_CFG_DIS_CNV_WC_SSO 0x00000004 371 #define DC_CFG_DIS_SMC_CHK_BUF 0x00000400 372 373 #define MSR_BU_CFG 0xc0011023 374 #define BU_CFG_THRL2IDXCMPDIS 0x0000080000000000ULL 375 #define BU_CFG_WBPFSMCCHKDIS 0x0000200000000000ULL 376 #define BU_CFG_WBENHWSBDIS 0x0001000000000000ULL 377 378 /* 379 * Constants related to MTRRs 380 */ 381 #define MTRR_N64K 8 /* numbers of fixed-size entries */ 382 #define MTRR_N16K 16 383 #define MTRR_N4K 64 384 385 /* 386 * the following four 3-byte registers control the non-cacheable regions. 387 * These registers must be written as three separate bytes. 388 * 389 * NCRx+0: A31-A24 of starting address 390 * NCRx+1: A23-A16 of starting address 391 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 392 * 393 * The non-cacheable region's starting address must be aligned to the 394 * size indicated by the NCR_SIZE_xx field. 395 */ 396 #define NCR1 0xc4 397 #define NCR2 0xc7 398 #define NCR3 0xca 399 #define NCR4 0xcd 400 401 #define NCR_SIZE_0K 0 402 #define NCR_SIZE_4K 1 403 #define NCR_SIZE_8K 2 404 #define NCR_SIZE_16K 3 405 #define NCR_SIZE_32K 4 406 #define NCR_SIZE_64K 5 407 #define NCR_SIZE_128K 6 408 #define NCR_SIZE_256K 7 409 #define NCR_SIZE_512K 8 410 #define NCR_SIZE_1M 9 411 #define NCR_SIZE_2M 10 412 #define NCR_SIZE_4M 11 413 #define NCR_SIZE_8M 12 414 #define NCR_SIZE_16M 13 415 #define NCR_SIZE_32M 14 416 #define NCR_SIZE_4G 15 417 418 /* 419 * Performance monitor events. 420 * 421 * Note that 586-class and 686-class CPUs have different performance 422 * monitors available, and they are accessed differently: 423 * 424 * 686-class: `rdpmc' instruction 425 * 586-class: `rdmsr' instruction, CESR MSR 426 * 427 * The descriptions of these events are too lenghy to include here. 428 * See Appendix A of "Intel Architecture Software Developer's 429 * Manual, Volume 3: System Programming" for more information. 430 */ 431 432 /* 433 * 586-class CESR MSR format. Lower 16 bits is CTR0, upper 16 bits 434 * is CTR1. 435 */ 436 437 #define PMC5_CESR_EVENT 0x003f 438 #define PMC5_CESR_OS 0x0040 439 #define PMC5_CESR_USR 0x0080 440 #define PMC5_CESR_E 0x0100 441 #define PMC5_CESR_P 0x0200 442 443 #define PMC5_DATA_READ 0x00 444 #define PMC5_DATA_WRITE 0x01 445 #define PMC5_DATA_TLB_MISS 0x02 446 #define PMC5_DATA_READ_MISS 0x03 447 #define PMC5_DATA_WRITE_MISS 0x04 448 #define PMC5_WRITE_M_E 0x05 449 #define PMC5_DATA_LINES_WBACK 0x06 450 #define PMC5_DATA_CACHE_SNOOP 0x07 451 #define PMC5_DATA_CACHE_SNOOP_HIT 0x08 452 #define PMC5_MEM_ACCESS_BOTH_PIPES 0x09 453 #define PMC5_BANK_CONFLICTS 0x0a 454 #define PMC5_MISALIGNED_DATA 0x0b 455 #define PMC5_INST_READ 0x0c 456 #define PMC5_INST_TLB_MISS 0x0d 457 #define PMC5_INST_CACHE_MISS 0x0e 458 #define PMC5_SEGMENT_REG_LOAD 0x0f 459 #define PMC5_BRANCHES 0x12 460 #define PMC5_BTB_HITS 0x13 461 #define PMC5_BRANCH_TAKEN 0x14 462 #define PMC5_PIPELINE_FLUSH 0x15 463 #define PMC5_INST_EXECUTED 0x16 464 #define PMC5_INST_EXECUTED_V_PIPE 0x17 465 #define PMC5_BUS_UTILIZATION 0x18 466 #define PMC5_WRITE_BACKUP_STALL 0x19 467 #define PMC5_DATA_READ_STALL 0x1a 468 #define PMC5_WRITE_E_M_STALL 0x1b 469 #define PMC5_LOCKED_BUS 0x1c 470 #define PMC5_IO_CYCLE 0x1d 471 #define PMC5_NONCACHE_MEM_READ 0x1e 472 #define PMC5_AGI_STALL 0x1f 473 #define PMC5_FLOPS 0x22 474 #define PMC5_BP0_MATCH 0x23 475 #define PMC5_BP1_MATCH 0x24 476 #define PMC5_BP2_MATCH 0x25 477 #define PMC5_BP3_MATCH 0x26 478 #define PMC5_HARDWARE_INTR 0x27 479 #define PMC5_DATA_RW 0x28 480 #define PMC5_DATA_RW_MISS 0x29 481 482 /* 483 * 686-class Event Selector MSR format. 484 */ 485 486 #define PMC6_EVTSEL_EVENT 0x000000ff 487 #define PMC6_EVTSEL_UNIT 0x0000ff00 488 #define PMC6_EVTSEL_UNIT_SHIFT 8 489 #define PMC6_EVTSEL_USR (1 << 16) 490 #define PMC6_EVTSEL_OS (1 << 17) 491 #define PMC6_EVTSEL_E (1 << 18) 492 #define PMC6_EVTSEL_PC (1 << 19) 493 #define PMC6_EVTSEL_INT (1 << 20) 494 #define PMC6_EVTSEL_EN (1 << 22) /* PerfEvtSel0 only */ 495 #define PMC6_EVTSEL_INV (1 << 23) 496 #define PMC6_EVTSEL_COUNTER_MASK 0xff000000 497 #define PMC6_EVTSEL_COUNTER_MASK_SHIFT 24 498 499 /* Data Cache Unit */ 500 #define PMC6_DATA_MEM_REFS 0x43 501 #define PMC6_DCU_LINES_IN 0x45 502 #define PMC6_DCU_M_LINES_IN 0x46 503 #define PMC6_DCU_M_LINES_OUT 0x47 504 #define PMC6_DCU_MISS_OUTSTANDING 0x48 505 506 /* Instruction Fetch Unit */ 507 #define PMC6_IFU_IFETCH 0x80 508 #define PMC6_IFU_IFETCH_MISS 0x81 509 #define PMC6_ITLB_MISS 0x85 510 #define PMC6_IFU_MEM_STALL 0x86 511 #define PMC6_ILD_STALL 0x87 512 513 /* L2 Cache */ 514 #define PMC6_L2_IFETCH 0x28 515 #define PMC6_L2_LD 0x29 516 #define PMC6_L2_ST 0x2a 517 #define PMC6_L2_LINES_IN 0x24 518 #define PMC6_L2_LINES_OUT 0x26 519 #define PMC6_L2_M_LINES_INM 0x25 520 #define PMC6_L2_M_LINES_OUTM 0x27 521 #define PMC6_L2_RQSTS 0x2e 522 #define PMC6_L2_ADS 0x21 523 #define PMC6_L2_DBUS_BUSY 0x22 524 #define PMC6_L2_DBUS_BUSY_RD 0x23 525 526 /* External Bus Logic */ 527 #define PMC6_BUS_DRDY_CLOCKS 0x62 528 #define PMC6_BUS_LOCK_CLOCKS 0x63 529 #define PMC6_BUS_REQ_OUTSTANDING 0x60 530 #define PMC6_BUS_TRAN_BRD 0x65 531 #define PMC6_BUS_TRAN_RFO 0x66 532 #define PMC6_BUS_TRANS_WB 0x67 533 #define PMC6_BUS_TRAN_IFETCH 0x68 534 #define PMC6_BUS_TRAN_INVAL 0x69 535 #define PMC6_BUS_TRAN_PWR 0x6a 536 #define PMC6_BUS_TRANS_P 0x6b 537 #define PMC6_BUS_TRANS_IO 0x6c 538 #define PMC6_BUS_TRAN_DEF 0x6d 539 #define PMC6_BUS_TRAN_BURST 0x6e 540 #define PMC6_BUS_TRAN_ANY 0x70 541 #define PMC6_BUS_TRAN_MEM 0x6f 542 #define PMC6_BUS_DATA_RCV 0x64 543 #define PMC6_BUS_BNR_DRV 0x61 544 #define PMC6_BUS_HIT_DRV 0x7a 545 #define PMC6_BUS_HITM_DRDV 0x7b 546 #define PMC6_BUS_SNOOP_STALL 0x7e 547 548 /* Floating Point Unit */ 549 #define PMC6_FLOPS 0xc1 550 #define PMC6_FP_COMP_OPS_EXE 0x10 551 #define PMC6_FP_ASSIST 0x11 552 #define PMC6_MUL 0x12 553 #define PMC6_DIV 0x12 554 #define PMC6_CYCLES_DIV_BUSY 0x14 555 556 /* Memory Ordering */ 557 #define PMC6_LD_BLOCKS 0x03 558 #define PMC6_SB_DRAINS 0x04 559 #define PMC6_MISALIGN_MEM_REF 0x05 560 #define PMC6_EMON_KNI_PREF_DISPATCHED 0x07 /* P-III only */ 561 #define PMC6_EMON_KNI_PREF_MISS 0x4b /* P-III only */ 562 563 /* Instruction Decoding and Retirement */ 564 #define PMC6_INST_RETIRED 0xc0 565 #define PMC6_UOPS_RETIRED 0xc2 566 #define PMC6_INST_DECODED 0xd0 567 #define PMC6_EMON_KNI_INST_RETIRED 0xd8 568 #define PMC6_EMON_KNI_COMP_INST_RET 0xd9 569 570 /* Interrupts */ 571 #define PMC6_HW_INT_RX 0xc8 572 #define PMC6_CYCLES_INT_MASKED 0xc6 573 #define PMC6_CYCLES_INT_PENDING_AND_MASKED 0xc7 574 575 /* Branches */ 576 #define PMC6_BR_INST_RETIRED 0xc4 577 #define PMC6_BR_MISS_PRED_RETIRED 0xc5 578 #define PMC6_BR_TAKEN_RETIRED 0xc9 579 #define PMC6_BR_MISS_PRED_TAKEN_RET 0xca 580 #define PMC6_BR_INST_DECODED 0xe0 581 #define PMC6_BTB_MISSES 0xe2 582 #define PMC6_BR_BOGUS 0xe4 583 #define PMC6_BACLEARS 0xe6 584 585 /* Stalls */ 586 #define PMC6_RESOURCE_STALLS 0xa2 587 #define PMC6_PARTIAL_RAT_STALLS 0xd2 588 589 /* Segment Register Loads */ 590 #define PMC6_SEGMENT_REG_LOADS 0x06 591 592 /* Clocks */ 593 #define PMC6_CPU_CLK_UNHALTED 0x79 594 595 /* MMX Unit */ 596 #define PMC6_MMX_INSTR_EXEC 0xb0 /* Celeron, P-II, P-IIX only */ 597 #define PMC6_MMX_SAT_INSTR_EXEC 0xb1 /* P-II and P-III only */ 598 #define PMC6_MMX_UOPS_EXEC 0xb2 /* P-II and P-III only */ 599 #define PMC6_MMX_INSTR_TYPE_EXEC 0xb3 /* P-II and P-III only */ 600 #define PMC6_FP_MMX_TRANS 0xcc /* P-II and P-III only */ 601 #define PMC6_MMX_ASSIST 0xcd /* P-II and P-III only */ 602 #define PMC6_MMX_INSTR_RET 0xc3 /* P-II only */ 603 604 /* Segment Register Renaming */ 605 #define PMC6_SEG_RENAME_STALLS 0xd4 /* P-II and P-III only */ 606 #define PMC6_SEG_REG_RENAMES 0xd5 /* P-II and P-III only */ 607 #define PMC6_RET_SEG_RENAMES 0xd6 /* P-II and P-III only */ 608 609 /* 610 * AMD K7 Event Selector MSR format. 611 */ 612 613 #define K7_EVTSEL_EVENT 0x000000ff 614 #define K7_EVTSEL_UNIT 0x0000ff00 615 #define K7_EVTSEL_UNIT_SHIFT 8 616 #define K7_EVTSEL_USR (1 << 16) 617 #define K7_EVTSEL_OS (1 << 17) 618 #define K7_EVTSEL_E (1 << 18) 619 #define K7_EVTSEL_PC (1 << 19) 620 #define K7_EVTSEL_INT (1 << 20) 621 #define K7_EVTSEL_EN (1 << 22) 622 #define K7_EVTSEL_INV (1 << 23) 623 #define K7_EVTSEL_COUNTER_MASK 0xff000000 624 #define K7_EVTSEL_COUNTER_MASK_SHIFT 24 625 626 /* Segment Register Loads */ 627 #define K7_SEGMENT_REG_LOADS 0x20 628 629 #define K7_STORES_TO_ACTIVE_INST_STREAM 0x21 630 631 /* Data Cache Unit */ 632 #define K7_DATA_CACHE_ACCESS 0x40 633 #define K7_DATA_CACHE_MISS 0x41 634 #define K7_DATA_CACHE_REFILL 0x42 635 #define K7_DATA_CACHE_REFILL_SYSTEM 0x43 636 #define K7_DATA_CACHE_WBACK 0x44 637 #define K7_L2_DTLB_HIT 0x45 638 #define K7_L2_DTLB_MISS 0x46 639 #define K7_MISALIGNED_DATA_REF 0x47 640 #define K7_SYSTEM_REQUEST 0x64 641 #define K7_SYSTEM_REQUEST_TYPE 0x65 642 643 #define K7_SNOOP_HIT 0x73 644 #define K7_SINGLE_BIT_ECC_ERROR 0x74 645 #define K7_CACHE_LINE_INVAL 0x75 646 #define K7_CYCLES_PROCESSOR_IS_RUNNING 0x76 647 #define K7_L2_REQUEST 0x79 648 #define K7_L2_REQUEST_BUSY 0x7a 649 650 /* Instruction Fetch Unit */ 651 #define K7_IFU_IFETCH 0x80 652 #define K7_IFU_IFETCH_MISS 0x81 653 #define K7_IFU_REFILL_FROM_L2 0x82 654 #define K7_IFU_REFILL_FROM_SYSTEM 0x83 655 #define K7_ITLB_L1_MISS 0x84 656 #define K7_ITLB_L2_MISS 0x85 657 #define K7_SNOOP_RESYNC 0x86 658 #define K7_IFU_STALL 0x87 659 660 #define K7_RETURN_STACK_HITS 0x88 661 #define K7_RETURN_STACK_OVERFLOW 0x89 662 663 /* Retired */ 664 #define K7_RETIRED_INST 0xc0 665 #define K7_RETIRED_OPS 0xc1 666 #define K7_RETIRED_BRANCHES 0xc2 667 #define K7_RETIRED_BRANCH_MISPREDICTED 0xc3 668 #define K7_RETIRED_TAKEN_BRANCH 0xc4 669 #define K7_RETIRED_TAKEN_BRANCH_MISPREDICTED 0xc5 670 #define K7_RETIRED_FAR_CONTROL_TRANSFER 0xc6 671 #define K7_RETIRED_RESYNC_BRANCH 0xc7 672 #define K7_RETIRED_NEAR_RETURNS 0xc8 673 #define K7_RETIRED_NEAR_RETURNS_MISPREDICTED 0xc9 674 #define K7_RETIRED_INDIRECT_MISPREDICTED 0xca 675 676 /* Interrupts */ 677 #define K7_CYCLES_INT_MASKED 0xcd 678 #define K7_CYCLES_INT_PENDING_AND_MASKED 0xce 679 #define K7_HW_INTR_RECV 0xcf 680 681 #define K7_INSTRUCTION_DECODER_EMPTY 0xd0 682 #define K7_DISPATCH_STALLS 0xd1 683 #define K7_BRANCH_ABORTS_TO_RETIRE 0xd2 684 #define K7_SERIALIZE 0xd3 685 #define K7_SEGMENT_LOAD_STALL 0xd4 686 #define K7_ICU_FULL 0xd5 687 #define K7_RESERVATION_STATIONS_FULL 0xd6 688 #define K7_FPU_FULL 0xd7 689 #define K7_LS_FULL 0xd8 690 #define K7_ALL_QUIET_STALL 0xd9 691 #define K7_FAR_TRANSFER_OR_RESYNC_BRANCH_PENDING 0xda 692 693 #define K7_BP0_MATCH 0xdc 694 #define K7_BP1_MATCH 0xdd 695 #define K7_BP2_MATCH 0xde 696 #define K7_BP3_MATCH 0xdf 697
Indexes created Sun Sep 28 16:09:52 GMT 2025