specialreg.h revision 1.3
1 /* $NetBSD: specialreg.h,v 1.3 2003/08/07 16:30:33 agc Exp $ */ 2 3 /*- 4 * Copyright (c) 1991 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of the University nor the names of its contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * @(#)specialreg.h 7.1 (Berkeley) 5/9/91 32 */ 33 34 /* 35 * Bits in 386 special registers: 36 */ 37 #define CR0_PE 0x00000001 /* Protected mode Enable */ 38 #define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */ 39 #define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */ 40 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 41 #define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */ 42 #define CR0_PG 0x80000000 /* PaGing enable */ 43 44 /* 45 * Bits in 486 special registers: 46 */ 47 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 48 #define CR0_WP 0x00010000 /* Write Protect (honor PG_RW in all modes) */ 49 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 50 #define CR0_NW 0x20000000 /* Not Write-through */ 51 #define CR0_CD 0x40000000 /* Cache Disable */ 52 53 /* 54 * Cyrix 486 DLC special registers, accessible as IO ports. 55 */ 56 #define CCR0 0xc0 /* configuration control register 0 */ 57 #define CCR0_NC0 0x01 /* first 64K of each 1M memory region is non-cacheable */ 58 #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 59 #define CCR0_A20M 0x04 /* enables A20M# input pin */ 60 #define CCR0_KEN 0x08 /* enables KEN# input pin */ 61 #define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */ 62 #define CCR0_BARB 0x20 /* flushes internal cache when entering hold state */ 63 #define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */ 64 #define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */ 65 66 #define CCR1 0xc1 /* configuration control register 1 */ 67 #define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */ 68 /* the remaining 7 bits of this register are reserved */ 69 70 /* 71 * bits in the pentiums %cr4 register: 72 */ 73 74 #define CR4_VME 0x00000001 /* virtual 8086 mode extension enable */ 75 #define CR4_PVI 0x00000002 /* protected mode virtual interrupt enable */ 76 #define CR4_TSD 0x00000004 /* restrict RDTSC instruction to cpl 0 only */ 77 #define CR4_DE 0x00000008 /* debugging extension */ 78 #define CR4_PSE 0x00000010 /* large (4MB) page size enable */ 79 #define CR4_PAE 0x00000020 /* physical address extension enable */ 80 #define CR4_MCE 0x00000040 /* machine check enable */ 81 #define CR4_PGE 0x00000080 /* page global enable */ 82 #define CR4_PCE 0x00000100 /* enable RDPMC instruction for all cpls */ 83 #define CR4_OSFXSR 0x00000200 /* enable fxsave/fxrestor and SSE */ 84 #define CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */ 85 86 /* 87 * CPUID "features" bits: 88 */ 89 90 #define CPUID_FPU 0x00000001 /* processor has an FPU? */ 91 #define CPUID_VME 0x00000002 /* has virtual mode (%cr4's VME/PVI) */ 92 #define CPUID_DE 0x00000004 /* has debugging extension */ 93 #define CPUID_PSE 0x00000008 /* has page 4MB page size extension */ 94 #define CPUID_TSC 0x00000010 /* has time stamp counter */ 95 #define CPUID_MSR 0x00000020 /* has mode specific registers */ 96 #define CPUID_PAE 0x00000040 /* has phys address extension */ 97 #define CPUID_MCE 0x00000080 /* has machine check exception */ 98 #define CPUID_CX8 0x00000100 /* has CMPXCHG8B instruction */ 99 #define CPUID_APIC 0x00000200 /* has enabled APIC */ 100 #define CPUID_B10 0x00000400 /* reserved, MTRR */ 101 #define CPUID_SEP 0x00000800 /* has SYSENTER/SYSEXIT extension */ 102 #define CPUID_MTRR 0x00001000 /* has memory type range register */ 103 #define CPUID_PGE 0x00002000 /* has page global extension */ 104 #define CPUID_MCA 0x00004000 /* has machine check architecture */ 105 #define CPUID_CMOV 0x00008000 /* has CMOVcc instruction */ 106 #define CPUID_PAT 0x00010000 /* Page Attribute Table */ 107 #define CPUID_PSE36 0x00020000 /* 36-bit PSE */ 108 #define CPUID_PN 0x00040000 /* processor serial number */ 109 #define CPUID_CFLUSH 0x00080000 /* CFLUSH insn supported */ 110 #define CPUID_B20 0x00100000 /* reserved */ 111 #define CPUID_DS 0x00200000 /* Debug Store */ 112 #define CPUID_ACPI 0x00400000 /* ACPI performance modulation regs */ 113 #define CPUID_MMX 0x00800000 /* MMX supported */ 114 #define CPUID_FXSR 0x01000000 /* fast FP/MMX save/restore */ 115 #define CPUID_SSE 0x02000000 /* streaming SIMD extensions */ 116 #define CPUID_SSE2 0x04000000 /* streaming SIMD extensions #2 */ 117 #define CPUID_SS 0x08000000 /* self-snoop */ 118 #define CPUID_HTT 0x10000000 /* Hyper-Threading Technology */ 119 #define CPUID_TM 0x20000000 /* thermal monitor (TCC) */ 120 #define CPUID_IA64 0x40000000 /* IA-64 architecture */ 121 #define CPUID_SBF 0x80000000 /* signal break on FERR */ 122 123 #define CPUID_FLAGS1 "\20\1FPU\2VME\3DE\4PSE\5TSC\6MSR\7PAE" \ 124 "\10MCE\11CX8\12APIC\13B10\14SEP\15MTRR" 125 #define CPUID_MASK1 0x00001fff 126 #define CPUID_FLAGS2 "\20\16PGE\17MCA\20CMOV\21PAT\22PSE36\23PN\24CFLUSH" \ 127 "\25B20\26DS\27ACPI\30MMX" 128 #define CPUID_MASK2 0x00ffe000 129 #define CPUID_FLAGS3 "\20\31FXSR\32SSE\33SSE2\34SS\35HTT\36TM\37IA64\40SBF" 130 #define CPUID_MASK3 0xff000000 131 132 /* 133 * AMD/VIA processor specific flags. 134 */ 135 136 #define CPUID_MPC 0x00080000 /* Multiprocessing Capable */ 137 #define CPUID_MMXX 0x00400000 /* AMD MMX Extensions */ 138 #define CPUID_3DNOW2 0x40000000 /* 3DNow! Instruction Extension */ 139 #define CPUID_3DNOW 0x80000000 /* 3DNow! Instructions */ 140 141 #define CPUID_EXT_FLAGS2 "\20\16PGE\17MCA\20CMOV\21PAT\22PSE36\23PN" \ 142 "\24MPC\25NOX\26B21\27MMXX\30MMX" 143 #define CPUID_EXT_FLAGS3 "\20\31FXSR\32SSE\33SSE2\34B27\35B28\36LONG" \ 144 "\0373DNOW2\0403DNOW" 145 146 #define CPUID2FAMILY(cpuid) (((cpuid) >> 8) & 15) 147 #define CPUID2MODEL(cpuid) (((cpuid) >> 4) & 15) 148 #define CPUID2STEPPING(cpuid) ((cpuid) & 15) 149 150 #define CPUID(code, eax, ebx, ecx, edx) \ 151 __asm("cpuid" \ 152 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) \ 153 : "a" (code)); 154 155 156 /* 157 * Model-specific registers for the i386 family 158 */ 159 #define MSR_P5_MC_ADDR 0x000 /* P5 only */ 160 #define MSR_P5_MC_TYPE 0x001 /* P5 only */ 161 #define MSR_TSC 0x010 162 #define MSR_CESR 0x011 /* P5 only (trap on P6) */ 163 #define MSR_CTR0 0x012 /* P5 only (trap on P6) */ 164 #define MSR_CTR1 0x013 /* P5 only (trap on P6) */ 165 #define MSR_APICBASE 0x01b 166 #define MSR_EBL_CR_POWERON 0x02a 167 #define MSR_TEST_CTL 0x033 168 #define MSR_BIOS_UPDT_TRIG 0x079 169 #define MSR_BBL_CR_D0 0x088 /* PII+ only */ 170 #define MSR_BBL_CR_D1 0x089 /* PII+ only */ 171 #define MSR_BBL_CR_D2 0x08a /* PII+ only */ 172 #define MSR_BIOS_SIGN 0x08b 173 #define MSR_PERFCTR0 0x0c1 174 #define MSR_PERFCTR1 0x0c2 175 #define MSR_MTRRcap 0x0fe 176 #define MSR_BBL_CR_ADDR 0x116 /* PII+ only */ 177 #define MSR_BBL_CR_DECC 0x118 /* PII+ only */ 178 #define MSR_BBL_CR_CTL 0x119 /* PII+ only */ 179 #define MSR_BBL_CR_TRIG 0x11a /* PII+ only */ 180 #define MSR_BBL_CR_BUSY 0x11b /* PII+ only */ 181 #define MSR_BBL_CR_CTR3 0x11e /* PII+ only */ 182 #define MSR_SYSENTER_CS 0x174 /* PII+ only */ 183 #define MSR_SYSENTER_ESP 0x175 /* PII+ only */ 184 #define MSR_SYSENTER_EIP 0x176 /* PII+ only */ 185 #define MSR_MCG_CAP 0x179 186 #define MSR_MCG_STATUS 0x17a 187 #define MSR_MCG_CTL 0x17b 188 #define MSR_EVNTSEL0 0x186 189 #define MSR_EVNTSEL1 0x187 190 #define MSR_DEBUGCTLMSR 0x1d9 191 #define MSR_LASTBRANCHFROMIP 0x1db 192 #define MSR_LASTBRANCHTOIP 0x1dc 193 #define MSR_LASTINTFROMIP 0x1dd 194 #define MSR_LASTINTTOIP 0x1de 195 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 196 #define MSR_MTRRphysBase0 0x200 197 #define MSR_MTRRphysMask0 0x201 198 #define MSR_MTRRphysBase1 0x202 199 #define MSR_MTRRphysMask1 0x203 200 #define MSR_MTRRphysBase2 0x204 201 #define MSR_MTRRphysMask2 0x205 202 #define MSR_MTRRphysBase3 0x206 203 #define MSR_MTRRphysMask3 0x207 204 #define MSR_MTRRphysBase4 0x208 205 #define MSR_MTRRphysMask4 0x209 206 #define MSR_MTRRphysBase5 0x20a 207 #define MSR_MTRRphysMask5 0x20b 208 #define MSR_MTRRphysBase6 0x20c 209 #define MSR_MTRRphysMask6 0x20d 210 #define MSR_MTRRphysBase7 0x20e 211 #define MSR_MTRRphysMask7 0x20f 212 #define MSR_MTRRfix64K_00000 0x250 213 #define MSR_MTRRfix16K_80000 0x258 214 #define MSR_MTRRfix16K_A0000 0x259 215 #define MSR_MTRRfix4K_C0000 0x268 216 #define MSR_MTRRfix4K_C8000 0x269 217 #define MSR_MTRRfix4K_D0000 0x26a 218 #define MSR_MTRRfix4K_D8000 0x26b 219 #define MSR_MTRRfix4K_E0000 0x26c 220 #define MSR_MTRRfix4K_E8000 0x26d 221 #define MSR_MTRRfix4K_F0000 0x26e 222 #define MSR_MTRRfix4K_F8000 0x26f 223 #define MSR_MTRRdefType 0x2ff 224 #define MSR_MC0_CTL 0x400 225 #define MSR_MC0_STATUS 0x401 226 #define MSR_MC0_ADDR 0x402 227 #define MSR_MC0_MISC 0x403 228 #define MSR_MC1_CTL 0x404 229 #define MSR_MC1_STATUS 0x405 230 #define MSR_MC1_ADDR 0x406 231 #define MSR_MC1_MISC 0x407 232 #define MSR_MC2_CTL 0x408 233 #define MSR_MC2_STATUS 0x409 234 #define MSR_MC2_ADDR 0x40a 235 #define MSR_MC2_MISC 0x40b 236 #define MSR_MC4_CTL 0x40c 237 #define MSR_MC4_STATUS 0x40d 238 #define MSR_MC4_ADDR 0x40e 239 #define MSR_MC4_MISC 0x40f 240 #define MSR_MC3_CTL 0x410 241 #define MSR_MC3_STATUS 0x411 242 #define MSR_MC3_ADDR 0x412 243 #define MSR_MC3_MISC 0x413 244 245 /* 246 * AMD K6/K7 MSRs. 247 */ 248 #define MSR_K6_UWCCR 0xc0000085 249 #define MSR_K7_EVNTSEL0 0xc0010000 250 #define MSR_K7_EVNTSEL1 0xc0010001 251 #define MSR_K7_EVNTSEL2 0xc0010002 252 #define MSR_K7_EVNTSEL3 0xc0010003 253 #define MSR_K7_PERFCTR0 0xc0010004 254 #define MSR_K7_PERFCTR1 0xc0010005 255 #define MSR_K7_PERFCTR2 0xc0010006 256 #define MSR_K7_PERFCTR3 0xc0010007 257 258 /* 259 * Constants related to MTRRs 260 */ 261 #define MTRR_N64K 8 /* numbers of fixed-size entries */ 262 #define MTRR_N16K 16 263 #define MTRR_N4K 64 264 265 /* 266 * the following four 3-byte registers control the non-cacheable regions. 267 * These registers must be written as three separate bytes. 268 * 269 * NCRx+0: A31-A24 of starting address 270 * NCRx+1: A23-A16 of starting address 271 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 272 * 273 * The non-cacheable region's starting address must be aligned to the 274 * size indicated by the NCR_SIZE_xx field. 275 */ 276 #define NCR1 0xc4 277 #define NCR2 0xc7 278 #define NCR3 0xca 279 #define NCR4 0xcd 280 281 #define NCR_SIZE_0K 0 282 #define NCR_SIZE_4K 1 283 #define NCR_SIZE_8K 2 284 #define NCR_SIZE_16K 3 285 #define NCR_SIZE_32K 4 286 #define NCR_SIZE_64K 5 287 #define NCR_SIZE_128K 6 288 #define NCR_SIZE_256K 7 289 #define NCR_SIZE_512K 8 290 #define NCR_SIZE_1M 9 291 #define NCR_SIZE_2M 10 292 #define NCR_SIZE_4M 11 293 #define NCR_SIZE_8M 12 294 #define NCR_SIZE_16M 13 295 #define NCR_SIZE_32M 14 296 #define NCR_SIZE_4G 15 297 298 /* 299 * Performance monitor events. 300 * 301 * Note that 586-class and 686-class CPUs have different performance 302 * monitors available, and they are accessed differently: 303 * 304 * 686-class: `rdpmc' instruction 305 * 586-class: `rdmsr' instruction, CESR MSR 306 * 307 * The descriptions of these events are too lenghy to include here. 308 * See Appendix A of "Intel Architecture Software Developer's 309 * Manual, Volume 3: System Programming" for more information. 310 */ 311 312 /* 313 * 586-class CESR MSR format. Lower 16 bits is CTR0, upper 16 bits 314 * is CTR1. 315 */ 316 317 #define PMC5_CESR_EVENT 0x003f 318 #define PMC5_CESR_OS 0x0040 319 #define PMC5_CESR_USR 0x0080 320 #define PMC5_CESR_E 0x0100 321 #define PMC5_CESR_P 0x0200 322 323 #define PMC5_DATA_READ 0x00 324 #define PMC5_DATA_WRITE 0x01 325 #define PMC5_DATA_TLB_MISS 0x02 326 #define PMC5_DATA_READ_MISS 0x03 327 #define PMC5_DATA_WRITE_MISS 0x04 328 #define PMC5_WRITE_M_E 0x05 329 #define PMC5_DATA_LINES_WBACK 0x06 330 #define PMC5_DATA_CACHE_SNOOP 0x07 331 #define PMC5_DATA_CACHE_SNOOP_HIT 0x08 332 #define PMC5_MEM_ACCESS_BOTH_PIPES 0x09 333 #define PMC5_BANK_CONFLICTS 0x0a 334 #define PMC5_MISALIGNED_DATA 0x0b 335 #define PMC5_INST_READ 0x0c 336 #define PMC5_INST_TLB_MISS 0x0d 337 #define PMC5_INST_CACHE_MISS 0x0e 338 #define PMC5_SEGMENT_REG_LOAD 0x0f 339 #define PMC5_BRANCHES 0x12 340 #define PMC5_BTB_HITS 0x13 341 #define PMC5_BRANCH_TAKEN 0x14 342 #define PMC5_PIPELINE_FLUSH 0x15 343 #define PMC5_INST_EXECUTED 0x16 344 #define PMC5_INST_EXECUTED_V_PIPE 0x17 345 #define PMC5_BUS_UTILIZATION 0x18 346 #define PMC5_WRITE_BACKUP_STALL 0x19 347 #define PMC5_DATA_READ_STALL 0x1a 348 #define PMC5_WRITE_E_M_STALL 0x1b 349 #define PMC5_LOCKED_BUS 0x1c 350 #define PMC5_IO_CYCLE 0x1d 351 #define PMC5_NONCACHE_MEM_READ 0x1e 352 #define PMC5_AGI_STALL 0x1f 353 #define PMC5_FLOPS 0x22 354 #define PMC5_BP0_MATCH 0x23 355 #define PMC5_BP1_MATCH 0x24 356 #define PMC5_BP2_MATCH 0x25 357 #define PMC5_BP3_MATCH 0x26 358 #define PMC5_HARDWARE_INTR 0x27 359 #define PMC5_DATA_RW 0x28 360 #define PMC5_DATA_RW_MISS 0x29 361 362 /* 363 * 686-class Event Selector MSR format. 364 */ 365 366 #define PMC6_EVTSEL_EVENT 0x000000ff 367 #define PMC6_EVTSEL_UNIT 0x0000ff00 368 #define PMC6_EVTSEL_UNIT_SHIFT 8 369 #define PMC6_EVTSEL_USR (1 << 16) 370 #define PMC6_EVTSEL_OS (1 << 17) 371 #define PMC6_EVTSEL_E (1 << 18) 372 #define PMC6_EVTSEL_PC (1 << 19) 373 #define PMC6_EVTSEL_INT (1 << 20) 374 #define PMC6_EVTSEL_EN (1 << 22) /* PerfEvtSel0 only */ 375 #define PMC6_EVTSEL_INV (1 << 23) 376 #define PMC6_EVTSEL_COUNTER_MASK 0xff000000 377 #define PMC6_EVTSEL_COUNTER_MASK_SHIFT 24 378 379 /* Data Cache Unit */ 380 #define PMC6_DATA_MEM_REFS 0x43 381 #define PMC6_DCU_LINES_IN 0x45 382 #define PMC6_DCU_M_LINES_IN 0x46 383 #define PMC6_DCU_M_LINES_OUT 0x47 384 #define PMC6_DCU_MISS_OUTSTANDING 0x48 385 386 /* Instruction Fetch Unit */ 387 #define PMC6_IFU_IFETCH 0x80 388 #define PMC6_IFU_IFETCH_MISS 0x81 389 #define PMC6_ITLB_MISS 0x85 390 #define PMC6_IFU_MEM_STALL 0x86 391 #define PMC6_ILD_STALL 0x87 392 393 /* L2 Cache */ 394 #define PMC6_L2_IFETCH 0x28 395 #define PMC6_L2_LD 0x29 396 #define PMC6_L2_ST 0x2a 397 #define PMC6_L2_LINES_IN 0x24 398 #define PMC6_L2_LINES_OUT 0x26 399 #define PMC6_L2_M_LINES_INM 0x25 400 #define PMC6_L2_M_LINES_OUTM 0x27 401 #define PMC6_L2_RQSTS 0x2e 402 #define PMC6_L2_ADS 0x21 403 #define PMC6_L2_DBUS_BUSY 0x22 404 #define PMC6_L2_DBUS_BUSY_RD 0x23 405 406 /* External Bus Logic */ 407 #define PMC6_BUS_DRDY_CLOCKS 0x62 408 #define PMC6_BUS_LOCK_CLOCKS 0x63 409 #define PMC6_BUS_REQ_OUTSTANDING 0x60 410 #define PMC6_BUS_TRAN_BRD 0x65 411 #define PMC6_BUS_TRAN_RFO 0x66 412 #define PMC6_BUS_TRANS_WB 0x67 413 #define PMC6_BUS_TRAN_IFETCH 0x68 414 #define PMC6_BUS_TRAN_INVAL 0x69 415 #define PMC6_BUS_TRAN_PWR 0x6a 416 #define PMC6_BUS_TRANS_P 0x6b 417 #define PMC6_BUS_TRANS_IO 0x6c 418 #define PMC6_BUS_TRAN_DEF 0x6d 419 #define PMC6_BUS_TRAN_BURST 0x6e 420 #define PMC6_BUS_TRAN_ANY 0x70 421 #define PMC6_BUS_TRAN_MEM 0x6f 422 #define PMC6_BUS_DATA_RCV 0x64 423 #define PMC6_BUS_BNR_DRV 0x61 424 #define PMC6_BUS_HIT_DRV 0x7a 425 #define PMC6_BUS_HITM_DRDV 0x7b 426 #define PMC6_BUS_SNOOP_STALL 0x7e 427 428 /* Floating Point Unit */ 429 #define PMC6_FLOPS 0xc1 430 #define PMC6_FP_COMP_OPS_EXE 0x10 431 #define PMC6_FP_ASSIST 0x11 432 #define PMC6_MUL 0x12 433 #define PMC6_DIV 0x12 434 #define PMC6_CYCLES_DIV_BUSY 0x14 435 436 /* Memory Ordering */ 437 #define PMC6_LD_BLOCKS 0x03 438 #define PMC6_SB_DRAINS 0x04 439 #define PMC6_MISALIGN_MEM_REF 0x05 440 #define PMC6_EMON_KNI_PREF_DISPATCHED 0x07 /* P-III only */ 441 #define PMC6_EMON_KNI_PREF_MISS 0x4b /* P-III only */ 442 443 /* Instruction Decoding and Retirement */ 444 #define PMC6_INST_RETIRED 0xc0 445 #define PMC6_UOPS_RETIRED 0xc2 446 #define PMC6_INST_DECODED 0xd0 447 #define PMC6_EMON_KNI_INST_RETIRED 0xd8 448 #define PMC6_EMON_KNI_COMP_INST_RET 0xd9 449 450 /* Interrupts */ 451 #define PMC6_HW_INT_RX 0xc8 452 #define PMC6_CYCLES_INT_MASKED 0xc6 453 #define PMC6_CYCLES_INT_PENDING_AND_MASKED 0xc7 454 455 /* Branches */ 456 #define PMC6_BR_INST_RETIRED 0xc4 457 #define PMC6_BR_MISS_PRED_RETIRED 0xc5 458 #define PMC6_BR_TAKEN_RETIRED 0xc9 459 #define PMC6_BR_MISS_PRED_TAKEN_RET 0xca 460 #define PMC6_BR_INST_DECODED 0xe0 461 #define PMC6_BTB_MISSES 0xe2 462 #define PMC6_BR_BOGUS 0xe4 463 #define PMC6_BACLEARS 0xe6 464 465 /* Stalls */ 466 #define PMC6_RESOURCE_STALLS 0xa2 467 #define PMC6_PARTIAL_RAT_STALLS 0xd2 468 469 /* Segment Register Loads */ 470 #define PMC6_SEGMENT_REG_LOADS 0x06 471 472 /* Clocks */ 473 #define PMC6_CPU_CLK_UNHALTED 0x79 474 475 /* MMX Unit */ 476 #define PMC6_MMX_INSTR_EXEC 0xb0 /* Celeron, P-II, P-IIX only */ 477 #define PMC6_MMX_SAT_INSTR_EXEC 0xb1 /* P-II and P-III only */ 478 #define PMC6_MMX_UOPS_EXEC 0xb2 /* P-II and P-III only */ 479 #define PMC6_MMX_INSTR_TYPE_EXEC 0xb3 /* P-II and P-III only */ 480 #define PMC6_FP_MMX_TRANS 0xcc /* P-II and P-III only */ 481 #define PMC6_MMX_ASSIST 0xcd /* P-II and P-III only */ 482 #define PMC6_MMX_INSTR_RET 0xc3 /* P-II only */ 483 484 /* Segment Register Renaming */ 485 #define PMC6_SEG_RENAME_STALLS 0xd4 /* P-II and P-III only */ 486 #define PMC6_SEG_REG_RENAMES 0xd5 /* P-II and P-III only */ 487 #define PMC6_RET_SEG_RENAMES 0xd6 /* P-II and P-III only */ 488 489 /* 490 * AMD K7 Event Selector MSR format. 491 */ 492 493 #define K7_EVTSEL_EVENT 0x000000ff 494 #define K7_EVTSEL_UNIT 0x0000ff00 495 #define K7_EVTSEL_UNIT_SHIFT 8 496 #define K7_EVTSEL_USR (1 << 16) 497 #define K7_EVTSEL_OS (1 << 17) 498 #define K7_EVTSEL_E (1 << 18) 499 #define K7_EVTSEL_PC (1 << 19) 500 #define K7_EVTSEL_INT (1 << 20) 501 #define K7_EVTSEL_EN (1 << 22) 502 #define K7_EVTSEL_INV (1 << 23) 503 #define K7_EVTSEL_COUNTER_MASK 0xff000000 504 #define K7_EVTSEL_COUNTER_MASK_SHIFT 24 505 506 /* Segment Register Loads */ 507 #define K7_SEGMENT_REG_LOADS 0x20 508 509 #define K7_STORES_TO_ACTIVE_INST_STREAM 0x21 510 511 /* Data Cache Unit */ 512 #define K7_DATA_CACHE_ACCESS 0x40 513 #define K7_DATA_CACHE_MISS 0x41 514 #define K7_DATA_CACHE_REFILL 0x42 515 #define K7_DATA_CACHE_REFILL_SYSTEM 0x43 516 #define K7_DATA_CACHE_WBACK 0x44 517 #define K7_L2_DTLB_HIT 0x45 518 #define K7_L2_DTLB_MISS 0x46 519 #define K7_MISALIGNED_DATA_REF 0x47 520 #define K7_SYSTEM_REQUEST 0x64 521 #define K7_SYSTEM_REQUEST_TYPE 0x65 522 523 #define K7_SNOOP_HIT 0x73 524 #define K7_SINGLE_BIT_ECC_ERROR 0x74 525 #define K7_CACHE_LINE_INVAL 0x75 526 #define K7_CYCLES_PROCESSOR_IS_RUNNING 0x76 527 #define K7_L2_REQUEST 0x79 528 #define K7_L2_REQUEST_BUSY 0x7a 529 530 /* Instruction Fetch Unit */ 531 #define K7_IFU_IFETCH 0x80 532 #define K7_IFU_IFETCH_MISS 0x81 533 #define K7_IFU_REFILL_FROM_L2 0x82 534 #define K7_IFU_REFILL_FROM_SYSTEM 0x83 535 #define K7_ITLB_L1_MISS 0x84 536 #define K7_ITLB_L2_MISS 0x85 537 #define K7_SNOOP_RESYNC 0x86 538 #define K7_IFU_STALL 0x87 539 540 #define K7_RETURN_STACK_HITS 0x88 541 #define K7_RETURN_STACK_OVERFLOW 0x89 542 543 /* Retired */ 544 #define K7_RETIRED_INST 0xc0 545 #define K7_RETIRED_OPS 0xc1 546 #define K7_RETIRED_BRANCHES 0xc2 547 #define K7_RETIRED_BRANCH_MISPREDICTED 0xc3 548 #define K7_RETIRED_TAKEN_BRANCH 0xc4 549 #define K7_RETIRED_TAKEN_BRANCH_MISPREDICTED 0xc5 550 #define K7_RETIRED_FAR_CONTROL_TRANSFER 0xc6 551 #define K7_RETIRED_RESYNC_BRANCH 0xc7 552 #define K7_RETIRED_NEAR_RETURNS 0xc8 553 #define K7_RETIRED_NEAR_RETURNS_MISPREDICTED 0xc9 554 #define K7_RETIRED_INDIRECT_MISPREDICTED 0xca 555 556 /* Interrupts */ 557 #define K7_CYCLES_INT_MASKED 0xcd 558 #define K7_CYCLES_INT_PENDING_AND_MASKED 0xce 559 #define K7_HW_INTR_RECV 0xcf 560 561 #define K7_INSTRUCTION_DECODER_EMPTY 0xd0 562 #define K7_DISPATCH_STALLS 0xd1 563 #define K7_BRANCH_ABORTS_TO_RETIRE 0xd2 564 #define K7_SERIALIZE 0xd3 565 #define K7_SEGMENT_LOAD_STALL 0xd4 566 #define K7_ICU_FULL 0xd5 567 #define K7_RESERVATION_STATIONS_FULL 0xd6 568 #define K7_FPU_FULL 0xd7 569 #define K7_LS_FULL 0xd8 570 #define K7_ALL_QUIET_STALL 0xd9 571 #define K7_FAR_TRANSFER_OR_RESYNC_BRANCH_PENDING 0xda 572 573 #define K7_BP0_MATCH 0xdc 574 #define K7_BP1_MATCH 0xdd 575 #define K7_BP2_MATCH 0xde 576 #define K7_BP3_MATCH 0xdf 577
Indexes created Sun Sep 28 12:09:53 GMT 2025