specialreg.h revision 1.52
1 /* $NetBSD: specialreg.h,v 1.52 2011/07/26 12:59:41 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 1991 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of the University nor the names of its contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * @(#)specialreg.h 7.1 (Berkeley) 5/9/91 32 */ 33 34 /* 35 * Bits in 386 special registers: 36 */ 37 #define CR0_PE 0x00000001 /* Protected mode Enable */ 38 #define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */ 39 #define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */ 40 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 41 #define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */ 42 #define CR0_PG 0x80000000 /* PaGing enable */ 43 44 /* 45 * Bits in 486 special registers: 46 */ 47 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 48 #define CR0_WP 0x00010000 /* Write Protect (honor PG_RW in all modes) */ 49 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 50 #define CR0_NW 0x20000000 /* Not Write-through */ 51 #define CR0_CD 0x40000000 /* Cache Disable */ 52 53 /* 54 * Cyrix 486 DLC special registers, accessible as IO ports. 55 */ 56 #define CCR0 0xc0 /* configuration control register 0 */ 57 #define CCR0_NC0 0x01 /* first 64K of each 1M memory region is non-cacheable */ 58 #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 59 #define CCR0_A20M 0x04 /* enables A20M# input pin */ 60 #define CCR0_KEN 0x08 /* enables KEN# input pin */ 61 #define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */ 62 #define CCR0_BARB 0x20 /* flushes internal cache when entering hold state */ 63 #define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */ 64 #define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */ 65 66 #define CCR1 0xc1 /* configuration control register 1 */ 67 #define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */ 68 /* the remaining 7 bits of this register are reserved */ 69 70 /* 71 * bits in the pentiums %cr4 register: 72 */ 73 74 #define CR4_VME 0x00000001 /* virtual 8086 mode extension enable */ 75 #define CR4_PVI 0x00000002 /* protected mode virtual interrupt enable */ 76 #define CR4_TSD 0x00000004 /* restrict RDTSC instruction to cpl 0 only */ 77 #define CR4_DE 0x00000008 /* debugging extension */ 78 #define CR4_PSE 0x00000010 /* large (4MB) page size enable */ 79 #define CR4_PAE 0x00000020 /* physical address extension enable */ 80 #define CR4_MCE 0x00000040 /* machine check enable */ 81 #define CR4_PGE 0x00000080 /* page global enable */ 82 #define CR4_PCE 0x00000100 /* enable RDPMC instruction for all cpls */ 83 #define CR4_OSFXSR 0x00000200 /* enable fxsave/fxrestor and SSE */ 84 #define CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */ 85 86 /* 87 * CPUID "features" bits 88 */ 89 90 /* Fn00000001 %edx features */ 91 #define CPUID_FPU 0x00000001 /* processor has an FPU? */ 92 #define CPUID_VME 0x00000002 /* has virtual mode (%cr4's VME/PVI) */ 93 #define CPUID_DE 0x00000004 /* has debugging extension */ 94 #define CPUID_PSE 0x00000008 /* has page 4MB page size extension */ 95 #define CPUID_TSC 0x00000010 /* has time stamp counter */ 96 #define CPUID_MSR 0x00000020 /* has mode specific registers */ 97 #define CPUID_PAE 0x00000040 /* has phys address extension */ 98 #define CPUID_MCE 0x00000080 /* has machine check exception */ 99 #define CPUID_CX8 0x00000100 /* has CMPXCHG8B instruction */ 100 #define CPUID_APIC 0x00000200 /* has enabled APIC */ 101 #define CPUID_B10 0x00000400 /* reserved, MTRR */ 102 #define CPUID_SEP 0x00000800 /* has SYSENTER/SYSEXIT extension */ 103 #define CPUID_MTRR 0x00001000 /* has memory type range register */ 104 #define CPUID_PGE 0x00002000 /* has page global extension */ 105 #define CPUID_MCA 0x00004000 /* has machine check architecture */ 106 #define CPUID_CMOV 0x00008000 /* has CMOVcc instruction */ 107 #define CPUID_PAT 0x00010000 /* Page Attribute Table */ 108 #define CPUID_PSE36 0x00020000 /* 36-bit PSE */ 109 #define CPUID_PN 0x00040000 /* processor serial number */ 110 #define CPUID_CFLUSH 0x00080000 /* CFLUSH insn supported */ 111 #define CPUID_B20 0x00100000 /* reserved */ 112 #define CPUID_DS 0x00200000 /* Debug Store */ 113 #define CPUID_ACPI 0x00400000 /* ACPI performance modulation regs */ 114 #define CPUID_MMX 0x00800000 /* MMX supported */ 115 #define CPUID_FXSR 0x01000000 /* fast FP/MMX save/restore */ 116 #define CPUID_SSE 0x02000000 /* streaming SIMD extensions */ 117 #define CPUID_SSE2 0x04000000 /* streaming SIMD extensions #2 */ 118 #define CPUID_SS 0x08000000 /* self-snoop */ 119 #define CPUID_HTT 0x10000000 /* Hyper-Threading Technology */ 120 #define CPUID_TM 0x20000000 /* thermal monitor (TCC) */ 121 #define CPUID_IA64 0x40000000 /* IA-64 architecture */ 122 #define CPUID_SBF 0x80000000 /* signal break on FERR */ 123 124 #define CPUID_FLAGS1 "\20\1FPU\2VME\3DE\4PSE\5TSC\6MSR\7PAE\10MCE\11CX8" \ 125 "\12APIC\13B10\14SEP\15MTRR\16PGE\17MCA\20CMOV" \ 126 "\21PAT\22PSE36\23PN\24CFLUSH\25B20\26DS\27ACPI" \ 127 "\30MMX\31FXSR\32SSE\33SSE2\34SS\35HTT\36TM" \ 128 "\37IA64\40SBF" 129 130 /* 131 * Intel Digital Thermal Sensor and 132 * Power Management, Fn0000_0006 - %eax. 133 */ 134 #define CPUID_DSPM_DTS 0x00000001 /* Digital Thermal Sensor */ 135 #define CPUID_DSPM_IDA 0x00000002 /* Intel Dynamic Acceleration */ 136 #define CPUID_DSPM_ARAT 0x00000004 /* Always Running APIC Timer */ 137 #define CPUID_DSPM_PLN 0x00000010 /* Power Limit Notification */ 138 #define CPUID_DSPM_CME 0x00000020 /* Clock Modulation Extension */ 139 #define CPUID_DSPM_PLTM 0x00000040 /* Package Level Thermal Management */ 140 141 #define CPUID_DSPM_FLAGS "\20\1DTS\2IDA\3ARAT\5PLN\6CME\7PLTM" 142 143 /* 144 * Intel Digital Thermal Sensor and 145 * Power Management, Fn0000_0006 - %ecx. 146 */ 147 #define CPUID_DSPM_HWF 0x00000001 /* MSR_APERF/MSR_MPERF available */ 148 149 #define CPUID_DSPM_FLAGS1 "\20\1HWF" 150 151 /* Intel Fn80000001 extended features - %edx */ 152 #define CPUID_SYSCALL 0x00000800 /* SYSCALL/SYSRET */ 153 #define CPUID_XD 0x00100000 /* Execute Disable (like CPUID_NOX) */ 154 #define CPUID_EM64T 0x20000000 /* Intel EM64T */ 155 156 #define CPUID_INTEL_EXT_FLAGS "\20\14SYSCALL/SYSRET\25XD\36EM64T" 157 158 /* Intel Fn80000001 extended features - %ecx */ 159 #define CPUID_LAHF 0x00000001 /* LAHF/SAHF in IA-32e mode, 64bit sub*/ 160 161 #define CPUID_INTEL_FLAGS4 "\20\1LAHF\02B02\03B03" 162 163 164 /* AMD/VIA Fn80000001 extended features - %edx */ 165 /* CPUID_SYSCALL SYSCALL/SYSRET */ 166 #define CPUID_MPC 0x00080000 /* Multiprocessing Capable */ 167 #define CPUID_NOX 0x00100000 /* No Execute Page Protection */ 168 #define CPUID_MMXX 0x00400000 /* AMD MMX Extensions */ 169 #define CPUID_FFXSR 0x02000000 /* FXSAVE/FXSTOR Extensions */ 170 #define CPUID_P1GB 0x04000000 /* 1GB Large Page Support */ 171 #define CPUID_RDTSCP 0x08000000 /* Read TSC Pair Instruction */ 172 /* CPUID_EM64T Long mode */ 173 #define CPUID_3DNOW2 0x40000000 /* 3DNow! Instruction Extension */ 174 #define CPUID_3DNOW 0x80000000 /* 3DNow! Instructions */ 175 176 #define CPUID_EXT_FLAGS "\20\14SYSCALL/SYSRET\24MPC\25NOX" \ 177 "\27MXX\32FFXSR\33P1GB\34RDTSCP" \ 178 "\36LONG\0373DNOW2\0403DNOW" \ 179 180 /* AMD Fn80000001 extended features - %ecx */ 181 #define CPUID_LAHF 0x00000001 /* LAHF/SAHF instruction */ 182 #define CPUID_CMPLEGACY 0x00000002 /* Compare Legacy */ 183 #define CPUID_SVM 0x00000004 /* Secure Virtual Machine */ 184 #define CPUID_EAPIC 0x00000008 /* Extended APIC space */ 185 #define CPUID_ALTMOVCR0 0x00000010 /* Lock Mov Cr0 */ 186 #define CPUID_LZCNT 0x00000020 /* LZCNT instruction */ 187 #define CPUID_SSE4A 0x00000040 /* SSE4A instruction set */ 188 #define CPUID_MISALIGNSSE 0x00000080 /* Misaligned SSE */ 189 #define CPUID_3DNOWPF 0x00000100 /* 3DNow Prefetch */ 190 #define CPUID_OSVW 0x00000200 /* OS visible workarounds */ 191 #define CPUID_IBS 0x00000400 /* Instruction Based Sampling */ 192 #define CPUID_XOP 0x00000800 /* XOP instruction set */ 193 #define CPUID_SKINIT 0x00001000 /* SKINIT */ 194 #define CPUID_WDT 0x00002000 /* watchdog timer support */ 195 #define CPUID_LWP 0x00008000 /* Light Weight Profiling */ 196 #define CPUID_FMA4 0x00010000 /* FMA4 instructions */ 197 #define CPUID_NODEID 0x00080000 /* NodeID MSR available*/ 198 #define CPUID_TBM 0x00200000 /* TBM instructions */ 199 #define CPUID_TOPOEXT 0x00400000 /* cpuid Topology Extension */ 200 201 #define CPUID_AMD_FLAGS4 "\20\1LAHF\2CMPLEGACY\3SVM\4EAPIC\5ALTMOVCR0" \ 202 "\6LZCNT\7SSE4A\10MISALIGNSSE" \ 203 "\0113DNOWPREFETCH\12OSVW\13IBS" \ 204 "\14XOP\15SKINIT\16WDT\20LWP" \ 205 "\21FMA4\22B17\23B18\24NodeID\25B20\26TBM" \ 206 "\27TopoExt\30B23\31B24" \ 207 "\32B25\33B25\34B26" \ 208 "\35B27\36B28\37B29\40B30\41B31\42B32" 209 210 /* AMD Fn8000000a %edx features (SVM features) */ 211 #define CPUID_AMD_SVM_NP 0x00000001 212 #define CPUID_AMD_SVM_LbrVirt 0x00000002 213 #define CPUID_AMD_SVM_SVML 0x00000004 214 #define CPUID_AMD_SVM_NRIPS 0x00000008 215 #define CPUID_AMD_SVM_TSCRateCtrl 0x00000010 216 #define CPUID_AMD_SVM_VMCBCleanBits 0x00000020 217 #define CPUID_AMD_SVM_FlushByASID 0x00000040 218 #define CPUID_AMD_SVM_DecodeAssist 0x00000080 219 #define CPUID_AMD_SVM_PauseFilter 0x00000400 220 #define CPUID_AMD_SVM_FLAGS "\20\1NP\2LbrVirt\3SVML\4NRIPS" \ 221 "\5TSCRate\6VMCBCleanBits\7FlushByASID" \ 222 "\10DecodeAssist\11B08" \ 223 "\12B09\13PauseFilter" \ 224 "\14B11\15B12" \ 225 "\16B13\17B17\20B18\21B19" 226 227 /* 228 * AMD Advanced Power Management 229 * CPUID Fn8000_0007 %edx 230 */ 231 #define CPUID_APM_TS 0x00000001 /* Temperature Sensor */ 232 #define CPUID_APM_FID 0x00000002 /* Frequency ID control */ 233 #define CPUID_APM_VID 0x00000004 /* Voltage ID control */ 234 #define CPUID_APM_TTP 0x00000008 /* THERMTRIP (PCI F3xE4 register) */ 235 #define CPUID_APM_HTC 0x00000010 /* Hardware thermal control (HTC) */ 236 #define CPUID_APM_STC 0x00000020 /* Software thermal control (STC) */ 237 #define CPUID_APM_100 0x00000040 /* 100MHz multiplier control */ 238 #define CPUID_APM_HWP 0x00000080 /* HW P-State control */ 239 #define CPUID_APM_TSC 0x00000100 /* TSC invariant */ 240 #define CPUID_APM_CPB 0x00000200 /* Core performance boost */ 241 #define CPUID_APM_EFF 0x00000400 /* Effective Frequency (read-only) */ 242 243 #define CPUID_APM_FLAGS "\20\1TS\2FID\3VID\4TTP\5HTC\6STC\007100" \ 244 "\10HWP\11TSC\12CPB\13EffFreq\14B11\15B12" 245 246 /* 247 * Centaur Extended Feature flags 248 */ 249 #define CPUID_VIA_HAS_RNG 0x00000004 /* Random number generator */ 250 #define CPUID_VIA_DO_RNG 0x00000008 251 #define CPUID_VIA_HAS_ACE 0x00000040 /* AES Encryption */ 252 #define CPUID_VIA_DO_ACE 0x00000080 253 #define CPUID_VIA_HAS_ACE2 0x00000100 /* AES+CTR instructions */ 254 #define CPUID_VIA_DO_ACE2 0x00000200 255 #define CPUID_VIA_HAS_PHE 0x00000400 /* SHA1+SHA256 HMAC */ 256 #define CPUID_VIA_DO_PHE 0x00000800 257 #define CPUID_VIA_HAS_PMM 0x00001000 /* RSA Instructions */ 258 #define CPUID_VIA_DO_PMM 0x00002000 259 260 #define CPUID_FLAGS_PADLOCK "\20\3RNG\7AES\11AES/CTR\13SHA1/SHA256\15RSA" 261 262 /* 263 * CPUID "features" bits in Fn00000001 %ecx 264 */ 265 266 #define CPUID2_SSE3 0x00000001 /* Streaming SIMD Extensions 3 */ 267 #define CPUID2_PCLMUL 0x00000002 /* PCLMULQDQ instructions */ 268 #define CPUID2_DTES64 0x00000004 /* 64-bit Debug Trace */ 269 #define CPUID2_MONITOR 0x00000008 /* MONITOR/MWAIT instructions */ 270 #define CPUID2_DS_CPL 0x00000010 /* CPL Qualified Debug Store */ 271 #define CPUID2_VMX 0x00000020 /* Virtual Machine Extensions */ 272 #define CPUID2_SMX 0x00000040 /* Safer Mode Extensions */ 273 #define CPUID2_EST 0x00000080 /* Enhanced SpeedStep Technology */ 274 #define CPUID2_TM2 0x00000100 /* Thermal Monitor 2 */ 275 #define CPUID2_SSSE3 0x00000200 /* Supplemental SSE3 */ 276 #define CPUID2_CID 0x00000400 /* Context ID */ 277 #define CPUID2_CX16 0x00002000 /* has CMPXCHG16B instruction */ 278 #define CPUID2_xTPR 0x00004000 /* Task Priority Messages disabled? */ 279 #define CPUID2_PDCM 0x00008000 /* Perf/Debug Capability MSR */ 280 #define CPUID2_PCID 0x00020000 /* Process Context ID */ 281 #define CPUID2_DCA 0x00040000 /* Direct Cache Access */ 282 #define CPUID2_SSE41 0x00080000 /* Streaming SIMD Extensions 4.1 */ 283 #define CPUID2_SSE42 0x00100000 /* Streaming SIMD Extensions 4.2 */ 284 #define CPUID2_X2APIC 0x00200000 /* xAPIC Extensions */ 285 #define CPUID2_POPCNT 0x00800000 /* popcount instruction available */ 286 #define CPUID2_AES 0x02000000 /* AES instructions */ 287 #define CPUID2_XSAVE 0x04000000 /* XSAVE instructions */ 288 #define CPUID2_OSXSAVE 0x08000000 /* XGETBV/XSETBV instructions */ 289 #define CPUID2_AVX 0x10000000 /* AVX instructions */ 290 #define CPUID2_F16C 0x20000000 /* half precision conversion */ 291 #define CPUID2_RAZ 0x80000000 /* RAZ. Indicates guest state. */ 292 293 #define CPUID2_FLAGS1 "\20\1SSE3\2PCLMULQDQ\3DTES64\4MONITOR\5DS-CPL\6VMX\7SMX" \ 294 "\10EST\11TM2\12SSSE3\13CID\14B11\15B12\16CX16" \ 295 "\17xTPR\20PDCM\21B16\22PCID\23DCA\24SSE41\25SSE42" \ 296 "\26X2APIC\27MOVBE\30POPCNT\31B24\32AES\33XSAVE" \ 297 "\34OSXSAVE\35AVX\36F16C\37B30\40RAZ" 298 299 #define CPUID2FAMILY(cpuid) (((cpuid) >> 8) & 0xf) 300 #define CPUID2MODEL(cpuid) (((cpuid) >> 4) & 0xf) 301 #define CPUID2STEPPING(cpuid) ((cpuid) & 0xf) 302 303 /* Extended family and model are defined on amd64 processors */ 304 #define CPUID2EXTFAMILY(cpuid) (((cpuid) >> 20) & 0xff) 305 #define CPUID2EXTMODEL(cpuid) (((cpuid) >> 16) & 0xf) 306 307 /* Blacklists of CPUID flags - used to mask certain features */ 308 #ifdef XEN 309 /* Not on Xen */ 310 #define CPUID_FEAT_BLACKLIST (CPUID_PGE|CPUID_PSE|CPUID_MTRR|CPUID_FXSR) 311 #else 312 #define CPUID_FEAT_BLACKLIST 0 313 #endif /* XEN */ 314 315 /* 316 * Model-specific registers for the i386 family 317 */ 318 #define MSR_P5_MC_ADDR 0x000 /* P5 only */ 319 #define MSR_P5_MC_TYPE 0x001 /* P5 only */ 320 #define MSR_TSC 0x010 321 #define MSR_CESR 0x011 /* P5 only (trap on P6) */ 322 #define MSR_CTR0 0x012 /* P5 only (trap on P6) */ 323 #define MSR_CTR1 0x013 /* P5 only (trap on P6) */ 324 #define MSR_APICBASE 0x01b 325 #define MSR_EBL_CR_POWERON 0x02a 326 #define MSR_EBC_FREQUENCY_ID 0x02c /* PIV only */ 327 #define MSR_TEST_CTL 0x033 328 #define MSR_BIOS_UPDT_TRIG 0x079 329 #define MSR_BBL_CR_D0 0x088 /* PII+ only */ 330 #define MSR_BBL_CR_D1 0x089 /* PII+ only */ 331 #define MSR_BBL_CR_D2 0x08a /* PII+ only */ 332 #define MSR_BIOS_SIGN 0x08b 333 #define MSR_PERFCTR0 0x0c1 334 #define MSR_PERFCTR1 0x0c2 335 #define MSR_FSB_FREQ 0x0cd /* Core Duo/Solo only */ 336 #define MSR_MPERF 0x0e7 337 #define MSR_APERF 0x0e8 338 #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ 339 #define MSR_MTRRcap 0x0fe 340 #define MSR_BBL_CR_ADDR 0x116 /* PII+ only */ 341 #define MSR_BBL_CR_DECC 0x118 /* PII+ only */ 342 #define MSR_BBL_CR_CTL 0x119 /* PII+ only */ 343 #define MSR_BBL_CR_TRIG 0x11a /* PII+ only */ 344 #define MSR_BBL_CR_BUSY 0x11b /* PII+ only */ 345 #define MSR_BBL_CR_CTR3 0x11e /* PII+ only */ 346 #define MSR_SYSENTER_CS 0x174 /* PII+ only */ 347 #define MSR_SYSENTER_ESP 0x175 /* PII+ only */ 348 #define MSR_SYSENTER_EIP 0x176 /* PII+ only */ 349 #define MSR_MCG_CAP 0x179 350 #define MSR_MCG_STATUS 0x17a 351 #define MSR_MCG_CTL 0x17b 352 #define MSR_EVNTSEL0 0x186 353 #define MSR_EVNTSEL1 0x187 354 #define MSR_PERF_STATUS 0x198 /* Pentium M */ 355 #define MSR_PERF_CTL 0x199 /* Pentium M */ 356 #define MSR_THERM_CONTROL 0x19a 357 #define MSR_THERM_INTERRUPT 0x19b 358 #define MSR_THERM_STATUS 0x19c 359 #define MSR_THERM2_CTL 0x19d /* Pentium M */ 360 #define MSR_MISC_ENABLE 0x1a0 361 #define MSR_TEMPERATURE_TARGET 0x1a2 362 #define MSR_DEBUGCTLMSR 0x1d9 363 #define MSR_LASTBRANCHFROMIP 0x1db 364 #define MSR_LASTBRANCHTOIP 0x1dc 365 #define MSR_LASTINTFROMIP 0x1dd 366 #define MSR_LASTINTTOIP 0x1de 367 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 368 #define MSR_MTRRphysBase0 0x200 369 #define MSR_MTRRphysMask0 0x201 370 #define MSR_MTRRphysBase1 0x202 371 #define MSR_MTRRphysMask1 0x203 372 #define MSR_MTRRphysBase2 0x204 373 #define MSR_MTRRphysMask2 0x205 374 #define MSR_MTRRphysBase3 0x206 375 #define MSR_MTRRphysMask3 0x207 376 #define MSR_MTRRphysBase4 0x208 377 #define MSR_MTRRphysMask4 0x209 378 #define MSR_MTRRphysBase5 0x20a 379 #define MSR_MTRRphysMask5 0x20b 380 #define MSR_MTRRphysBase6 0x20c 381 #define MSR_MTRRphysMask6 0x20d 382 #define MSR_MTRRphysBase7 0x20e 383 #define MSR_MTRRphysMask7 0x20f 384 #define MSR_MTRRfix64K_00000 0x250 385 #define MSR_MTRRfix16K_80000 0x258 386 #define MSR_MTRRfix16K_A0000 0x259 387 #define MSR_MTRRfix4K_C0000 0x268 388 #define MSR_MTRRfix4K_C8000 0x269 389 #define MSR_MTRRfix4K_D0000 0x26a 390 #define MSR_MTRRfix4K_D8000 0x26b 391 #define MSR_MTRRfix4K_E0000 0x26c 392 #define MSR_MTRRfix4K_E8000 0x26d 393 #define MSR_MTRRfix4K_F0000 0x26e 394 #define MSR_MTRRfix4K_F8000 0x26f 395 #define MSR_CR_PAT 0x277 396 #define MSR_MTRRdefType 0x2ff 397 #define MSR_MC0_CTL 0x400 398 #define MSR_MC0_STATUS 0x401 399 #define MSR_MC0_ADDR 0x402 400 #define MSR_MC0_MISC 0x403 401 #define MSR_MC1_CTL 0x404 402 #define MSR_MC1_STATUS 0x405 403 #define MSR_MC1_ADDR 0x406 404 #define MSR_MC1_MISC 0x407 405 #define MSR_MC2_CTL 0x408 406 #define MSR_MC2_STATUS 0x409 407 #define MSR_MC2_ADDR 0x40a 408 #define MSR_MC2_MISC 0x40b 409 #define MSR_MC4_CTL 0x40c 410 #define MSR_MC4_STATUS 0x40d 411 #define MSR_MC4_ADDR 0x40e 412 #define MSR_MC4_MISC 0x40f 413 #define MSR_MC3_CTL 0x410 414 #define MSR_MC3_STATUS 0x411 415 #define MSR_MC3_ADDR 0x412 416 #define MSR_MC3_MISC 0x413 417 /* 0x480 - 0x490 VMX */ 418 419 /* 420 * VIA "Nehemiah" MSRs 421 */ 422 #define MSR_VIA_RNG 0x0000110b 423 #define MSR_VIA_RNG_ENABLE 0x00000040 424 #define MSR_VIA_RNG_NOISE_MASK 0x00000300 425 #define MSR_VIA_RNG_NOISE_A 0x00000000 426 #define MSR_VIA_RNG_NOISE_B 0x00000100 427 #define MSR_VIA_RNG_2NOISE 0x00000300 428 #define MSR_VIA_ACE 0x00001107 429 #define MSR_VIA_ACE_ENABLE 0x10000000 430 431 /* 432 * AMD K6/K7 MSRs. 433 */ 434 #define MSR_K6_UWCCR 0xc0000085 435 #define MSR_K7_EVNTSEL0 0xc0010000 436 #define MSR_K7_EVNTSEL1 0xc0010001 437 #define MSR_K7_EVNTSEL2 0xc0010002 438 #define MSR_K7_EVNTSEL3 0xc0010003 439 #define MSR_K7_PERFCTR0 0xc0010004 440 #define MSR_K7_PERFCTR1 0xc0010005 441 #define MSR_K7_PERFCTR2 0xc0010006 442 #define MSR_K7_PERFCTR3 0xc0010007 443 444 /* 445 * AMD K8 (Opteron) MSRs. 446 */ 447 #define MSR_SYSCFG 0xc0000010 448 449 #define MSR_EFER 0xc0000080 /* Extended feature enable */ 450 #define EFER_SCE 0x00000001 /* SYSCALL extension */ 451 #define EFER_LME 0x00000100 /* Long Mode Active */ 452 #define EFER_LMA 0x00000400 /* Long Mode Enabled */ 453 #define EFER_NXE 0x00000800 /* No-Execute Enabled */ 454 455 #define MSR_STAR 0xc0000081 /* 32 bit syscall gate addr */ 456 #define MSR_LSTAR 0xc0000082 /* 64 bit syscall gate addr */ 457 #define MSR_CSTAR 0xc0000083 /* compat syscall gate addr */ 458 #define MSR_SFMASK 0xc0000084 /* flags to clear on syscall */ 459 460 #define MSR_FSBASE 0xc0000100 /* 64bit offset for fs: */ 461 #define MSR_GSBASE 0xc0000101 /* 64bit offset for gs: */ 462 #define MSR_KERNELGSBASE 0xc0000102 /* storage for swapgs ins */ 463 464 #define MSR_VMCR 0xc0010114 /* Virtual Machine Control Register */ 465 #define VMCR_DPD 0x00000001 /* Debug port disable */ 466 #define VMCR_RINIT 0x00000002 /* intercept init */ 467 #define VMCR_DISA20 0x00000004 /* Disable A20 masking */ 468 #define VMCR_LOCK 0x00000008 /* SVM Lock */ 469 #define VMCR_SVMED 0x00000010 /* SVME Disable */ 470 #define MSR_SVMLOCK 0xc0010118 /* SVM Lock key */ 471 472 /* 473 * These require a 'passcode' for access. See cpufunc.h. 474 */ 475 #define MSR_HWCR 0xc0010015 476 #define HWCR_TLBCACHEDIS 0x00000008 477 #define HWCR_FFDIS 0x00000040 478 479 #define MSR_NB_CFG 0xc001001f 480 #define NB_CFG_DISIOREQLOCK 0x0000000000000008ULL 481 #define NB_CFG_DISDATMSK 0x0000001000000000ULL 482 #define NB_CFG_INITAPICCPUIDLO (1ULL << 54) 483 484 #define MSR_LS_CFG 0xc0011020 485 #define LS_CFG_DIS_LS2_SQUISH 0x02000000 486 487 #define MSR_IC_CFG 0xc0011021 488 #define IC_CFG_DIS_SEQ_PREFETCH 0x00000800 489 490 #define MSR_DC_CFG 0xc0011022 491 #define DC_CFG_DIS_CNV_WC_SSO 0x00000008 492 #define DC_CFG_DIS_SMC_CHK_BUF 0x00000400 493 #define DC_CFG_ERRATA_261 0x01000000 494 495 #define MSR_BU_CFG 0xc0011023 496 #define BU_CFG_ERRATA_298 0x0000000000000002ULL 497 #define BU_CFG_ERRATA_254 0x0000000000200000ULL 498 #define BU_CFG_ERRATA_309 0x0000000000800000ULL 499 #define BU_CFG_THRL2IDXCMPDIS 0x0000080000000000ULL 500 #define BU_CFG_WBPFSMCCHKDIS 0x0000200000000000ULL 501 #define BU_CFG_WBENHWSBDIS 0x0001000000000000ULL 502 503 /* AMD Family10h MSRs */ 504 #define MSR_OSVW_ID_LENGTH 0xc0010140 505 #define MSR_OSVW_STATUS 0xc0010141 506 507 /* X86 MSRs */ 508 #define MSR_RDTSCP_AUX 0xc0000103 509 510 /* 511 * Constants related to MTRRs 512 */ 513 #define MTRR_N64K 8 /* numbers of fixed-size entries */ 514 #define MTRR_N16K 16 515 #define MTRR_N4K 64 516 517 /* 518 * the following four 3-byte registers control the non-cacheable regions. 519 * These registers must be written as three separate bytes. 520 * 521 * NCRx+0: A31-A24 of starting address 522 * NCRx+1: A23-A16 of starting address 523 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 524 * 525 * The non-cacheable region's starting address must be aligned to the 526 * size indicated by the NCR_SIZE_xx field. 527 */ 528 #define NCR1 0xc4 529 #define NCR2 0xc7 530 #define NCR3 0xca 531 #define NCR4 0xcd 532 533 #define NCR_SIZE_0K 0 534 #define NCR_SIZE_4K 1 535 #define NCR_SIZE_8K 2 536 #define NCR_SIZE_16K 3 537 #define NCR_SIZE_32K 4 538 #define NCR_SIZE_64K 5 539 #define NCR_SIZE_128K 6 540 #define NCR_SIZE_256K 7 541 #define NCR_SIZE_512K 8 542 #define NCR_SIZE_1M 9 543 #define NCR_SIZE_2M 10 544 #define NCR_SIZE_4M 11 545 #define NCR_SIZE_8M 12 546 #define NCR_SIZE_16M 13 547 #define NCR_SIZE_32M 14 548 #define NCR_SIZE_4G 15 549 550 /* 551 * Performance monitor events. 552 * 553 * Note that 586-class and 686-class CPUs have different performance 554 * monitors available, and they are accessed differently: 555 * 556 * 686-class: `rdpmc' instruction 557 * 586-class: `rdmsr' instruction, CESR MSR 558 * 559 * The descriptions of these events are too lenghy to include here. 560 * See Appendix A of "Intel Architecture Software Developer's 561 * Manual, Volume 3: System Programming" for more information. 562 */ 563 564 /* 565 * 586-class CESR MSR format. Lower 16 bits is CTR0, upper 16 bits 566 * is CTR1. 567 */ 568 569 #define PMC5_CESR_EVENT 0x003f 570 #define PMC5_CESR_OS 0x0040 571 #define PMC5_CESR_USR 0x0080 572 #define PMC5_CESR_E 0x0100 573 #define PMC5_CESR_P 0x0200 574 575 #define PMC5_DATA_READ 0x00 576 #define PMC5_DATA_WRITE 0x01 577 #define PMC5_DATA_TLB_MISS 0x02 578 #define PMC5_DATA_READ_MISS 0x03 579 #define PMC5_DATA_WRITE_MISS 0x04 580 #define PMC5_WRITE_M_E 0x05 581 #define PMC5_DATA_LINES_WBACK 0x06 582 #define PMC5_DATA_CACHE_SNOOP 0x07 583 #define PMC5_DATA_CACHE_SNOOP_HIT 0x08 584 #define PMC5_MEM_ACCESS_BOTH_PIPES 0x09 585 #define PMC5_BANK_CONFLICTS 0x0a 586 #define PMC5_MISALIGNED_DATA 0x0b 587 #define PMC5_INST_READ 0x0c 588 #define PMC5_INST_TLB_MISS 0x0d 589 #define PMC5_INST_CACHE_MISS 0x0e 590 #define PMC5_SEGMENT_REG_LOAD 0x0f 591 #define PMC5_BRANCHES 0x12 592 #define PMC5_BTB_HITS 0x13 593 #define PMC5_BRANCH_TAKEN 0x14 594 #define PMC5_PIPELINE_FLUSH 0x15 595 #define PMC5_INST_EXECUTED 0x16 596 #define PMC5_INST_EXECUTED_V_PIPE 0x17 597 #define PMC5_BUS_UTILIZATION 0x18 598 #define PMC5_WRITE_BACKUP_STALL 0x19 599 #define PMC5_DATA_READ_STALL 0x1a 600 #define PMC5_WRITE_E_M_STALL 0x1b 601 #define PMC5_LOCKED_BUS 0x1c 602 #define PMC5_IO_CYCLE 0x1d 603 #define PMC5_NONCACHE_MEM_READ 0x1e 604 #define PMC5_AGI_STALL 0x1f 605 #define PMC5_FLOPS 0x22 606 #define PMC5_BP0_MATCH 0x23 607 #define PMC5_BP1_MATCH 0x24 608 #define PMC5_BP2_MATCH 0x25 609 #define PMC5_BP3_MATCH 0x26 610 #define PMC5_HARDWARE_INTR 0x27 611 #define PMC5_DATA_RW 0x28 612 #define PMC5_DATA_RW_MISS 0x29 613 614 /* 615 * 686-class Event Selector MSR format. 616 */ 617 618 #define PMC6_EVTSEL_EVENT 0x000000ff 619 #define PMC6_EVTSEL_UNIT 0x0000ff00 620 #define PMC6_EVTSEL_UNIT_SHIFT 8 621 #define PMC6_EVTSEL_USR (1 << 16) 622 #define PMC6_EVTSEL_OS (1 << 17) 623 #define PMC6_EVTSEL_E (1 << 18) 624 #define PMC6_EVTSEL_PC (1 << 19) 625 #define PMC6_EVTSEL_INT (1 << 20) 626 #define PMC6_EVTSEL_EN (1 << 22) /* PerfEvtSel0 only */ 627 #define PMC6_EVTSEL_INV (1 << 23) 628 #define PMC6_EVTSEL_COUNTER_MASK 0xff000000 629 #define PMC6_EVTSEL_COUNTER_MASK_SHIFT 24 630 631 /* Data Cache Unit */ 632 #define PMC6_DATA_MEM_REFS 0x43 633 #define PMC6_DCU_LINES_IN 0x45 634 #define PMC6_DCU_M_LINES_IN 0x46 635 #define PMC6_DCU_M_LINES_OUT 0x47 636 #define PMC6_DCU_MISS_OUTSTANDING 0x48 637 638 /* Instruction Fetch Unit */ 639 #define PMC6_IFU_IFETCH 0x80 640 #define PMC6_IFU_IFETCH_MISS 0x81 641 #define PMC6_ITLB_MISS 0x85 642 #define PMC6_IFU_MEM_STALL 0x86 643 #define PMC6_ILD_STALL 0x87 644 645 /* L2 Cache */ 646 #define PMC6_L2_IFETCH 0x28 647 #define PMC6_L2_LD 0x29 648 #define PMC6_L2_ST 0x2a 649 #define PMC6_L2_LINES_IN 0x24 650 #define PMC6_L2_LINES_OUT 0x26 651 #define PMC6_L2_M_LINES_INM 0x25 652 #define PMC6_L2_M_LINES_OUTM 0x27 653 #define PMC6_L2_RQSTS 0x2e 654 #define PMC6_L2_ADS 0x21 655 #define PMC6_L2_DBUS_BUSY 0x22 656 #define PMC6_L2_DBUS_BUSY_RD 0x23 657 658 /* External Bus Logic */ 659 #define PMC6_BUS_DRDY_CLOCKS 0x62 660 #define PMC6_BUS_LOCK_CLOCKS 0x63 661 #define PMC6_BUS_REQ_OUTSTANDING 0x60 662 #define PMC6_BUS_TRAN_BRD 0x65 663 #define PMC6_BUS_TRAN_RFO 0x66 664 #define PMC6_BUS_TRANS_WB 0x67 665 #define PMC6_BUS_TRAN_IFETCH 0x68 666 #define PMC6_BUS_TRAN_INVAL 0x69 667 #define PMC6_BUS_TRAN_PWR 0x6a 668 #define PMC6_BUS_TRANS_P 0x6b 669 #define PMC6_BUS_TRANS_IO 0x6c 670 #define PMC6_BUS_TRAN_DEF 0x6d 671 #define PMC6_BUS_TRAN_BURST 0x6e 672 #define PMC6_BUS_TRAN_ANY 0x70 673 #define PMC6_BUS_TRAN_MEM 0x6f 674 #define PMC6_BUS_DATA_RCV 0x64 675 #define PMC6_BUS_BNR_DRV 0x61 676 #define PMC6_BUS_HIT_DRV 0x7a 677 #define PMC6_BUS_HITM_DRDV 0x7b 678 #define PMC6_BUS_SNOOP_STALL 0x7e 679 680 /* Floating Point Unit */ 681 #define PMC6_FLOPS 0xc1 682 #define PMC6_FP_COMP_OPS_EXE 0x10 683 #define PMC6_FP_ASSIST 0x11 684 #define PMC6_MUL 0x12 685 #define PMC6_DIV 0x12 686 #define PMC6_CYCLES_DIV_BUSY 0x14 687 688 /* Memory Ordering */ 689 #define PMC6_LD_BLOCKS 0x03 690 #define PMC6_SB_DRAINS 0x04 691 #define PMC6_MISALIGN_MEM_REF 0x05 692 #define PMC6_EMON_KNI_PREF_DISPATCHED 0x07 /* P-III only */ 693 #define PMC6_EMON_KNI_PREF_MISS 0x4b /* P-III only */ 694 695 /* Instruction Decoding and Retirement */ 696 #define PMC6_INST_RETIRED 0xc0 697 #define PMC6_UOPS_RETIRED 0xc2 698 #define PMC6_INST_DECODED 0xd0 699 #define PMC6_EMON_KNI_INST_RETIRED 0xd8 700 #define PMC6_EMON_KNI_COMP_INST_RET 0xd9 701 702 /* Interrupts */ 703 #define PMC6_HW_INT_RX 0xc8 704 #define PMC6_CYCLES_INT_MASKED 0xc6 705 #define PMC6_CYCLES_INT_PENDING_AND_MASKED 0xc7 706 707 /* Branches */ 708 #define PMC6_BR_INST_RETIRED 0xc4 709 #define PMC6_BR_MISS_PRED_RETIRED 0xc5 710 #define PMC6_BR_TAKEN_RETIRED 0xc9 711 #define PMC6_BR_MISS_PRED_TAKEN_RET 0xca 712 #define PMC6_BR_INST_DECODED 0xe0 713 #define PMC6_BTB_MISSES 0xe2 714 #define PMC6_BR_BOGUS 0xe4 715 #define PMC6_BACLEARS 0xe6 716 717 /* Stalls */ 718 #define PMC6_RESOURCE_STALLS 0xa2 719 #define PMC6_PARTIAL_RAT_STALLS 0xd2 720 721 /* Segment Register Loads */ 722 #define PMC6_SEGMENT_REG_LOADS 0x06 723 724 /* Clocks */ 725 #define PMC6_CPU_CLK_UNHALTED 0x79 726 727 /* MMX Unit */ 728 #define PMC6_MMX_INSTR_EXEC 0xb0 /* Celeron, P-II, P-IIX only */ 729 #define PMC6_MMX_SAT_INSTR_EXEC 0xb1 /* P-II and P-III only */ 730 #define PMC6_MMX_UOPS_EXEC 0xb2 /* P-II and P-III only */ 731 #define PMC6_MMX_INSTR_TYPE_EXEC 0xb3 /* P-II and P-III only */ 732 #define PMC6_FP_MMX_TRANS 0xcc /* P-II and P-III only */ 733 #define PMC6_MMX_ASSIST 0xcd /* P-II and P-III only */ 734 #define PMC6_MMX_INSTR_RET 0xc3 /* P-II only */ 735 736 /* Segment Register Renaming */ 737 #define PMC6_SEG_RENAME_STALLS 0xd4 /* P-II and P-III only */ 738 #define PMC6_SEG_REG_RENAMES 0xd5 /* P-II and P-III only */ 739 #define PMC6_RET_SEG_RENAMES 0xd6 /* P-II and P-III only */ 740 741 /* 742 * AMD K7 Event Selector MSR format. 743 */ 744 745 #define K7_EVTSEL_EVENT 0x000000ff 746 #define K7_EVTSEL_UNIT 0x0000ff00 747 #define K7_EVTSEL_UNIT_SHIFT 8 748 #define K7_EVTSEL_USR (1 << 16) 749 #define K7_EVTSEL_OS (1 << 17) 750 #define K7_EVTSEL_E (1 << 18) 751 #define K7_EVTSEL_PC (1 << 19) 752 #define K7_EVTSEL_INT (1 << 20) 753 #define K7_EVTSEL_EN (1 << 22) 754 #define K7_EVTSEL_INV (1 << 23) 755 #define K7_EVTSEL_COUNTER_MASK 0xff000000 756 #define K7_EVTSEL_COUNTER_MASK_SHIFT 24 757 758 /* Segment Register Loads */ 759 #define K7_SEGMENT_REG_LOADS 0x20 760 761 #define K7_STORES_TO_ACTIVE_INST_STREAM 0x21 762 763 /* Data Cache Unit */ 764 #define K7_DATA_CACHE_ACCESS 0x40 765 #define K7_DATA_CACHE_MISS 0x41 766 #define K7_DATA_CACHE_REFILL 0x42 767 #define K7_DATA_CACHE_REFILL_SYSTEM 0x43 768 #define K7_DATA_CACHE_WBACK 0x44 769 #define K7_L2_DTLB_HIT 0x45 770 #define K7_L2_DTLB_MISS 0x46 771 #define K7_MISALIGNED_DATA_REF 0x47 772 #define K7_SYSTEM_REQUEST 0x64 773 #define K7_SYSTEM_REQUEST_TYPE 0x65 774 775 #define K7_SNOOP_HIT 0x73 776 #define K7_SINGLE_BIT_ECC_ERROR 0x74 777 #define K7_CACHE_LINE_INVAL 0x75 778 #define K7_CYCLES_PROCESSOR_IS_RUNNING 0x76 779 #define K7_L2_REQUEST 0x79 780 #define K7_L2_REQUEST_BUSY 0x7a 781 782 /* Instruction Fetch Unit */ 783 #define K7_IFU_IFETCH 0x80 784 #define K7_IFU_IFETCH_MISS 0x81 785 #define K7_IFU_REFILL_FROM_L2 0x82 786 #define K7_IFU_REFILL_FROM_SYSTEM 0x83 787 #define K7_ITLB_L1_MISS 0x84 788 #define K7_ITLB_L2_MISS 0x85 789 #define K7_SNOOP_RESYNC 0x86 790 #define K7_IFU_STALL 0x87 791 792 #define K7_RETURN_STACK_HITS 0x88 793 #define K7_RETURN_STACK_OVERFLOW 0x89 794 795 /* Retired */ 796 #define K7_RETIRED_INST 0xc0 797 #define K7_RETIRED_OPS 0xc1 798 #define K7_RETIRED_BRANCHES 0xc2 799 #define K7_RETIRED_BRANCH_MISPREDICTED 0xc3 800 #define K7_RETIRED_TAKEN_BRANCH 0xc4 801 #define K7_RETIRED_TAKEN_BRANCH_MISPREDICTED 0xc5 802 #define K7_RETIRED_FAR_CONTROL_TRANSFER 0xc6 803 #define K7_RETIRED_RESYNC_BRANCH 0xc7 804 #define K7_RETIRED_NEAR_RETURNS 0xc8 805 #define K7_RETIRED_NEAR_RETURNS_MISPREDICTED 0xc9 806 #define K7_RETIRED_INDIRECT_MISPREDICTED 0xca 807 808 /* Interrupts */ 809 #define K7_CYCLES_INT_MASKED 0xcd 810 #define K7_CYCLES_INT_PENDING_AND_MASKED 0xce 811 #define K7_HW_INTR_RECV 0xcf 812 813 #define K7_INSTRUCTION_DECODER_EMPTY 0xd0 814 #define K7_DISPATCH_STALLS 0xd1 815 #define K7_BRANCH_ABORTS_TO_RETIRE 0xd2 816 #define K7_SERIALIZE 0xd3 817 #define K7_SEGMENT_LOAD_STALL 0xd4 818 #define K7_ICU_FULL 0xd5 819 #define K7_RESERVATION_STATIONS_FULL 0xd6 820 #define K7_FPU_FULL 0xd7 821 #define K7_LS_FULL 0xd8 822 #define K7_ALL_QUIET_STALL 0xd9 823 #define K7_FAR_TRANSFER_OR_RESYNC_BRANCH_PENDING 0xda 824 825 #define K7_BP0_MATCH 0xdc 826 #define K7_BP1_MATCH 0xdd 827 #define K7_BP2_MATCH 0xde 828 #define K7_BP3_MATCH 0xdf 829
Indexes created Mon Sep 29 15:09:53 GMT 2025