specialreg.h revision 1.65
1 /* $NetBSD: specialreg.h,v 1.65 2013/07/25 16:34:29 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1991 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of the University nor the names of its contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * @(#)specialreg.h 7.1 (Berkeley) 5/9/91 32 */ 33 34 /* 35 * Bits in 386 special registers: 36 */ 37 #define CR0_PE 0x00000001 /* Protected mode Enable */ 38 #define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */ 39 #define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */ 40 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 41 #define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */ 42 #define CR0_PG 0x80000000 /* PaGing enable */ 43 44 /* 45 * Bits in 486 special registers: 46 */ 47 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 48 #define CR0_WP 0x00010000 /* Write Protect (honor PG_RW in all modes) */ 49 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 50 #define CR0_NW 0x20000000 /* Not Write-through */ 51 #define CR0_CD 0x40000000 /* Cache Disable */ 52 53 /* 54 * Cyrix 486 DLC special registers, accessible as IO ports. 55 */ 56 #define CCR0 0xc0 /* configuration control register 0 */ 57 #define CCR0_NC0 0x01 /* first 64K of each 1M memory region is non-cacheable */ 58 #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 59 #define CCR0_A20M 0x04 /* enables A20M# input pin */ 60 #define CCR0_KEN 0x08 /* enables KEN# input pin */ 61 #define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */ 62 #define CCR0_BARB 0x20 /* flushes internal cache when entering hold state */ 63 #define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */ 64 #define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */ 65 66 #define CCR1 0xc1 /* configuration control register 1 */ 67 #define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */ 68 /* the remaining 7 bits of this register are reserved */ 69 70 /* 71 * bits in the %cr4 control register: 72 */ 73 #define CR4_VME 0x00000001 /* virtual 8086 mode extension enable */ 74 #define CR4_PVI 0x00000002 /* protected mode virtual interrupt enable */ 75 #define CR4_TSD 0x00000004 /* restrict RDTSC instruction to cpl 0 */ 76 #define CR4_DE 0x00000008 /* debugging extension */ 77 #define CR4_PSE 0x00000010 /* large (4MB) page size enable */ 78 #define CR4_PAE 0x00000020 /* physical address extension enable */ 79 #define CR4_MCE 0x00000040 /* machine check enable */ 80 #define CR4_PGE 0x00000080 /* page global enable */ 81 #define CR4_PCE 0x00000100 /* enable RDPMC instruction for all cpls */ 82 #define CR4_OSFXSR 0x00000200 /* enable fxsave/fxrestor and SSE */ 83 #define CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */ 84 #define CR4_VMXE 0x00002000 /* enable VMX operations */ 85 #define CR4_SMXE 0x00004000 /* enable SMX operations */ 86 #define CR4_FSGSBASE 0x00010000 /* enable *FSBASE and *GSBASE instructions */ 87 #define CR4_PCIDE 0x00020000 /* enable Process Context IDentifiers */ 88 #define CR4_OSXSAVE 0x00040000 /* enable xsave and xrestore */ 89 #define CR4_SMEP 0x00100000 /* enable SMEP support */ 90 91 92 /* 93 * CPUID "features" bits 94 */ 95 96 /* Fn00000001 %edx features */ 97 #define CPUID_FPU 0x00000001 /* processor has an FPU? */ 98 #define CPUID_VME 0x00000002 /* has virtual mode (%cr4's VME/PVI) */ 99 #define CPUID_DE 0x00000004 /* has debugging extension */ 100 #define CPUID_PSE 0x00000008 /* has page 4MB page size extension */ 101 #define CPUID_TSC 0x00000010 /* has time stamp counter */ 102 #define CPUID_MSR 0x00000020 /* has mode specific registers */ 103 #define CPUID_PAE 0x00000040 /* has phys address extension */ 104 #define CPUID_MCE 0x00000080 /* has machine check exception */ 105 #define CPUID_CX8 0x00000100 /* has CMPXCHG8B instruction */ 106 #define CPUID_APIC 0x00000200 /* has enabled APIC */ 107 #define CPUID_B10 0x00000400 /* reserved, MTRR */ 108 #define CPUID_SEP 0x00000800 /* has SYSENTER/SYSEXIT extension */ 109 #define CPUID_MTRR 0x00001000 /* has memory type range register */ 110 #define CPUID_PGE 0x00002000 /* has page global extension */ 111 #define CPUID_MCA 0x00004000 /* has machine check architecture */ 112 #define CPUID_CMOV 0x00008000 /* has CMOVcc instruction */ 113 #define CPUID_PAT 0x00010000 /* Page Attribute Table */ 114 #define CPUID_PSE36 0x00020000 /* 36-bit PSE */ 115 #define CPUID_PN 0x00040000 /* processor serial number */ 116 #define CPUID_CFLUSH 0x00080000 /* CFLUSH insn supported */ 117 #define CPUID_B20 0x00100000 /* reserved */ 118 #define CPUID_DS 0x00200000 /* Debug Store */ 119 #define CPUID_ACPI 0x00400000 /* ACPI performance modulation regs */ 120 #define CPUID_MMX 0x00800000 /* MMX supported */ 121 #define CPUID_FXSR 0x01000000 /* fast FP/MMX save/restore */ 122 #define CPUID_SSE 0x02000000 /* streaming SIMD extensions */ 123 #define CPUID_SSE2 0x04000000 /* streaming SIMD extensions #2 */ 124 #define CPUID_SS 0x08000000 /* self-snoop */ 125 #define CPUID_HTT 0x10000000 /* Hyper-Threading Technology */ 126 #define CPUID_TM 0x20000000 /* thermal monitor (TCC) */ 127 #define CPUID_IA64 0x40000000 /* IA-64 architecture */ 128 #define CPUID_SBF 0x80000000 /* signal break on FERR */ 129 130 #define CPUID_FLAGS1 "\20" \ 131 "\1" "FPU" "\2" "VME" "\3" "DE" "\4" "PSE" \ 132 "\5" "TSC" "\6" "MSR" "\7" "PAE" "\10" "MCE" \ 133 "\11" "CX8" "\12" "APIC" "\13" "B10" "\14" "SEP" \ 134 "\15" "MTRR" "\16" "PGE" "\17" "MCA" "\20" "CMOV" \ 135 "\21" "PAT" "\22" "PSE36" "\23" "PN" "\24" "CFLUSH" \ 136 "\25" "B20" "\26" "DS" "\27" "ACPI" "\30" "MMX" \ 137 "\31" "FXSR" "\32" "SSE" "\33" "SSE2" "\34" "SS" \ 138 "\35" "HTT" "\36" "TM" "\37" "IA64" "\40" "SBF" 139 140 /* 141 * Intel Digital Thermal Sensor and 142 * Power Management, Fn0000_0006 - %eax. 143 */ 144 #define CPUID_DSPM_DTS 0x00000001 /* Digital Thermal Sensor */ 145 #define CPUID_DSPM_IDA 0x00000002 /* Intel Dynamic Acceleration */ 146 #define CPUID_DSPM_ARAT 0x00000004 /* Always Running APIC Timer */ 147 #define CPUID_DSPM_PLN 0x00000010 /* Power Limit Notification */ 148 #define CPUID_DSPM_CME 0x00000020 /* Clock Modulation Extension */ 149 #define CPUID_DSPM_PLTM 0x00000040 /* Package Level Thermal Management */ 150 151 #define CPUID_DSPM_FLAGS "\20" \ 152 "\1" "DTS" "\2" "IDA" "\3" "ARAT" \ 153 "\5" "PLN" "\6" "CME" "\7" "PLTM" 154 155 /* 156 * Intel Digital Thermal Sensor and 157 * Power Management, Fn0000_0006 - %ecx. 158 */ 159 #define CPUID_DSPM_HWF 0x00000001 /* MSR_APERF/MSR_MPERF available */ 160 161 #define CPUID_DSPM_FLAGS1 "\20" "\1" "HWF" 162 163 /* 164 * Intel Structured Extended Feature leaf 165 * Fn0000_0007 main leaf - %ebx. 166 */ 167 #define CPUID_SEF_FSGSBASE __BIT(0) 168 #define CPUID_SEF_TSC_ADJUST __BIT(1) 169 #define CPUID_SEF_BMI1 __BIT(3) 170 #define CPUID_SEF_HLE __BIT(4) 171 #define CPUID_SEF_AVX2 __BIT(5) 172 #define CPUID_SEF_SMEP __BIT(7) 173 #define CPUID_SEF_BMI2 __BIT(8) 174 #define CPUID_SEF_ERMS __BIT(9) 175 #define CPUID_SEF_INVPCID __BIT(10) 176 #define CPUID_SEF_RTM __BIT(11) 177 #define CPUID_SEF_QM __BIT(12) 178 #define CPUID_SEF_FPUCSDS __BIT(13) 179 #define CPUID_SEF_RDSEED __BIT(18) 180 #define CPUID_SEF_ADX __BIT(19) 181 #define CPUID_SEF_SMAP __BIT(20) 182 183 #define CPUID_SEF_FLAGS "\20" \ 184 "\1" "FSGSBASE" \ 185 "\2" "TSCADJUST" \ 186 "\4" "BMI1" \ 187 "\5" "HLE" \ 188 "\6" "AVX2" \ 189 "\10" "SMEP" \ 190 "\11" "BMI2" \ 191 "\12" "ERMS" \ 192 "\13" "INVPCID" \ 193 "\14" "RTM" \ 194 "\15" "QM" \ 195 "\16" "FPUCSDS" \ 196 "\23" "RDSEED" \ 197 "\24" "ADX" \ 198 "\25" "SMAP" 199 200 /* Intel Fn80000001 extended features - %edx */ 201 #define CPUID_SYSCALL 0x00000800 /* SYSCALL/SYSRET */ 202 #define CPUID_XD 0x00100000 /* Execute Disable (like CPUID_NOX) */ 203 #define CPUID_P1GB 0x04000000 /* 1GB Large Page Support */ 204 #define CPUID_RDTSCP 0x08000000 /* Read TSC Pair Instruction */ 205 #define CPUID_EM64T 0x20000000 /* Intel EM64T */ 206 207 #define CPUID_INTEL_EXT_FLAGS "\20" \ 208 "\14" "SYSCALL/SYSRET" "\25" "XD" "\33" "P1GB" \ 209 "\34" "RDTSCP" "\36" "EM64T" 210 211 /* Intel Fn80000001 extended features - %ecx */ 212 #define CPUID_LAHF 0x00000001 /* LAHF/SAHF in IA-32e mode, 64bit sub*/ 213 214 #define CPUID_INTEL_FLAGS4 "\20" \ 215 "\1" "LAHF" "\02" "B01" "\03" "B02" 216 217 218 /* AMD/VIA Fn80000001 extended features - %edx */ 219 /* CPUID_SYSCALL SYSCALL/SYSRET */ 220 #define CPUID_MPC 0x00080000 /* Multiprocessing Capable */ 221 #define CPUID_NOX 0x00100000 /* No Execute Page Protection */ 222 #define CPUID_MMXX 0x00400000 /* AMD MMX Extensions */ 223 #define CPUID_FFXSR 0x02000000 /* FXSAVE/FXSTOR Extensions */ 224 /* CPUID_P1GB 1GB Large Page Support */ 225 /* CPUID_RDTSCP Read TSC Pair Instruction */ 226 /* CPUID_EM64T Long mode */ 227 #define CPUID_3DNOW2 0x40000000 /* 3DNow! Instruction Extension */ 228 #define CPUID_3DNOW 0x80000000 /* 3DNow! Instructions */ 229 230 #define CPUID_EXT_FLAGS "\20" \ 231 "\14" "SYSCALL/SYSRET" "\24" "MPC" "\25" "NOX" \ 232 "\27" "MXX" "\32" "FFXSR" "\33" "P1GB" "\34" "RDTSCP" \ 233 "\36" "LONG" "\37" "3DNOW2" "\40" "3DNOW" 234 235 /* AMD Fn80000001 extended features - %ecx */ 236 /* CPUID_LAHF LAHF/SAHF instruction */ 237 #define CPUID_CMPLEGACY 0x00000002 /* Compare Legacy */ 238 #define CPUID_SVM 0x00000004 /* Secure Virtual Machine */ 239 #define CPUID_EAPIC 0x00000008 /* Extended APIC space */ 240 #define CPUID_ALTMOVCR0 0x00000010 /* Lock Mov Cr0 */ 241 #define CPUID_LZCNT 0x00000020 /* LZCNT instruction */ 242 #define CPUID_SSE4A 0x00000040 /* SSE4A instruction set */ 243 #define CPUID_MISALIGNSSE 0x00000080 /* Misaligned SSE */ 244 #define CPUID_3DNOWPF 0x00000100 /* 3DNow Prefetch */ 245 #define CPUID_OSVW 0x00000200 /* OS visible workarounds */ 246 #define CPUID_IBS 0x00000400 /* Instruction Based Sampling */ 247 #define CPUID_XOP 0x00000800 /* XOP instruction set */ 248 #define CPUID_SKINIT 0x00001000 /* SKINIT */ 249 #define CPUID_WDT 0x00002000 /* watchdog timer support */ 250 #define CPUID_LWP 0x00008000 /* Light Weight Profiling */ 251 #define CPUID_FMA4 0x00010000 /* FMA4 instructions */ 252 #define CPUID_NODEID 0x00080000 /* NodeID MSR available*/ 253 #define CPUID_TBM 0x00200000 /* TBM instructions */ 254 #define CPUID_TOPOEXT 0x00400000 /* cpuid Topology Extension */ 255 256 #define CPUID_AMD_FLAGS4 "\20" \ 257 "\1" "LAHF" "\2" "CMPLEGACY" "\3" "SVM" "\4" "EAPIC" \ 258 "\5" "ALTMOVCR0" "\6" "LZCNT" "\7" "SSE4A" "\10" "MISALIGNSSE" \ 259 "\11" "3DNOWPREFETCH" \ 260 "\12" "OSVW" "\13" "IBS" "\14" "XOP" \ 261 "\15" "SKINIT" "\16" "WDT" "\17" "B14" "\20" "LWP" \ 262 "\21" "FMA4" "\22" "B17" "\23" "B18" "\24" "NodeID" \ 263 "\25" "B20" "\26" "TBM" "\27" "TopoExt" "\30" "B23" \ 264 "\31" "B24" "\32" "B25" "\33" "B26" "\34" "B27" \ 265 "\35" "B28" "\36" "B29" "\37" "B30" "\40" "B31" 266 267 /* AMD Fn8000000a %edx features (SVM features) */ 268 #define CPUID_AMD_SVM_NP 0x00000001 269 #define CPUID_AMD_SVM_LbrVirt 0x00000002 270 #define CPUID_AMD_SVM_SVML 0x00000004 271 #define CPUID_AMD_SVM_NRIPS 0x00000008 272 #define CPUID_AMD_SVM_TSCRateCtrl 0x00000010 273 #define CPUID_AMD_SVM_VMCBCleanBits 0x00000020 274 #define CPUID_AMD_SVM_FlushByASID 0x00000040 275 #define CPUID_AMD_SVM_DecodeAssist 0x00000080 276 #define CPUID_AMD_SVM_PauseFilter 0x00000400 277 #define CPUID_AMD_SVM_FLAGS "\20" \ 278 "\1" "NP" "\2" "LbrVirt" "\3" "SVML" "\4" "NRIPS" \ 279 "\5" "TSCRate" "\6" "VMCBCleanBits" \ 280 "\7" "FlushByASID" "\10" "DecodeAssist" \ 281 "\11" "B08" "\12" "B09" "\13" "PauseFilter" "\14" "B11" \ 282 "\15" "B12" "\16" "B13" "\17" "B17" "\20" "B18" \ 283 "\21" "B19" 284 285 /* 286 * AMD Advanced Power Management 287 * CPUID Fn8000_0007 %edx 288 */ 289 #define CPUID_APM_TS 0x00000001 /* Temperature Sensor */ 290 #define CPUID_APM_FID 0x00000002 /* Frequency ID control */ 291 #define CPUID_APM_VID 0x00000004 /* Voltage ID control */ 292 #define CPUID_APM_TTP 0x00000008 /* THERMTRIP (PCI F3xE4 register) */ 293 #define CPUID_APM_HTC 0x00000010 /* Hardware thermal control (HTC) */ 294 #define CPUID_APM_STC 0x00000020 /* Software thermal control (STC) */ 295 #define CPUID_APM_100 0x00000040 /* 100MHz multiplier control */ 296 #define CPUID_APM_HWP 0x00000080 /* HW P-State control */ 297 #define CPUID_APM_TSC 0x00000100 /* TSC invariant */ 298 #define CPUID_APM_CPB 0x00000200 /* Core performance boost */ 299 #define CPUID_APM_EFF 0x00000400 /* Effective Frequency (read-only) */ 300 301 #define CPUID_APM_FLAGS "\20" \ 302 "\1" "TS" "\2" "FID" "\3" "VID" "\4" "TTP" \ 303 "\5" "HTC" "\6" "STC" "\7" "100" "\10" "HWP" \ 304 "\11" "TSC" "\12" "CPB" "\13" "EffFreq" "\14" "B11" \ 305 "\15" "B12" 306 307 /* 308 * Centaur Extended Feature flags 309 */ 310 #define CPUID_VIA_HAS_RNG 0x00000004 /* Random number generator */ 311 #define CPUID_VIA_DO_RNG 0x00000008 312 #define CPUID_VIA_HAS_ACE 0x00000040 /* AES Encryption */ 313 #define CPUID_VIA_DO_ACE 0x00000080 314 #define CPUID_VIA_HAS_ACE2 0x00000100 /* AES+CTR instructions */ 315 #define CPUID_VIA_DO_ACE2 0x00000200 316 #define CPUID_VIA_HAS_PHE 0x00000400 /* SHA1+SHA256 HMAC */ 317 #define CPUID_VIA_DO_PHE 0x00000800 318 #define CPUID_VIA_HAS_PMM 0x00001000 /* RSA Instructions */ 319 #define CPUID_VIA_DO_PMM 0x00002000 320 321 #define CPUID_FLAGS_PADLOCK "\20" \ 322 "\3" "RNG" "\7" "AES" "\11" "AES/CTR" "\13" "SHA1/SHA256" \ 323 "\15" "RSA" 324 325 /* 326 * CPUID "features" bits in Fn00000001 %ecx 327 */ 328 329 #define CPUID2_SSE3 0x00000001 /* Streaming SIMD Extensions 3 */ 330 #define CPUID2_PCLMUL 0x00000002 /* PCLMULQDQ instructions */ 331 #define CPUID2_DTES64 0x00000004 /* 64-bit Debug Trace */ 332 #define CPUID2_MONITOR 0x00000008 /* MONITOR/MWAIT instructions */ 333 #define CPUID2_DS_CPL 0x00000010 /* CPL Qualified Debug Store */ 334 #define CPUID2_VMX 0x00000020 /* Virtual Machine Extensions */ 335 #define CPUID2_SMX 0x00000040 /* Safer Mode Extensions */ 336 #define CPUID2_EST 0x00000080 /* Enhanced SpeedStep Technology */ 337 #define CPUID2_TM2 0x00000100 /* Thermal Monitor 2 */ 338 #define CPUID2_SSSE3 0x00000200 /* Supplemental SSE3 */ 339 #define CPUID2_CID 0x00000400 /* Context ID */ 340 /* bit 11 unused 0x00000800 */ 341 #define CPUID2_FMA 0x00001000 /* has Fused Multiply Add */ 342 #define CPUID2_CX16 0x00002000 /* has CMPXCHG16B instruction */ 343 #define CPUID2_xTPR 0x00004000 /* Task Priority Messages disabled? */ 344 #define CPUID2_PDCM 0x00008000 /* Perf/Debug Capability MSR */ 345 /* bit 16 unused 0x00010000 */ 346 #define CPUID2_PCID 0x00020000 /* Process Context ID */ 347 #define CPUID2_DCA 0x00040000 /* Direct Cache Access */ 348 #define CPUID2_SSE41 0x00080000 /* Streaming SIMD Extensions 4.1 */ 349 #define CPUID2_SSE42 0x00100000 /* Streaming SIMD Extensions 4.2 */ 350 #define CPUID2_X2APIC 0x00200000 /* xAPIC Extensions */ 351 #define CPUID2_MOVBE 0x00400000 /* MOVBE (move after byteswap) */ 352 #define CPUID2_POPCNT 0x00800000 /* popcount instruction available */ 353 #define CPUID2_DEADLINE 0x01000000 /* APIC Timer supports TSC Deadline */ 354 #define CPUID2_AES 0x02000000 /* AES instructions */ 355 #define CPUID2_XSAVE 0x04000000 /* XSAVE instructions */ 356 #define CPUID2_OSXSAVE 0x08000000 /* XGETBV/XSETBV instructions */ 357 #define CPUID2_AVX 0x10000000 /* AVX instructions */ 358 #define CPUID2_F16C 0x20000000 /* half precision conversion */ 359 #define CPUID2_RDRAND 0x40000000 /* RDRAND (hardware random number) */ 360 #define CPUID2_RAZ 0x80000000 /* RAZ. Indicates guest state. */ 361 362 #define CPUID2_FLAGS1 "\20" \ 363 "\1" "SSE3" "\2" "PCLMULQDQ" "\3" "DTES64" "\4" "MONITOR" \ 364 "\5" "DS-CPL" "\6" "VMX" "\7" "SMX" "\10" "EST" \ 365 "\11" "TM2" "\12" "SSSE3" "\13" "CID" "\14" "B11" \ 366 "\15" "FMA" "\16" "CX16" "\17" "xTPR" "\20" "PDCM" \ 367 "\21" "B16" "\22" "PCID" "\23" "DCA" "\24" "SSE41" \ 368 "\25" "SSE42" "\26" "X2APIC" "\27" "MOVBE" "\30" "POPCNT" \ 369 "\31" "DEADLINE" "\32" "AES" "\33" "XSAVE" "\34" "OSXSAVE" \ 370 "\35" "AVX" "\36" "F16C" "\37" "RDRAND" "\40" "RAZ" 371 372 #define CPUID2FAMILY(cpuid) (((cpuid) >> 8) & 0xf) 373 #define CPUID2MODEL(cpuid) (((cpuid) >> 4) & 0xf) 374 #define CPUID2STEPPING(cpuid) ((cpuid) & 0xf) 375 376 /* 377 * The Extended family bits should only be inspected when CPUID2FAMILY() 378 * returns 15. They are use to encode family value 16 to 270 (add 15). 379 * The Extended model hits are the high 4 bits of the model. 380 * They are only valid for family >= 15 or family 6 (intel, but all amd 381 * family 6 are documented to return zero bits for them). 382 */ 383 #define CPUID2EXTFAMILY(cpuid) (((cpuid) >> 20) & 0xff) 384 #define CPUID2EXTMODEL(cpuid) (((cpuid) >> 16) & 0xf) 385 386 /* Blacklists of CPUID flags - used to mask certain features */ 387 #ifdef XEN 388 /* Not on Xen */ 389 #define CPUID_FEAT_BLACKLIST (CPUID_PGE|CPUID_PSE|CPUID_MTRR) 390 #else 391 #define CPUID_FEAT_BLACKLIST 0 392 #endif /* XEN */ 393 394 /* 395 * Extended Control Register XCR0 396 */ 397 #define XCR0_X87 0x00000001 /* x87 FPU/MMX state */ 398 #define XCR0_SSE 0x00000002 /* SSE state */ 399 #define XCR0_AVX 0x00000004 /* AVX state (ymmn registers) */ 400 401 #define XCR0_FLAGS1 "\20" \ 402 "\1" "x87" "\2" "SSE" "\3" "AVX" "\4" "B03" 403 404 /* 405 * CPUID Processor extended state Enumeration Fn0000000d 406 * 407 * %ecx == 0: supported features info: 408 * %edx:%eax bits valid for XCR0 409 * %ebx Save area size for features enabled in XCR0 410 * %ecx Maximim save area size for all cpu features 411 * 412 * %ecx == 1: Bit 0 => xsaveopt instruction avalaible (sandy bridge onwards) 413 * 414 * %ecx >= 2: Save area details for XCR0 bit n 415 * %eax: size of save area for this feature 416 * %ebx: offset of save area for this feature 417 * %ecx, %edx: reserved 418 * All of %eax, %ebx, %ecx and %edx zero for unsupported features. 419 */ 420 421 #define CPUID_PES1_XSAVEOPT 0x00000001 /* xsaveopt instruction */ 422 423 #define CPUID_PES1_FLAGS "\20" \ 424 "\1" "XSAVEOPT" 425 426 /* 427 * Model-specific registers for the i386 family 428 */ 429 #define MSR_P5_MC_ADDR 0x000 /* P5 only */ 430 #define MSR_P5_MC_TYPE 0x001 /* P5 only */ 431 #define MSR_TSC 0x010 432 #define MSR_CESR 0x011 /* P5 only (trap on P6) */ 433 #define MSR_CTR0 0x012 /* P5 only (trap on P6) */ 434 #define MSR_CTR1 0x013 /* P5 only (trap on P6) */ 435 #define MSR_APICBASE 0x01b 436 #define MSR_EBL_CR_POWERON 0x02a 437 #define MSR_EBC_FREQUENCY_ID 0x02c /* PIV only */ 438 #define MSR_TEST_CTL 0x033 439 #define MSR_BIOS_UPDT_TRIG 0x079 440 #define MSR_BBL_CR_D0 0x088 /* PII+ only */ 441 #define MSR_BBL_CR_D1 0x089 /* PII+ only */ 442 #define MSR_BBL_CR_D2 0x08a /* PII+ only */ 443 #define MSR_BIOS_SIGN 0x08b 444 #define MSR_PERFCTR0 0x0c1 445 #define MSR_PERFCTR1 0x0c2 446 #define MSR_FSB_FREQ 0x0cd /* Core Duo/Solo only */ 447 #define MSR_MPERF 0x0e7 448 #define MSR_APERF 0x0e8 449 #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ 450 #define MSR_MTRRcap 0x0fe 451 #define MSR_BBL_CR_ADDR 0x116 /* PII+ only */ 452 #define MSR_BBL_CR_DECC 0x118 /* PII+ only */ 453 #define MSR_BBL_CR_CTL 0x119 /* PII+ only */ 454 #define MSR_BBL_CR_TRIG 0x11a /* PII+ only */ 455 #define MSR_BBL_CR_BUSY 0x11b /* PII+ only */ 456 #define MSR_BBL_CR_CTR3 0x11e /* PII+ only */ 457 #define MSR_SYSENTER_CS 0x174 /* PII+ only */ 458 #define MSR_SYSENTER_ESP 0x175 /* PII+ only */ 459 #define MSR_SYSENTER_EIP 0x176 /* PII+ only */ 460 #define MSR_MCG_CAP 0x179 461 #define MSR_MCG_STATUS 0x17a 462 #define MSR_MCG_CTL 0x17b 463 #define MSR_EVNTSEL0 0x186 464 #define MSR_EVNTSEL1 0x187 465 #define MSR_PERF_STATUS 0x198 /* Pentium M */ 466 #define MSR_PERF_CTL 0x199 /* Pentium M */ 467 #define MSR_THERM_CONTROL 0x19a 468 #define MSR_THERM_INTERRUPT 0x19b 469 #define MSR_THERM_STATUS 0x19c 470 #define MSR_THERM2_CTL 0x19d /* Pentium M */ 471 #define MSR_MISC_ENABLE 0x1a0 472 #define MSR_TEMPERATURE_TARGET 0x1a2 473 #define MSR_DEBUGCTLMSR 0x1d9 474 #define MSR_LASTBRANCHFROMIP 0x1db 475 #define MSR_LASTBRANCHTOIP 0x1dc 476 #define MSR_LASTINTFROMIP 0x1dd 477 #define MSR_LASTINTTOIP 0x1de 478 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 479 #define MSR_MTRRphysBase0 0x200 480 #define MSR_MTRRphysMask0 0x201 481 #define MSR_MTRRphysBase1 0x202 482 #define MSR_MTRRphysMask1 0x203 483 #define MSR_MTRRphysBase2 0x204 484 #define MSR_MTRRphysMask2 0x205 485 #define MSR_MTRRphysBase3 0x206 486 #define MSR_MTRRphysMask3 0x207 487 #define MSR_MTRRphysBase4 0x208 488 #define MSR_MTRRphysMask4 0x209 489 #define MSR_MTRRphysBase5 0x20a 490 #define MSR_MTRRphysMask5 0x20b 491 #define MSR_MTRRphysBase6 0x20c 492 #define MSR_MTRRphysMask6 0x20d 493 #define MSR_MTRRphysBase7 0x20e 494 #define MSR_MTRRphysMask7 0x20f 495 #define MSR_MTRRphysBase8 0x210 496 #define MSR_MTRRphysMask8 0x211 497 #define MSR_MTRRphysBase9 0x212 498 #define MSR_MTRRphysMask9 0x213 499 #define MSR_MTRRphysBase10 0x214 500 #define MSR_MTRRphysMask10 0x215 501 #define MSR_MTRRphysBase11 0x216 502 #define MSR_MTRRphysMask11 0x217 503 #define MSR_MTRRphysBase12 0x218 504 #define MSR_MTRRphysMask12 0x219 505 #define MSR_MTRRphysBase13 0x21a 506 #define MSR_MTRRphysMask13 0x21b 507 #define MSR_MTRRphysBase14 0x21c 508 #define MSR_MTRRphysMask14 0x21d 509 #define MSR_MTRRphysBase15 0x21e 510 #define MSR_MTRRphysMask15 0x21f 511 #define MSR_MTRRfix64K_00000 0x250 512 #define MSR_MTRRfix16K_80000 0x258 513 #define MSR_MTRRfix16K_A0000 0x259 514 #define MSR_MTRRfix4K_C0000 0x268 515 #define MSR_MTRRfix4K_C8000 0x269 516 #define MSR_MTRRfix4K_D0000 0x26a 517 #define MSR_MTRRfix4K_D8000 0x26b 518 #define MSR_MTRRfix4K_E0000 0x26c 519 #define MSR_MTRRfix4K_E8000 0x26d 520 #define MSR_MTRRfix4K_F0000 0x26e 521 #define MSR_MTRRfix4K_F8000 0x26f 522 #define MSR_CR_PAT 0x277 523 #define MSR_MTRRdefType 0x2ff 524 #define MSR_MC0_CTL 0x400 525 #define MSR_MC0_STATUS 0x401 526 #define MSR_MC0_ADDR 0x402 527 #define MSR_MC0_MISC 0x403 528 #define MSR_MC1_CTL 0x404 529 #define MSR_MC1_STATUS 0x405 530 #define MSR_MC1_ADDR 0x406 531 #define MSR_MC1_MISC 0x407 532 #define MSR_MC2_CTL 0x408 533 #define MSR_MC2_STATUS 0x409 534 #define MSR_MC2_ADDR 0x40a 535 #define MSR_MC2_MISC 0x40b 536 #define MSR_MC4_CTL 0x40c 537 #define MSR_MC4_STATUS 0x40d 538 #define MSR_MC4_ADDR 0x40e 539 #define MSR_MC4_MISC 0x40f 540 #define MSR_MC3_CTL 0x410 541 #define MSR_MC3_STATUS 0x411 542 #define MSR_MC3_ADDR 0x412 543 #define MSR_MC3_MISC 0x413 544 /* 0x480 - 0x490 VMX */ 545 546 /* 547 * VIA "Nehemiah" MSRs 548 */ 549 #define MSR_VIA_RNG 0x0000110b 550 #define MSR_VIA_RNG_ENABLE 0x00000040 551 #define MSR_VIA_RNG_NOISE_MASK 0x00000300 552 #define MSR_VIA_RNG_NOISE_A 0x00000000 553 #define MSR_VIA_RNG_NOISE_B 0x00000100 554 #define MSR_VIA_RNG_2NOISE 0x00000300 555 #define MSR_VIA_ACE 0x00001107 556 #define MSR_VIA_ACE_ENABLE 0x10000000 557 558 /* 559 * VIA "Eden" MSRs 560 */ 561 #define MSR_VIA_FCR MSR_VIA_ACE 562 563 /* 564 * AMD K6/K7 MSRs. 565 */ 566 #define MSR_K6_UWCCR 0xc0000085 567 #define MSR_K7_EVNTSEL0 0xc0010000 568 #define MSR_K7_EVNTSEL1 0xc0010001 569 #define MSR_K7_EVNTSEL2 0xc0010002 570 #define MSR_K7_EVNTSEL3 0xc0010003 571 #define MSR_K7_PERFCTR0 0xc0010004 572 #define MSR_K7_PERFCTR1 0xc0010005 573 #define MSR_K7_PERFCTR2 0xc0010006 574 #define MSR_K7_PERFCTR3 0xc0010007 575 576 /* 577 * AMD K8 (Opteron) MSRs. 578 */ 579 #define MSR_SYSCFG 0xc0000010 580 581 #define MSR_EFER 0xc0000080 /* Extended feature enable */ 582 #define EFER_SCE 0x00000001 /* SYSCALL extension */ 583 #define EFER_LME 0x00000100 /* Long Mode Active */ 584 #define EFER_LMA 0x00000400 /* Long Mode Enabled */ 585 #define EFER_NXE 0x00000800 /* No-Execute Enabled */ 586 587 #define MSR_STAR 0xc0000081 /* 32 bit syscall gate addr */ 588 #define MSR_LSTAR 0xc0000082 /* 64 bit syscall gate addr */ 589 #define MSR_CSTAR 0xc0000083 /* compat syscall gate addr */ 590 #define MSR_SFMASK 0xc0000084 /* flags to clear on syscall */ 591 592 #define MSR_FSBASE 0xc0000100 /* 64bit offset for fs: */ 593 #define MSR_GSBASE 0xc0000101 /* 64bit offset for gs: */ 594 #define MSR_KERNELGSBASE 0xc0000102 /* storage for swapgs ins */ 595 596 #define MSR_VMCR 0xc0010114 /* Virtual Machine Control Register */ 597 #define VMCR_DPD 0x00000001 /* Debug port disable */ 598 #define VMCR_RINIT 0x00000002 /* intercept init */ 599 #define VMCR_DISA20 0x00000004 /* Disable A20 masking */ 600 #define VMCR_LOCK 0x00000008 /* SVM Lock */ 601 #define VMCR_SVMED 0x00000010 /* SVME Disable */ 602 #define MSR_SVMLOCK 0xc0010118 /* SVM Lock key */ 603 604 /* 605 * These require a 'passcode' for access. See cpufunc.h. 606 */ 607 #define MSR_HWCR 0xc0010015 608 #define HWCR_TLBCACHEDIS 0x00000008 609 #define HWCR_FFDIS 0x00000040 610 611 #define MSR_NB_CFG 0xc001001f 612 #define NB_CFG_DISIOREQLOCK 0x0000000000000008ULL 613 #define NB_CFG_DISDATMSK 0x0000001000000000ULL 614 #define NB_CFG_INITAPICCPUIDLO (1ULL << 54) 615 616 #define MSR_LS_CFG 0xc0011020 617 #define LS_CFG_DIS_LS2_SQUISH 0x02000000 618 619 #define MSR_IC_CFG 0xc0011021 620 #define IC_CFG_DIS_SEQ_PREFETCH 0x00000800 621 622 #define MSR_DC_CFG 0xc0011022 623 #define DC_CFG_DIS_CNV_WC_SSO 0x00000008 624 #define DC_CFG_DIS_SMC_CHK_BUF 0x00000400 625 #define DC_CFG_ERRATA_261 0x01000000 626 627 #define MSR_BU_CFG 0xc0011023 628 #define BU_CFG_ERRATA_298 0x0000000000000002ULL 629 #define BU_CFG_ERRATA_254 0x0000000000200000ULL 630 #define BU_CFG_ERRATA_309 0x0000000000800000ULL 631 #define BU_CFG_THRL2IDXCMPDIS 0x0000080000000000ULL 632 #define BU_CFG_WBPFSMCCHKDIS 0x0000200000000000ULL 633 #define BU_CFG_WBENHWSBDIS 0x0001000000000000ULL 634 635 #define MSR_DE_CFG 0xc0011029 636 #define DE_CFG_ERRATA_721 0x00000001 637 638 /* AMD Family10h MSRs */ 639 #define MSR_OSVW_ID_LENGTH 0xc0010140 640 #define MSR_OSVW_STATUS 0xc0010141 641 #define MSR_UCODE_AMD_PATCHLEVEL 0x0000008b 642 #define MSR_UCODE_AMD_PATCHLOADER 0xc0010020 643 644 /* X86 MSRs */ 645 #define MSR_RDTSCP_AUX 0xc0000103 646 647 /* 648 * Constants related to MTRRs 649 */ 650 #define MTRR_N64K 8 /* numbers of fixed-size entries */ 651 #define MTRR_N16K 16 652 #define MTRR_N4K 64 653 654 /* 655 * the following four 3-byte registers control the non-cacheable regions. 656 * These registers must be written as three separate bytes. 657 * 658 * NCRx+0: A31-A24 of starting address 659 * NCRx+1: A23-A16 of starting address 660 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 661 * 662 * The non-cacheable region's starting address must be aligned to the 663 * size indicated by the NCR_SIZE_xx field. 664 */ 665 #define NCR1 0xc4 666 #define NCR2 0xc7 667 #define NCR3 0xca 668 #define NCR4 0xcd 669 670 #define NCR_SIZE_0K 0 671 #define NCR_SIZE_4K 1 672 #define NCR_SIZE_8K 2 673 #define NCR_SIZE_16K 3 674 #define NCR_SIZE_32K 4 675 #define NCR_SIZE_64K 5 676 #define NCR_SIZE_128K 6 677 #define NCR_SIZE_256K 7 678 #define NCR_SIZE_512K 8 679 #define NCR_SIZE_1M 9 680 #define NCR_SIZE_2M 10 681 #define NCR_SIZE_4M 11 682 #define NCR_SIZE_8M 12 683 #define NCR_SIZE_16M 13 684 #define NCR_SIZE_32M 14 685 #define NCR_SIZE_4G 15 686 687 /* 688 * Performance monitor events. 689 * 690 * Note that 586-class and 686-class CPUs have different performance 691 * monitors available, and they are accessed differently: 692 * 693 * 686-class: `rdpmc' instruction 694 * 586-class: `rdmsr' instruction, CESR MSR 695 * 696 * The descriptions of these events are too lenghy to include here. 697 * See Appendix A of "Intel Architecture Software Developer's 698 * Manual, Volume 3: System Programming" for more information. 699 */ 700 701 /* 702 * 586-class CESR MSR format. Lower 16 bits is CTR0, upper 16 bits 703 * is CTR1. 704 */ 705 706 #define PMC5_CESR_EVENT 0x003f 707 #define PMC5_CESR_OS 0x0040 708 #define PMC5_CESR_USR 0x0080 709 #define PMC5_CESR_E 0x0100 710 #define PMC5_CESR_P 0x0200 711 712 #define PMC5_DATA_READ 0x00 713 #define PMC5_DATA_WRITE 0x01 714 #define PMC5_DATA_TLB_MISS 0x02 715 #define PMC5_DATA_READ_MISS 0x03 716 #define PMC5_DATA_WRITE_MISS 0x04 717 #define PMC5_WRITE_M_E 0x05 718 #define PMC5_DATA_LINES_WBACK 0x06 719 #define PMC5_DATA_CACHE_SNOOP 0x07 720 #define PMC5_DATA_CACHE_SNOOP_HIT 0x08 721 #define PMC5_MEM_ACCESS_BOTH_PIPES 0x09 722 #define PMC5_BANK_CONFLICTS 0x0a 723 #define PMC5_MISALIGNED_DATA 0x0b 724 #define PMC5_INST_READ 0x0c 725 #define PMC5_INST_TLB_MISS 0x0d 726 #define PMC5_INST_CACHE_MISS 0x0e 727 #define PMC5_SEGMENT_REG_LOAD 0x0f 728 #define PMC5_BRANCHES 0x12 729 #define PMC5_BTB_HITS 0x13 730 #define PMC5_BRANCH_TAKEN 0x14 731 #define PMC5_PIPELINE_FLUSH 0x15 732 #define PMC5_INST_EXECUTED 0x16 733 #define PMC5_INST_EXECUTED_V_PIPE 0x17 734 #define PMC5_BUS_UTILIZATION 0x18 735 #define PMC5_WRITE_BACKUP_STALL 0x19 736 #define PMC5_DATA_READ_STALL 0x1a 737 #define PMC5_WRITE_E_M_STALL 0x1b 738 #define PMC5_LOCKED_BUS 0x1c 739 #define PMC5_IO_CYCLE 0x1d 740 #define PMC5_NONCACHE_MEM_READ 0x1e 741 #define PMC5_AGI_STALL 0x1f 742 #define PMC5_FLOPS 0x22 743 #define PMC5_BP0_MATCH 0x23 744 #define PMC5_BP1_MATCH 0x24 745 #define PMC5_BP2_MATCH 0x25 746 #define PMC5_BP3_MATCH 0x26 747 #define PMC5_HARDWARE_INTR 0x27 748 #define PMC5_DATA_RW 0x28 749 #define PMC5_DATA_RW_MISS 0x29 750 751 /* 752 * 686-class Event Selector MSR format. 753 */ 754 755 #define PMC6_EVTSEL_EVENT 0x000000ff 756 #define PMC6_EVTSEL_UNIT 0x0000ff00 757 #define PMC6_EVTSEL_UNIT_SHIFT 8 758 #define PMC6_EVTSEL_USR (1 << 16) 759 #define PMC6_EVTSEL_OS (1 << 17) 760 #define PMC6_EVTSEL_E (1 << 18) 761 #define PMC6_EVTSEL_PC (1 << 19) 762 #define PMC6_EVTSEL_INT (1 << 20) 763 #define PMC6_EVTSEL_EN (1 << 22) /* PerfEvtSel0 only */ 764 #define PMC6_EVTSEL_INV (1 << 23) 765 #define PMC6_EVTSEL_COUNTER_MASK 0xff000000 766 #define PMC6_EVTSEL_COUNTER_MASK_SHIFT 24 767 768 /* Data Cache Unit */ 769 #define PMC6_DATA_MEM_REFS 0x43 770 #define PMC6_DCU_LINES_IN 0x45 771 #define PMC6_DCU_M_LINES_IN 0x46 772 #define PMC6_DCU_M_LINES_OUT 0x47 773 #define PMC6_DCU_MISS_OUTSTANDING 0x48 774 775 /* Instruction Fetch Unit */ 776 #define PMC6_IFU_IFETCH 0x80 777 #define PMC6_IFU_IFETCH_MISS 0x81 778 #define PMC6_ITLB_MISS 0x85 779 #define PMC6_IFU_MEM_STALL 0x86 780 #define PMC6_ILD_STALL 0x87 781 782 /* L2 Cache */ 783 #define PMC6_L2_IFETCH 0x28 784 #define PMC6_L2_LD 0x29 785 #define PMC6_L2_ST 0x2a 786 #define PMC6_L2_LINES_IN 0x24 787 #define PMC6_L2_LINES_OUT 0x26 788 #define PMC6_L2_M_LINES_INM 0x25 789 #define PMC6_L2_M_LINES_OUTM 0x27 790 #define PMC6_L2_RQSTS 0x2e 791 #define PMC6_L2_ADS 0x21 792 #define PMC6_L2_DBUS_BUSY 0x22 793 #define PMC6_L2_DBUS_BUSY_RD 0x23 794 795 /* External Bus Logic */ 796 #define PMC6_BUS_DRDY_CLOCKS 0x62 797 #define PMC6_BUS_LOCK_CLOCKS 0x63 798 #define PMC6_BUS_REQ_OUTSTANDING 0x60 799 #define PMC6_BUS_TRAN_BRD 0x65 800 #define PMC6_BUS_TRAN_RFO 0x66 801 #define PMC6_BUS_TRANS_WB 0x67 802 #define PMC6_BUS_TRAN_IFETCH 0x68 803 #define PMC6_BUS_TRAN_INVAL 0x69 804 #define PMC6_BUS_TRAN_PWR 0x6a 805 #define PMC6_BUS_TRANS_P 0x6b 806 #define PMC6_BUS_TRANS_IO 0x6c 807 #define PMC6_BUS_TRAN_DEF 0x6d 808 #define PMC6_BUS_TRAN_BURST 0x6e 809 #define PMC6_BUS_TRAN_ANY 0x70 810 #define PMC6_BUS_TRAN_MEM 0x6f 811 #define PMC6_BUS_DATA_RCV 0x64 812 #define PMC6_BUS_BNR_DRV 0x61 813 #define PMC6_BUS_HIT_DRV 0x7a 814 #define PMC6_BUS_HITM_DRDV 0x7b 815 #define PMC6_BUS_SNOOP_STALL 0x7e 816 817 /* Floating Point Unit */ 818 #define PMC6_FLOPS 0xc1 819 #define PMC6_FP_COMP_OPS_EXE 0x10 820 #define PMC6_FP_ASSIST 0x11 821 #define PMC6_MUL 0x12 822 #define PMC6_DIV 0x12 823 #define PMC6_CYCLES_DIV_BUSY 0x14 824 825 /* Memory Ordering */ 826 #define PMC6_LD_BLOCKS 0x03 827 #define PMC6_SB_DRAINS 0x04 828 #define PMC6_MISALIGN_MEM_REF 0x05 829 #define PMC6_EMON_KNI_PREF_DISPATCHED 0x07 /* P-III only */ 830 #define PMC6_EMON_KNI_PREF_MISS 0x4b /* P-III only */ 831 832 /* Instruction Decoding and Retirement */ 833 #define PMC6_INST_RETIRED 0xc0 834 #define PMC6_UOPS_RETIRED 0xc2 835 #define PMC6_INST_DECODED 0xd0 836 #define PMC6_EMON_KNI_INST_RETIRED 0xd8 837 #define PMC6_EMON_KNI_COMP_INST_RET 0xd9 838 839 /* Interrupts */ 840 #define PMC6_HW_INT_RX 0xc8 841 #define PMC6_CYCLES_INT_MASKED 0xc6 842 #define PMC6_CYCLES_INT_PENDING_AND_MASKED 0xc7 843 844 /* Branches */ 845 #define PMC6_BR_INST_RETIRED 0xc4 846 #define PMC6_BR_MISS_PRED_RETIRED 0xc5 847 #define PMC6_BR_TAKEN_RETIRED 0xc9 848 #define PMC6_BR_MISS_PRED_TAKEN_RET 0xca 849 #define PMC6_BR_INST_DECODED 0xe0 850 #define PMC6_BTB_MISSES 0xe2 851 #define PMC6_BR_BOGUS 0xe4 852 #define PMC6_BACLEARS 0xe6 853 854 /* Stalls */ 855 #define PMC6_RESOURCE_STALLS 0xa2 856 #define PMC6_PARTIAL_RAT_STALLS 0xd2 857 858 /* Segment Register Loads */ 859 #define PMC6_SEGMENT_REG_LOADS 0x06 860 861 /* Clocks */ 862 #define PMC6_CPU_CLK_UNHALTED 0x79 863 864 /* MMX Unit */ 865 #define PMC6_MMX_INSTR_EXEC 0xb0 /* Celeron, P-II, P-IIX only */ 866 #define PMC6_MMX_SAT_INSTR_EXEC 0xb1 /* P-II and P-III only */ 867 #define PMC6_MMX_UOPS_EXEC 0xb2 /* P-II and P-III only */ 868 #define PMC6_MMX_INSTR_TYPE_EXEC 0xb3 /* P-II and P-III only */ 869 #define PMC6_FP_MMX_TRANS 0xcc /* P-II and P-III only */ 870 #define PMC6_MMX_ASSIST 0xcd /* P-II and P-III only */ 871 #define PMC6_MMX_INSTR_RET 0xc3 /* P-II only */ 872 873 /* Segment Register Renaming */ 874 #define PMC6_SEG_RENAME_STALLS 0xd4 /* P-II and P-III only */ 875 #define PMC6_SEG_REG_RENAMES 0xd5 /* P-II and P-III only */ 876 #define PMC6_RET_SEG_RENAMES 0xd6 /* P-II and P-III only */ 877 878 /* 879 * AMD K7 Event Selector MSR format. 880 */ 881 882 #define K7_EVTSEL_EVENT 0x000000ff 883 #define K7_EVTSEL_UNIT 0x0000ff00 884 #define K7_EVTSEL_UNIT_SHIFT 8 885 #define K7_EVTSEL_USR (1 << 16) 886 #define K7_EVTSEL_OS (1 << 17) 887 #define K7_EVTSEL_E (1 << 18) 888 #define K7_EVTSEL_PC (1 << 19) 889 #define K7_EVTSEL_INT (1 << 20) 890 #define K7_EVTSEL_EN (1 << 22) 891 #define K7_EVTSEL_INV (1 << 23) 892 #define K7_EVTSEL_COUNTER_MASK 0xff000000 893 #define K7_EVTSEL_COUNTER_MASK_SHIFT 24 894 895 /* Segment Register Loads */ 896 #define K7_SEGMENT_REG_LOADS 0x20 897 898 #define K7_STORES_TO_ACTIVE_INST_STREAM 0x21 899 900 /* Data Cache Unit */ 901 #define K7_DATA_CACHE_ACCESS 0x40 902 #define K7_DATA_CACHE_MISS 0x41 903 #define K7_DATA_CACHE_REFILL 0x42 904 #define K7_DATA_CACHE_REFILL_SYSTEM 0x43 905 #define K7_DATA_CACHE_WBACK 0x44 906 #define K7_L2_DTLB_HIT 0x45 907 #define K7_L2_DTLB_MISS 0x46 908 #define K7_MISALIGNED_DATA_REF 0x47 909 #define K7_SYSTEM_REQUEST 0x64 910 #define K7_SYSTEM_REQUEST_TYPE 0x65 911 912 #define K7_SNOOP_HIT 0x73 913 #define K7_SINGLE_BIT_ECC_ERROR 0x74 914 #define K7_CACHE_LINE_INVAL 0x75 915 #define K7_CYCLES_PROCESSOR_IS_RUNNING 0x76 916 #define K7_L2_REQUEST 0x79 917 #define K7_L2_REQUEST_BUSY 0x7a 918 919 /* Instruction Fetch Unit */ 920 #define K7_IFU_IFETCH 0x80 921 #define K7_IFU_IFETCH_MISS 0x81 922 #define K7_IFU_REFILL_FROM_L2 0x82 923 #define K7_IFU_REFILL_FROM_SYSTEM 0x83 924 #define K7_ITLB_L1_MISS 0x84 925 #define K7_ITLB_L2_MISS 0x85 926 #define K7_SNOOP_RESYNC 0x86 927 #define K7_IFU_STALL 0x87 928 929 #define K7_RETURN_STACK_HITS 0x88 930 #define K7_RETURN_STACK_OVERFLOW 0x89 931 932 /* Retired */ 933 #define K7_RETIRED_INST 0xc0 934 #define K7_RETIRED_OPS 0xc1 935 #define K7_RETIRED_BRANCHES 0xc2 936 #define K7_RETIRED_BRANCH_MISPREDICTED 0xc3 937 #define K7_RETIRED_TAKEN_BRANCH 0xc4 938 #define K7_RETIRED_TAKEN_BRANCH_MISPREDICTED 0xc5 939 #define K7_RETIRED_FAR_CONTROL_TRANSFER 0xc6 940 #define K7_RETIRED_RESYNC_BRANCH 0xc7 941 #define K7_RETIRED_NEAR_RETURNS 0xc8 942 #define K7_RETIRED_NEAR_RETURNS_MISPREDICTED 0xc9 943 #define K7_RETIRED_INDIRECT_MISPREDICTED 0xca 944 945 /* Interrupts */ 946 #define K7_CYCLES_INT_MASKED 0xcd 947 #define K7_CYCLES_INT_PENDING_AND_MASKED 0xce 948 #define K7_HW_INTR_RECV 0xcf 949 950 #define K7_INSTRUCTION_DECODER_EMPTY 0xd0 951 #define K7_DISPATCH_STALLS 0xd1 952 #define K7_BRANCH_ABORTS_TO_RETIRE 0xd2 953 #define K7_SERIALIZE 0xd3 954 #define K7_SEGMENT_LOAD_STALL 0xd4 955 #define K7_ICU_FULL 0xd5 956 #define K7_RESERVATION_STATIONS_FULL 0xd6 957 #define K7_FPU_FULL 0xd7 958 #define K7_LS_FULL 0xd8 959 #define K7_ALL_QUIET_STALL 0xd9 960 #define K7_FAR_TRANSFER_OR_RESYNC_BRANCH_PENDING 0xda 961 962 #define K7_BP0_MATCH 0xdc 963 #define K7_BP1_MATCH 0xdd 964 #define K7_BP2_MATCH 0xde 965 #define K7_BP3_MATCH 0xdf 966
Indexes created Mon Sep 29 21:09:56 GMT 2025