specialreg.h revision 1.71
1 /* $NetBSD: specialreg.h,v 1.71 2013/10/21 06:11:49 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1991 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of the University nor the names of its contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * @(#)specialreg.h 7.1 (Berkeley) 5/9/91 32 */ 33 34 /* 35 * Bits in 386 special registers: 36 */ 37 #define CR0_PE 0x00000001 /* Protected mode Enable */ 38 #define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */ 39 #define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */ 40 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 41 #define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */ 42 #define CR0_PG 0x80000000 /* PaGing enable */ 43 44 /* 45 * Bits in 486 special registers: 46 */ 47 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 48 #define CR0_WP 0x00010000 /* Write Protect (honor PG_RW in all modes) */ 49 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 50 #define CR0_NW 0x20000000 /* Not Write-through */ 51 #define CR0_CD 0x40000000 /* Cache Disable */ 52 53 /* 54 * Cyrix 486 DLC special registers, accessible as IO ports. 55 */ 56 #define CCR0 0xc0 /* configuration control register 0 */ 57 #define CCR0_NC0 0x01 /* first 64K of each 1M memory region is non-cacheable */ 58 #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 59 #define CCR0_A20M 0x04 /* enables A20M# input pin */ 60 #define CCR0_KEN 0x08 /* enables KEN# input pin */ 61 #define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */ 62 #define CCR0_BARB 0x20 /* flushes internal cache when entering hold state */ 63 #define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */ 64 #define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */ 65 66 #define CCR1 0xc1 /* configuration control register 1 */ 67 #define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */ 68 /* the remaining 7 bits of this register are reserved */ 69 70 /* 71 * bits in the %cr4 control register: 72 */ 73 #define CR4_VME 0x00000001 /* virtual 8086 mode extension enable */ 74 #define CR4_PVI 0x00000002 /* protected mode virtual interrupt enable */ 75 #define CR4_TSD 0x00000004 /* restrict RDTSC instruction to cpl 0 */ 76 #define CR4_DE 0x00000008 /* debugging extension */ 77 #define CR4_PSE 0x00000010 /* large (4MB) page size enable */ 78 #define CR4_PAE 0x00000020 /* physical address extension enable */ 79 #define CR4_MCE 0x00000040 /* machine check enable */ 80 #define CR4_PGE 0x00000080 /* page global enable */ 81 #define CR4_PCE 0x00000100 /* enable RDPMC instruction for all cpls */ 82 #define CR4_OSFXSR 0x00000200 /* enable fxsave/fxrestor and SSE */ 83 #define CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */ 84 #define CR4_VMXE 0x00002000 /* enable VMX operations */ 85 #define CR4_SMXE 0x00004000 /* enable SMX operations */ 86 #define CR4_FSGSBASE 0x00010000 /* enable *FSBASE and *GSBASE instructions */ 87 #define CR4_PCIDE 0x00020000 /* enable Process Context IDentifiers */ 88 #define CR4_OSXSAVE 0x00040000 /* enable xsave and xrestore */ 89 #define CR4_SMEP 0x00100000 /* enable SMEP support */ 90 91 92 /* 93 * CPUID "features" bits 94 */ 95 96 /* Fn00000001 %edx features */ 97 #define CPUID_FPU 0x00000001 /* processor has an FPU? */ 98 #define CPUID_VME 0x00000002 /* has virtual mode (%cr4's VME/PVI) */ 99 #define CPUID_DE 0x00000004 /* has debugging extension */ 100 #define CPUID_PSE 0x00000008 /* has 4MB page size extension */ 101 #define CPUID_TSC 0x00000010 /* has time stamp counter */ 102 #define CPUID_MSR 0x00000020 /* has mode specific registers */ 103 #define CPUID_PAE 0x00000040 /* has phys address extension */ 104 #define CPUID_MCE 0x00000080 /* has machine check exception */ 105 #define CPUID_CX8 0x00000100 /* has CMPXCHG8B instruction */ 106 #define CPUID_APIC 0x00000200 /* has enabled APIC */ 107 #define CPUID_B10 0x00000400 /* reserved, MTRR */ 108 #define CPUID_SEP 0x00000800 /* has SYSENTER/SYSEXIT extension */ 109 #define CPUID_MTRR 0x00001000 /* has memory type range register */ 110 #define CPUID_PGE 0x00002000 /* has page global extension */ 111 #define CPUID_MCA 0x00004000 /* has machine check architecture */ 112 #define CPUID_CMOV 0x00008000 /* has CMOVcc instruction */ 113 #define CPUID_PAT 0x00010000 /* Page Attribute Table */ 114 #define CPUID_PSE36 0x00020000 /* 36-bit PSE */ 115 #define CPUID_PN 0x00040000 /* processor serial number */ 116 #define CPUID_CFLUSH 0x00080000 /* CFLUSH insn supported */ 117 #define CPUID_B20 0x00100000 /* reserved */ 118 #define CPUID_DS 0x00200000 /* Debug Store */ 119 #define CPUID_ACPI 0x00400000 /* ACPI performance modulation regs */ 120 #define CPUID_MMX 0x00800000 /* MMX supported */ 121 #define CPUID_FXSR 0x01000000 /* fast FP/MMX save/restore */ 122 #define CPUID_SSE 0x02000000 /* streaming SIMD extensions */ 123 #define CPUID_SSE2 0x04000000 /* streaming SIMD extensions #2 */ 124 #define CPUID_SS 0x08000000 /* self-snoop */ 125 #define CPUID_HTT 0x10000000 /* Hyper-Threading Technology */ 126 #define CPUID_TM 0x20000000 /* thermal monitor (TCC) */ 127 #define CPUID_IA64 0x40000000 /* IA-64 architecture */ 128 #define CPUID_SBF 0x80000000 /* signal break on FERR */ 129 130 #define CPUID_FLAGS1 "\20" \ 131 "\1" "FPU" "\2" "VME" "\3" "DE" "\4" "PSE" \ 132 "\5" "TSC" "\6" "MSR" "\7" "PAE" "\10" "MCE" \ 133 "\11" "CX8" "\12" "APIC" "\13" "B10" "\14" "SEP" \ 134 "\15" "MTRR" "\16" "PGE" "\17" "MCA" "\20" "CMOV" \ 135 "\21" "PAT" "\22" "PSE36" "\23" "PN" "\24" "CFLUSH" \ 136 "\25" "B20" "\26" "DS" "\27" "ACPI" "\30" "MMX" \ 137 "\31" "FXSR" "\32" "SSE" "\33" "SSE2" "\34" "SS" \ 138 "\35" "HTT" "\36" "TM" "\37" "IA64" "\40" "SBF" 139 140 /* Blacklists of CPUID flags - used to mask certain features */ 141 #ifdef XEN 142 /* Not on Xen */ 143 #define CPUID_FEAT_BLACKLIST (CPUID_PGE|CPUID_PSE|CPUID_MTRR) 144 #else 145 #define CPUID_FEAT_BLACKLIST 0 146 #endif /* XEN */ 147 148 /* 149 * CPUID "features" bits in Fn00000001 %ecx 150 */ 151 152 #define CPUID2_SSE3 0x00000001 /* Streaming SIMD Extensions 3 */ 153 #define CPUID2_PCLMUL 0x00000002 /* PCLMULQDQ instructions */ 154 #define CPUID2_DTES64 0x00000004 /* 64-bit Debug Trace */ 155 #define CPUID2_MONITOR 0x00000008 /* MONITOR/MWAIT instructions */ 156 #define CPUID2_DS_CPL 0x00000010 /* CPL Qualified Debug Store */ 157 #define CPUID2_VMX 0x00000020 /* Virtual Machine Extensions */ 158 #define CPUID2_SMX 0x00000040 /* Safer Mode Extensions */ 159 #define CPUID2_EST 0x00000080 /* Enhanced SpeedStep Technology */ 160 #define CPUID2_TM2 0x00000100 /* Thermal Monitor 2 */ 161 #define CPUID2_SSSE3 0x00000200 /* Supplemental SSE3 */ 162 #define CPUID2_CID 0x00000400 /* Context ID */ 163 /* bit 11 unused 0x00000800 */ 164 #define CPUID2_FMA 0x00001000 /* has Fused Multiply Add */ 165 #define CPUID2_CX16 0x00002000 /* has CMPXCHG16B instruction */ 166 #define CPUID2_xTPR 0x00004000 /* Task Priority Messages disabled? */ 167 #define CPUID2_PDCM 0x00008000 /* Perf/Debug Capability MSR */ 168 /* bit 16 unused 0x00010000 */ 169 #define CPUID2_PCID 0x00020000 /* Process Context ID */ 170 #define CPUID2_DCA 0x00040000 /* Direct Cache Access */ 171 #define CPUID2_SSE41 0x00080000 /* Streaming SIMD Extensions 4.1 */ 172 #define CPUID2_SSE42 0x00100000 /* Streaming SIMD Extensions 4.2 */ 173 #define CPUID2_X2APIC 0x00200000 /* xAPIC Extensions */ 174 #define CPUID2_MOVBE 0x00400000 /* MOVBE (move after byteswap) */ 175 #define CPUID2_POPCNT 0x00800000 /* popcount instruction available */ 176 #define CPUID2_DEADLINE 0x01000000 /* APIC Timer supports TSC Deadline */ 177 #define CPUID2_AES 0x02000000 /* AES instructions */ 178 #define CPUID2_XSAVE 0x04000000 /* XSAVE instructions */ 179 #define CPUID2_OSXSAVE 0x08000000 /* XGETBV/XSETBV instructions */ 180 #define CPUID2_AVX 0x10000000 /* AVX instructions */ 181 #define CPUID2_F16C 0x20000000 /* half precision conversion */ 182 #define CPUID2_RDRAND 0x40000000 /* RDRAND (hardware random number) */ 183 #define CPUID2_RAZ 0x80000000 /* RAZ. Indicates guest state. */ 184 185 #define CPUID2_FLAGS1 "\20" \ 186 "\1" "SSE3" "\2" "PCLMULQDQ" "\3" "DTES64" "\4" "MONITOR" \ 187 "\5" "DS-CPL" "\6" "VMX" "\7" "SMX" "\10" "EST" \ 188 "\11" "TM2" "\12" "SSSE3" "\13" "CID" "\14" "B11" \ 189 "\15" "FMA" "\16" "CX16" "\17" "xTPR" "\20" "PDCM" \ 190 "\21" "B16" "\22" "PCID" "\23" "DCA" "\24" "SSE41" \ 191 "\25" "SSE42" "\26" "X2APIC" "\27" "MOVBE" "\30" "POPCNT" \ 192 "\31" "DEADLINE" "\32" "AES" "\33" "XSAVE" "\34" "OSXSAVE" \ 193 "\35" "AVX" "\36" "F16C" "\37" "RDRAND" "\40" "RAZ" 194 195 #define CPUID2FAMILY(cpuid) (((cpuid) >> 8) & 0xf) 196 #define CPUID2MODEL(cpuid) (((cpuid) >> 4) & 0xf) 197 #define CPUID2STEPPING(cpuid) ((cpuid) & 0xf) 198 199 /* 200 * The Extended family bits should only be inspected when CPUID2FAMILY() 201 * returns 15. They are use to encode family value 16 to 270 (add 15). 202 * The Extended model hits are the high 4 bits of the model. 203 * They are only valid for family >= 15 or family 6 (intel, but all amd 204 * family 6 are documented to return zero bits for them). 205 */ 206 #define CPUID2EXTFAMILY(cpuid) (((cpuid) >> 20) & 0xff) 207 #define CPUID2EXTMODEL(cpuid) (((cpuid) >> 16) & 0xf) 208 209 /* 210 * Intel Deterministic Cache Parameter Leaf 211 * Fn0000_0004 212 */ 213 214 /* %eax */ 215 #define CPUID_DCP_CACHETYPE __BITS(4, 0) /* Cache type */ 216 #define CPUID_DCP_CACHETYPE_N 0 /* NULL */ 217 #define CPUID_DCP_CACHETYPE_D 1 /* Data cache */ 218 #define CPUID_DCP_CACHETYPE_I 2 /* Instruction cache */ 219 #define CPUID_DCP_CACHETYPE_U 3 /* Unified cache */ 220 #define CPUID_DCP_CACHELEVEL __BITS(7, 5) /* Cache level (start at 1) */ 221 #define CPUID_DCP_SELFINITCL __BIT(8) /* Self initializing cachelvl*/ 222 #define CPUID_DCP_FULLASSOC __BIT(9) /* Full associative */ 223 #define CPUID_DCP_SHAREING __BITS(25, 14) /* shareing */ 224 #define CPUID_DCP_CORE_P_PKG __BITS(31, 26) /* Cores/package */ 225 226 /* %ebx */ 227 #define CPUID_DCP_LINESIZE __BITS(11, 0) /* System coherency linesize */ 228 #define CPUID_DCP_PARTITIONS __BITS(21, 12) /* Physical line partitions */ 229 #define CPUID_DCP_WAYS __BITS(31, 22) /* Ways of associativity */ 230 231 /* Number of sets: %ecx */ 232 233 /* %edx */ 234 #define CPUID_DCP_INVALIDATE __BIT(0) /* WB invalidate/invalidate */ 235 #define CPUID_DCP_INCLUSIVE __BIT(1) /* Cache inclusiveness */ 236 #define CPUID_DCP_COMPLEX __BIT(2) /* Complex cache indexing */ 237 238 /* 239 * Intel Digital Thermal Sensor and 240 * Power Management, Fn0000_0006 - %eax. 241 */ 242 #define CPUID_DSPM_DTS 0x00000001 /* Digital Thermal Sensor */ 243 #define CPUID_DSPM_IDA 0x00000002 /* Intel Dynamic Acceleration */ 244 #define CPUID_DSPM_ARAT 0x00000004 /* Always Running APIC Timer */ 245 #define CPUID_DSPM_PLN 0x00000010 /* Power Limit Notification */ 246 #define CPUID_DSPM_CME 0x00000020 /* Clock Modulation Extension */ 247 #define CPUID_DSPM_PLTM 0x00000040 /* Package Level Thermal Management */ 248 249 #define CPUID_DSPM_FLAGS "\20" \ 250 "\1" "DTS" "\2" "IDA" "\3" "ARAT" \ 251 "\5" "PLN" "\6" "CME" "\7" "PLTM" 252 253 /* 254 * Intel Digital Thermal Sensor and 255 * Power Management, Fn0000_0006 - %ecx. 256 */ 257 #define CPUID_DSPM_HWF 0x00000001 /* MSR_APERF/MSR_MPERF available */ 258 259 #define CPUID_DSPM_FLAGS1 "\20" "\1" "HWF" 260 261 /* 262 * Intel Structured Extended Feature leaf 263 * Fn0000_0007 main leaf - %ebx. 264 */ 265 #define CPUID_SEF_FSGSBASE __BIT(0) 266 #define CPUID_SEF_TSC_ADJUST __BIT(1) 267 #define CPUID_SEF_BMI1 __BIT(3) 268 #define CPUID_SEF_HLE __BIT(4) 269 #define CPUID_SEF_AVX2 __BIT(5) 270 #define CPUID_SEF_SMEP __BIT(7) 271 #define CPUID_SEF_BMI2 __BIT(8) 272 #define CPUID_SEF_ERMS __BIT(9) 273 #define CPUID_SEF_INVPCID __BIT(10) 274 #define CPUID_SEF_RTM __BIT(11) 275 #define CPUID_SEF_QM __BIT(12) 276 #define CPUID_SEF_FPUCSDS __BIT(13) 277 #define CPUID_SEF_MPX __BIT(14) 278 #define CPUID_SEF_AVX512F __BIT(16) 279 #define CPUID_SEF_RDSEED __BIT(18) 280 #define CPUID_SEF_ADX __BIT(19) 281 #define CPUID_SEF_SMAP __BIT(20) 282 #define CPUID_SEF_PT __BIT(25) 283 #define CPUID_SEF_AVX512PF __BIT(26) 284 #define CPUID_SEF_AVX512ER __BIT(27) 285 #define CPUID_SEF_AVX512CD __BIT(28) 286 #define CPUID_SEF_SHA __BIT(29) 287 288 #define CPUID_SEF_FLAGS "\20" \ 289 "\1" "FSGSBASE" "\2" "TSCADJUST" "\4" "BMI1" \ 290 "\5" "HLE" "\6" "AVX2" "\10" "SMEP" \ 291 "\11" "BMI2" "\12" "ERMS" "\13" "INVPCID" "\14" "RTM" \ 292 "\15" "QM" "\16" "FPUCSDS" "\17" "MPX" \ 293 "\21" "AVX512F" "\23" "RDSEED" "\24" "ADX" \ 294 "\25" "SMAP" \ 295 "\32" "PT" "\33" "AVX512PF""\34" "AVX512ER"\ 296 "\35" "AVX512CD""\36" "SHA" 297 298 /* 299 * CPUID Processor extended state Enumeration Fn0000000d %eax 300 * 301 * Extended Control Register XCR0 302 */ 303 #define XCR0_X87 0x00000001 /* x87 FPU/MMX state */ 304 #define XCR0_SSE 0x00000002 /* SSE state */ 305 #define XCR0_AVX 0x00000004 /* AVX state (ymmn registers) */ 306 307 #define XCR0_FLAGS1 "\20" \ 308 "\1" "x87" "\2" "SSE" "\3" "AVX" "\4" "B03" 309 310 /* 311 * CPUID Processor extended state Enumeration Fn0000000d 312 * 313 * %ecx == 0: supported features info: 314 * %edx:%eax bits valid for XCR0 315 * %ebx Save area size for features enabled in XCR0 316 * %ecx Maximim save area size for all cpu features 317 * 318 * %ecx == 1: Bit 0 => xsaveopt instruction avalaible (sandy bridge onwards) 319 * 320 * %ecx >= 2: Save area details for XCR0 bit n 321 * %eax: size of save area for this feature 322 * %ebx: offset of save area for this feature 323 * %ecx, %edx: reserved 324 * All of %eax, %ebx, %ecx and %edx zero for unsupported features. 325 */ 326 327 #define CPUID_PES1_XSAVEOPT 0x00000001 /* xsaveopt instruction */ 328 329 #define CPUID_PES1_FLAGS "\20" \ 330 "\1" "XSAVEOPT" 331 332 /* Intel Fn80000001 extended features - %edx */ 333 #define CPUID_SYSCALL 0x00000800 /* SYSCALL/SYSRET */ 334 #define CPUID_XD 0x00100000 /* Execute Disable (like CPUID_NOX) */ 335 #define CPUID_P1GB 0x04000000 /* 1GB Large Page Support */ 336 #define CPUID_RDTSCP 0x08000000 /* Read TSC Pair Instruction */ 337 #define CPUID_EM64T 0x20000000 /* Intel EM64T */ 338 339 #define CPUID_INTEL_EXT_FLAGS "\20" \ 340 "\14" "SYSCALL/SYSRET" "\25" "XD" "\33" "P1GB" \ 341 "\34" "RDTSCP" "\36" "EM64T" 342 343 /* Intel Fn80000001 extended features - %ecx */ 344 #define CPUID_LAHF 0x00000001 /* LAHF/SAHF in IA-32e mode, 64bit sub*/ 345 /* 0x00000020 */ /* LZCNT. Same as AMD's CPUID_LZCNT */ 346 #define CPUID_PREFETCHW 0x00000100 /* PREFETCHW */ 347 348 #define CPUID_INTEL_FLAGS4 "\20" \ 349 "\1" "LAHF" "\02" "B01" "\03" "B02" \ 350 "\06" "LZCNT" \ 351 "\11" "PREFETCHW" 352 353 /* AMD/VIA Fn80000001 extended features - %edx */ 354 /* CPUID_SYSCALL SYSCALL/SYSRET */ 355 #define CPUID_MPC 0x00080000 /* Multiprocessing Capable */ 356 #define CPUID_NOX 0x00100000 /* No Execute Page Protection */ 357 #define CPUID_MMXX 0x00400000 /* AMD MMX Extensions */ 358 #define CPUID_FFXSR 0x02000000 /* FXSAVE/FXSTOR Extensions */ 359 /* CPUID_P1GB 1GB Large Page Support */ 360 /* CPUID_RDTSCP Read TSC Pair Instruction */ 361 /* CPUID_EM64T Long mode */ 362 #define CPUID_3DNOW2 0x40000000 /* 3DNow! Instruction Extension */ 363 #define CPUID_3DNOW 0x80000000 /* 3DNow! Instructions */ 364 365 #define CPUID_EXT_FLAGS "\20" \ 366 "\14" "SYSCALL/SYSRET" "\24" "MPC" "\25" "NOX" \ 367 "\27" "MXX" "\32" "FFXSR" "\33" "P1GB" "\34" "RDTSCP" \ 368 "\36" "LONG" "\37" "3DNOW2" "\40" "3DNOW" 369 370 /* AMD Fn80000001 extended features - %ecx */ 371 /* CPUID_LAHF LAHF/SAHF instruction */ 372 #define CPUID_CMPLEGACY 0x00000002 /* Compare Legacy */ 373 #define CPUID_SVM 0x00000004 /* Secure Virtual Machine */ 374 #define CPUID_EAPIC 0x00000008 /* Extended APIC space */ 375 #define CPUID_ALTMOVCR0 0x00000010 /* Lock Mov Cr0 */ 376 #define CPUID_LZCNT 0x00000020 /* LZCNT instruction */ 377 #define CPUID_SSE4A 0x00000040 /* SSE4A instruction set */ 378 #define CPUID_MISALIGNSSE 0x00000080 /* Misaligned SSE */ 379 #define CPUID_3DNOWPF 0x00000100 /* 3DNow Prefetch */ 380 #define CPUID_OSVW 0x00000200 /* OS visible workarounds */ 381 #define CPUID_IBS 0x00000400 /* Instruction Based Sampling */ 382 #define CPUID_XOP 0x00000800 /* XOP instruction set */ 383 #define CPUID_SKINIT 0x00001000 /* SKINIT */ 384 #define CPUID_WDT 0x00002000 /* watchdog timer support */ 385 #define CPUID_LWP 0x00008000 /* Light Weight Profiling */ 386 #define CPUID_FMA4 0x00010000 /* FMA4 instructions */ 387 #define CPUID_NODEID 0x00080000 /* NodeID MSR available*/ 388 #define CPUID_TBM 0x00200000 /* TBM instructions */ 389 #define CPUID_TOPOEXT 0x00400000 /* cpuid Topology Extension */ 390 391 #define CPUID_AMD_FLAGS4 "\20" \ 392 "\1" "LAHF" "\2" "CMPLEGACY" "\3" "SVM" "\4" "EAPIC" \ 393 "\5" "ALTMOVCR0" "\6" "LZCNT" "\7" "SSE4A" "\10" "MISALIGNSSE" \ 394 "\11" "3DNOWPREFETCH" \ 395 "\12" "OSVW" "\13" "IBS" "\14" "XOP" \ 396 "\15" "SKINIT" "\16" "WDT" "\17" "B14" "\20" "LWP" \ 397 "\21" "FMA4" "\22" "B17" "\23" "B18" "\24" "NodeID" \ 398 "\25" "B20" "\26" "TBM" "\27" "TopoExt" "\30" "B23" \ 399 "\31" "B24" "\32" "B25" "\33" "B26" "\34" "B27" \ 400 "\35" "B28" "\36" "B29" "\37" "B30" "\40" "B31" 401 402 /* 403 * AMD Advanced Power Management 404 * CPUID Fn8000_0007 %edx 405 */ 406 #define CPUID_APM_TS 0x00000001 /* Temperature Sensor */ 407 #define CPUID_APM_FID 0x00000002 /* Frequency ID control */ 408 #define CPUID_APM_VID 0x00000004 /* Voltage ID control */ 409 #define CPUID_APM_TTP 0x00000008 /* THERMTRIP (PCI F3xE4 register) */ 410 #define CPUID_APM_HTC 0x00000010 /* Hardware thermal control (HTC) */ 411 #define CPUID_APM_STC 0x00000020 /* Software thermal control (STC) */ 412 #define CPUID_APM_100 0x00000040 /* 100MHz multiplier control */ 413 #define CPUID_APM_HWP 0x00000080 /* HW P-State control */ 414 #define CPUID_APM_TSC 0x00000100 /* TSC invariant */ 415 #define CPUID_APM_CPB 0x00000200 /* Core performance boost */ 416 #define CPUID_APM_EFF 0x00000400 /* Effective Frequency (read-only) */ 417 418 #define CPUID_APM_FLAGS "\20" \ 419 "\1" "TS" "\2" "FID" "\3" "VID" "\4" "TTP" \ 420 "\5" "HTC" "\6" "STC" "\7" "100" "\10" "HWP" \ 421 "\11" "TSC" "\12" "CPB" "\13" "EffFreq" "\14" "B11" \ 422 "\15" "B12" 423 424 /* AMD Fn8000000a %edx features (SVM features) */ 425 #define CPUID_AMD_SVM_NP 0x00000001 426 #define CPUID_AMD_SVM_LbrVirt 0x00000002 427 #define CPUID_AMD_SVM_SVML 0x00000004 428 #define CPUID_AMD_SVM_NRIPS 0x00000008 429 #define CPUID_AMD_SVM_TSCRateCtrl 0x00000010 430 #define CPUID_AMD_SVM_VMCBCleanBits 0x00000020 431 #define CPUID_AMD_SVM_FlushByASID 0x00000040 432 #define CPUID_AMD_SVM_DecodeAssist 0x00000080 433 #define CPUID_AMD_SVM_PauseFilter 0x00000400 434 #define CPUID_AMD_SVM_FLAGS "\20" \ 435 "\1" "NP" "\2" "LbrVirt" "\3" "SVML" "\4" "NRIPS" \ 436 "\5" "TSCRate" "\6" "VMCBCleanBits" \ 437 "\7" "FlushByASID" "\10" "DecodeAssist" \ 438 "\11" "B08" "\12" "B09" "\13" "PauseFilter" "\14" "B11" \ 439 "\15" "B12" "\16" "B13" "\17" "B17" "\20" "B18" \ 440 "\21" "B19" 441 442 /* 443 * Centaur Extended Feature flags 444 */ 445 #define CPUID_VIA_HAS_RNG 0x00000004 /* Random number generator */ 446 #define CPUID_VIA_DO_RNG 0x00000008 447 #define CPUID_VIA_HAS_ACE 0x00000040 /* AES Encryption */ 448 #define CPUID_VIA_DO_ACE 0x00000080 449 #define CPUID_VIA_HAS_ACE2 0x00000100 /* AES+CTR instructions */ 450 #define CPUID_VIA_DO_ACE2 0x00000200 451 #define CPUID_VIA_HAS_PHE 0x00000400 /* SHA1+SHA256 HMAC */ 452 #define CPUID_VIA_DO_PHE 0x00000800 453 #define CPUID_VIA_HAS_PMM 0x00001000 /* RSA Instructions */ 454 #define CPUID_VIA_DO_PMM 0x00002000 455 456 #define CPUID_FLAGS_PADLOCK "\20" \ 457 "\3" "RNG" "\7" "AES" "\11" "AES/CTR" "\13" "SHA1/SHA256" \ 458 "\15" "RSA" 459 460 /* 461 * Model-specific registers for the i386 family 462 */ 463 #define MSR_P5_MC_ADDR 0x000 /* P5 only */ 464 #define MSR_P5_MC_TYPE 0x001 /* P5 only */ 465 #define MSR_TSC 0x010 466 #define MSR_CESR 0x011 /* P5 only (trap on P6) */ 467 #define MSR_CTR0 0x012 /* P5 only (trap on P6) */ 468 #define MSR_CTR1 0x013 /* P5 only (trap on P6) */ 469 #define MSR_APICBASE 0x01b 470 #define MSR_EBL_CR_POWERON 0x02a 471 #define MSR_EBC_FREQUENCY_ID 0x02c /* PIV only */ 472 #define MSR_TEST_CTL 0x033 473 #define MSR_BIOS_UPDT_TRIG 0x079 474 #define MSR_BBL_CR_D0 0x088 /* PII+ only */ 475 #define MSR_BBL_CR_D1 0x089 /* PII+ only */ 476 #define MSR_BBL_CR_D2 0x08a /* PII+ only */ 477 #define MSR_BIOS_SIGN 0x08b 478 #define MSR_PERFCTR0 0x0c1 479 #define MSR_PERFCTR1 0x0c2 480 #define MSR_FSB_FREQ 0x0cd /* Core Duo/Solo only */ 481 #define MSR_MPERF 0x0e7 482 #define MSR_APERF 0x0e8 483 #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ 484 #define MSR_MTRRcap 0x0fe 485 #define MSR_BBL_CR_ADDR 0x116 /* PII+ only */ 486 #define MSR_BBL_CR_DECC 0x118 /* PII+ only */ 487 #define MSR_BBL_CR_CTL 0x119 /* PII+ only */ 488 #define MSR_BBL_CR_TRIG 0x11a /* PII+ only */ 489 #define MSR_BBL_CR_BUSY 0x11b /* PII+ only */ 490 #define MSR_BBL_CR_CTR3 0x11e /* PII+ only */ 491 #define MSR_SYSENTER_CS 0x174 /* PII+ only */ 492 #define MSR_SYSENTER_ESP 0x175 /* PII+ only */ 493 #define MSR_SYSENTER_EIP 0x176 /* PII+ only */ 494 #define MSR_MCG_CAP 0x179 495 #define MSR_MCG_STATUS 0x17a 496 #define MSR_MCG_CTL 0x17b 497 #define MSR_EVNTSEL0 0x186 498 #define MSR_EVNTSEL1 0x187 499 #define MSR_PERF_STATUS 0x198 /* Pentium M */ 500 #define MSR_PERF_CTL 0x199 /* Pentium M */ 501 #define MSR_THERM_CONTROL 0x19a 502 #define MSR_THERM_INTERRUPT 0x19b 503 #define MSR_THERM_STATUS 0x19c 504 #define MSR_THERM2_CTL 0x19d /* Pentium M */ 505 #define MSR_MISC_ENABLE 0x1a0 506 #define MSR_TEMPERATURE_TARGET 0x1a2 507 #define MSR_DEBUGCTLMSR 0x1d9 508 #define MSR_LASTBRANCHFROMIP 0x1db 509 #define MSR_LASTBRANCHTOIP 0x1dc 510 #define MSR_LASTINTFROMIP 0x1dd 511 #define MSR_LASTINTTOIP 0x1de 512 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 513 #define MSR_MTRRphysBase0 0x200 514 #define MSR_MTRRphysMask0 0x201 515 #define MSR_MTRRphysBase1 0x202 516 #define MSR_MTRRphysMask1 0x203 517 #define MSR_MTRRphysBase2 0x204 518 #define MSR_MTRRphysMask2 0x205 519 #define MSR_MTRRphysBase3 0x206 520 #define MSR_MTRRphysMask3 0x207 521 #define MSR_MTRRphysBase4 0x208 522 #define MSR_MTRRphysMask4 0x209 523 #define MSR_MTRRphysBase5 0x20a 524 #define MSR_MTRRphysMask5 0x20b 525 #define MSR_MTRRphysBase6 0x20c 526 #define MSR_MTRRphysMask6 0x20d 527 #define MSR_MTRRphysBase7 0x20e 528 #define MSR_MTRRphysMask7 0x20f 529 #define MSR_MTRRphysBase8 0x210 530 #define MSR_MTRRphysMask8 0x211 531 #define MSR_MTRRphysBase9 0x212 532 #define MSR_MTRRphysMask9 0x213 533 #define MSR_MTRRphysBase10 0x214 534 #define MSR_MTRRphysMask10 0x215 535 #define MSR_MTRRphysBase11 0x216 536 #define MSR_MTRRphysMask11 0x217 537 #define MSR_MTRRphysBase12 0x218 538 #define MSR_MTRRphysMask12 0x219 539 #define MSR_MTRRphysBase13 0x21a 540 #define MSR_MTRRphysMask13 0x21b 541 #define MSR_MTRRphysBase14 0x21c 542 #define MSR_MTRRphysMask14 0x21d 543 #define MSR_MTRRphysBase15 0x21e 544 #define MSR_MTRRphysMask15 0x21f 545 #define MSR_MTRRfix64K_00000 0x250 546 #define MSR_MTRRfix16K_80000 0x258 547 #define MSR_MTRRfix16K_A0000 0x259 548 #define MSR_MTRRfix4K_C0000 0x268 549 #define MSR_MTRRfix4K_C8000 0x269 550 #define MSR_MTRRfix4K_D0000 0x26a 551 #define MSR_MTRRfix4K_D8000 0x26b 552 #define MSR_MTRRfix4K_E0000 0x26c 553 #define MSR_MTRRfix4K_E8000 0x26d 554 #define MSR_MTRRfix4K_F0000 0x26e 555 #define MSR_MTRRfix4K_F8000 0x26f 556 #define MSR_CR_PAT 0x277 557 #define MSR_MTRRdefType 0x2ff 558 #define MSR_MC0_CTL 0x400 559 #define MSR_MC0_STATUS 0x401 560 #define MSR_MC0_ADDR 0x402 561 #define MSR_MC0_MISC 0x403 562 #define MSR_MC1_CTL 0x404 563 #define MSR_MC1_STATUS 0x405 564 #define MSR_MC1_ADDR 0x406 565 #define MSR_MC1_MISC 0x407 566 #define MSR_MC2_CTL 0x408 567 #define MSR_MC2_STATUS 0x409 568 #define MSR_MC2_ADDR 0x40a 569 #define MSR_MC2_MISC 0x40b 570 #define MSR_MC4_CTL 0x40c 571 #define MSR_MC4_STATUS 0x40d 572 #define MSR_MC4_ADDR 0x40e 573 #define MSR_MC4_MISC 0x40f 574 #define MSR_MC3_CTL 0x410 575 #define MSR_MC3_STATUS 0x411 576 #define MSR_MC3_ADDR 0x412 577 #define MSR_MC3_MISC 0x413 578 /* 0x480 - 0x490 VMX */ 579 580 /* 581 * VIA "Nehemiah" MSRs 582 */ 583 #define MSR_VIA_RNG 0x0000110b 584 #define MSR_VIA_RNG_ENABLE 0x00000040 585 #define MSR_VIA_RNG_NOISE_MASK 0x00000300 586 #define MSR_VIA_RNG_NOISE_A 0x00000000 587 #define MSR_VIA_RNG_NOISE_B 0x00000100 588 #define MSR_VIA_RNG_2NOISE 0x00000300 589 #define MSR_VIA_ACE 0x00001107 590 #define MSR_VIA_ACE_ENABLE 0x10000000 591 592 /* 593 * VIA "Eden" MSRs 594 */ 595 #define MSR_VIA_FCR MSR_VIA_ACE 596 597 /* 598 * AMD K6/K7 MSRs. 599 */ 600 #define MSR_K6_UWCCR 0xc0000085 601 #define MSR_K7_EVNTSEL0 0xc0010000 602 #define MSR_K7_EVNTSEL1 0xc0010001 603 #define MSR_K7_EVNTSEL2 0xc0010002 604 #define MSR_K7_EVNTSEL3 0xc0010003 605 #define MSR_K7_PERFCTR0 0xc0010004 606 #define MSR_K7_PERFCTR1 0xc0010005 607 #define MSR_K7_PERFCTR2 0xc0010006 608 #define MSR_K7_PERFCTR3 0xc0010007 609 610 /* 611 * AMD K8 (Opteron) MSRs. 612 */ 613 #define MSR_SYSCFG 0xc0000010 614 615 #define MSR_EFER 0xc0000080 /* Extended feature enable */ 616 #define EFER_SCE 0x00000001 /* SYSCALL extension */ 617 #define EFER_LME 0x00000100 /* Long Mode Active */ 618 #define EFER_LMA 0x00000400 /* Long Mode Enabled */ 619 #define EFER_NXE 0x00000800 /* No-Execute Enabled */ 620 621 #define MSR_STAR 0xc0000081 /* 32 bit syscall gate addr */ 622 #define MSR_LSTAR 0xc0000082 /* 64 bit syscall gate addr */ 623 #define MSR_CSTAR 0xc0000083 /* compat syscall gate addr */ 624 #define MSR_SFMASK 0xc0000084 /* flags to clear on syscall */ 625 626 #define MSR_FSBASE 0xc0000100 /* 64bit offset for fs: */ 627 #define MSR_GSBASE 0xc0000101 /* 64bit offset for gs: */ 628 #define MSR_KERNELGSBASE 0xc0000102 /* storage for swapgs ins */ 629 630 #define MSR_VMCR 0xc0010114 /* Virtual Machine Control Register */ 631 #define VMCR_DPD 0x00000001 /* Debug port disable */ 632 #define VMCR_RINIT 0x00000002 /* intercept init */ 633 #define VMCR_DISA20 0x00000004 /* Disable A20 masking */ 634 #define VMCR_LOCK 0x00000008 /* SVM Lock */ 635 #define VMCR_SVMED 0x00000010 /* SVME Disable */ 636 #define MSR_SVMLOCK 0xc0010118 /* SVM Lock key */ 637 638 /* 639 * These require a 'passcode' for access. See cpufunc.h. 640 */ 641 #define MSR_HWCR 0xc0010015 642 #define HWCR_TLBCACHEDIS 0x00000008 643 #define HWCR_FFDIS 0x00000040 644 645 #define MSR_NB_CFG 0xc001001f 646 #define NB_CFG_DISIOREQLOCK 0x0000000000000008ULL 647 #define NB_CFG_DISDATMSK 0x0000001000000000ULL 648 #define NB_CFG_INITAPICCPUIDLO (1ULL << 54) 649 650 #define MSR_LS_CFG 0xc0011020 651 #define LS_CFG_DIS_LS2_SQUISH 0x02000000 652 653 #define MSR_IC_CFG 0xc0011021 654 #define IC_CFG_DIS_SEQ_PREFETCH 0x00000800 655 656 #define MSR_DC_CFG 0xc0011022 657 #define DC_CFG_DIS_CNV_WC_SSO 0x00000008 658 #define DC_CFG_DIS_SMC_CHK_BUF 0x00000400 659 #define DC_CFG_ERRATA_261 0x01000000 660 661 #define MSR_BU_CFG 0xc0011023 662 #define BU_CFG_ERRATA_298 0x0000000000000002ULL 663 #define BU_CFG_ERRATA_254 0x0000000000200000ULL 664 #define BU_CFG_ERRATA_309 0x0000000000800000ULL 665 #define BU_CFG_THRL2IDXCMPDIS 0x0000080000000000ULL 666 #define BU_CFG_WBPFSMCCHKDIS 0x0000200000000000ULL 667 #define BU_CFG_WBENHWSBDIS 0x0001000000000000ULL 668 669 #define MSR_DE_CFG 0xc0011029 670 #define DE_CFG_ERRATA_721 0x00000001 671 672 /* AMD Family10h MSRs */ 673 #define MSR_OSVW_ID_LENGTH 0xc0010140 674 #define MSR_OSVW_STATUS 0xc0010141 675 #define MSR_UCODE_AMD_PATCHLEVEL 0x0000008b 676 #define MSR_UCODE_AMD_PATCHLOADER 0xc0010020 677 678 /* X86 MSRs */ 679 #define MSR_RDTSCP_AUX 0xc0000103 680 681 /* 682 * Constants related to MTRRs 683 */ 684 #define MTRR_N64K 8 /* numbers of fixed-size entries */ 685 #define MTRR_N16K 16 686 #define MTRR_N4K 64 687 688 /* 689 * the following four 3-byte registers control the non-cacheable regions. 690 * These registers must be written as three separate bytes. 691 * 692 * NCRx+0: A31-A24 of starting address 693 * NCRx+1: A23-A16 of starting address 694 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 695 * 696 * The non-cacheable region's starting address must be aligned to the 697 * size indicated by the NCR_SIZE_xx field. 698 */ 699 #define NCR1 0xc4 700 #define NCR2 0xc7 701 #define NCR3 0xca 702 #define NCR4 0xcd 703 704 #define NCR_SIZE_0K 0 705 #define NCR_SIZE_4K 1 706 #define NCR_SIZE_8K 2 707 #define NCR_SIZE_16K 3 708 #define NCR_SIZE_32K 4 709 #define NCR_SIZE_64K 5 710 #define NCR_SIZE_128K 6 711 #define NCR_SIZE_256K 7 712 #define NCR_SIZE_512K 8 713 #define NCR_SIZE_1M 9 714 #define NCR_SIZE_2M 10 715 #define NCR_SIZE_4M 11 716 #define NCR_SIZE_8M 12 717 #define NCR_SIZE_16M 13 718 #define NCR_SIZE_32M 14 719 #define NCR_SIZE_4G 15 720 721 /* 722 * Performance monitor events. 723 * 724 * Note that 586-class and 686-class CPUs have different performance 725 * monitors available, and they are accessed differently: 726 * 727 * 686-class: `rdpmc' instruction 728 * 586-class: `rdmsr' instruction, CESR MSR 729 * 730 * The descriptions of these events are too lenghy to include here. 731 * See Appendix A of "Intel Architecture Software Developer's 732 * Manual, Volume 3: System Programming" for more information. 733 */ 734 735 /* 736 * 586-class CESR MSR format. Lower 16 bits is CTR0, upper 16 bits 737 * is CTR1. 738 */ 739 740 #define PMC5_CESR_EVENT 0x003f 741 #define PMC5_CESR_OS 0x0040 742 #define PMC5_CESR_USR 0x0080 743 #define PMC5_CESR_E 0x0100 744 #define PMC5_CESR_P 0x0200 745 746 #define PMC5_DATA_READ 0x00 747 #define PMC5_DATA_WRITE 0x01 748 #define PMC5_DATA_TLB_MISS 0x02 749 #define PMC5_DATA_READ_MISS 0x03 750 #define PMC5_DATA_WRITE_MISS 0x04 751 #define PMC5_WRITE_M_E 0x05 752 #define PMC5_DATA_LINES_WBACK 0x06 753 #define PMC5_DATA_CACHE_SNOOP 0x07 754 #define PMC5_DATA_CACHE_SNOOP_HIT 0x08 755 #define PMC5_MEM_ACCESS_BOTH_PIPES 0x09 756 #define PMC5_BANK_CONFLICTS 0x0a 757 #define PMC5_MISALIGNED_DATA 0x0b 758 #define PMC5_INST_READ 0x0c 759 #define PMC5_INST_TLB_MISS 0x0d 760 #define PMC5_INST_CACHE_MISS 0x0e 761 #define PMC5_SEGMENT_REG_LOAD 0x0f 762 #define PMC5_BRANCHES 0x12 763 #define PMC5_BTB_HITS 0x13 764 #define PMC5_BRANCH_TAKEN 0x14 765 #define PMC5_PIPELINE_FLUSH 0x15 766 #define PMC5_INST_EXECUTED 0x16 767 #define PMC5_INST_EXECUTED_V_PIPE 0x17 768 #define PMC5_BUS_UTILIZATION 0x18 769 #define PMC5_WRITE_BACKUP_STALL 0x19 770 #define PMC5_DATA_READ_STALL 0x1a 771 #define PMC5_WRITE_E_M_STALL 0x1b 772 #define PMC5_LOCKED_BUS 0x1c 773 #define PMC5_IO_CYCLE 0x1d 774 #define PMC5_NONCACHE_MEM_READ 0x1e 775 #define PMC5_AGI_STALL 0x1f 776 #define PMC5_FLOPS 0x22 777 #define PMC5_BP0_MATCH 0x23 778 #define PMC5_BP1_MATCH 0x24 779 #define PMC5_BP2_MATCH 0x25 780 #define PMC5_BP3_MATCH 0x26 781 #define PMC5_HARDWARE_INTR 0x27 782 #define PMC5_DATA_RW 0x28 783 #define PMC5_DATA_RW_MISS 0x29 784 785 /* 786 * 686-class Event Selector MSR format. 787 */ 788 789 #define PMC6_EVTSEL_EVENT 0x000000ff 790 #define PMC6_EVTSEL_UNIT 0x0000ff00 791 #define PMC6_EVTSEL_UNIT_SHIFT 8 792 #define PMC6_EVTSEL_USR (1 << 16) 793 #define PMC6_EVTSEL_OS (1 << 17) 794 #define PMC6_EVTSEL_E (1 << 18) 795 #define PMC6_EVTSEL_PC (1 << 19) 796 #define PMC6_EVTSEL_INT (1 << 20) 797 #define PMC6_EVTSEL_EN (1 << 22) /* PerfEvtSel0 only */ 798 #define PMC6_EVTSEL_INV (1 << 23) 799 #define PMC6_EVTSEL_COUNTER_MASK 0xff000000 800 #define PMC6_EVTSEL_COUNTER_MASK_SHIFT 24 801 802 /* Data Cache Unit */ 803 #define PMC6_DATA_MEM_REFS 0x43 804 #define PMC6_DCU_LINES_IN 0x45 805 #define PMC6_DCU_M_LINES_IN 0x46 806 #define PMC6_DCU_M_LINES_OUT 0x47 807 #define PMC6_DCU_MISS_OUTSTANDING 0x48 808 809 /* Instruction Fetch Unit */ 810 #define PMC6_IFU_IFETCH 0x80 811 #define PMC6_IFU_IFETCH_MISS 0x81 812 #define PMC6_ITLB_MISS 0x85 813 #define PMC6_IFU_MEM_STALL 0x86 814 #define PMC6_ILD_STALL 0x87 815 816 /* L2 Cache */ 817 #define PMC6_L2_IFETCH 0x28 818 #define PMC6_L2_LD 0x29 819 #define PMC6_L2_ST 0x2a 820 #define PMC6_L2_LINES_IN 0x24 821 #define PMC6_L2_LINES_OUT 0x26 822 #define PMC6_L2_M_LINES_INM 0x25 823 #define PMC6_L2_M_LINES_OUTM 0x27 824 #define PMC6_L2_RQSTS 0x2e 825 #define PMC6_L2_ADS 0x21 826 #define PMC6_L2_DBUS_BUSY 0x22 827 #define PMC6_L2_DBUS_BUSY_RD 0x23 828 829 /* External Bus Logic */ 830 #define PMC6_BUS_DRDY_CLOCKS 0x62 831 #define PMC6_BUS_LOCK_CLOCKS 0x63 832 #define PMC6_BUS_REQ_OUTSTANDING 0x60 833 #define PMC6_BUS_TRAN_BRD 0x65 834 #define PMC6_BUS_TRAN_RFO 0x66 835 #define PMC6_BUS_TRANS_WB 0x67 836 #define PMC6_BUS_TRAN_IFETCH 0x68 837 #define PMC6_BUS_TRAN_INVAL 0x69 838 #define PMC6_BUS_TRAN_PWR 0x6a 839 #define PMC6_BUS_TRANS_P 0x6b 840 #define PMC6_BUS_TRANS_IO 0x6c 841 #define PMC6_BUS_TRAN_DEF 0x6d 842 #define PMC6_BUS_TRAN_BURST 0x6e 843 #define PMC6_BUS_TRAN_ANY 0x70 844 #define PMC6_BUS_TRAN_MEM 0x6f 845 #define PMC6_BUS_DATA_RCV 0x64 846 #define PMC6_BUS_BNR_DRV 0x61 847 #define PMC6_BUS_HIT_DRV 0x7a 848 #define PMC6_BUS_HITM_DRDV 0x7b 849 #define PMC6_BUS_SNOOP_STALL 0x7e 850 851 /* Floating Point Unit */ 852 #define PMC6_FLOPS 0xc1 853 #define PMC6_FP_COMP_OPS_EXE 0x10 854 #define PMC6_FP_ASSIST 0x11 855 #define PMC6_MUL 0x12 856 #define PMC6_DIV 0x12 857 #define PMC6_CYCLES_DIV_BUSY 0x14 858 859 /* Memory Ordering */ 860 #define PMC6_LD_BLOCKS 0x03 861 #define PMC6_SB_DRAINS 0x04 862 #define PMC6_MISALIGN_MEM_REF 0x05 863 #define PMC6_EMON_KNI_PREF_DISPATCHED 0x07 /* P-III only */ 864 #define PMC6_EMON_KNI_PREF_MISS 0x4b /* P-III only */ 865 866 /* Instruction Decoding and Retirement */ 867 #define PMC6_INST_RETIRED 0xc0 868 #define PMC6_UOPS_RETIRED 0xc2 869 #define PMC6_INST_DECODED 0xd0 870 #define PMC6_EMON_KNI_INST_RETIRED 0xd8 871 #define PMC6_EMON_KNI_COMP_INST_RET 0xd9 872 873 /* Interrupts */ 874 #define PMC6_HW_INT_RX 0xc8 875 #define PMC6_CYCLES_INT_MASKED 0xc6 876 #define PMC6_CYCLES_INT_PENDING_AND_MASKED 0xc7 877 878 /* Branches */ 879 #define PMC6_BR_INST_RETIRED 0xc4 880 #define PMC6_BR_MISS_PRED_RETIRED 0xc5 881 #define PMC6_BR_TAKEN_RETIRED 0xc9 882 #define PMC6_BR_MISS_PRED_TAKEN_RET 0xca 883 #define PMC6_BR_INST_DECODED 0xe0 884 #define PMC6_BTB_MISSES 0xe2 885 #define PMC6_BR_BOGUS 0xe4 886 #define PMC6_BACLEARS 0xe6 887 888 /* Stalls */ 889 #define PMC6_RESOURCE_STALLS 0xa2 890 #define PMC6_PARTIAL_RAT_STALLS 0xd2 891 892 /* Segment Register Loads */ 893 #define PMC6_SEGMENT_REG_LOADS 0x06 894 895 /* Clocks */ 896 #define PMC6_CPU_CLK_UNHALTED 0x79 897 898 /* MMX Unit */ 899 #define PMC6_MMX_INSTR_EXEC 0xb0 /* Celeron, P-II, P-IIX only */ 900 #define PMC6_MMX_SAT_INSTR_EXEC 0xb1 /* P-II and P-III only */ 901 #define PMC6_MMX_UOPS_EXEC 0xb2 /* P-II and P-III only */ 902 #define PMC6_MMX_INSTR_TYPE_EXEC 0xb3 /* P-II and P-III only */ 903 #define PMC6_FP_MMX_TRANS 0xcc /* P-II and P-III only */ 904 #define PMC6_MMX_ASSIST 0xcd /* P-II and P-III only */ 905 #define PMC6_MMX_INSTR_RET 0xc3 /* P-II only */ 906 907 /* Segment Register Renaming */ 908 #define PMC6_SEG_RENAME_STALLS 0xd4 /* P-II and P-III only */ 909 #define PMC6_SEG_REG_RENAMES 0xd5 /* P-II and P-III only */ 910 #define PMC6_RET_SEG_RENAMES 0xd6 /* P-II and P-III only */ 911 912 /* 913 * AMD K7 Event Selector MSR format. 914 */ 915 916 #define K7_EVTSEL_EVENT 0x000000ff 917 #define K7_EVTSEL_UNIT 0x0000ff00 918 #define K7_EVTSEL_UNIT_SHIFT 8 919 #define K7_EVTSEL_USR (1 << 16) 920 #define K7_EVTSEL_OS (1 << 17) 921 #define K7_EVTSEL_E (1 << 18) 922 #define K7_EVTSEL_PC (1 << 19) 923 #define K7_EVTSEL_INT (1 << 20) 924 #define K7_EVTSEL_EN (1 << 22) 925 #define K7_EVTSEL_INV (1 << 23) 926 #define K7_EVTSEL_COUNTER_MASK 0xff000000 927 #define K7_EVTSEL_COUNTER_MASK_SHIFT 24 928 929 /* Segment Register Loads */ 930 #define K7_SEGMENT_REG_LOADS 0x20 931 932 #define K7_STORES_TO_ACTIVE_INST_STREAM 0x21 933 934 /* Data Cache Unit */ 935 #define K7_DATA_CACHE_ACCESS 0x40 936 #define K7_DATA_CACHE_MISS 0x41 937 #define K7_DATA_CACHE_REFILL 0x42 938 #define K7_DATA_CACHE_REFILL_SYSTEM 0x43 939 #define K7_DATA_CACHE_WBACK 0x44 940 #define K7_L2_DTLB_HIT 0x45 941 #define K7_L2_DTLB_MISS 0x46 942 #define K7_MISALIGNED_DATA_REF 0x47 943 #define K7_SYSTEM_REQUEST 0x64 944 #define K7_SYSTEM_REQUEST_TYPE 0x65 945 946 #define K7_SNOOP_HIT 0x73 947 #define K7_SINGLE_BIT_ECC_ERROR 0x74 948 #define K7_CACHE_LINE_INVAL 0x75 949 #define K7_CYCLES_PROCESSOR_IS_RUNNING 0x76 950 #define K7_L2_REQUEST 0x79 951 #define K7_L2_REQUEST_BUSY 0x7a 952 953 /* Instruction Fetch Unit */ 954 #define K7_IFU_IFETCH 0x80 955 #define K7_IFU_IFETCH_MISS 0x81 956 #define K7_IFU_REFILL_FROM_L2 0x82 957 #define K7_IFU_REFILL_FROM_SYSTEM 0x83 958 #define K7_ITLB_L1_MISS 0x84 959 #define K7_ITLB_L2_MISS 0x85 960 #define K7_SNOOP_RESYNC 0x86 961 #define K7_IFU_STALL 0x87 962 963 #define K7_RETURN_STACK_HITS 0x88 964 #define K7_RETURN_STACK_OVERFLOW 0x89 965 966 /* Retired */ 967 #define K7_RETIRED_INST 0xc0 968 #define K7_RETIRED_OPS 0xc1 969 #define K7_RETIRED_BRANCHES 0xc2 970 #define K7_RETIRED_BRANCH_MISPREDICTED 0xc3 971 #define K7_RETIRED_TAKEN_BRANCH 0xc4 972 #define K7_RETIRED_TAKEN_BRANCH_MISPREDICTED 0xc5 973 #define K7_RETIRED_FAR_CONTROL_TRANSFER 0xc6 974 #define K7_RETIRED_RESYNC_BRANCH 0xc7 975 #define K7_RETIRED_NEAR_RETURNS 0xc8 976 #define K7_RETIRED_NEAR_RETURNS_MISPREDICTED 0xc9 977 #define K7_RETIRED_INDIRECT_MISPREDICTED 0xca 978 979 /* Interrupts */ 980 #define K7_CYCLES_INT_MASKED 0xcd 981 #define K7_CYCLES_INT_PENDING_AND_MASKED 0xce 982 #define K7_HW_INTR_RECV 0xcf 983 984 #define K7_INSTRUCTION_DECODER_EMPTY 0xd0 985 #define K7_DISPATCH_STALLS 0xd1 986 #define K7_BRANCH_ABORTS_TO_RETIRE 0xd2 987 #define K7_SERIALIZE 0xd3 988 #define K7_SEGMENT_LOAD_STALL 0xd4 989 #define K7_ICU_FULL 0xd5 990 #define K7_RESERVATION_STATIONS_FULL 0xd6 991 #define K7_FPU_FULL 0xd7 992 #define K7_LS_FULL 0xd8 993 #define K7_ALL_QUIET_STALL 0xd9 994 #define K7_FAR_TRANSFER_OR_RESYNC_BRANCH_PENDING 0xda 995 996 #define K7_BP0_MATCH 0xdc 997 #define K7_BP1_MATCH 0xdd 998 #define K7_BP2_MATCH 0xde 999 #define K7_BP3_MATCH 0xdf 1000
Indexes created Tue Sep 30 20:09:53 GMT 2025