specialreg.h revision 1.9
1 /* $NetBSD: specialreg.h,v 1.9 2005/12/02 17:11:19 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1991 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of the University nor the names of its contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * @(#)specialreg.h 7.1 (Berkeley) 5/9/91 32 */ 33 34 /* 35 * Bits in 386 special registers: 36 */ 37 #define CR0_PE 0x00000001 /* Protected mode Enable */ 38 #define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */ 39 #define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */ 40 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 41 #define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */ 42 #define CR0_PG 0x80000000 /* PaGing enable */ 43 44 /* 45 * Bits in 486 special registers: 46 */ 47 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 48 #define CR0_WP 0x00010000 /* Write Protect (honor PG_RW in all modes) */ 49 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 50 #define CR0_NW 0x20000000 /* Not Write-through */ 51 #define CR0_CD 0x40000000 /* Cache Disable */ 52 53 /* 54 * Cyrix 486 DLC special registers, accessible as IO ports. 55 */ 56 #define CCR0 0xc0 /* configuration control register 0 */ 57 #define CCR0_NC0 0x01 /* first 64K of each 1M memory region is non-cacheable */ 58 #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 59 #define CCR0_A20M 0x04 /* enables A20M# input pin */ 60 #define CCR0_KEN 0x08 /* enables KEN# input pin */ 61 #define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */ 62 #define CCR0_BARB 0x20 /* flushes internal cache when entering hold state */ 63 #define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */ 64 #define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */ 65 66 #define CCR1 0xc1 /* configuration control register 1 */ 67 #define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */ 68 /* the remaining 7 bits of this register are reserved */ 69 70 /* 71 * bits in the pentiums %cr4 register: 72 */ 73 74 #define CR4_VME 0x00000001 /* virtual 8086 mode extension enable */ 75 #define CR4_PVI 0x00000002 /* protected mode virtual interrupt enable */ 76 #define CR4_TSD 0x00000004 /* restrict RDTSC instruction to cpl 0 only */ 77 #define CR4_DE 0x00000008 /* debugging extension */ 78 #define CR4_PSE 0x00000010 /* large (4MB) page size enable */ 79 #define CR4_PAE 0x00000020 /* physical address extension enable */ 80 #define CR4_MCE 0x00000040 /* machine check enable */ 81 #define CR4_PGE 0x00000080 /* page global enable */ 82 #define CR4_PCE 0x00000100 /* enable RDPMC instruction for all cpls */ 83 #define CR4_OSFXSR 0x00000200 /* enable fxsave/fxrestor and SSE */ 84 #define CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */ 85 86 /* 87 * CPUID "features" bits in %edx 88 */ 89 90 #define CPUID_FPU 0x00000001 /* processor has an FPU? */ 91 #define CPUID_VME 0x00000002 /* has virtual mode (%cr4's VME/PVI) */ 92 #define CPUID_DE 0x00000004 /* has debugging extension */ 93 #define CPUID_PSE 0x00000008 /* has page 4MB page size extension */ 94 #define CPUID_TSC 0x00000010 /* has time stamp counter */ 95 #define CPUID_MSR 0x00000020 /* has mode specific registers */ 96 #define CPUID_PAE 0x00000040 /* has phys address extension */ 97 #define CPUID_MCE 0x00000080 /* has machine check exception */ 98 #define CPUID_CX8 0x00000100 /* has CMPXCHG8B instruction */ 99 #define CPUID_APIC 0x00000200 /* has enabled APIC */ 100 #define CPUID_B10 0x00000400 /* reserved, MTRR */ 101 #define CPUID_SEP 0x00000800 /* has SYSENTER/SYSEXIT extension */ 102 #define CPUID_MTRR 0x00001000 /* has memory type range register */ 103 #define CPUID_PGE 0x00002000 /* has page global extension */ 104 #define CPUID_MCA 0x00004000 /* has machine check architecture */ 105 #define CPUID_CMOV 0x00008000 /* has CMOVcc instruction */ 106 #define CPUID_PAT 0x00010000 /* Page Attribute Table */ 107 #define CPUID_PSE36 0x00020000 /* 36-bit PSE */ 108 #define CPUID_PN 0x00040000 /* processor serial number */ 109 #define CPUID_CFLUSH 0x00080000 /* CFLUSH insn supported */ 110 #define CPUID_B20 0x00100000 /* reserved */ 111 #define CPUID_DS 0x00200000 /* Debug Store */ 112 #define CPUID_ACPI 0x00400000 /* ACPI performance modulation regs */ 113 #define CPUID_MMX 0x00800000 /* MMX supported */ 114 #define CPUID_FXSR 0x01000000 /* fast FP/MMX save/restore */ 115 #define CPUID_SSE 0x02000000 /* streaming SIMD extensions */ 116 #define CPUID_SSE2 0x04000000 /* streaming SIMD extensions #2 */ 117 #define CPUID_SS 0x08000000 /* self-snoop */ 118 #define CPUID_HTT 0x10000000 /* Hyper-Threading Technology */ 119 #define CPUID_TM 0x20000000 /* thermal monitor (TCC) */ 120 #define CPUID_IA64 0x40000000 /* IA-64 architecture */ 121 #define CPUID_SBF 0x80000000 /* signal break on FERR */ 122 123 #define CPUID_FLAGS1 "\20\1FPU\2VME\3DE\4PSE\5TSC\6MSR\7PAE" \ 124 "\10MCE\11CX8\12APIC\13B10\14SEP\15MTRR" 125 #define CPUID_MASK1 0x00001fff 126 #define CPUID_FLAGS2 "\20\16PGE\17MCA\20CMOV\21PAT\22PSE36\23PN\24CFLUSH" \ 127 "\25B20\26DS\27ACPI\30MMX" 128 #define CPUID_MASK2 0x00ffe000 129 #define CPUID_FLAGS3 "\20\31FXSR\32SSE\33SSE2\34SS\35HTT\36TM\37IA64\40SBF" 130 #define CPUID_MASK3 0xff000000 131 132 /* 133 * CPUID Intel extended features 134 */ 135 #define CPUID_SYSCALL 0x00000800 /* SYSCALL/SYSRET */ 136 #define CPUID_EM64T 0x20000000 /* Intel EM64T */ 137 138 #define CPUID_MASK4 0x20000800 139 #define CPUID_FLAGS4 "\20\14SYSCALL/SYSRET\36EM64T" 140 141 /* 142 * AMD/VIA processor specific flags. 143 */ 144 145 #define CPUID_MPC 0x00080000 /* Multiprocessing Capable */ 146 #define CPUID_NOX 0x00100000 /* No Execute Page Protection */ 147 #define CPUID_MMXX 0x00400000 /* AMD MMX Extensions */ 148 #define CPUID_3DNOW2 0x40000000 /* 3DNow! Instruction Extension */ 149 #define CPUID_3DNOW 0x80000000 /* 3DNow! Instructions */ 150 151 #define CPUID_EXT_FLAGS2 "\20\16PGE\17MCA\20CMOV\21PAT\22PSE36\23PN" \ 152 "\24MPC\25NOX\26B21\27MMXX\30MMX" 153 #define CPUID_EXT_FLAGS3 "\20\31FXSR\32SSE\33SSE2\34B27\35HTT\36LONG" \ 154 "\0373DNOW2\0403DNOW" 155 156 /* 157 * CPUID "features" bits in %ecx 158 */ 159 160 #define CPUID2_SSE3 0x00000001 /* Streaming SIMD Extensions 3 */ 161 #define CPUID2_MONITOR 0x00000008 /* MONITOR/MWAIT instructions */ 162 #define CPUID2_DS_CPL 0x00000010 /* CPL Qualified Debug Store */ 163 #define CPUID2_VMX 0x00000020 /* Virtual Machine Extensions */ 164 #define CPUID2_EST 0x00000080 /* Enhanced SpeedStep Technology */ 165 #define CPUID2_TM2 0x00000100 /* Thermal Monitor 2 */ 166 #define CPUID2_CID 0x00000400 /* Context ID */ 167 #define CPUID2_xTPR 0x00004000 /* Task Priority Messages disabled? */ 168 169 #define CPUID2_FLAGS "\20\1SSE3\4MONITOR\5DS-CPL\6VMX\10EST\11TM2\13CID\17xTPR" 170 171 #define CPUID2FAMILY(cpuid) (((cpuid) >> 8) & 15) 172 #define CPUID2MODEL(cpuid) (((cpuid) >> 4) & 15) 173 #define CPUID2STEPPING(cpuid) ((cpuid) & 15) 174 175 #define CPUID(code, eax, ebx, ecx, edx) \ 176 __asm("cpuid" \ 177 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) \ 178 : "a" (code)); 179 180 181 /* 182 * Model-specific registers for the i386 family 183 */ 184 #define MSR_P5_MC_ADDR 0x000 /* P5 only */ 185 #define MSR_P5_MC_TYPE 0x001 /* P5 only */ 186 #define MSR_TSC 0x010 187 #define MSR_CESR 0x011 /* P5 only (trap on P6) */ 188 #define MSR_CTR0 0x012 /* P5 only (trap on P6) */ 189 #define MSR_CTR1 0x013 /* P5 only (trap on P6) */ 190 #define MSR_APICBASE 0x01b 191 #define MSR_EBL_CR_POWERON 0x02a 192 #define MSR_TEST_CTL 0x033 193 #define MSR_BIOS_UPDT_TRIG 0x079 194 #define MSR_BBL_CR_D0 0x088 /* PII+ only */ 195 #define MSR_BBL_CR_D1 0x089 /* PII+ only */ 196 #define MSR_BBL_CR_D2 0x08a /* PII+ only */ 197 #define MSR_BIOS_SIGN 0x08b 198 #define MSR_PERFCTR0 0x0c1 199 #define MSR_PERFCTR1 0x0c2 200 #define MSR_MTRRcap 0x0fe 201 #define MSR_BBL_CR_ADDR 0x116 /* PII+ only */ 202 #define MSR_BBL_CR_DECC 0x118 /* PII+ only */ 203 #define MSR_BBL_CR_CTL 0x119 /* PII+ only */ 204 #define MSR_BBL_CR_TRIG 0x11a /* PII+ only */ 205 #define MSR_BBL_CR_BUSY 0x11b /* PII+ only */ 206 #define MSR_BBL_CR_CTR3 0x11e /* PII+ only */ 207 #define MSR_SYSENTER_CS 0x174 /* PII+ only */ 208 #define MSR_SYSENTER_ESP 0x175 /* PII+ only */ 209 #define MSR_SYSENTER_EIP 0x176 /* PII+ only */ 210 #define MSR_MCG_CAP 0x179 211 #define MSR_MCG_STATUS 0x17a 212 #define MSR_MCG_CTL 0x17b 213 #define MSR_EVNTSEL0 0x186 214 #define MSR_EVNTSEL1 0x187 215 #define MSR_PERF_STATUS 0x198 /* Pentium M */ 216 #define MSR_PERF_CTL 0x199 /* Pentium M */ 217 #define MSR_THERM_CONTROL 0x19a 218 #define MSR_THERM_INTERRUPT 0x19b 219 #define MSR_THERM_STATUS 0x19c 220 #define MSR_THERM2_CTL 0x19d /* Pentium M */ 221 #define MSR_MISC_ENABLE 0x1a0 222 #define MSR_DEBUGCTLMSR 0x1d9 223 #define MSR_LASTBRANCHFROMIP 0x1db 224 #define MSR_LASTBRANCHTOIP 0x1dc 225 #define MSR_LASTINTFROMIP 0x1dd 226 #define MSR_LASTINTTOIP 0x1de 227 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 228 #define MSR_MTRRphysBase0 0x200 229 #define MSR_MTRRphysMask0 0x201 230 #define MSR_MTRRphysBase1 0x202 231 #define MSR_MTRRphysMask1 0x203 232 #define MSR_MTRRphysBase2 0x204 233 #define MSR_MTRRphysMask2 0x205 234 #define MSR_MTRRphysBase3 0x206 235 #define MSR_MTRRphysMask3 0x207 236 #define MSR_MTRRphysBase4 0x208 237 #define MSR_MTRRphysMask4 0x209 238 #define MSR_MTRRphysBase5 0x20a 239 #define MSR_MTRRphysMask5 0x20b 240 #define MSR_MTRRphysBase6 0x20c 241 #define MSR_MTRRphysMask6 0x20d 242 #define MSR_MTRRphysBase7 0x20e 243 #define MSR_MTRRphysMask7 0x20f 244 #define MSR_MTRRfix64K_00000 0x250 245 #define MSR_MTRRfix16K_80000 0x258 246 #define MSR_MTRRfix16K_A0000 0x259 247 #define MSR_MTRRfix4K_C0000 0x268 248 #define MSR_MTRRfix4K_C8000 0x269 249 #define MSR_MTRRfix4K_D0000 0x26a 250 #define MSR_MTRRfix4K_D8000 0x26b 251 #define MSR_MTRRfix4K_E0000 0x26c 252 #define MSR_MTRRfix4K_E8000 0x26d 253 #define MSR_MTRRfix4K_F0000 0x26e 254 #define MSR_MTRRfix4K_F8000 0x26f 255 #define MSR_MTRRdefType 0x2ff 256 #define MSR_MC0_CTL 0x400 257 #define MSR_MC0_STATUS 0x401 258 #define MSR_MC0_ADDR 0x402 259 #define MSR_MC0_MISC 0x403 260 #define MSR_MC1_CTL 0x404 261 #define MSR_MC1_STATUS 0x405 262 #define MSR_MC1_ADDR 0x406 263 #define MSR_MC1_MISC 0x407 264 #define MSR_MC2_CTL 0x408 265 #define MSR_MC2_STATUS 0x409 266 #define MSR_MC2_ADDR 0x40a 267 #define MSR_MC2_MISC 0x40b 268 #define MSR_MC4_CTL 0x40c 269 #define MSR_MC4_STATUS 0x40d 270 #define MSR_MC4_ADDR 0x40e 271 #define MSR_MC4_MISC 0x40f 272 #define MSR_MC3_CTL 0x410 273 #define MSR_MC3_STATUS 0x411 274 #define MSR_MC3_ADDR 0x412 275 #define MSR_MC3_MISC 0x413 276 277 /* 278 * AMD K6/K7 MSRs. 279 */ 280 #define MSR_K6_UWCCR 0xc0000085 281 #define MSR_K7_EVNTSEL0 0xc0010000 282 #define MSR_K7_EVNTSEL1 0xc0010001 283 #define MSR_K7_EVNTSEL2 0xc0010002 284 #define MSR_K7_EVNTSEL3 0xc0010003 285 #define MSR_K7_PERFCTR0 0xc0010004 286 #define MSR_K7_PERFCTR1 0xc0010005 287 #define MSR_K7_PERFCTR2 0xc0010006 288 #define MSR_K7_PERFCTR3 0xc0010007 289 290 /* 291 * Constants related to MTRRs 292 */ 293 #define MTRR_N64K 8 /* numbers of fixed-size entries */ 294 #define MTRR_N16K 16 295 #define MTRR_N4K 64 296 297 /* 298 * the following four 3-byte registers control the non-cacheable regions. 299 * These registers must be written as three separate bytes. 300 * 301 * NCRx+0: A31-A24 of starting address 302 * NCRx+1: A23-A16 of starting address 303 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 304 * 305 * The non-cacheable region's starting address must be aligned to the 306 * size indicated by the NCR_SIZE_xx field. 307 */ 308 #define NCR1 0xc4 309 #define NCR2 0xc7 310 #define NCR3 0xca 311 #define NCR4 0xcd 312 313 #define NCR_SIZE_0K 0 314 #define NCR_SIZE_4K 1 315 #define NCR_SIZE_8K 2 316 #define NCR_SIZE_16K 3 317 #define NCR_SIZE_32K 4 318 #define NCR_SIZE_64K 5 319 #define NCR_SIZE_128K 6 320 #define NCR_SIZE_256K 7 321 #define NCR_SIZE_512K 8 322 #define NCR_SIZE_1M 9 323 #define NCR_SIZE_2M 10 324 #define NCR_SIZE_4M 11 325 #define NCR_SIZE_8M 12 326 #define NCR_SIZE_16M 13 327 #define NCR_SIZE_32M 14 328 #define NCR_SIZE_4G 15 329 330 /* 331 * Performance monitor events. 332 * 333 * Note that 586-class and 686-class CPUs have different performance 334 * monitors available, and they are accessed differently: 335 * 336 * 686-class: `rdpmc' instruction 337 * 586-class: `rdmsr' instruction, CESR MSR 338 * 339 * The descriptions of these events are too lenghy to include here. 340 * See Appendix A of "Intel Architecture Software Developer's 341 * Manual, Volume 3: System Programming" for more information. 342 */ 343 344 /* 345 * 586-class CESR MSR format. Lower 16 bits is CTR0, upper 16 bits 346 * is CTR1. 347 */ 348 349 #define PMC5_CESR_EVENT 0x003f 350 #define PMC5_CESR_OS 0x0040 351 #define PMC5_CESR_USR 0x0080 352 #define PMC5_CESR_E 0x0100 353 #define PMC5_CESR_P 0x0200 354 355 #define PMC5_DATA_READ 0x00 356 #define PMC5_DATA_WRITE 0x01 357 #define PMC5_DATA_TLB_MISS 0x02 358 #define PMC5_DATA_READ_MISS 0x03 359 #define PMC5_DATA_WRITE_MISS 0x04 360 #define PMC5_WRITE_M_E 0x05 361 #define PMC5_DATA_LINES_WBACK 0x06 362 #define PMC5_DATA_CACHE_SNOOP 0x07 363 #define PMC5_DATA_CACHE_SNOOP_HIT 0x08 364 #define PMC5_MEM_ACCESS_BOTH_PIPES 0x09 365 #define PMC5_BANK_CONFLICTS 0x0a 366 #define PMC5_MISALIGNED_DATA 0x0b 367 #define PMC5_INST_READ 0x0c 368 #define PMC5_INST_TLB_MISS 0x0d 369 #define PMC5_INST_CACHE_MISS 0x0e 370 #define PMC5_SEGMENT_REG_LOAD 0x0f 371 #define PMC5_BRANCHES 0x12 372 #define PMC5_BTB_HITS 0x13 373 #define PMC5_BRANCH_TAKEN 0x14 374 #define PMC5_PIPELINE_FLUSH 0x15 375 #define PMC5_INST_EXECUTED 0x16 376 #define PMC5_INST_EXECUTED_V_PIPE 0x17 377 #define PMC5_BUS_UTILIZATION 0x18 378 #define PMC5_WRITE_BACKUP_STALL 0x19 379 #define PMC5_DATA_READ_STALL 0x1a 380 #define PMC5_WRITE_E_M_STALL 0x1b 381 #define PMC5_LOCKED_BUS 0x1c 382 #define PMC5_IO_CYCLE 0x1d 383 #define PMC5_NONCACHE_MEM_READ 0x1e 384 #define PMC5_AGI_STALL 0x1f 385 #define PMC5_FLOPS 0x22 386 #define PMC5_BP0_MATCH 0x23 387 #define PMC5_BP1_MATCH 0x24 388 #define PMC5_BP2_MATCH 0x25 389 #define PMC5_BP3_MATCH 0x26 390 #define PMC5_HARDWARE_INTR 0x27 391 #define PMC5_DATA_RW 0x28 392 #define PMC5_DATA_RW_MISS 0x29 393 394 /* 395 * 686-class Event Selector MSR format. 396 */ 397 398 #define PMC6_EVTSEL_EVENT 0x000000ff 399 #define PMC6_EVTSEL_UNIT 0x0000ff00 400 #define PMC6_EVTSEL_UNIT_SHIFT 8 401 #define PMC6_EVTSEL_USR (1 << 16) 402 #define PMC6_EVTSEL_OS (1 << 17) 403 #define PMC6_EVTSEL_E (1 << 18) 404 #define PMC6_EVTSEL_PC (1 << 19) 405 #define PMC6_EVTSEL_INT (1 << 20) 406 #define PMC6_EVTSEL_EN (1 << 22) /* PerfEvtSel0 only */ 407 #define PMC6_EVTSEL_INV (1 << 23) 408 #define PMC6_EVTSEL_COUNTER_MASK 0xff000000 409 #define PMC6_EVTSEL_COUNTER_MASK_SHIFT 24 410 411 /* Data Cache Unit */ 412 #define PMC6_DATA_MEM_REFS 0x43 413 #define PMC6_DCU_LINES_IN 0x45 414 #define PMC6_DCU_M_LINES_IN 0x46 415 #define PMC6_DCU_M_LINES_OUT 0x47 416 #define PMC6_DCU_MISS_OUTSTANDING 0x48 417 418 /* Instruction Fetch Unit */ 419 #define PMC6_IFU_IFETCH 0x80 420 #define PMC6_IFU_IFETCH_MISS 0x81 421 #define PMC6_ITLB_MISS 0x85 422 #define PMC6_IFU_MEM_STALL 0x86 423 #define PMC6_ILD_STALL 0x87 424 425 /* L2 Cache */ 426 #define PMC6_L2_IFETCH 0x28 427 #define PMC6_L2_LD 0x29 428 #define PMC6_L2_ST 0x2a 429 #define PMC6_L2_LINES_IN 0x24 430 #define PMC6_L2_LINES_OUT 0x26 431 #define PMC6_L2_M_LINES_INM 0x25 432 #define PMC6_L2_M_LINES_OUTM 0x27 433 #define PMC6_L2_RQSTS 0x2e 434 #define PMC6_L2_ADS 0x21 435 #define PMC6_L2_DBUS_BUSY 0x22 436 #define PMC6_L2_DBUS_BUSY_RD 0x23 437 438 /* External Bus Logic */ 439 #define PMC6_BUS_DRDY_CLOCKS 0x62 440 #define PMC6_BUS_LOCK_CLOCKS 0x63 441 #define PMC6_BUS_REQ_OUTSTANDING 0x60 442 #define PMC6_BUS_TRAN_BRD 0x65 443 #define PMC6_BUS_TRAN_RFO 0x66 444 #define PMC6_BUS_TRANS_WB 0x67 445 #define PMC6_BUS_TRAN_IFETCH 0x68 446 #define PMC6_BUS_TRAN_INVAL 0x69 447 #define PMC6_BUS_TRAN_PWR 0x6a 448 #define PMC6_BUS_TRANS_P 0x6b 449 #define PMC6_BUS_TRANS_IO 0x6c 450 #define PMC6_BUS_TRAN_DEF 0x6d 451 #define PMC6_BUS_TRAN_BURST 0x6e 452 #define PMC6_BUS_TRAN_ANY 0x70 453 #define PMC6_BUS_TRAN_MEM 0x6f 454 #define PMC6_BUS_DATA_RCV 0x64 455 #define PMC6_BUS_BNR_DRV 0x61 456 #define PMC6_BUS_HIT_DRV 0x7a 457 #define PMC6_BUS_HITM_DRDV 0x7b 458 #define PMC6_BUS_SNOOP_STALL 0x7e 459 460 /* Floating Point Unit */ 461 #define PMC6_FLOPS 0xc1 462 #define PMC6_FP_COMP_OPS_EXE 0x10 463 #define PMC6_FP_ASSIST 0x11 464 #define PMC6_MUL 0x12 465 #define PMC6_DIV 0x12 466 #define PMC6_CYCLES_DIV_BUSY 0x14 467 468 /* Memory Ordering */ 469 #define PMC6_LD_BLOCKS 0x03 470 #define PMC6_SB_DRAINS 0x04 471 #define PMC6_MISALIGN_MEM_REF 0x05 472 #define PMC6_EMON_KNI_PREF_DISPATCHED 0x07 /* P-III only */ 473 #define PMC6_EMON_KNI_PREF_MISS 0x4b /* P-III only */ 474 475 /* Instruction Decoding and Retirement */ 476 #define PMC6_INST_RETIRED 0xc0 477 #define PMC6_UOPS_RETIRED 0xc2 478 #define PMC6_INST_DECODED 0xd0 479 #define PMC6_EMON_KNI_INST_RETIRED 0xd8 480 #define PMC6_EMON_KNI_COMP_INST_RET 0xd9 481 482 /* Interrupts */ 483 #define PMC6_HW_INT_RX 0xc8 484 #define PMC6_CYCLES_INT_MASKED 0xc6 485 #define PMC6_CYCLES_INT_PENDING_AND_MASKED 0xc7 486 487 /* Branches */ 488 #define PMC6_BR_INST_RETIRED 0xc4 489 #define PMC6_BR_MISS_PRED_RETIRED 0xc5 490 #define PMC6_BR_TAKEN_RETIRED 0xc9 491 #define PMC6_BR_MISS_PRED_TAKEN_RET 0xca 492 #define PMC6_BR_INST_DECODED 0xe0 493 #define PMC6_BTB_MISSES 0xe2 494 #define PMC6_BR_BOGUS 0xe4 495 #define PMC6_BACLEARS 0xe6 496 497 /* Stalls */ 498 #define PMC6_RESOURCE_STALLS 0xa2 499 #define PMC6_PARTIAL_RAT_STALLS 0xd2 500 501 /* Segment Register Loads */ 502 #define PMC6_SEGMENT_REG_LOADS 0x06 503 504 /* Clocks */ 505 #define PMC6_CPU_CLK_UNHALTED 0x79 506 507 /* MMX Unit */ 508 #define PMC6_MMX_INSTR_EXEC 0xb0 /* Celeron, P-II, P-IIX only */ 509 #define PMC6_MMX_SAT_INSTR_EXEC 0xb1 /* P-II and P-III only */ 510 #define PMC6_MMX_UOPS_EXEC 0xb2 /* P-II and P-III only */ 511 #define PMC6_MMX_INSTR_TYPE_EXEC 0xb3 /* P-II and P-III only */ 512 #define PMC6_FP_MMX_TRANS 0xcc /* P-II and P-III only */ 513 #define PMC6_MMX_ASSIST 0xcd /* P-II and P-III only */ 514 #define PMC6_MMX_INSTR_RET 0xc3 /* P-II only */ 515 516 /* Segment Register Renaming */ 517 #define PMC6_SEG_RENAME_STALLS 0xd4 /* P-II and P-III only */ 518 #define PMC6_SEG_REG_RENAMES 0xd5 /* P-II and P-III only */ 519 #define PMC6_RET_SEG_RENAMES 0xd6 /* P-II and P-III only */ 520 521 /* 522 * AMD K7 Event Selector MSR format. 523 */ 524 525 #define K7_EVTSEL_EVENT 0x000000ff 526 #define K7_EVTSEL_UNIT 0x0000ff00 527 #define K7_EVTSEL_UNIT_SHIFT 8 528 #define K7_EVTSEL_USR (1 << 16) 529 #define K7_EVTSEL_OS (1 << 17) 530 #define K7_EVTSEL_E (1 << 18) 531 #define K7_EVTSEL_PC (1 << 19) 532 #define K7_EVTSEL_INT (1 << 20) 533 #define K7_EVTSEL_EN (1 << 22) 534 #define K7_EVTSEL_INV (1 << 23) 535 #define K7_EVTSEL_COUNTER_MASK 0xff000000 536 #define K7_EVTSEL_COUNTER_MASK_SHIFT 24 537 538 /* Segment Register Loads */ 539 #define K7_SEGMENT_REG_LOADS 0x20 540 541 #define K7_STORES_TO_ACTIVE_INST_STREAM 0x21 542 543 /* Data Cache Unit */ 544 #define K7_DATA_CACHE_ACCESS 0x40 545 #define K7_DATA_CACHE_MISS 0x41 546 #define K7_DATA_CACHE_REFILL 0x42 547 #define K7_DATA_CACHE_REFILL_SYSTEM 0x43 548 #define K7_DATA_CACHE_WBACK 0x44 549 #define K7_L2_DTLB_HIT 0x45 550 #define K7_L2_DTLB_MISS 0x46 551 #define K7_MISALIGNED_DATA_REF 0x47 552 #define K7_SYSTEM_REQUEST 0x64 553 #define K7_SYSTEM_REQUEST_TYPE 0x65 554 555 #define K7_SNOOP_HIT 0x73 556 #define K7_SINGLE_BIT_ECC_ERROR 0x74 557 #define K7_CACHE_LINE_INVAL 0x75 558 #define K7_CYCLES_PROCESSOR_IS_RUNNING 0x76 559 #define K7_L2_REQUEST 0x79 560 #define K7_L2_REQUEST_BUSY 0x7a 561 562 /* Instruction Fetch Unit */ 563 #define K7_IFU_IFETCH 0x80 564 #define K7_IFU_IFETCH_MISS 0x81 565 #define K7_IFU_REFILL_FROM_L2 0x82 566 #define K7_IFU_REFILL_FROM_SYSTEM 0x83 567 #define K7_ITLB_L1_MISS 0x84 568 #define K7_ITLB_L2_MISS 0x85 569 #define K7_SNOOP_RESYNC 0x86 570 #define K7_IFU_STALL 0x87 571 572 #define K7_RETURN_STACK_HITS 0x88 573 #define K7_RETURN_STACK_OVERFLOW 0x89 574 575 /* Retired */ 576 #define K7_RETIRED_INST 0xc0 577 #define K7_RETIRED_OPS 0xc1 578 #define K7_RETIRED_BRANCHES 0xc2 579 #define K7_RETIRED_BRANCH_MISPREDICTED 0xc3 580 #define K7_RETIRED_TAKEN_BRANCH 0xc4 581 #define K7_RETIRED_TAKEN_BRANCH_MISPREDICTED 0xc5 582 #define K7_RETIRED_FAR_CONTROL_TRANSFER 0xc6 583 #define K7_RETIRED_RESYNC_BRANCH 0xc7 584 #define K7_RETIRED_NEAR_RETURNS 0xc8 585 #define K7_RETIRED_NEAR_RETURNS_MISPREDICTED 0xc9 586 #define K7_RETIRED_INDIRECT_MISPREDICTED 0xca 587 588 /* Interrupts */ 589 #define K7_CYCLES_INT_MASKED 0xcd 590 #define K7_CYCLES_INT_PENDING_AND_MASKED 0xce 591 #define K7_HW_INTR_RECV 0xcf 592 593 #define K7_INSTRUCTION_DECODER_EMPTY 0xd0 594 #define K7_DISPATCH_STALLS 0xd1 595 #define K7_BRANCH_ABORTS_TO_RETIRE 0xd2 596 #define K7_SERIALIZE 0xd3 597 #define K7_SEGMENT_LOAD_STALL 0xd4 598 #define K7_ICU_FULL 0xd5 599 #define K7_RESERVATION_STATIONS_FULL 0xd6 600 #define K7_FPU_FULL 0xd7 601 #define K7_LS_FULL 0xd8 602 #define K7_ALL_QUIET_STALL 0xd9 603 #define K7_FAR_TRANSFER_OR_RESYNC_BRANCH_PENDING 0xda 604 605 #define K7_BP0_MATCH 0xdc 606 #define K7_BP1_MATCH 0xdd 607 #define K7_BP2_MATCH 0xde 608 #define K7_BP3_MATCH 0xdf 609
Indexes created Mon Sep 29 21:09:56 GMT 2025