specialreg.h revision 1.98.2.22
1 /* $NetBSD: specialreg.h,v 1.98.2.22 2021/12/08 15:56:17 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2014-2019 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * Copyright (c) 1991 The Regents of the University of California. 31 * All rights reserved. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 1. Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * 2. Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in the 40 * documentation and/or other materials provided with the distribution. 41 * 3. Neither the name of the University nor the names of its contributors 42 * may be used to endorse or promote products derived from this software 43 * without specific prior written permission. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 * 57 * @(#)specialreg.h 7.1 (Berkeley) 5/9/91 58 */ 59 60 /* 61 * CR0 62 */ 63 #define CR0_PE 0x00000001 /* Protected mode Enable */ 64 #define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */ 65 #define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */ 66 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 67 #define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */ 68 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 69 #define CR0_WP 0x00010000 /* Write Protect (honor PG_RW in all modes) */ 70 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 71 #define CR0_NW 0x20000000 /* Not Write-through */ 72 #define CR0_CD 0x40000000 /* Cache Disable */ 73 #define CR0_PG 0x80000000 /* PaGing enable */ 74 75 /* 76 * Cyrix 486 DLC special registers, accessible as IO ports 77 */ 78 #define CCR0 0xc0 /* configuration control register 0 */ 79 #define CCR0_NC0 0x01 /* first 64K of each 1M memory region is non-cacheable */ 80 #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 81 #define CCR0_A20M 0x04 /* enables A20M# input pin */ 82 #define CCR0_KEN 0x08 /* enables KEN# input pin */ 83 #define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */ 84 #define CCR0_BARB 0x20 /* flushes internal cache when entering hold state */ 85 #define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */ 86 #define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */ 87 #define CCR1 0xc1 /* configuration control register 1 */ 88 #define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */ 89 90 /* 91 * CR4 92 */ 93 #define CR4_VME 0x00000001 /* virtual 8086 mode extension enable */ 94 #define CR4_PVI 0x00000002 /* protected mode virtual interrupt enable */ 95 #define CR4_TSD 0x00000004 /* restrict RDTSC instruction to cpl 0 */ 96 #define CR4_DE 0x00000008 /* debugging extension */ 97 #define CR4_PSE 0x00000010 /* large (4MB) page size enable */ 98 #define CR4_PAE 0x00000020 /* physical address extension enable */ 99 #define CR4_MCE 0x00000040 /* machine check enable */ 100 #define CR4_PGE 0x00000080 /* page global enable */ 101 #define CR4_PCE 0x00000100 /* enable RDPMC instruction for all cpls */ 102 #define CR4_OSFXSR 0x00000200 /* enable fxsave/fxrestor and SSE */ 103 #define CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */ 104 #define CR4_UMIP 0x00000800 /* user-mode instruction prevention */ 105 #define CR4_LA57 0x00001000 /* 57-bit linear addresses */ 106 #define CR4_VMXE 0x00002000 /* enable VMX operations */ 107 #define CR4_SMXE 0x00004000 /* enable SMX operations */ 108 #define CR4_FSGSBASE 0x00010000 /* enable *FSBASE and *GSBASE instructions */ 109 #define CR4_PCIDE 0x00020000 /* enable Process Context IDentifiers */ 110 #define CR4_OSXSAVE 0x00040000 /* enable xsave and xrestore */ 111 #define CR4_SMEP 0x00100000 /* enable SMEP support */ 112 #define CR4_SMAP 0x00200000 /* enable SMAP support */ 113 #define CR4_PKE 0x00400000 /* enable Protection Keys for user pages */ 114 #define CR4_CET 0x00800000 /* enable CET */ 115 #define CR4_PKS 0x01000000 /* enable Protection Keys for kern pages */ 116 117 /* 118 * Extended Control Register XCR0 119 */ 120 #define XCR0_X87 0x00000001 /* x87 FPU/MMX state */ 121 #define XCR0_SSE 0x00000002 /* SSE state */ 122 #define XCR0_YMM_Hi128 0x00000004 /* AVX-256 (ymmn registers) */ 123 #define XCR0_BNDREGS 0x00000008 /* Memory protection ext bounds */ 124 #define XCR0_BNDCSR 0x00000010 /* Memory protection ext state */ 125 #define XCR0_Opmask 0x00000020 /* AVX-512 Opmask */ 126 #define XCR0_ZMM_Hi256 0x00000040 /* AVX-512 upper 256 bits low regs */ 127 #define XCR0_Hi16_ZMM 0x00000080 /* AVX-512 512 bits upper registers */ 128 #define XCR0_PT 0x00000100 /* Processor Trace state */ 129 #define XCR0_PKRU 0x00000200 /* Protection Key state */ 130 #define XCR0_CET_U 0x00000800 /* User CET state */ 131 #define XCR0_CET_S 0x00001000 /* Kern CET state */ 132 #define XCR0_HDC 0x00002000 /* Hardware Duty Cycle state */ 133 #define XCR0_HWP 0x00010000 /* Hardware P-states */ 134 135 #define XCR0_FLAGS1 "\20" \ 136 "\1" "x87" "\2" "SSE" "\3" "AVX" \ 137 "\4" "BNDREGS" "\5" "BNDCSR" "\6" "Opmask" \ 138 "\7" "ZMM_Hi256" "\10" "Hi16_ZMM" "\11" "PT" \ 139 "\12" "PKRU" "\14" "CET_U" "\15" "CET_S" \ 140 "\16" "HDC" "\21" "HWP" 141 142 /* 143 * Known FPU bits, only these get enabled. The save area is sized for all the 144 * fields below. 145 */ 146 #define XCR0_FPU (XCR0_X87 | XCR0_SSE | XCR0_YMM_Hi128 | \ 147 XCR0_Opmask | XCR0_ZMM_Hi256 | XCR0_Hi16_ZMM) 148 149 /* 150 * CPUID "features" bits 151 */ 152 153 /* Fn00000001 %edx features */ 154 #define CPUID_FPU 0x00000001 /* processor has an FPU? */ 155 #define CPUID_VME 0x00000002 /* has virtual mode (%cr4's VME/PVI) */ 156 #define CPUID_DE 0x00000004 /* has debugging extension */ 157 #define CPUID_PSE 0x00000008 /* has 4MB page size extension */ 158 #define CPUID_TSC 0x00000010 /* has time stamp counter */ 159 #define CPUID_MSR 0x00000020 /* has model specific registers */ 160 #define CPUID_PAE 0x00000040 /* has phys address extension */ 161 #define CPUID_MCE 0x00000080 /* has machine check exception */ 162 #define CPUID_CX8 0x00000100 /* has CMPXCHG8B instruction */ 163 #define CPUID_APIC 0x00000200 /* has enabled APIC */ 164 #define CPUID_SEP 0x00000800 /* has SYSENTER/SYSEXIT extension */ 165 #define CPUID_MTRR 0x00001000 /* has memory type range register */ 166 #define CPUID_PGE 0x00002000 /* has page global extension */ 167 #define CPUID_MCA 0x00004000 /* has machine check architecture */ 168 #define CPUID_CMOV 0x00008000 /* has CMOVcc instruction */ 169 #define CPUID_PAT 0x00010000 /* Page Attribute Table */ 170 #define CPUID_PSE36 0x00020000 /* 36-bit PSE */ 171 #define CPUID_PSN 0x00040000 /* processor serial number */ 172 #define CPUID_CLFSH 0x00080000 /* CLFLUSH insn supported */ 173 #define CPUID_DS 0x00200000 /* Debug Store */ 174 #define CPUID_ACPI 0x00400000 /* ACPI performance modulation regs */ 175 #define CPUID_MMX 0x00800000 /* MMX supported */ 176 #define CPUID_FXSR 0x01000000 /* fast FP/MMX save/restore */ 177 #define CPUID_SSE 0x02000000 /* streaming SIMD extensions */ 178 #define CPUID_SSE2 0x04000000 /* streaming SIMD extensions #2 */ 179 #define CPUID_SS 0x08000000 /* self-snoop */ 180 #define CPUID_HTT 0x10000000 /* Hyper-Threading Technology */ 181 #define CPUID_TM 0x20000000 /* thermal monitor (TCC) */ 182 #define CPUID_PBE 0x80000000 /* Pending Break Enable */ 183 184 #define CPUID_FLAGS1 "\20" \ 185 "\1" "FPU" "\2" "VME" "\3" "DE" "\4" "PSE" \ 186 "\5" "TSC" "\6" "MSR" "\7" "PAE" "\10" "MCE" \ 187 "\11" "CX8" "\12" "APIC" "\13" "B10" "\14" "SEP" \ 188 "\15" "MTRR" "\16" "PGE" "\17" "MCA" "\20" "CMOV" \ 189 "\21" "PAT" "\22" "PSE36" "\23" "PN" "\24" "CLFLUSH" \ 190 "\25" "B20" "\26" "DS" "\27" "ACPI" "\30" "MMX" \ 191 "\31" "FXSR" "\32" "SSE" "\33" "SSE2" "\34" "SS" \ 192 "\35" "HTT" "\36" "TM" "\37" "IA64" "\40" "PBE" 193 194 /* Blacklists of CPUID flags - used to mask certain features */ 195 #ifdef XEN 196 #define CPUID_FEAT_BLACKLIST (CPUID_PGE|CPUID_PSE|CPUID_MTRR) 197 #else 198 #define CPUID_FEAT_BLACKLIST 0 199 #endif 200 201 /* 202 * CPUID "features" bits in Fn00000001 %ecx 203 */ 204 205 #define CPUID2_SSE3 0x00000001 /* Streaming SIMD Extensions 3 */ 206 #define CPUID2_PCLMULQDQ 0x00000002 /* PCLMULQDQ instructions */ 207 #define CPUID2_DTES64 0x00000004 /* 64-bit Debug Trace */ 208 #define CPUID2_MONITOR 0x00000008 /* MONITOR/MWAIT instructions */ 209 #define CPUID2_DS_CPL 0x00000010 /* CPL Qualified Debug Store */ 210 #define CPUID2_VMX 0x00000020 /* Virtual Machine Extensions */ 211 #define CPUID2_SMX 0x00000040 /* Safer Mode Extensions */ 212 #define CPUID2_EST 0x00000080 /* Enhanced SpeedStep Technology */ 213 #define CPUID2_TM2 0x00000100 /* Thermal Monitor 2 */ 214 #define CPUID2_SSSE3 0x00000200 /* Supplemental SSE3 */ 215 #define CPUID2_CNXTID 0x00000400 /* Context ID */ 216 #define CPUID2_SDBG 0x00000800 /* Silicon Debug */ 217 #define CPUID2_FMA 0x00001000 /* has Fused Multiply Add */ 218 #define CPUID2_CX16 0x00002000 /* has CMPXCHG16B instruction */ 219 #define CPUID2_XTPR 0x00004000 /* Task Priority Messages disabled? */ 220 #define CPUID2_PDCM 0x00008000 /* Perf/Debug Capability MSR */ 221 /* bit 16 unused 0x00010000 */ 222 #define CPUID2_PCID 0x00020000 /* Process Context ID */ 223 #define CPUID2_DCA 0x00040000 /* Direct Cache Access */ 224 #define CPUID2_SSE41 0x00080000 /* Streaming SIMD Extensions 4.1 */ 225 #define CPUID2_SSE42 0x00100000 /* Streaming SIMD Extensions 4.2 */ 226 #define CPUID2_X2APIC 0x00200000 /* xAPIC Extensions */ 227 #define CPUID2_MOVBE 0x00400000 /* MOVBE (move after byteswap) */ 228 #define CPUID2_POPCNT 0x00800000 /* popcount instruction available */ 229 #define CPUID2_DEADLINE 0x01000000 /* APIC Timer supports TSC Deadline */ 230 #define CPUID2_AESNI 0x02000000 /* AES instructions */ 231 #define CPUID2_XSAVE 0x04000000 /* XSAVE instructions */ 232 #define CPUID2_OSXSAVE 0x08000000 /* XGETBV/XSETBV instructions */ 233 #define CPUID2_AVX 0x10000000 /* AVX instructions */ 234 #define CPUID2_F16C 0x20000000 /* half precision conversion */ 235 #define CPUID2_RDRAND 0x40000000 /* RDRAND (hardware random number) */ 236 #define CPUID2_RAZ 0x80000000 /* RAZ. Indicates guest state. */ 237 238 #define CPUID2_FLAGS1 "\20" \ 239 "\1" "SSE3" "\2" "PCLMULQDQ" "\3" "DTES64" "\4" "MONITOR" \ 240 "\5" "DS-CPL" "\6" "VMX" "\7" "SMX" "\10" "EST" \ 241 "\11" "TM2" "\12" "SSSE3" "\13" "CID" "\14" "SDBG" \ 242 "\15" "FMA" "\16" "CX16" "\17" "xTPR" "\20" "PDCM" \ 243 "\21" "B16" "\22" "PCID" "\23" "DCA" "\24" "SSE41" \ 244 "\25" "SSE42" "\26" "X2APIC" "\27" "MOVBE" "\30" "POPCNT" \ 245 "\31" "DEADLINE" "\32" "AES" "\33" "XSAVE" "\34" "OSXSAVE" \ 246 "\35" "AVX" "\36" "F16C" "\37" "RDRAND" "\40" "RAZ" 247 248 /* CPUID Fn00000001 %eax */ 249 250 #define CPUID_TO_BASEFAMILY(cpuid) (((cpuid) >> 8) & 0xf) 251 #define CPUID_TO_BASEMODEL(cpuid) (((cpuid) >> 4) & 0xf) 252 #define CPUID_TO_STEPPING(cpuid) ((cpuid) & 0xf) 253 254 /* 255 * The Extended family bits should only be inspected when CPUID_TO_BASEFAMILY() 256 * returns 15. They are use to encode family value 16 to 270 (add 15). 257 * The Extended model bits are the high 4 bits of the model. 258 * They are only valid for family >= 15 or family 6 (intel, but all amd 259 * family 6 are documented to return zero bits for them). 260 */ 261 #define CPUID_TO_EXTFAMILY(cpuid) (((cpuid) >> 20) & 0xff) 262 #define CPUID_TO_EXTMODEL(cpuid) (((cpuid) >> 16) & 0xf) 263 264 /* The macros for the Display Family and the Display Model */ 265 #define CPUID_TO_FAMILY(cpuid) (CPUID_TO_BASEFAMILY(cpuid) \ 266 + ((CPUID_TO_BASEFAMILY(cpuid) != 0x0f) \ 267 ? 0 : CPUID_TO_EXTFAMILY(cpuid))) 268 #define CPUID_TO_MODEL(cpuid) (CPUID_TO_BASEMODEL(cpuid) \ 269 | ((CPUID_TO_BASEFAMILY(cpuid) != 0x0f) \ 270 && (CPUID_TO_BASEFAMILY(cpuid) != 0x06) \ 271 ? 0 : (CPUID_TO_EXTMODEL(cpuid) << 4))) 272 273 /* CPUID Fn00000001 %ebx */ 274 #define CPUID_BRAND_INDEX __BITS(7,0) 275 #define CPUID_CLFLUSH_SIZE __BITS(15,8) 276 #define CPUID_HTT_CORES __BITS(23,16) 277 #define CPUID_LOCAL_APIC_ID __BITS(31,24) 278 279 /* 280 * Intel Deterministic Cache Parameter Leaf 281 * Fn0000_0004 282 */ 283 284 /* %eax */ 285 #define CPUID_DCP_CACHETYPE __BITS(4, 0) /* Cache type */ 286 #define CPUID_DCP_CACHETYPE_N 0 /* NULL */ 287 #define CPUID_DCP_CACHETYPE_D 1 /* Data cache */ 288 #define CPUID_DCP_CACHETYPE_I 2 /* Instruction cache */ 289 #define CPUID_DCP_CACHETYPE_U 3 /* Unified cache */ 290 #define CPUID_DCP_CACHELEVEL __BITS(7, 5) /* Cache level (start at 1) */ 291 #define CPUID_DCP_SELFINITCL __BIT(8) /* Self initializing cachelvl*/ 292 #define CPUID_DCP_FULLASSOC __BIT(9) /* Full associative */ 293 #define CPUID_DCP_SHAREING __BITS(25, 14) /* shareing */ 294 #define CPUID_DCP_CORE_P_PKG __BITS(31, 26) /* Cores/package */ 295 296 /* %ebx */ 297 #define CPUID_DCP_LINESIZE __BITS(11, 0) /* System coherency linesize */ 298 #define CPUID_DCP_PARTITIONS __BITS(21, 12) /* Physical line partitions */ 299 #define CPUID_DCP_WAYS __BITS(31, 22) /* Ways of associativity */ 300 301 /* Number of sets: %ecx */ 302 303 /* %edx */ 304 #define CPUID_DCP_INVALIDATE __BIT(0) /* WB invalidate/invalidate */ 305 #define CPUID_DCP_INCLUSIVE __BIT(1) /* Cache inclusiveness */ 306 #define CPUID_DCP_COMPLEX __BIT(2) /* Complex cache indexing */ 307 308 /* 309 * Intel/AMD MONITOR/MWAIT 310 * Fn0000_0005 311 */ 312 /* %eax */ 313 #define CPUID_MON_MINSIZE __BITS(15, 0) /* Smallest monitor-line size */ 314 /* %ebx */ 315 #define CPUID_MON_MAXSIZE __BITS(15, 0) /* Largest monitor-line size */ 316 /* %ecx */ 317 #define CPUID_MON_EMX __BIT(0) /* MONITOR/MWAIT Extensions */ 318 #define CPUID_MON_IBE __BIT(1) /* Interrupt as Break Event */ 319 320 #define CPUID_MON_FLAGS "\20" \ 321 "\1" "EMX" "\2" "IBE" 322 323 /* %edx: number of substates for specific C-state */ 324 #define CPUID_MON_SUBSTATE(edx, cstate) (((edx) >> (cstate * 4)) & 0x0000000f) 325 326 /* 327 * Intel/AMD Digital Thermal Sensor and 328 * Power Management, Fn0000_0006 - %eax. 329 */ 330 #define CPUID_DSPM_DTS __BIT(0) /* Digital Thermal Sensor */ 331 #define CPUID_DSPM_IDA __BIT(1) /* Intel Dynamic Acceleration */ 332 #define CPUID_DSPM_ARAT __BIT(2) /* Always Running APIC Timer */ 333 #define CPUID_DSPM_PLN __BIT(4) /* Power Limit Notification */ 334 #define CPUID_DSPM_ECMD __BIT(5) /* Clock Modulation Extension */ 335 #define CPUID_DSPM_PTM __BIT(6) /* Package Level Thermal Management */ 336 #define CPUID_DSPM_HWP __BIT(7) /* HWP */ 337 #define CPUID_DSPM_HWP_NOTIFY __BIT(8) /* HWP Notification */ 338 #define CPUID_DSPM_HWP_ACTWIN __BIT(9) /* HWP Activity Window */ 339 #define CPUID_DSPM_HWP_EPP __BIT(10) /* HWP Energy Performance Preference */ 340 #define CPUID_DSPM_HWP_PLR __BIT(11) /* HWP Package Level Request */ 341 #define CPUID_DSPM_HDC __BIT(13) /* Hardware Duty Cycling */ 342 #define CPUID_DSPM_TBMT3 __BIT(14) /* Turbo Boost Max Technology 3.0 */ 343 #define CPUID_DSPM_HWP_CAP __BIT(15) /* HWP Capabilities */ 344 #define CPUID_DSPM_HWP_PECI __BIT(16) /* HWP PECI override */ 345 #define CPUID_DSPM_HWP_FLEX __BIT(17) /* Flexible HWP */ 346 #define CPUID_DSPM_HWP_FAST __BIT(18) /* Fast access for IA32_HWP_REQUEST */ 347 #define CPUID_DSPM_HW_FEEDBACK __BIT(19) /* HW_FEEDBACK*, IA32_PACKAGE_TERM* */ 348 #define CPUID_DSPM_HWP_IGNIDL __BIT(20) /* Ignore Idle Logical Processor HWP */ 349 350 #define CPUID_DSPM_FLAGS "\20" \ 351 "\1" "DTS" "\2" "IDA" "\3" "ARAT" \ 352 "\5" "PLN" "\6" "ECMD" "\7" "PTM" "\10" "HWP" \ 353 "\11" "HWP_NOTIFY" "\12" "HWP_ACTWIN" "\13" "HWP_EPP" "\14" "HWP_PLR" \ 354 "\16" "HDC" "\17" "TBM3" "\20" "HWP_CAP" \ 355 "\21" "HWP_PECI" "\22" "HWP_FLEX" "\23" "HWP_FAST" "\24HW_FEEDBACK" \ 356 "\25" "HWP_IGNIDL" 357 358 /* 359 * Intel/AMD Digital Thermal Sensor and 360 * Power Management, Fn0000_0006 - %ecx. 361 */ 362 #define CPUID_DSPM_HWF 0x00000001 /* MSR_APERF/MSR_MPERF available */ 363 #define CPUID_DSPM_EPB 0x00000008 /* Energy Performance Bias */ 364 365 #define CPUID_DSPM_FLAGS1 "\20" "\1" "HWF" "\4" "EPB" 366 367 /* 368 * Intel/AMD Structured Extended Feature leaf Fn0000_0007 369 * %ecx == 0: Subleaf 0 370 * %eax: The Maximum input value for supported subleaf. 371 * %ebx: Feature bits. 372 * %ecx: Feature bits. 373 * %edx: Feature bits. 374 * 375 * %ecx == 1: Structure Extendede Feature Enumeration Sub-leaf 376 * %eax: See below. 377 */ 378 379 /* %ecx = 0, %ebx */ 380 #define CPUID_SEF_FSGSBASE __BIT(0) /* {RD,WR}{FS,GS}BASE */ 381 #define CPUID_SEF_TSC_ADJUST __BIT(1) /* IA32_TSC_ADJUST MSR support */ 382 #define CPUID_SEF_SGX __BIT(2) /* Software Guard Extensions */ 383 #define CPUID_SEF_BMI1 __BIT(3) /* advanced bit manipulation ext. 1st grp */ 384 #define CPUID_SEF_HLE __BIT(4) /* Hardware Lock Elision */ 385 #define CPUID_SEF_AVX2 __BIT(5) /* Advanced Vector Extensions 2 */ 386 #define CPUID_SEF_FDPEXONLY __BIT(6) /* x87FPU Data ptr updated only on x87exp */ 387 #define CPUID_SEF_SMEP __BIT(7) /* Supervisor-Mode Execution Prevention */ 388 #define CPUID_SEF_BMI2 __BIT(8) /* advanced bit manipulation ext. 2nd grp */ 389 #define CPUID_SEF_ERMS __BIT(9) /* Enhanced REP MOVSB/STOSB */ 390 #define CPUID_SEF_INVPCID __BIT(10) /* INVPCID instruction */ 391 #define CPUID_SEF_RTM __BIT(11) /* Restricted Transactional Memory */ 392 #define CPUID_SEF_QM __BIT(12) /* Resource Director Technology Monitoring */ 393 #define CPUID_SEF_FPUCSDS __BIT(13) /* Deprecate FPU CS and FPU DS values */ 394 #define CPUID_SEF_MPX __BIT(14) /* Memory Protection Extensions */ 395 #define CPUID_SEF_PQE __BIT(15) /* Resource Director Technology Allocation */ 396 #define CPUID_SEF_AVX512F __BIT(16) /* AVX-512 Foundation */ 397 #define CPUID_SEF_AVX512DQ __BIT(17) /* AVX-512 Double/Quadword */ 398 #define CPUID_SEF_RDSEED __BIT(18) /* RDSEED instruction */ 399 #define CPUID_SEF_ADX __BIT(19) /* ADCX/ADOX instructions */ 400 #define CPUID_SEF_SMAP __BIT(20) /* Supervisor-Mode Access Prevention */ 401 #define CPUID_SEF_AVX512_IFMA __BIT(21) /* AVX-512 Integer Fused Multiply Add */ 402 /* Bit 22 was PCOMMIT */ 403 #define CPUID_SEF_CLFLUSHOPT __BIT(23) /* Cache Line FLUSH OPTimized */ 404 #define CPUID_SEF_CLWB __BIT(24) /* Cache Line Write Back */ 405 #define CPUID_SEF_PT __BIT(25) /* Processor Trace */ 406 #define CPUID_SEF_AVX512PF __BIT(26) /* AVX-512 PreFetch */ 407 #define CPUID_SEF_AVX512ER __BIT(27) /* AVX-512 Exponential and Reciprocal */ 408 #define CPUID_SEF_AVX512CD __BIT(28) /* AVX-512 Conflict Detection */ 409 #define CPUID_SEF_SHA __BIT(29) /* SHA Extensions */ 410 #define CPUID_SEF_AVX512BW __BIT(30) /* AVX-512 Byte and Word */ 411 #define CPUID_SEF_AVX512VL __BIT(31) /* AVX-512 Vector Length */ 412 413 #define CPUID_SEF_FLAGS "\20" \ 414 "\1" "FSGSBASE" "\2" "TSCADJUST" "\3" "SGX" "\4" "BMI1" \ 415 "\5" "HLE" "\6" "AVX2" "\7" "FDPEXONLY" "\10" "SMEP" \ 416 "\11" "BMI2" "\12" "ERMS" "\13" "INVPCID" "\14" "RTM" \ 417 "\15" "QM" "\16" "FPUCSDS" "\17" "MPX" "\20" "PQE" \ 418 "\21" "AVX512F" "\22" "AVX512DQ" "\23" "RDSEED" "\24" "ADX" \ 419 "\25" "SMAP" "\26" "AVX512_IFMA" "\30" "CLFLUSHOPT" \ 420 "\31" "CLWB" "\32" "PT" "\33" "AVX512PF" "\34" "AVX512ER" \ 421 "\35" "AVX512CD""\36" "SHA" "\37" "AVX512BW" "\40" "AVX512VL" 422 423 /* %ecx = 0, %ecx */ 424 #define CPUID_SEF_PREFETCHWT1 __BIT(0) /* PREFETCHWT1 instruction */ 425 #define CPUID_SEF_AVX512_VBMI __BIT(1) /* AVX-512 Vector Byte Manipulation */ 426 #define CPUID_SEF_UMIP __BIT(2) /* User-Mode Instruction prevention */ 427 #define CPUID_SEF_PKU __BIT(3) /* Protection Keys for User-mode pages */ 428 #define CPUID_SEF_OSPKE __BIT(4) /* OS has set CR4.PKE to ena. protec. keys */ 429 #define CPUID_SEF_WAITPKG __BIT(5) /* TPAUSE,UMONITOR,UMWAIT */ 430 #define CPUID_SEF_AVX512_VBMI2 __BIT(6) /* AVX-512 Vector Byte Manipulation 2 */ 431 #define CPUID_SEF_CET_SS __BIT(7) /* CET Shadow Stack */ 432 #define CPUID_SEF_GFNI __BIT(8) 433 #define CPUID_SEF_VAES __BIT(9) 434 #define CPUID_SEF_VPCLMULQDQ __BIT(10) 435 #define CPUID_SEF_AVX512_VNNI __BIT(11) /* Vector neural Network Instruction */ 436 #define CPUID_SEF_AVX512_BITALG __BIT(12) 437 #define CPUID_SEF_TME_EN __BIT(13) /* Total Memory Encryption */ 438 #define CPUID_SEF_AVX512_VPOPCNTDQ __BIT(14) 439 #define CPUID_SEF_LA57 __BIT(16) /* 57bit linear addr & 5LVL paging */ 440 #define CPUID_SEF_MAWAU __BITS(21, 17) /* MAWAU for BND{LD,ST}X */ 441 #define CPUID_SEF_RDPID __BIT(22) /* RDPID and IA32_TSC_AUX */ 442 #define CPUID_SEF_KL __BIT(23) /* Key Locker */ 443 #define CPUID_SEF_CLDEMOTE __BIT(25) /* Cache line demote */ 444 #define CPUID_SEF_MOVDIRI __BIT(27) /* MOVDIRI instruction */ 445 #define CPUID_SEF_MOVDIR64B __BIT(28) /* MOVDIR64B instruction */ 446 #define CPUID_SEF_SGXLC __BIT(30) /* SGX Launch Configuration */ 447 #define CPUID_SEF_PKS __BIT(31) /* Protection Keys for Kern-mode pages */ 448 449 #define CPUID_SEF_FLAGS1 "\177\20" \ 450 "b\0PREFETCHWT1\0" "b\1AVX512_VBMI\0" "b\2UMIP\0" "b\3PKU\0" \ 451 "b\4OSPKE\0" "b\5WAITPKG\0" "b\6AVX512_VBMI2\0" "b\7CET_SS\0" \ 452 "b\10GFNI\0" "b\11VAES\0" "b\12VPCLMULQDQ\0" "b\13AVX512_VNNI\0"\ 453 "b\14AVX512_BITALG\0" "b\15TME_EN\0" "b\16AVX512_VPOPCNTDQ\0" \ 454 "b\20LA57\0" \ 455 "f\21\5MAWAU\0" "b\26RDPID\0" "b\27KL\0" \ 456 "b\31CLDEMOTE\0" "b\33MOVDIRI\0" \ 457 "b\34MOVDIR64B\0" "b\36SGXLC\0" "b\37PKS\0" 458 459 /* %ecx = 0, %edx */ 460 #define CPUID_SEF_AVX512_4VNNIW __BIT(2) 461 #define CPUID_SEF_AVX512_4FMAPS __BIT(3) 462 #define CPUID_SEF_FSREP_MOV __BIT(4) /* Fast Short REP MOV */ 463 #define CPUID_SEF_AVX512_VP2INTERSECT __BIT(8) 464 #define CPUID_SEF_SRBDS_CTRL __BIT(9) /* IA32_MCU_OPT_CTRL */ 465 #define CPUID_SEF_MD_CLEAR __BIT(10) 466 #define CPUID_SEF_TSX_FORCE_ABORT __BIT(13) /* MSR_TSX_FORCE_ABORT bit 0 */ 467 #define CPUID_SEF_SERIALIZE __BIT(14) /* SERIALIZE instruction */ 468 #define CPUID_SEF_HYBRID __BIT(15) /* Hybrid part */ 469 #define CPUID_SEF_TSXLDTRK __BIT(16) /* TSX suspend load addr tracking */ 470 #define CPUID_SEF_PCONFIG __BIT(18) /* Platform CONFIGuration */ 471 #define CPUID_SEF_CET_IBT __BIT(20) /* CET Indirect Branch Tracking */ 472 #define CPUID_SEF_IBRS __BIT(26) /* IBRS / IBPB Speculation Control */ 473 #define CPUID_SEF_STIBP __BIT(27) /* STIBP Speculation Control */ 474 #define CPUID_SEF_L1D_FLUSH __BIT(28) /* IA32_FLUSH_CMD MSR */ 475 #define CPUID_SEF_ARCH_CAP __BIT(29) /* IA32_ARCH_CAPABILITIES */ 476 #define CPUID_SEF_CORE_CAP __BIT(30) /* IA32_CORE_CAPABILITIES */ 477 #define CPUID_SEF_SSBD __BIT(31) /* Speculative Store Bypass Disable */ 478 479 #define CPUID_SEF_FLAGS2 "\20" \ 480 "\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS" \ 481 "\5" "FSREP_MOV" \ 482 "\11VP2INTERSECT" "\12SRBDS_CTRL" "\13MD_CLEAR" \ 483 "\16TSX_FORCE_ABORT" "\17SERIALIZE" "\20HYBRID" \ 484 "\21" "TSXLDTRK" "\23" "PCONFIG" \ 485 "\25" "CET_IBT" \ 486 "\33" "IBRS" "\34" "STIBP" \ 487 "\35" "L1D_FLUSH" "\36" "ARCH_CAP" "\37CORE_CAP" "\40" "SSBD" 488 489 /* %ecx = 1, %eax */ 490 #define CPUID_SEF_AVX512_BF16 __BIT(5) 491 #define CPUID_SEF1_FLAGS_A "\20" \ 492 "\6" "AVX512_BF16" 493 /* 494 * Intel CPUID Architectural Performance Monitoring Fn0000000a 495 * 496 * See also src/usr.sbin/tprof/arch/tprof_x86.c 497 */ 498 499 /* %eax */ 500 #define CPUID_PERF_VERSION __BITS(7, 0) /* Version ID */ 501 #define CPUID_PERF_NGPPC __BITS(15, 8) /* Num of G.P. perf counter */ 502 #define CPUID_PERF_NBWGPPC __BITS(23, 16) /* Bit width of G.P. perfcnt */ 503 #define CPUID_PERF_BVECLEN __BITS(31, 24) /* Length of EBX bit vector */ 504 505 #define CPUID_PERF_FLAGS0 "\177\20" \ 506 "f\0\10VERSION\0" "f\10\10GPCounter\0" \ 507 "f\20\10GPBitwidth\0" "f\30\10Vectorlen\0" 508 509 /* %ebx */ 510 #define CPUID_PERF_CORECYCL __BIT(0) /* No core cycle */ 511 #define CPUID_PERF_INSTRETRY __BIT(1) /* No instruction retried */ 512 #define CPUID_PERF_REFCYCL __BIT(2) /* No reference cycles */ 513 #define CPUID_PERF_LLCREF __BIT(3) /* No LLCache reference */ 514 #define CPUID_PERF_LLCMISS __BIT(4) /* No LLCache miss */ 515 #define CPUID_PERF_BRINSRETR __BIT(5) /* No branch inst. retried */ 516 #define CPUID_PERF_BRMISPRRETR __BIT(6) /* No branch mispredict retry */ 517 518 #define CPUID_PERF_FLAGS1 "\177\20" \ 519 "b\0CORECYCL\0" "b\1INSTRETRY\0" "b\2REFCYCL\0" "b\3LLCREF\0" \ 520 "b\4LLCMISS\0" "b\5BRINSRETR\0" "b\6BRMISPRRETR\0" 521 522 /* %edx */ 523 #define CPUID_PERF_NFFPC __BITS(4, 0) /* Num of fixed-funct perfcnt */ 524 #define CPUID_PERF_NBWFFPC __BITS(12, 5) /* Bit width of fixed-func pc */ 525 #define CPUID_PERF_ANYTHREADDEPR __BIT(15) /* Any Thread deprecation */ 526 527 #define CPUID_PERF_FLAGS3 "\177\20" \ 528 "f\0\5FixedFunc\0" "f\5\10FFBitwidth\0" "b\17ANYTHREADDEPR\0" 529 530 /* 531 * Intel CPUID Extended Topology Enumeration Fn0000000b 532 * %ecx == level number 533 * %eax: See below. 534 * %ebx: Number of logical processors at this level. 535 * %ecx: See below. 536 * %edx: x2APIC ID of the current logical processor. 537 */ 538 /* %eax */ 539 #define CPUID_TOP_SHIFTNUM __BITS(4, 0) /* Topology ID shift value */ 540 /* %ecx */ 541 #define CPUID_TOP_LVLNUM __BITS(7, 0) /* Level number */ 542 #define CPUID_TOP_LVLTYPE __BITS(15, 8) /* Level type */ 543 #define CPUID_TOP_LVLTYPE_INVAL 0 /* Invalid */ 544 #define CPUID_TOP_LVLTYPE_SMT 1 /* SMT */ 545 #define CPUID_TOP_LVLTYPE_CORE 2 /* Core */ 546 547 /* 548 * Intel/AMD CPUID Processor extended state Enumeration Fn0000000d 549 * 550 * %ecx == 0: supported features info: 551 * %eax: Valid bits of lower 32bits of XCR0 552 * %ebx: Maximum save area size for features enabled in XCR0 553 * %ecx: Maximum save area size for all cpu features 554 * %edx: Valid bits of upper 32bits of XCR0 555 * 556 * %ecx == 1: 557 * %eax: Bit 0 => xsaveopt instruction available (sandy bridge onwards) 558 * %ebx: Save area size for features enabled by XCR0 | IA32_XSS 559 * %ecx: Valid bits of lower 32bits of IA32_XSS 560 * %edx: Valid bits of upper 32bits of IA32_XSS 561 * 562 * %ecx >= 2: Save area details for XCR0 bit n 563 * %eax: size of save area for this feature 564 * %ebx: offset of save area for this feature 565 * %ecx, %edx: reserved 566 * All of %eax, %ebx, %ecx and %edx are zero for unsupported features. 567 */ 568 569 /* %ecx=1 %eax */ 570 #define CPUID_PES1_XSAVEOPT 0x00000001 /* xsaveopt instruction */ 571 #define CPUID_PES1_XSAVEC 0x00000002 /* xsavec & compacted XRSTOR */ 572 #define CPUID_PES1_XGETBV 0x00000004 /* xgetbv with ECX = 1 */ 573 #define CPUID_PES1_XSAVES 0x00000008 /* xsaves/xrstors, IA32_XSS */ 574 575 #define CPUID_PES1_FLAGS "\20" \ 576 "\1" "XSAVEOPT" "\2" "XSAVEC" "\3" "XGETBV" "\4" "XSAVES" 577 578 /* 579 * Intel Deterministic Address Translation Parameter Leaf 580 * Fn0000_0018 581 */ 582 583 /* %ecx=0 %eax __BITS(31, 0): the maximum input value of supported sub-leaf */ 584 585 /* %ebx */ 586 #define CPUID_DATP_PGSIZE __BITS(3, 0) /* page size */ 587 #define CPUID_DATP_PGSIZE_4KB __BIT(0) /* 4KB page support */ 588 #define CPUID_DATP_PGSIZE_2MB __BIT(1) /* 2MB page support */ 589 #define CPUID_DATP_PGSIZE_4MB __BIT(2) /* 4MB page support */ 590 #define CPUID_DATP_PGSIZE_1GB __BIT(3) /* 1GB page support */ 591 #define CPUID_DATP_PARTITIONING __BITS(10, 8) /* Partitioning */ 592 #define CPUID_DATP_WAYS __BITS(31, 16) /* Ways of associativity */ 593 594 /* Number of sets: %ecx */ 595 596 /* %edx */ 597 #define CPUID_DATP_TCTYPE __BITS(4, 0) /* Translation Cache type */ 598 #define CPUID_DATP_TCTYPE_N 0 /* NULL (not valid) */ 599 #define CPUID_DATP_TCTYPE_D 1 /* Data TLB */ 600 #define CPUID_DATP_TCTYPE_I 2 /* Instruction TLB */ 601 #define CPUID_DATP_TCTYPE_U 3 /* Unified TLB */ 602 #define CPUID_DATP_TCTYPE_L 4 /* Load only TLB */ 603 #define CPUID_DATP_TCTYPE_S 5 /* Store only TLB */ 604 #define CPUID_DATP_TCLEVEL __BITS(7, 5) /* TLB level (start at 1) */ 605 #define CPUID_DATP_FULLASSOC __BIT(8) /* Full associative */ 606 #define CPUID_DATP_SHAREING __BITS(25, 14) /* shareing */ 607 608 609 /* Intel Fn80000001 extended features - %edx */ 610 #define CPUID_SYSCALL 0x00000800 /* SYSCALL/SYSRET */ 611 #define CPUID_XD 0x00100000 /* Execute Disable (like CPUID_NOX) */ 612 #define CPUID_PAGE1GB 0x04000000 /* 1GB Large Page Support */ 613 #define CPUID_RDTSCP 0x08000000 /* Read TSC Pair Instruction */ 614 #define CPUID_EM64T 0x20000000 /* Intel EM64T */ 615 616 #define CPUID_INTEL_EXT_FLAGS "\20" \ 617 "\14" "SYSCALL/SYSRET" "\25" "XD" "\33" "P1GB" \ 618 "\34" "RDTSCP" "\36" "EM64T" 619 620 /* Intel Fn80000001 extended features - %ecx */ 621 #define CPUID_LAHF 0x00000001 /* LAHF/SAHF in IA-32e mode, 64bit sub*/ 622 /* 0x00000020 */ /* LZCNT. Same as AMD's CPUID_ABM */ 623 #define CPUID_PREFETCHW 0x00000100 /* PREFETCHW */ 624 625 #define CPUID_INTEL_FLAGS4 "\20" \ 626 "\1" "LAHF" "\02" "B01" "\03" "B02" \ 627 "\06" "LZCNT" \ 628 "\11" "PREFETCHW" 629 630 631 /* AMD/VIA Fn80000001 extended features - %edx */ 632 /* CPUID_SYSCALL SYSCALL/SYSRET */ 633 #define CPUID_MPC 0x00080000 /* Multiprocessing Capable */ 634 #define CPUID_NOX 0x00100000 /* No Execute Page Protection */ 635 #define CPUID_MMXX 0x00400000 /* AMD MMX Extensions */ 636 /* CPUID_MMX MMX supported */ 637 /* CPUID_FXSR fast FP/MMX save/restore */ 638 #define CPUID_FFXSR 0x02000000 /* FXSAVE/FXSTOR Extensions */ 639 /* CPUID_PAGE1GB 1GB Large Page Support */ 640 /* CPUID_RDTSCP Read TSC Pair Instruction */ 641 /* CPUID_EM64T Long mode */ 642 #define CPUID_3DNOW2 0x40000000 /* 3DNow! Instruction Extension */ 643 #define CPUID_3DNOW 0x80000000 /* 3DNow! Instructions */ 644 645 #define CPUID_EXT_FLAGS "\20" \ 646 "\14" "SYSCALL/SYSRET" \ 647 "\24" "MPC" \ 648 "\25" "NOX" "\27" "MMXX" "\30" "MMX" \ 649 "\31" "FXSR" "\32" "FFXSR" "\33" "P1GB" "\34" "RDTSCP" \ 650 "\36" "LONG" "\37" "3DNOW2" "\40" "3DNOW" 651 652 /* AMD Fn8000_0001 extended features - %ecx */ 653 /* CPUID_LAHF LAHF/SAHF instruction */ 654 #define CPUID_CMPLEGACY 0x00000002 /* Compare Legacy */ 655 #define CPUID_SVM 0x00000004 /* Secure Virtual Machine */ 656 #define CPUID_EAPIC 0x00000008 /* Extended APIC space */ 657 #define CPUID_ALTMOVCR0 0x00000010 /* Lock Mov Cr0 */ 658 #define CPUID_ABM 0x00000020 /* LZCNT instruction */ 659 #define CPUID_SSE4A 0x00000040 /* SSE4A instruction set */ 660 #define CPUID_MISALIGNSSE 0x00000080 /* Misaligned SSE */ 661 #define CPUID_3DNOWPF 0x00000100 /* 3DNow Prefetch */ 662 #define CPUID_OSVW 0x00000200 /* OS visible workarounds */ 663 #define CPUID_IBS 0x00000400 /* Instruction Based Sampling */ 664 #define CPUID_XOP 0x00000800 /* XOP instruction set */ 665 #define CPUID_SKINIT 0x00001000 /* SKINIT */ 666 #define CPUID_WDT 0x00002000 /* watchdog timer support */ 667 #define CPUID_LWP 0x00008000 /* Light Weight Profiling */ 668 #define CPUID_FMA4 0x00010000 /* FMA4 instructions */ 669 #define CPUID_TCE 0x00020000 /* Translation cache Extension */ 670 #define CPUID_NODEID 0x00080000 /* NodeID MSR available*/ 671 #define CPUID_TBM 0x00200000 /* TBM instructions */ 672 #define CPUID_TOPOEXT 0x00400000 /* cpuid Topology Extension */ 673 #define CPUID_PCEC 0x00800000 /* Perf Ctr Ext Core */ 674 #define CPUID_PCENB 0x01000000 /* Perf Ctr Ext NB */ 675 #define CPUID_SPM 0x02000000 /* Stream Perf Mon */ 676 #define CPUID_DBE 0x04000000 /* Data Breakpoint Extension */ 677 #define CPUID_PTSC 0x08000000 /* PerfTsc */ 678 #define CPUID_L2IPERFC 0x10000000 /* L2I performance counter Extension */ 679 #define CPUID_MWAITX 0x20000000 /* MWAITX/MONITORX support */ 680 681 #define CPUID_AMD_FLAGS4 "\20" \ 682 "\1" "LAHF" "\2" "CMPLEGACY" "\3" "SVM" "\4" "EAPIC" \ 683 "\5" "ALTMOVCR0" "\6" "LZCNT" "\7" "SSE4A" "\10" "MISALIGNSSE" \ 684 "\11" "3DNOWPREFETCH" \ 685 "\12" "OSVW" "\13" "IBS" "\14" "XOP" \ 686 "\15" "SKINIT" "\16" "WDT" "\17" "B14" "\20" "LWP" \ 687 "\21" "FMA4" "\22" "TCE" "\23" "B18" "\24" "NodeID" \ 688 "\25" "B20" "\26" "TBM" "\27" "TopoExt" "\30" "PCExtC" \ 689 "\31" "PCExtNB" "\32" "StrmPM" "\33" "DBExt" "\34" "PerfTsc" \ 690 "\35" "L2IPERFC" "\36" "MWAITX" "\37" "B30" "\40" "B31" 691 692 /* 693 * Advanced Power Management 694 * CPUID Fn8000_0007 %edx 695 * 696 * Only ITSC is for both Intel and AMD. Others are only for AMD. 697 */ 698 #define CPUID_APM_TS 0x00000001 /* Temperature Sensor */ 699 #define CPUID_APM_FID 0x00000002 /* Frequency ID control */ 700 #define CPUID_APM_VID 0x00000004 /* Voltage ID control */ 701 #define CPUID_APM_TTP 0x00000008 /* THERMTRIP (PCI F3xE4 register) */ 702 #define CPUID_APM_HTC 0x00000010 /* Hardware thermal control (HTC) */ 703 #define CPUID_APM_STC 0x00000020 /* Software thermal control (STC) */ 704 #define CPUID_APM_100 0x00000040 /* 100MHz multiplier control */ 705 #define CPUID_APM_HWP 0x00000080 /* HW P-State control */ 706 #define CPUID_APM_ITSC 0x00000100 /* invariant TSC */ 707 #define CPUID_APM_CPB 0x00000200 /* Core performance boost */ 708 #define CPUID_APM_EFF 0x00000400 /* Effective Frequency (read-only) */ 709 #define CPUID_APM_PROCFI 0x00000800 /* Proc Feedback Interface */ 710 #define CPUID_APM_PROCPR 0x00001000 /* Proc Power Reporting */ 711 #define CPUID_APM_CONNSTBY 0x00002000 /* Connected Standby */ 712 #define CPUID_APM_RAPL 0x00004000 /* Running Average Power Limit */ 713 714 #define CPUID_APM_FLAGS "\20" \ 715 "\1" "TS" "\2" "FID" "\3" "VID" "\4" "TTP" \ 716 "\5" "HTC" "\6" "STC" "\7" "100" "\10" "HWP" \ 717 "\11" "ITSC" "\12" "CPB" "\13" "EffFreq" "\14" "PROCFI" \ 718 "\15" "PROCPR" "\16" "CONNSTBY" "\17" "RAPL" 719 720 /* 721 * AMD Processor Capacity Parameters and Extended Features 722 * CPUID Fn8000_0008 723 * %eax: Long Mode Size Identifiers 724 * %ebx: Extended Feature Identifiers 725 * %ecx: Size Identifiers 726 * %edx: RDPRU Register Identifier Range 727 */ 728 729 /* %ebx */ 730 #define CPUID_CAPEX_CLZERO __BIT(0) /* CLZERO instruction */ 731 #define CPUID_CAPEX_IRPERF __BIT(1) /* InstRetCntMsr */ 732 #define CPUID_CAPEX_XSAVEERPTR __BIT(2) /* RstrFpErrPtrs by XRSTOR */ 733 #define CPUID_CAPEX_RDPRU __BIT(4) /* RDPRU instruction */ 734 #define CPUID_CAPEX_MCOMMIT __BIT(8) /* MCOMMIT instruction */ 735 #define CPUID_CAPEX_WBNOINVD __BIT(9) /* WBNOINVD instruction */ 736 #define CPUID_CAPEX_IBPB __BIT(12) /* Speculation Control IBPB */ 737 #define CPUID_CAPEX_IBRS __BIT(14) /* Speculation Control IBRS */ 738 #define CPUID_CAPEX_STIBP __BIT(15) /* Speculation Control STIBP */ 739 #define CPUID_CAPEX_IBRS_ALWAYSON __BIT(16) /* IBRS always on mode */ 740 #define CPUID_CAPEX_STIBP_ALWAYSON __BIT(17) /* STIBP always on mode */ 741 #define CPUID_CAPEX_PREFER_IBRS __BIT(18) /* IBRS preferred */ 742 #define CPUID_CAPEX_SSBD __BIT(24) /* Speculation Control SSBD */ 743 #define CPUID_CAPEX_VIRT_SSBD __BIT(25) /* Virt Spec Control SSBD */ 744 #define CPUID_CAPEX_SSB_NO __BIT(26) /* SSBD not required */ 745 746 /* %ecx */ 747 #define CPUID_CAPEX_PerfTscSize __BITS(17,16) 748 #define CPUID_CAPEX_ApicIdSize __BITS(15,12) 749 #define CPUID_CAPEX_NC __BITS(7,0) 750 751 #define CPUID_CAPEX_FLAGS "\20" \ 752 "\1CLZERO" "\2IRPERF" "\3XSAVEERPTR" \ 753 "\5RDPRU" "\7B6" \ 754 "\11MCOMMIT" "\12WBNOINVD" "\13B10" \ 755 "\15IBPB" "\16B13" "\17IBRS" "\20STIBP" \ 756 "\21IBRS_ALWAYSON" "\22STIBP_ALWAYSON" "\23PREFER_IBRS" "\24B19" \ 757 "\31SSBD" "\32VIRT_SSBD" "\33SSB_NO" 758 759 /* AMD Fn8000_000a %eax (SVM Revision) */ 760 #define CPUID_AMD_SVM_REV __BITS(7,0) 761 762 /* AMD Fn8000_000a %edx features (SVM features) */ 763 #define CPUID_AMD_SVM_NP 0x00000001 764 #define CPUID_AMD_SVM_LbrVirt 0x00000002 765 #define CPUID_AMD_SVM_SVML 0x00000004 766 #define CPUID_AMD_SVM_NRIPS 0x00000008 767 #define CPUID_AMD_SVM_TSCRateCtrl 0x00000010 768 #define CPUID_AMD_SVM_VMCBCleanBits 0x00000020 769 #define CPUID_AMD_SVM_FlushByASID 0x00000040 770 #define CPUID_AMD_SVM_DecodeAssist 0x00000080 771 #define CPUID_AMD_SVM_PauseFilter 0x00000400 772 #define CPUID_AMD_SVM_PFThreshold 0x00001000 /* PAUSE filter threshold */ 773 #define CPUID_AMD_SVM_AVIC 0x00002000 /* AMD Virtual intr. ctrl */ 774 #define CPUID_AMD_SVM_V_VMSAVE_VMLOAD 0x00008000 /* Virtual VM{SAVE/LOAD} */ 775 #define CPUID_AMD_SVM_vGIF 0x00010000 /* Virtualized GIF */ 776 #define CPUID_AMD_SVM_GMET 0x00020000 777 #define CPUID_AMD_SVM_SPEC_CTRL __BIT(20) 778 #define CPUID_AMD_SVM_TLBICTL __BIT(24) /* TLB Inttercept Control */ 779 780 #define CPUID_AMD_SVM_FLAGS "\20" \ 781 "\1" "NP" "\2" "LbrVirt" "\3" "SVML" "\4" "NRIPS" \ 782 "\5" "TSCRate" "\6" "VMCBCleanBits" \ 783 "\7" "FlushByASID" "\10" "DecodeAssist" \ 784 "\11" "B08" "\12" "B09" "\13" "PauseFilter" "\14" "B11" \ 785 "\15" "PFThreshold" "\16" "AVIC" "\17" "B14" \ 786 "\20" "V_VMSAVE_VMLOAD" \ 787 "\21" "VGIF" "\22" "GMET" \ 788 "\25" "SPEC_CTRL" \ 789 "\31" "TLBICTL" 790 791 /* 792 * AMD Fn8000_001d Cache Topology Information. 793 * It's almost the same as Intel Deterministic Cache Parameter Leaf(0x04) 794 * except the following: 795 * No Cores/package (%eax bit 31..26) 796 * No Complex cache indexing (%edx bit 2) 797 */ 798 799 /* 800 * AMD Fn8000_001f Encrypted Memory Capabilities. 801 * %eax: flags 802 * %ebx: 5-0: Cbit Position 803 * 11-6: PhysAddrReduction 804 * 15-12: NumVMPL 805 * %ecx: 31-0: NumEncryptedGuests 806 * %edx: 31-0: MinSevNoEsAsid 807 */ 808 #define CPUID_AMD_ENCMEM_SME __BIT(0) /* Secure Memory Encryption */ 809 #define CPUID_AMD_ENCMEM_SEV __BIT(1) /* Secure Encrypted Virtualiz. */ 810 #define CPUID_AMD_ENCMEM_PGFLMSR __BIT(2) /* Page Flush MSR */ 811 #define CPUID_AMD_ENCMEM_SEVES __BIT(3) /* SEV Encrypted State */ 812 #define CPUID_AMD_ENCMEM_SEV_SNP __BIT(4) /* Secure Nested Paging */ 813 #define CPUID_AMD_ENCMEM_VMPL __BIT(5) /* Virtual Machine Privilege Lvl */ 814 #define CPUID_AMD_ENCMEM_HECC __BIT(10) /* HW Enf Cache Coh across enc dom */ 815 #define CPUID_AMD_ENCMEM_64BH __BIT(11) /* 64Bit Host */ 816 #define CPUID_AMD_ENCMEM_RSTRINJ __BIT(12) /* Restricted Injection */ 817 #define CPUID_AMD_ENCMEM_ALTINJ __BIT(13) /* Alternate Injection */ 818 #define CPUID_AMD_ENCMEM_DBGSWAP __BIT(14) /* Debug Swap */ 819 #define CPUID_AMD_ENCMEM_PREVHOSTIBS __BIT(15) /* Prevent Host IBS */ 820 #define CPUID_AMD_ENCMEM_VTE __BIT(16) /* Virtual Transparent Encryption */ 821 822 #define CPUID_AMD_ENCMEM_FLAGS "\20" \ 823 "\1" "SME" "\2" "SEV" "\3" "PageFlushMsr" "\4" "SEV-ES" \ 824 "\5" "SEV-SNP" "\6" "VMPL" \ 825 "\13HwEnfCacheCoh" "\14" "64BitHost" \ 826 "\15" "RSTRINJ" "\16" "ALTINJ" "\17" "DebugSwap" "\20PreventHostlbs" \ 827 "\21" "VTE" 828 829 /* 830 * Centaur Extended Feature flags 831 */ 832 #define CPUID_VIA_HAS_RNG 0x00000004 /* Random number generator */ 833 #define CPUID_VIA_DO_RNG 0x00000008 834 #define CPUID_VIA_HAS_ACE 0x00000040 /* AES Encryption */ 835 #define CPUID_VIA_DO_ACE 0x00000080 836 #define CPUID_VIA_HAS_ACE2 0x00000100 /* AES+CTR instructions */ 837 #define CPUID_VIA_DO_ACE2 0x00000200 838 #define CPUID_VIA_HAS_PHE 0x00000400 /* SHA1+SHA256 HMAC */ 839 #define CPUID_VIA_DO_PHE 0x00000800 840 #define CPUID_VIA_HAS_PMM 0x00001000 /* RSA Instructions */ 841 #define CPUID_VIA_DO_PMM 0x00002000 842 843 #define CPUID_FLAGS_PADLOCK "\20" \ 844 "\3" "RNG" "\7" "AES" "\11" "AES/CTR" "\13" "SHA1/SHA256" \ 845 "\15" "RSA" 846 847 /* 848 * Model-Specific Registers 849 */ 850 #define MSR_TSC 0x010 851 #define MSR_IA32_PLATFORM_ID 0x017 852 #define MSR_APICBASE 0x01b 853 #define APICBASE_BSP 0x00000100 /* boot processor */ 854 #define APICBASE_EXTD 0x00000400 /* x2APIC mode */ 855 #define APICBASE_EN 0x00000800 /* software enable */ 856 /* 857 * APICBASE_PHYSADDR is actually variable-sized on some CPUs. But we're 858 * only interested in the initial value, which is guaranteed to fit the 859 * first 32 bits. So this macro is fine. 860 */ 861 #define APICBASE_PHYSADDR 0xfffff000 /* physical address */ 862 #define MSR_EBL_CR_POWERON 0x02a 863 #define MSR_EBC_FREQUENCY_ID 0x02c /* PIV only */ 864 #define MSR_IA32_SPEC_CTRL 0x048 865 #define IA32_SPEC_CTRL_IBRS 0x01 866 #define IA32_SPEC_CTRL_STIBP 0x02 867 #define IA32_SPEC_CTRL_SSBD 0x04 868 #define MSR_IA32_PRED_CMD 0x049 869 #define IA32_PRED_CMD_IBPB 0x01 870 #define MSR_BIOS_UPDT_TRIG 0x079 871 #define MSR_BIOS_SIGN 0x08b 872 #define MSR_PERFCTR0 0x0c1 873 #define MSR_PERFCTR1 0x0c2 874 #define MSR_FSB_FREQ 0x0cd /* Core Duo/Solo only */ 875 #define MSR_MPERF 0x0e7 876 #define MSR_APERF 0x0e8 877 #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ 878 #define MSR_MTRRcap 0x0fe 879 #define MSR_IA32_ARCH_CAPABILITIES 0x10a 880 #define IA32_ARCH_RDCL_NO 0x01 881 #define IA32_ARCH_IBRS_ALL 0x02 882 #define IA32_ARCH_RSBA 0x04 883 #define IA32_ARCH_SKIP_L1DFL_VMENTRY 0x08 884 #define IA32_ARCH_SSB_NO 0x10 885 #define IA32_ARCH_MDS_NO 0x20 886 #define IA32_ARCH_IF_PSCHANGE_MC_NO 0x40 887 #define IA32_ARCH_TSX_CTRL 0x80 888 #define IA32_ARCH_TAA_NO 0x100 889 #define MSR_IA32_FLUSH_CMD 0x10b 890 #define IA32_FLUSH_CMD_L1D_FLUSH 0x01 891 #define MSR_TSX_FORCE_ABORT 0x10f 892 #define MSR_IA32_TSX_CTRL 0x122 893 #define IA32_TSX_CTRL_RTM_DISABLE __BIT(0) 894 #define IA32_TSX_CTRL_TSX_CPUID_CLEAR __BIT(1) 895 #define MSR_SYSENTER_CS 0x174 /* PII+ only */ 896 #define MSR_SYSENTER_ESP 0x175 /* PII+ only */ 897 #define MSR_SYSENTER_EIP 0x176 /* PII+ only */ 898 #define MSR_MCG_CAP 0x179 899 #define MSR_MCG_STATUS 0x17a 900 #define MSR_MCG_CTL 0x17b 901 #define MSR_EVNTSEL0 0x186 902 #define MSR_EVNTSEL1 0x187 903 #define MSR_PERF_STATUS 0x198 /* Pentium M */ 904 #define MSR_PERF_CTL 0x199 /* Pentium M */ 905 #define MSR_THERM_CONTROL 0x19a 906 #define MSR_THERM_INTERRUPT 0x19b 907 #define MSR_THERM_STATUS 0x19c 908 #define MSR_THERM2_CTL 0x19d /* Pentium M */ 909 #define MSR_MISC_ENABLE 0x1a0 910 #define IA32_MISC_MWAIT_EN 0x40000 911 #define MSR_TEMPERATURE_TARGET 0x1a2 912 #define MSR_DEBUGCTLMSR 0x1d9 913 #define MSR_LASTBRANCHFROMIP 0x1db 914 #define MSR_LASTBRANCHTOIP 0x1dc 915 #define MSR_LASTINTFROMIP 0x1dd 916 #define MSR_LASTINTTOIP 0x1de 917 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 918 #define MSR_MTRRphysBase0 0x200 919 #define MSR_MTRRphysMask0 0x201 920 #define MSR_MTRRphysBase1 0x202 921 #define MSR_MTRRphysMask1 0x203 922 #define MSR_MTRRphysBase2 0x204 923 #define MSR_MTRRphysMask2 0x205 924 #define MSR_MTRRphysBase3 0x206 925 #define MSR_MTRRphysMask3 0x207 926 #define MSR_MTRRphysBase4 0x208 927 #define MSR_MTRRphysMask4 0x209 928 #define MSR_MTRRphysBase5 0x20a 929 #define MSR_MTRRphysMask5 0x20b 930 #define MSR_MTRRphysBase6 0x20c 931 #define MSR_MTRRphysMask6 0x20d 932 #define MSR_MTRRphysBase7 0x20e 933 #define MSR_MTRRphysMask7 0x20f 934 #define MSR_MTRRphysBase8 0x210 935 #define MSR_MTRRphysMask8 0x211 936 #define MSR_MTRRphysBase9 0x212 937 #define MSR_MTRRphysMask9 0x213 938 #define MSR_MTRRphysBase10 0x214 939 #define MSR_MTRRphysMask10 0x215 940 #define MSR_MTRRphysBase11 0x216 941 #define MSR_MTRRphysMask11 0x217 942 #define MSR_MTRRphysBase12 0x218 943 #define MSR_MTRRphysMask12 0x219 944 #define MSR_MTRRphysBase13 0x21a 945 #define MSR_MTRRphysMask13 0x21b 946 #define MSR_MTRRphysBase14 0x21c 947 #define MSR_MTRRphysMask14 0x21d 948 #define MSR_MTRRphysBase15 0x21e 949 #define MSR_MTRRphysMask15 0x21f 950 #define MSR_MTRRfix64K_00000 0x250 951 #define MSR_MTRRfix16K_80000 0x258 952 #define MSR_MTRRfix16K_A0000 0x259 953 #define MSR_MTRRfix4K_C0000 0x268 954 #define MSR_MTRRfix4K_C8000 0x269 955 #define MSR_MTRRfix4K_D0000 0x26a 956 #define MSR_MTRRfix4K_D8000 0x26b 957 #define MSR_MTRRfix4K_E0000 0x26c 958 #define MSR_MTRRfix4K_E8000 0x26d 959 #define MSR_MTRRfix4K_F0000 0x26e 960 #define MSR_MTRRfix4K_F8000 0x26f 961 #define MSR_CR_PAT 0x277 962 #define MSR_MTRRdefType 0x2ff 963 #define MSR_MC0_CTL 0x400 964 #define MSR_MC0_STATUS 0x401 965 #define MSR_MC0_ADDR 0x402 966 #define MSR_MC0_MISC 0x403 967 #define MSR_MC1_CTL 0x404 968 #define MSR_MC1_STATUS 0x405 969 #define MSR_MC1_ADDR 0x406 970 #define MSR_MC1_MISC 0x407 971 #define MSR_MC2_CTL 0x408 972 #define MSR_MC2_STATUS 0x409 973 #define MSR_MC2_ADDR 0x40a 974 #define MSR_MC2_MISC 0x40b 975 #define MSR_MC3_CTL 0x40c 976 #define MSR_MC3_STATUS 0x40d 977 #define MSR_MC3_ADDR 0x40e 978 #define MSR_MC3_MISC 0x40f 979 #define MSR_MC4_CTL 0x410 980 #define MSR_MC4_STATUS 0x411 981 #define MSR_MC4_ADDR 0x412 982 #define MSR_MC4_MISC 0x413 983 /* 0x480 - 0x490 VMX */ 984 #define MSR_X2APIC_BASE 0x800 /* 0x800 - 0xBFF */ 985 #define MSR_X2APIC_ID 0x002 /* x2APIC ID. (RO) */ 986 #define MSR_X2APIC_VERS 0x003 /* Version. (RO) */ 987 #define MSR_X2APIC_TPRI 0x008 /* Task Prio. (RW) */ 988 #define MSR_X2APIC_PPRI 0x00a /* Processor prio. (RO) */ 989 #define MSR_X2APIC_EOI 0x00b /* End Int. (W) */ 990 #define MSR_X2APIC_LDR 0x00d /* Logical dest. (RO) */ 991 #define MSR_X2APIC_SVR 0x00f /* Spurious intvec (RW) */ 992 #define MSR_X2APIC_ISR 0x010 /* In-Service Status (RO) */ 993 #define MSR_X2APIC_TMR 0x018 /* Trigger Mode (RO) */ 994 #define MSR_X2APIC_IRR 0x020 /* Interrupt Req (RO) */ 995 #define MSR_X2APIC_ESR 0x028 /* Err status. (RW) */ 996 #define MSR_X2APIC_LVT_CMCI 0x02f /* LVT CMCI (RW) */ 997 #define MSR_X2APIC_ICRLO 0x030 /* Int. cmd. (RW64) */ 998 #define MSR_X2APIC_LVTT 0x032 /* Loc.vec.(timer) (RW) */ 999 #define MSR_X2APIC_TMINT 0x033 /* Loc.vec (Thermal) (RW) */ 1000 #define MSR_X2APIC_PCINT 0x034 /* Loc.vec (Perf Mon) (RW) */ 1001 #define MSR_X2APIC_LVINT0 0x035 /* Loc.vec (LINT0) (RW) */ 1002 #define MSR_X2APIC_LVINT1 0x036 /* Loc.vec (LINT1) (RW) */ 1003 #define MSR_X2APIC_LVERR 0x037 /* Loc.vec (ERROR) (RW) */ 1004 #define MSR_X2APIC_ICR_TIMER 0x038 /* Initial count (RW) */ 1005 #define MSR_X2APIC_CCR_TIMER 0x039 /* Current count (RO) */ 1006 #define MSR_X2APIC_DCR_TIMER 0x03e /* Divisor config (RW) */ 1007 #define MSR_X2APIC_SELF_IPI 0x03f /* SELF IPI (W) */ 1008 1009 /* 1010 * VIA "Nehemiah" MSRs 1011 */ 1012 #define MSR_VIA_RNG 0x0000110b 1013 #define MSR_VIA_RNG_ENABLE 0x00000040 1014 #define MSR_VIA_RNG_NOISE_MASK 0x00000300 1015 #define MSR_VIA_RNG_NOISE_A 0x00000000 1016 #define MSR_VIA_RNG_NOISE_B 0x00000100 1017 #define MSR_VIA_RNG_2NOISE 0x00000300 1018 #define MSR_VIA_ACE 0x00001107 1019 #define VIA_ACE_ALTINST 0x00000001 1020 #define VIA_ACE_ECX8 0x00000002 1021 #define VIA_ACE_ENABLE 0x10000000 1022 1023 /* 1024 * VIA "Eden" MSRs 1025 */ 1026 #define MSR_VIA_FCR MSR_VIA_ACE 1027 1028 /* 1029 * AMD K6/K7 MSRs. 1030 */ 1031 #define MSR_K6_UWCCR 0xc0000085 1032 #define MSR_K7_EVNTSEL0 0xc0010000 1033 #define MSR_K7_EVNTSEL1 0xc0010001 1034 #define MSR_K7_EVNTSEL2 0xc0010002 1035 #define MSR_K7_EVNTSEL3 0xc0010003 1036 #define MSR_K7_PERFCTR0 0xc0010004 1037 #define MSR_K7_PERFCTR1 0xc0010005 1038 #define MSR_K7_PERFCTR2 0xc0010006 1039 #define MSR_K7_PERFCTR3 0xc0010007 1040 1041 /* 1042 * AMD K8 (Opteron) MSRs. 1043 */ 1044 #define MSR_SYSCFG 0xc0010010 1045 1046 #define MSR_EFER 0xc0000080 /* Extended feature enable */ 1047 #define EFER_SCE 0x00000001 /* SYSCALL extension */ 1048 #define EFER_LME 0x00000100 /* Long Mode Enable */ 1049 #define EFER_LMA 0x00000400 /* Long Mode Active */ 1050 #define EFER_NXE 0x00000800 /* No-Execute Enabled */ 1051 #define EFER_SVME 0x00001000 /* Secure Virtual Machine En. */ 1052 #define EFER_LMSLE 0x00002000 /* Long Mode Segment Limit E. */ 1053 #define EFER_FFXSR 0x00004000 /* Fast FXSAVE/FXRSTOR En. */ 1054 #define EFER_TCE 0x00008000 /* Translation Cache Ext. */ 1055 1056 #define MSR_STAR 0xc0000081 /* 32 bit syscall gate addr */ 1057 #define MSR_LSTAR 0xc0000082 /* 64 bit syscall gate addr */ 1058 #define MSR_CSTAR 0xc0000083 /* compat syscall gate addr */ 1059 #define MSR_SFMASK 0xc0000084 /* flags to clear on syscall */ 1060 1061 #define MSR_FSBASE 0xc0000100 /* 64bit offset for fs: */ 1062 #define MSR_GSBASE 0xc0000101 /* 64bit offset for gs: */ 1063 #define MSR_KERNELGSBASE 0xc0000102 /* storage for swapgs ins */ 1064 1065 #define MSR_VMCR 0xc0010114 /* Virtual Machine Control Register */ 1066 #define VMCR_DPD 0x00000001 /* Debug port disable */ 1067 #define VMCR_RINIT 0x00000002 /* intercept init */ 1068 #define VMCR_DISA20 0x00000004 /* Disable A20 masking */ 1069 #define VMCR_LOCK 0x00000008 /* SVM Lock */ 1070 #define VMCR_SVMED 0x00000010 /* SVME Disable */ 1071 #define MSR_SVMLOCK 0xc0010118 /* SVM Lock key */ 1072 1073 /* 1074 * These require a 'passcode' for access. See cpufunc.h. 1075 */ 1076 #define MSR_HWCR 0xc0010015 1077 #define HWCR_TLBCACHEDIS 0x00000008 1078 #define HWCR_FFDIS 0x00000040 1079 1080 #define MSR_NB_CFG 0xc001001f 1081 #define NB_CFG_DISIOREQLOCK 0x0000000000000008ULL 1082 #define NB_CFG_DISDATMSK 0x0000001000000000ULL 1083 #define NB_CFG_INITAPICCPUIDLO (1ULL << 54) 1084 1085 #define MSR_LS_CFG 0xc0011020 1086 #define LS_CFG_ERRATA_1033 __BIT(4) 1087 #define LS_CFG_ERRATA_793 __BIT(15) 1088 #define LS_CFG_ERRATA_1095 __BIT(57) 1089 #define LS_CFG_DIS_LS2_SQUISH 0x02000000 1090 #define LS_CFG_DIS_SSB_F15H 0x0040000000000000ULL 1091 #define LS_CFG_DIS_SSB_F16H 0x0000000200000000ULL 1092 #define LS_CFG_DIS_SSB_F17H 0x0000000000000400ULL 1093 1094 #define MSR_IC_CFG 0xc0011021 1095 #define IC_CFG_DIS_SEQ_PREFETCH 0x00000800 1096 #define IC_CFG_DIS_IND 0x00004000 1097 #define IC_CFG_ERRATA_776 __BIT(26) 1098 1099 #define MSR_DC_CFG 0xc0011022 1100 #define DC_CFG_DIS_CNV_WC_SSO 0x00000008 1101 #define DC_CFG_DIS_SMC_CHK_BUF 0x00000400 1102 #define DC_CFG_ERRATA_261 0x01000000 1103 1104 #define MSR_BU_CFG 0xc0011023 1105 #define BU_CFG_ERRATA_298 0x0000000000000002ULL 1106 #define BU_CFG_ERRATA_254 0x0000000000200000ULL 1107 #define BU_CFG_ERRATA_309 0x0000000000800000ULL 1108 #define BU_CFG_THRL2IDXCMPDIS 0x0000080000000000ULL 1109 #define BU_CFG_WBPFSMCCHKDIS 0x0000200000000000ULL 1110 #define BU_CFG_WBENHWSBDIS 0x0001000000000000ULL 1111 1112 #define MSR_FP_CFG 0xc0011028 1113 #define FP_CFG_ERRATA_1049 __BIT(4) 1114 1115 #define MSR_DE_CFG 0xc0011029 1116 #define DE_CFG_ERRATA_721 0x00000001 1117 #define DE_CFG_LFENCE_SERIALIZE __BIT(1) 1118 #define DE_CFG_ERRATA_1021 __BIT(13) 1119 1120 #define MSR_LS_CFG2 0xc001102d 1121 #define LS_CFG2_ERRATA_1091 __BIT(34) 1122 1123 /* AMD Family10h MSRs */ 1124 #define MSR_OSVW_ID_LENGTH 0xc0010140 1125 #define MSR_OSVW_STATUS 0xc0010141 1126 #define MSR_UCODE_AMD_PATCHLEVEL 0x0000008b 1127 #define MSR_UCODE_AMD_PATCHLOADER 0xc0010020 1128 1129 /* X86 MSRs */ 1130 #define MSR_RDTSCP_AUX 0xc0000103 1131 1132 /* 1133 * Constants related to MTRRs 1134 */ 1135 #define MTRR_N64K 8 /* numbers of fixed-size entries */ 1136 #define MTRR_N16K 16 1137 #define MTRR_N4K 64 1138 1139 /* 1140 * the following four 3-byte registers control the non-cacheable regions. 1141 * These registers must be written as three separate bytes. 1142 * 1143 * NCRx+0: A31-A24 of starting address 1144 * NCRx+1: A23-A16 of starting address 1145 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 1146 * 1147 * The non-cacheable region's starting address must be aligned to the 1148 * size indicated by the NCR_SIZE_xx field. 1149 */ 1150 #define NCR1 0xc4 1151 #define NCR2 0xc7 1152 #define NCR3 0xca 1153 #define NCR4 0xcd 1154 1155 #define NCR_SIZE_0K 0 1156 #define NCR_SIZE_4K 1 1157 #define NCR_SIZE_8K 2 1158 #define NCR_SIZE_16K 3 1159 #define NCR_SIZE_32K 4 1160 #define NCR_SIZE_64K 5 1161 #define NCR_SIZE_128K 6 1162 #define NCR_SIZE_256K 7 1163 #define NCR_SIZE_512K 8 1164 #define NCR_SIZE_1M 9 1165 #define NCR_SIZE_2M 10 1166 #define NCR_SIZE_4M 11 1167 #define NCR_SIZE_8M 12 1168 #define NCR_SIZE_16M 13 1169 #define NCR_SIZE_32M 14 1170 #define NCR_SIZE_4G 15 1171 1172 /* 1173 * Performance monitor events. 1174 * 1175 * Note that 586-class and 686-class CPUs have different performance 1176 * monitors available, and they are accessed differently: 1177 * 1178 * 686-class: `rdpmc' instruction 1179 * 586-class: `rdmsr' instruction, CESR MSR 1180 * 1181 * The descriptions of these events are too lengthy to include here. 1182 * See Appendix A of "Intel Architecture Software Developer's 1183 * Manual, Volume 3: System Programming" for more information. 1184 */ 1185 1186 /* 1187 * 586-class CESR MSR format. Lower 16 bits is CTR0, upper 16 bits 1188 * is CTR1. 1189 */ 1190 1191 #define PMC5_CESR_EVENT 0x003f 1192 #define PMC5_CESR_OS 0x0040 1193 #define PMC5_CESR_USR 0x0080 1194 #define PMC5_CESR_E 0x0100 1195 #define PMC5_CESR_P 0x0200 1196 1197 #define PMC5_DATA_READ 0x00 1198 #define PMC5_DATA_WRITE 0x01 1199 #define PMC5_DATA_TLB_MISS 0x02 1200 #define PMC5_DATA_READ_MISS 0x03 1201 #define PMC5_DATA_WRITE_MISS 0x04 1202 #define PMC5_WRITE_M_E 0x05 1203 #define PMC5_DATA_LINES_WBACK 0x06 1204 #define PMC5_DATA_CACHE_SNOOP 0x07 1205 #define PMC5_DATA_CACHE_SNOOP_HIT 0x08 1206 #define PMC5_MEM_ACCESS_BOTH_PIPES 0x09 1207 #define PMC5_BANK_CONFLICTS 0x0a 1208 #define PMC5_MISALIGNED_DATA 0x0b 1209 #define PMC5_INST_READ 0x0c 1210 #define PMC5_INST_TLB_MISS 0x0d 1211 #define PMC5_INST_CACHE_MISS 0x0e 1212 #define PMC5_SEGMENT_REG_LOAD 0x0f 1213 #define PMC5_BRANCHES 0x12 1214 #define PMC5_BTB_HITS 0x13 1215 #define PMC5_BRANCH_TAKEN 0x14 1216 #define PMC5_PIPELINE_FLUSH 0x15 1217 #define PMC5_INST_EXECUTED 0x16 1218 #define PMC5_INST_EXECUTED_V_PIPE 0x17 1219 #define PMC5_BUS_UTILIZATION 0x18 1220 #define PMC5_WRITE_BACKUP_STALL 0x19 1221 #define PMC5_DATA_READ_STALL 0x1a 1222 #define PMC5_WRITE_E_M_STALL 0x1b 1223 #define PMC5_LOCKED_BUS 0x1c 1224 #define PMC5_IO_CYCLE 0x1d 1225 #define PMC5_NONCACHE_MEM_READ 0x1e 1226 #define PMC5_AGI_STALL 0x1f 1227 #define PMC5_FLOPS 0x22 1228 #define PMC5_BP0_MATCH 0x23 1229 #define PMC5_BP1_MATCH 0x24 1230 #define PMC5_BP2_MATCH 0x25 1231 #define PMC5_BP3_MATCH 0x26 1232 #define PMC5_HARDWARE_INTR 0x27 1233 #define PMC5_DATA_RW 0x28 1234 #define PMC5_DATA_RW_MISS 0x29 1235 1236 /* 1237 * 686-class Event Selector MSR format. 1238 */ 1239 1240 #define PMC6_EVTSEL_EVENT 0x000000ff 1241 #define PMC6_EVTSEL_UNIT 0x0000ff00 1242 #define PMC6_EVTSEL_UNIT_SHIFT 8 1243 #define PMC6_EVTSEL_USR (1 << 16) 1244 #define PMC6_EVTSEL_OS (1 << 17) 1245 #define PMC6_EVTSEL_E (1 << 18) 1246 #define PMC6_EVTSEL_PC (1 << 19) 1247 #define PMC6_EVTSEL_INT (1 << 20) 1248 #define PMC6_EVTSEL_EN (1 << 22) /* PerfEvtSel0 only */ 1249 #define PMC6_EVTSEL_INV (1 << 23) 1250 #define PMC6_EVTSEL_COUNTER_MASK 0xff000000 1251 #define PMC6_EVTSEL_COUNTER_MASK_SHIFT 24 1252 1253 /* Data Cache Unit */ 1254 #define PMC6_DATA_MEM_REFS 0x43 1255 #define PMC6_DCU_LINES_IN 0x45 1256 #define PMC6_DCU_M_LINES_IN 0x46 1257 #define PMC6_DCU_M_LINES_OUT 0x47 1258 #define PMC6_DCU_MISS_OUTSTANDING 0x48 1259 1260 /* Instruction Fetch Unit */ 1261 #define PMC6_IFU_IFETCH 0x80 1262 #define PMC6_IFU_IFETCH_MISS 0x81 1263 #define PMC6_ITLB_MISS 0x85 1264 #define PMC6_IFU_MEM_STALL 0x86 1265 #define PMC6_ILD_STALL 0x87 1266 1267 /* L2 Cache */ 1268 #define PMC6_L2_IFETCH 0x28 1269 #define PMC6_L2_LD 0x29 1270 #define PMC6_L2_ST 0x2a 1271 #define PMC6_L2_LINES_IN 0x24 1272 #define PMC6_L2_LINES_OUT 0x26 1273 #define PMC6_L2_M_LINES_INM 0x25 1274 #define PMC6_L2_M_LINES_OUTM 0x27 1275 #define PMC6_L2_RQSTS 0x2e 1276 #define PMC6_L2_ADS 0x21 1277 #define PMC6_L2_DBUS_BUSY 0x22 1278 #define PMC6_L2_DBUS_BUSY_RD 0x23 1279 1280 /* External Bus Logic */ 1281 #define PMC6_BUS_DRDY_CLOCKS 0x62 1282 #define PMC6_BUS_LOCK_CLOCKS 0x63 1283 #define PMC6_BUS_REQ_OUTSTANDING 0x60 1284 #define PMC6_BUS_TRAN_BRD 0x65 1285 #define PMC6_BUS_TRAN_RFO 0x66 1286 #define PMC6_BUS_TRANS_WB 0x67 1287 #define PMC6_BUS_TRAN_IFETCH 0x68 1288 #define PMC6_BUS_TRAN_INVAL 0x69 1289 #define PMC6_BUS_TRAN_PWR 0x6a 1290 #define PMC6_BUS_TRANS_P 0x6b 1291 #define PMC6_BUS_TRANS_IO 0x6c 1292 #define PMC6_BUS_TRAN_DEF 0x6d 1293 #define PMC6_BUS_TRAN_BURST 0x6e 1294 #define PMC6_BUS_TRAN_ANY 0x70 1295 #define PMC6_BUS_TRAN_MEM 0x6f 1296 #define PMC6_BUS_DATA_RCV 0x64 1297 #define PMC6_BUS_BNR_DRV 0x61 1298 #define PMC6_BUS_HIT_DRV 0x7a 1299 #define PMC6_BUS_HITM_DRDV 0x7b 1300 #define PMC6_BUS_SNOOP_STALL 0x7e 1301 1302 /* Floating Point Unit */ 1303 #define PMC6_FLOPS 0xc1 1304 #define PMC6_FP_COMP_OPS_EXE 0x10 1305 #define PMC6_FP_ASSIST 0x11 1306 #define PMC6_MUL 0x12 1307 #define PMC6_DIV 0x12 1308 #define PMC6_CYCLES_DIV_BUSY 0x14 1309 1310 /* Memory Ordering */ 1311 #define PMC6_LD_BLOCKS 0x03 1312 #define PMC6_SB_DRAINS 0x04 1313 #define PMC6_MISALIGN_MEM_REF 0x05 1314 #define PMC6_EMON_KNI_PREF_DISPATCHED 0x07 /* P-III only */ 1315 #define PMC6_EMON_KNI_PREF_MISS 0x4b /* P-III only */ 1316 1317 /* Instruction Decoding and Retirement */ 1318 #define PMC6_INST_RETIRED 0xc0 1319 #define PMC6_UOPS_RETIRED 0xc2 1320 #define PMC6_INST_DECODED 0xd0 1321 #define PMC6_EMON_KNI_INST_RETIRED 0xd8 1322 #define PMC6_EMON_KNI_COMP_INST_RET 0xd9 1323 1324 /* Interrupts */ 1325 #define PMC6_HW_INT_RX 0xc8 1326 #define PMC6_CYCLES_INT_MASKED 0xc6 1327 #define PMC6_CYCLES_INT_PENDING_AND_MASKED 0xc7 1328 1329 /* Branches */ 1330 #define PMC6_BR_INST_RETIRED 0xc4 1331 #define PMC6_BR_MISS_PRED_RETIRED 0xc5 1332 #define PMC6_BR_TAKEN_RETIRED 0xc9 1333 #define PMC6_BR_MISS_PRED_TAKEN_RET 0xca 1334 #define PMC6_BR_INST_DECODED 0xe0 1335 #define PMC6_BTB_MISSES 0xe2 1336 #define PMC6_BR_BOGUS 0xe4 1337 #define PMC6_BACLEARS 0xe6 1338 1339 /* Stalls */ 1340 #define PMC6_RESOURCE_STALLS 0xa2 1341 #define PMC6_PARTIAL_RAT_STALLS 0xd2 1342 1343 /* Segment Register Loads */ 1344 #define PMC6_SEGMENT_REG_LOADS 0x06 1345 1346 /* Clocks */ 1347 #define PMC6_CPU_CLK_UNHALTED 0x79 1348 1349 /* MMX Unit */ 1350 #define PMC6_MMX_INSTR_EXEC 0xb0 /* Celeron, P-II, P-IIX only */ 1351 #define PMC6_MMX_SAT_INSTR_EXEC 0xb1 /* P-II and P-III only */ 1352 #define PMC6_MMX_UOPS_EXEC 0xb2 /* P-II and P-III only */ 1353 #define PMC6_MMX_INSTR_TYPE_EXEC 0xb3 /* P-II and P-III only */ 1354 #define PMC6_FP_MMX_TRANS 0xcc /* P-II and P-III only */ 1355 #define PMC6_MMX_ASSIST 0xcd /* P-II and P-III only */ 1356 #define PMC6_MMX_INSTR_RET 0xc3 /* P-II only */ 1357 1358 /* Segment Register Renaming */ 1359 #define PMC6_SEG_RENAME_STALLS 0xd4 /* P-II and P-III only */ 1360 #define PMC6_SEG_REG_RENAMES 0xd5 /* P-II and P-III only */ 1361 #define PMC6_RET_SEG_RENAMES 0xd6 /* P-II and P-III only */ 1362 1363 /* 1364 * AMD K7. [Doc: 22007K.pdf, Feb 2002] 1365 */ 1366 /* Event Selector MSR format */ 1367 #define K7_EVTSEL_EVENT 0x000000ff 1368 #define K7_EVTSEL_UNIT 0x0000ff00 1369 #define K7_EVTSEL_UNIT_SHIFT 8 1370 #define K7_EVTSEL_USR __BIT(16) 1371 #define K7_EVTSEL_OS __BIT(17) 1372 #define K7_EVTSEL_E __BIT(18) 1373 #define K7_EVTSEL_PC __BIT(19) 1374 #define K7_EVTSEL_INT __BIT(20) 1375 #define K7_EVTSEL_EN __BIT(22) 1376 #define K7_EVTSEL_INV __BIT(23) 1377 #define K7_EVTSEL_COUNTER_MASK 0xff000000 1378 #define K7_EVTSEL_COUNTER_MASK_SHIFT 24 1379 /* Data Cache Unit */ 1380 #define K7_DATA_CACHE_ACCESS 0x40 1381 #define K7_DATA_CACHE_MISS 0x41 1382 #define K7_DATA_CACHE_REFILL 0x42 1383 #define K7_DATA_CACHE_REFILL_SYSTEM 0x43 1384 #define K7_DATA_CACHE_WBACK 0x44 1385 #define K7_L1_DTLB_MISS 0x45 1386 #define K7_L2_DTLB_MISS 0x46 1387 #define K7_MISALIGNED_DATA_REF 0x47 1388 /* Instruction Fetch Unit */ 1389 #define K7_IFU_IFETCH 0x80 1390 #define K7_IFU_IFETCH_MISS 0x81 1391 #define K7_IFU_REFILL_FROM_L2 0x82 1392 #define K7_IFU_REFILL_FROM_SYSTEM 0x83 1393 #define K7_L1_ITLB_MISS 0x84 1394 #define K7_L2_ITLB_MISS 0x85 1395 /* Retired */ 1396 #define K7_RETIRED_INST 0xc0 1397 #define K7_RETIRED_OPS 0xc1 1398 #define K7_RETIRED_BRANCH 0xc2 1399 #define K7_RETIRED_BRANCH_MISPREDICTED 0xc3 1400 #define K7_RETIRED_TAKEN_BRANCH 0xc4 1401 #define K7_RETIRED_TAKEN_BRANCH_MISPREDICTED 0xc5 1402 #define K7_RETIRED_FAR_CONTROL_TRANSFER 0xc6 1403 #define K7_RETIRED_RESYNC_BRANCH 0xc7 1404 /* Interrupts */ 1405 #define K7_CYCLES_INT_MASKED 0xcd 1406 #define K7_CYCLES_INT_PENDING_AND_MASKED 0xce 1407 #define K7_HW_INTR_RECV 0xcf 1408 1409 /* 1410 * AMD 10h family PMCs. [Doc: 31116.pdf, Jan 2013] 1411 */ 1412 /* Register MSRs */ 1413 #define MSR_F10H_EVNTSEL0 0xc0010000 1414 #define MSR_F10H_EVNTSEL1 0xc0010001 1415 #define MSR_F10H_EVNTSEL2 0xc0010002 1416 #define MSR_F10H_EVNTSEL3 0xc0010003 1417 #define MSR_F10H_PERFCTR0 0xc0010004 1418 #define MSR_F10H_PERFCTR1 0xc0010005 1419 #define MSR_F10H_PERFCTR2 0xc0010006 1420 #define MSR_F10H_PERFCTR3 0xc0010007 1421 /* Event Selector MSR format */ 1422 #define F10H_EVTSEL_EVENT_MASK 0x000F000000FF 1423 #define F10H_EVTSEL_EVENT_SHIFT_LOW 0 1424 #define F10H_EVTSEL_EVENT_SHIFT_HIGH 32 1425 #define F10H_EVTSEL_UNIT_MASK 0x0000FF00 1426 #define F10H_EVTSEL_UNIT_SHIFT 8 1427 #define F10H_EVTSEL_USR __BIT(16) 1428 #define F10H_EVTSEL_OS __BIT(17) 1429 #define F10H_EVTSEL_EDGE __BIT(18) 1430 #define F10H_EVTSEL_RSVD1 __BIT(19) 1431 #define F10H_EVTSEL_INT __BIT(20) 1432 #define F10H_EVTSEL_RSVD2 __BIT(21) 1433 #define F10H_EVTSEL_EN __BIT(22) 1434 #define F10H_EVTSEL_INV __BIT(23) 1435 #define F10H_EVTSEL_COUNTER_MASK 0xFF000000 1436 #define F10H_EVTSEL_COUNTER_MASK_SHIFT 24 1437 /* Floating Point Events */ 1438 #define F10H_FP_DISPATCHED_FPU_OPS 0x00 1439 #define F10H_FP_CYCLES_EMPTY_FPU_OPS 0x01 1440 #define F10H_FP_DISPATCHED_FASTFLAG_OPS 0x02 1441 #define F10H_FP_RETIRED_SSE_OPS 0x03 1442 #define F10H_FP_RETIRED_MOVE_OPS 0x04 1443 #define F10H_FP_RETIRED_SERIALIZING_OPS 0x05 1444 #define F10H_FP_CYCLES_SERIALIZING_OP_SCHEDULER 0x06 1445 /* Load/Store and TLB Events */ 1446 #define F10H_SEGMENT_REG_LOADS 0x20 1447 #define F10H_PIPELINE_RESTART_SELFMOD_CODE 0x21 1448 #define F10H_PIPELINE_RESTART_PROBE_HIT 0x22 1449 #define F10H_LS_BUFFER_2_FILL 0x23 1450 #define F10H_LOCKED_OPERATIONS 0x24 1451 #define F10H_RETIRED_CLFLUSH_INSTRUCTIONS 0x26 1452 #define F10H_RETIRED_CPUID_INSTRUCTIONS 0x27 1453 #define F10H_CANCELLED_STORE_LOAD_FORWARD_OPS 0x2A 1454 #define F10H_SMI_RECEIVED 0x2B 1455 /* Data Cache Events */ 1456 #define F10H_DATA_CACHE_ACCESS 0x40 1457 #define F10H_DATA_CACHE_MISS 0x41 1458 #define F10H_DATA_CACHE_REFILL_FROM_L2 0x42 1459 #define F10H_DATA_CACHE_REFILL_FROM_NORTHBRIDGE 0x43 1460 #define F10H_CACHE_LINES_EVICTED 0x44 1461 #define F10H_L1_DTLB_MISS 0x45 1462 #define F10H_L2_DTLB_MISS 0x46 1463 #define F10H_MISALIGNED_ACCESS 0x47 1464 #define F10H_MICROARCH_LATE_CANCEL_OF_ACCESS 0x48 1465 #define F10H_MICROARCH_EARLY_CANCEL_OF_ACCESS 0x49 1466 #define F10H_SINGLE_BIT_ECC_ERRORS_RECORDED 0x4A 1467 #define F10H_PREFETCH_INSTRUCTIONS_DISPATCHED 0x4B 1468 #define F10H_DCACHE_MISSES_LOCKED_INSTRUCTIONS 0x4C 1469 #define F10H_L1_DTLB_HIT 0x4D 1470 #define F10H_INEFFECTIVE_SOFTWARE_PREFETCHS 0x52 1471 #define F10H_GLOBAL_TLB_FLUSHES 0x54 1472 #define F10H_MEMORY_REQUESTS_BY_TYPE 0x65 1473 #define F10H_DATA_PREFETCHER 0x67 1474 #define F10H_MAB_REQUESTS 0x68 1475 #define F10H_MAB_WAIT_CYCLES 0x69 1476 #define F10H_NORTHBRIDGE_READ_RESP_BY_COH_STATE 0x6C 1477 #define F10H_OCTWORDS_WRITTEN_TO_SYSTEM 0x6D 1478 #define F10H_CPU_CLOCKS_NOT_HALTED 0x76 1479 #define F10H_REQUESTS_TO_L2_CACHE 0x7D 1480 #define F10H_L2_CACHE_MISSES 0x7E 1481 #define F10H_L2_FILL 0x7F 1482 /* F10H_PAGE_SIZE_MISMATCHES (0x01C0): reserved on some revisions */ 1483 /* Instruction Cache Events */ 1484 #define F10H_INSTRUCTION_CACHE_FETCH 0x80 1485 #define F10H_INSTRUCTION_CACHE_MISS 0x81 1486 #define F10H_INSTRUCTION_CACHE_REFILL_FROM_L2 0x82 1487 #define F10H_INSTRUCTION_CACHE_REFILL_FROM_SYS 0x83 1488 #define F10H_L1_ITLB_MISS 0x84 1489 #define F10H_L2_ITLB_MISS 0x85 1490 #define F10H_PIPELINE_RESTART_INSTR_STREAM_PROBE 0x86 1491 #define F10H_INSTRUCTION_FETCH_STALL 0x87 1492 #define F10H_RETURN_STACK_HITS 0x88 1493 #define F10H_RETURN_STACK_OVERFLOWS 0x89 1494 #define F10H_INSTRUCTION_CACHE_VICTIMS 0x8B 1495 #define F10H_INSTRUCTION_CACHE_LINES_INVALIDATED 0x8C 1496 #define F10H_ITLD_RELOADS 0x99 1497 #define F10H_ITLD_RELOADS_ABORTED 0x9A 1498 /* Execution Unit Events */ 1499 #define F10H_RETIRED_INSTRUCTIONS 0xC0 1500 #define F10H_RETIRED_UOPS 0xC1 1501 #define F10H_RETIRED_BRANCH 0xC2 1502 #define F10H_RETIRED_MISPREDICTED_BRANCH 0xC3 1503 #define F10H_RETIRED_TAKEN_BRANCH 0xC4 1504 #define F10H_RETIRED_TAKEN_BRANCH_MISPREDICTED 0xC5 1505 #define F10H_RETIRED_FAR_CONTROL_TRANSFER 0xC6 1506 #define F10H_RETIRED_BRANCH_RESYNC 0xC7 1507 #define F10H_RETIRED_NEAR_RETURNS 0xC8 1508 #define F10H_RETIRED_NEAR_RETURNS_MISPREDICTED 0xC9 1509 #define F10H_RETIRED_INDIRECT_BRANCH_MISPREDICTED 0xCA 1510 #define F10H_RETIRED_MMX_FP_INSTRUCTIONS 0xCB 1511 #define F10H_RETIRED_FASTPATH_DOUBLE_OP_INSTR 0xCC 1512 #define F10H_INTERRUPTS_MASKED_CYCLES 0xCD 1513 #define F10H_INTERRUPTS_MASKED_CYCLES_INTERRUPT_PENDING 0xCE 1514 #define F10H_INTERRUPTS_TAKEN 0xCF 1515 #define F10H_DECODER_EMPTY 0xD0 1516 #define F10H_DISPATCH_STALLS 0xD1 1517 #define F10H_DISPATCH_STALLS_BRANCH_ABORT_RETIRE 0xD2 1518 #define F10H_DISPATCH_STALLS_SERIALIZATION 0xD3 1519 #define F10H_DISPATCH_STALLS_SEGMENT_LOAD 0xD4 1520 #define F10H_DISPATCH_STALLS_REORDER_BUF_FULL 0xD5 1521 #define F10H_DISPATCH_STALLS_RSV_STATION_FULL 0xD6 1522 #define F10H_DISPATCH_STALLS_FPU_FULL 0xD7 1523 #define F10H_DISPATCH_STALLS_LS_FULL 0xD8 1524 #define F10H_DISPATCH_STALLS_WAITING_ALL_QUITE 0xD9 1525 #define F10H_DISPATCH_STALLS_FAR_TRANSFER 0xDA 1526 #define F10H_FPU_EXCEPTIONS 0xDB 1527 #define F10H_DR0_BREAKPOINT_MATCHES 0xDC 1528 #define F10H_DR1_BREAKPOINT_MATCHES 0xDD 1529 #define F10H_DR2_BREAKPOINT_MATCHES 0xDE 1530 #define F10H_DR3_BREAKPOINT_MATCHES 0xDF 1531 /* F10H_RETIRED_X87_FP_OPERATIONS (0x01C0): reserved on some revisions */ 1532 /* F10H_IBS_OPS_TAGGED (0x1CF): reserved on some revisions */ 1533 /* F10H_LFENCE_INSTRUCTIONS_RETIRED (0x01D3): reserved on some revisions */ 1534 /* F10H_SFENCE_INSTRUCTIONS_RETIRED (0x01D4): reserved on some revisions */ 1535 /* F10H_MFENCE_INSTRUCTIONS_RETIRED (0x01D5): reserved on some revisions */ 1536 /* Memory Controller Events */ 1537 #define F10H_DRAM_ACCESSES 0xE0 1538 #define F10H_DRAM_CONTROLLER_PT_OVERFLOWS 0xE1 1539 #define F10H_MEM_CONTROLLER_DRAM_COMMAND_SLOTS_MISSED 0xE2 1540 #define F10H_MEM_CONTROLLER_TURNAROUNDS 0xE3 1541 #define F10H_MEM_CONTROLLER_BYPASS_COUNTER_SATURATION 0xE4 1542 #define F10H_THERMAL_STATUS 0xE8 1543 #define F10H_CPU_IO_REQUESTS_TO_MEMORY_IO 0xE9 1544 #define F10H_CACHE_BLOCK_COMMANDS 0xEA 1545 #define F10H_SIZED_COMMANDS 0xEB 1546 #define F10H_PROBE_RESPONSES_AND_UPSTREAM_REQUESTS 0xEC 1547 #define F10H_GART_EVENTS 0xEE 1548 #define F10H_MEMORY_CONTROLLER_REQUESTS 0x01F0 1549 #define F10H_CPU_TO_DRAM_REQUESTS_TO_TARGET_NODE 0x01E0 1550 #define F10H_IO_TO_DRAM_REQUESTS_TO_TARGET_NODE 0x01E1 1551 #define F10H_CPU_READ_CMD_LATENCY_TARGET_NODE_03 0x01E2 1552 #define F10H_CPU_READ_CMD_REQUESTS_TARGET_NODE_03 0x01E3 1553 #define F10H_CPU_READ_CMD_LATENCY_TARGET_NODE_47 0x01E4 1554 #define F10H_CPU_READ_CMD_REQUESTS_TARGET_NODE_47 0x01E5 1555 #define F10H_CPU_CMD_LATENCY_TO_TARGET_NODE_0347 0x01E6 1556 #define F10H_CPU_REQUESTS_TO_TARGET_NODE_0347 0x01E7 1557 /* Link Events */ 1558 #define F10H_HYPERTRANSPORT_LINK0_TRANSMIT_BANDWIDTH 0xF6 1559 #define F10H_HYPERTRANSPORT_LINK1_TRANSMIT_BANDWIDTH 0xF7 1560 #define F10H_HYPERTRANSPORT_LINK2_TRANSMIT_BANDWIDTH 0xF8 1561 #define F10H_HYPERTRANSPORT_LINK3_TRANSMIT_BANDWIDTH 0x01F9 1562 /* L3 Cache Events */ 1563 /* F10H_READ_READ_REQUEST_TO_L3_CACHE (0x04E0): depends on the revision */ 1564 /* F10H_L3_CACHE_MISSES (0x04E1): depends on the revision */ 1565 /* F10H_L3_FILLS_FROM_L2_EVICTIONS (0x04E2): depends on the revision */ 1566 #define F10H_L3_EVICTIONS 0x04E3 1567 /* F10H_NONCANCELLED_L3_READ_REQUESTS (0x04ED): depends on the revision */ 1568 1569
Indexes created Tue Oct 21 12:09:54 GMT 2025