specialreg.h revision 1.98.2.25
1 /* $NetBSD: specialreg.h,v 1.98.2.25 2023/01/23 13:09:54 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2014-2019 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * Copyright (c) 1991 The Regents of the University of California. 31 * All rights reserved. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 1. Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * 2. Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in the 40 * documentation and/or other materials provided with the distribution. 41 * 3. Neither the name of the University nor the names of its contributors 42 * may be used to endorse or promote products derived from this software 43 * without specific prior written permission. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 * 57 * @(#)specialreg.h 7.1 (Berkeley) 5/9/91 58 */ 59 60 /* 61 * CR0 62 */ 63 #define CR0_PE 0x00000001 /* Protected mode Enable */ 64 #define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */ 65 #define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */ 66 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 67 #define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */ 68 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 69 #define CR0_WP 0x00010000 /* Write Protect (honor PG_RW in all modes) */ 70 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 71 #define CR0_NW 0x20000000 /* Not Write-through */ 72 #define CR0_CD 0x40000000 /* Cache Disable */ 73 #define CR0_PG 0x80000000 /* PaGing enable */ 74 75 /* 76 * Cyrix 486 DLC special registers, accessible as IO ports 77 */ 78 #define CCR0 0xc0 /* configuration control register 0 */ 79 #define CCR0_NC0 0x01 /* first 64K of each 1M memory region is non-cacheable */ 80 #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 81 #define CCR0_A20M 0x04 /* enables A20M# input pin */ 82 #define CCR0_KEN 0x08 /* enables KEN# input pin */ 83 #define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */ 84 #define CCR0_BARB 0x20 /* flushes internal cache when entering hold state */ 85 #define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */ 86 #define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */ 87 #define CCR1 0xc1 /* configuration control register 1 */ 88 #define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */ 89 90 /* 91 * CR4 92 */ 93 #define CR4_VME 0x00000001 /* Virtual 8086 mode extension enable */ 94 #define CR4_PVI 0x00000002 /* Protected mode virtual interrupt enable */ 95 #define CR4_TSD 0x00000004 /* Restrict RDTSC instruction to cpl 0 */ 96 #define CR4_DE 0x00000008 /* Debugging extension */ 97 #define CR4_PSE 0x00000010 /* Large (4MB) page size enable */ 98 #define CR4_PAE 0x00000020 /* Physical address extension enable */ 99 #define CR4_MCE 0x00000040 /* Machine check enable */ 100 #define CR4_PGE 0x00000080 /* Page global enable */ 101 #define CR4_PCE 0x00000100 /* Enable RDPMC instruction for all cpls */ 102 #define CR4_OSFXSR 0x00000200 /* Enable fxsave/fxrestor and SSE */ 103 #define CR4_OSXMMEXCPT 0x00000400 /* Enable unmasked SSE exceptions */ 104 #define CR4_UMIP 0x00000800 /* User Mode Instruction Prevention */ 105 #define CR4_LA57 0x00001000 /* 57-bit linear addresses */ 106 #define CR4_VMXE 0x00002000 /* Enable VMX operations */ 107 #define CR4_SMXE 0x00004000 /* Enable SMX operations */ 108 #define CR4_FSGSBASE 0x00010000 /* Enable *FSBASE and *GSBASE instructions */ 109 #define CR4_PCIDE 0x00020000 /* Enable Process Context IDentifiers */ 110 #define CR4_OSXSAVE 0x00040000 /* Enable xsave and xrestore */ 111 #define CR4_SMEP 0x00100000 /* Enable SMEP support */ 112 #define CR4_SMAP 0x00200000 /* Enable SMAP support */ 113 #define CR4_PKE 0x00400000 /* Enable Protection Keys for user pages */ 114 #define CR4_CET 0x00800000 /* Enable CET */ 115 #define CR4_PKS 0x01000000 /* Enable Protection Keys for kern pages */ 116 117 /* 118 * Extended Control Register XCR0 119 */ 120 #define XCR0_X87 __BIT(0) /* x87 FPU/MMX state */ 121 #define XCR0_SSE __BIT(1) /* SSE state */ 122 #define XCR0_YMM_Hi128 __BIT(2) /* AVX-256 (ymmn registers) */ 123 #define XCR0_BNDREGS __BIT(3) /* Memory protection ext bounds */ 124 #define XCR0_BNDCSR __BIT(4) /* Memory protection ext state */ 125 #define XCR0_Opmask __BIT(5) /* AVX-512 Opmask */ 126 #define XCR0_ZMM_Hi256 __BIT(6) /* AVX-512 upper 256 bits low regs */ 127 #define XCR0_Hi16_ZMM __BIT(7) /* AVX-512 512 bits upper registers */ 128 #define XCR0_PT __BIT(8) /* Processor Trace state */ 129 #define XCR0_PKRU __BIT(9) /* Protection Key state */ 130 #define XCR0_CET_U __BIT(11) /* User CET state */ 131 #define XCR0_CET_S __BIT(12) /* Kern CET state */ 132 #define XCR0_HDC __BIT(13) /* Hardware Duty Cycle state */ 133 #define XCR0_LBR __BIT(15) /* Last Branch Record */ 134 #define XCR0_HWP __BIT(16) /* Hardware P-states */ 135 136 #define XCR0_FLAGS1 "\20" \ 137 "\1" "x87" "\2" "SSE" "\3" "AVX" "\4" "BNDREGS" \ 138 "\5" "BNDCSR" "\6" "Opmask" "\7" "ZMM_Hi256" "\10" "Hi16_ZMM" \ 139 "\11" "PT" "\12" "PKRU" "\14" "CET_U" \ 140 "\15" "CET_S" "\16" "HDC" "\20" "LBR" \ 141 "\21" "HWP" 142 143 /* 144 * Known FPU bits, only these get enabled. The save area is sized for all the 145 * fields below. 146 */ 147 #define XCR0_FPU (XCR0_X87 | XCR0_SSE | XCR0_YMM_Hi128 | \ 148 XCR0_Opmask | XCR0_ZMM_Hi256 | XCR0_Hi16_ZMM) 149 150 /* 151 * "features" bits. 152 * CPUID Fn00000001 153 */ 154 /* %edx */ 155 #define CPUID_FPU 0x00000001 /* processor has an FPU? */ 156 #define CPUID_VME 0x00000002 /* has virtual mode (%cr4's VME/PVI) */ 157 #define CPUID_DE 0x00000004 /* has debugging extension */ 158 #define CPUID_PSE 0x00000008 /* has 4MB page size extension */ 159 #define CPUID_TSC 0x00000010 /* has time stamp counter */ 160 #define CPUID_MSR 0x00000020 /* has model specific registers */ 161 #define CPUID_PAE 0x00000040 /* has physical address extension */ 162 #define CPUID_MCE 0x00000080 /* has machine check exception */ 163 #define CPUID_CX8 0x00000100 /* has CMPXCHG8B instruction */ 164 #define CPUID_APIC 0x00000200 /* has enabled APIC */ 165 #define CPUID_SEP 0x00000800 /* has SYSENTER/SYSEXIT extension */ 166 #define CPUID_MTRR 0x00001000 /* has memory type range register */ 167 #define CPUID_PGE 0x00002000 /* has page global extension */ 168 #define CPUID_MCA 0x00004000 /* has machine check architecture */ 169 #define CPUID_CMOV 0x00008000 /* has CMOVcc instruction */ 170 #define CPUID_PAT 0x00010000 /* Page Attribute Table */ 171 #define CPUID_PSE36 0x00020000 /* 36-bit PSE */ 172 #define CPUID_PSN 0x00040000 /* Processor Serial Number */ 173 #define CPUID_CLFSH 0x00080000 /* CLFLUSH instruction supported */ 174 #define CPUID_DS 0x00200000 /* Debug Store */ 175 #define CPUID_ACPI 0x00400000 /* ACPI performance modulation regs */ 176 #define CPUID_MMX 0x00800000 /* MMX supported */ 177 #define CPUID_FXSR 0x01000000 /* Fast FP/MMX Save/Restore */ 178 #define CPUID_SSE 0x02000000 /* Streaming SIMD Extensions */ 179 #define CPUID_SSE2 0x04000000 /* Streaming SIMD Extensions #2 */ 180 #define CPUID_SS 0x08000000 /* Self-Snoop */ 181 #define CPUID_HTT 0x10000000 /* Hyper-Threading Technology */ 182 #define CPUID_TM 0x20000000 /* Thermal Monitor (TCC) */ 183 #define CPUID_PBE 0x80000000 /* Pending Break Enable */ 184 185 #define CPUID_FLAGS1 "\20" \ 186 "\1" "FPU" "\2" "VME" "\3" "DE" "\4" "PSE" \ 187 "\5" "TSC" "\6" "MSR" "\7" "PAE" "\10" "MCE" \ 188 "\11" "CX8" "\12" "APIC" "\13" "B10" "\14" "SEP" \ 189 "\15" "MTRR" "\16" "PGE" "\17" "MCA" "\20" "CMOV" \ 190 "\21" "PAT" "\22" "PSE36" "\23" "PN" "\24" "CLFSH" \ 191 "\25" "B20" "\26" "DS" "\27" "ACPI" "\30" "MMX" \ 192 "\31" "FXSR" "\32" "SSE" "\33" "SSE2" "\34" "SS" \ 193 "\35" "HTT" "\36" "TM" "\37" "IA64" "\40" "PBE" 194 195 /* Blacklists of CPUID flags - used to mask certain features */ 196 #ifdef XEN 197 #define CPUID_FEAT_BLACKLIST (CPUID_PGE|CPUID_PSE|CPUID_MTRR) 198 #else 199 #define CPUID_FEAT_BLACKLIST 0 200 #endif 201 202 /* %ecx */ 203 #define CPUID2_SSE3 __BIT(0) /* Streaming SIMD Extensions 3 */ 204 #define CPUID2_PCLMULQDQ __BIT(1) /* PCLMULQDQ instructions */ 205 #define CPUID2_DTES64 __BIT(2) /* 64-bit Debug Trace */ 206 #define CPUID2_MONITOR __BIT(3) /* MONITOR/MWAIT instructions */ 207 #define CPUID2_DS_CPL __BIT(4) /* CPL Qualified Debug Store */ 208 #define CPUID2_VMX __BIT(5) /* Virtual Machine eXtensions */ 209 #define CPUID2_SMX __BIT(6) /* Safer Mode eXtensions */ 210 #define CPUID2_EST __BIT(7) /* Enhanced SpeedStep Technology */ 211 #define CPUID2_TM2 __BIT(8) /* Thermal Monitor 2 */ 212 #define CPUID2_SSSE3 __BIT(9) /* Supplemental SSE3 */ 213 #define CPUID2_CNXTID __BIT(10) /* Context ID */ 214 #define CPUID2_SDBG __BIT(11) /* Silicon Debug */ 215 #define CPUID2_FMA __BIT(12) /* Fused Multiply Add */ 216 #define CPUID2_CX16 __BIT(13) /* CMPXCHG16B instruction */ 217 #define CPUID2_XTPR __BIT(14) /* Task Priority Messages disabled? */ 218 #define CPUID2_PDCM __BIT(15) /* Perf/Debug Capability MSR */ 219 /* bit 16 unused __BIT(16) */ 220 #define CPUID2_PCID __BIT(17) /* Process Context ID */ 221 #define CPUID2_DCA __BIT(18) /* Direct Cache Access */ 222 #define CPUID2_SSE41 __BIT(19) /* Streaming SIMD Extensions 4.1 */ 223 #define CPUID2_SSE42 __BIT(20) /* Streaming SIMD Extensions 4.2 */ 224 #define CPUID2_X2APIC __BIT(21) /* xAPIC Extensions */ 225 #define CPUID2_MOVBE __BIT(22) /* MOVBE (move after byteswap) */ 226 #define CPUID2_POPCNT __BIT(23) /* POPCNT instruction available */ 227 #define CPUID2_DEADLINE __BIT(24) /* APIC Timer supports TSC Deadline */ 228 #define CPUID2_AESNI __BIT(25) /* AES instructions */ 229 #define CPUID2_XSAVE __BIT(26) /* XSAVE instructions */ 230 #define CPUID2_OSXSAVE __BIT(27) /* XGETBV/XSETBV instructions */ 231 #define CPUID2_AVX __BIT(28) /* AVX instructions */ 232 #define CPUID2_F16C __BIT(29) /* half precision conversion */ 233 #define CPUID2_RDRAND __BIT(30) /* RDRAND (hardware random number) */ 234 #define CPUID2_RAZ __BIT(31) /* RAZ. Indicates guest state. */ 235 236 #define CPUID2_FLAGS1 "\20" \ 237 "\1" "SSE3" "\2" "PCLMULQDQ" "\3" "DTES64" "\4" "MONITOR" \ 238 "\5" "DS-CPL" "\6" "VMX" "\7" "SMX" "\10" "EST" \ 239 "\11" "TM2" "\12" "SSSE3" "\13" "CID" "\14" "SDBG" \ 240 "\15" "FMA" "\16" "CX16" "\17" "xTPR" "\20" "PDCM" \ 241 "\21" "B16" "\22" "PCID" "\23" "DCA" "\24" "SSE41" \ 242 "\25" "SSE42" "\26" "X2APIC" "\27" "MOVBE" "\30" "POPCNT" \ 243 "\31" "DEADLINE" "\32" "AES" "\33" "XSAVE" "\34" "OSXSAVE" \ 244 "\35" "AVX" "\36" "F16C" "\37" "RDRAND" "\40" "RAZ" 245 246 /* %eax */ 247 #define CPUID_TO_BASEFAMILY(cpuid) (((cpuid) >> 8) & 0xf) 248 #define CPUID_TO_BASEMODEL(cpuid) (((cpuid) >> 4) & 0xf) 249 #define CPUID_TO_STEPPING(cpuid) ((cpuid) & 0xf) 250 251 /* 252 * The Extended family bits should only be inspected when CPUID_TO_BASEFAMILY() 253 * returns 15. They are use to encode family value 16 to 270 (add 15). 254 * The Extended model bits are the high 4 bits of the model. 255 * They are only valid for family >= 15 or family 6 (intel, but all amd 256 * family 6 are documented to return zero bits for them). 257 */ 258 #define CPUID_TO_EXTFAMILY(cpuid) (((cpuid) >> 20) & 0xff) 259 #define CPUID_TO_EXTMODEL(cpuid) (((cpuid) >> 16) & 0xf) 260 261 /* The macros for the Display Family and the Display Model */ 262 #define CPUID_TO_FAMILY(cpuid) (CPUID_TO_BASEFAMILY(cpuid) \ 263 + ((CPUID_TO_BASEFAMILY(cpuid) != 0x0f) \ 264 ? 0 : CPUID_TO_EXTFAMILY(cpuid))) 265 #define CPUID_TO_MODEL(cpuid) (CPUID_TO_BASEMODEL(cpuid) \ 266 | ((CPUID_TO_BASEFAMILY(cpuid) != 0x0f) \ 267 && (CPUID_TO_BASEFAMILY(cpuid) != 0x06) \ 268 ? 0 : (CPUID_TO_EXTMODEL(cpuid) << 4))) 269 270 /* %ebx */ 271 #define CPUID_BRAND_INDEX __BITS(7,0) 272 #define CPUID_CLFLUSH_SIZE __BITS(15,8) 273 #define CPUID_HTT_CORES __BITS(23,16) 274 #define CPUID_LOCAL_APIC_ID __BITS(31,24) 275 276 /* 277 * Intel Deterministic Cache Parameter. 278 * CPUID Fn0000_0004 279 */ 280 281 /* %eax */ 282 #define CPUID_DCP_CACHETYPE __BITS(4, 0) /* Cache type */ 283 #define CPUID_DCP_CACHETYPE_N 0 /* NULL */ 284 #define CPUID_DCP_CACHETYPE_D 1 /* Data cache */ 285 #define CPUID_DCP_CACHETYPE_I 2 /* Instruction cache */ 286 #define CPUID_DCP_CACHETYPE_U 3 /* Unified cache */ 287 #define CPUID_DCP_CACHELEVEL __BITS(7, 5) /* Cache level (start at 1) */ 288 #define CPUID_DCP_SELFINITCL __BIT(8) /* Self initializing cachelvl*/ 289 #define CPUID_DCP_FULLASSOC __BIT(9) /* Full associative */ 290 #define CPUID_DCP_SHARING __BITS(25, 14) /* sharing */ 291 #define CPUID_DCP_CORE_P_PKG __BITS(31, 26) /* Cores/package */ 292 293 /* %ebx */ 294 #define CPUID_DCP_LINESIZE __BITS(11, 0) /* System coherency linesize */ 295 #define CPUID_DCP_PARTITIONS __BITS(21, 12) /* Physical line partitions */ 296 #define CPUID_DCP_WAYS __BITS(31, 22) /* Ways of associativity */ 297 298 /* %ecx: Number of sets */ 299 300 /* %edx */ 301 #define CPUID_DCP_INVALIDATE __BIT(0) /* WB invalidate/invalidate */ 302 #define CPUID_DCP_INCLUSIVE __BIT(1) /* Cache inclusiveness */ 303 #define CPUID_DCP_COMPLEX __BIT(2) /* Complex cache indexing */ 304 305 /* 306 * Intel/AMD MONITOR/MWAIT. 307 * CPUID Fn0000_0005 308 */ 309 /* %eax */ 310 #define CPUID_MON_MINSIZE __BITS(15, 0) /* Smallest monitor-line size */ 311 /* %ebx */ 312 #define CPUID_MON_MAXSIZE __BITS(15, 0) /* Largest monitor-line size */ 313 /* %ecx */ 314 #define CPUID_MON_EMX __BIT(0) /* MONITOR/MWAIT Extensions */ 315 #define CPUID_MON_IBE __BIT(1) /* Interrupt as Break Event */ 316 317 #define CPUID_MON_FLAGS "\20" \ 318 "\1" "EMX" "\2" "IBE" 319 320 /* %edx: number of substates for specific C-state */ 321 #define CPUID_MON_SUBSTATE(edx, cstate) (((edx) >> (cstate * 4)) & 0x0000000f) 322 323 /* 324 * Intel/AMD Digital Thermal Sensor and Power Management. 325 * CPUID Fn0000_0006 326 */ 327 /* %eax */ 328 #define CPUID_DSPM_DTS __BIT(0) /* Digital Thermal Sensor */ 329 #define CPUID_DSPM_IDA __BIT(1) /* Intel Dynamic Acceleration */ 330 #define CPUID_DSPM_ARAT __BIT(2) /* Always Running APIC Timer */ 331 #define CPUID_DSPM_PLN __BIT(4) /* Power Limit Notification */ 332 #define CPUID_DSPM_ECMD __BIT(5) /* Clock Modulation Extension */ 333 #define CPUID_DSPM_PTM __BIT(6) /* Package Level Thermal Management */ 334 #define CPUID_DSPM_HWP __BIT(7) /* HWP */ 335 #define CPUID_DSPM_HWP_NOTIFY __BIT(8) /* HWP Notification */ 336 #define CPUID_DSPM_HWP_ACTWIN __BIT(9) /* HWP Activity Window */ 337 #define CPUID_DSPM_HWP_EPP __BIT(10) /* HWP Energy Performance Preference */ 338 #define CPUID_DSPM_HWP_PLR __BIT(11) /* HWP Package Level Request */ 339 #define CPUID_DSPM_HDC __BIT(13) /* Hardware Duty Cycling */ 340 #define CPUID_DSPM_TBMT3 __BIT(14) /* Turbo Boost Max Technology 3.0 */ 341 #define CPUID_DSPM_HWP_CAP __BIT(15) /* HWP Capabilities */ 342 #define CPUID_DSPM_HWP_PECI __BIT(16) /* HWP PECI override */ 343 #define CPUID_DSPM_HWP_FLEX __BIT(17) /* Flexible HWP */ 344 #define CPUID_DSPM_HWP_FAST __BIT(18) /* Fast access for IA32_HWP_REQUEST */ 345 #define CPUID_DSPM_HFI __BIT(19) /* Hardware Feedback Interface */ 346 #define CPUID_DSPM_HWP_IGNIDL __BIT(20) /* Ignore Idle Logical Processor HWP */ 347 #define CPUID_DSPM_TD __BIT(23) /* Thread Director */ 348 #define CPUID_DSPM_THERMI_HFN __BIT(24) /* THERM_INTERRUPT MSR HFN bit */ 349 350 #define CPUID_DSPM_FLAGS "\20" \ 351 "\1" "DTS" "\2" "IDA" "\3" "ARAT" \ 352 "\5" "PLN" "\6" "ECMD" "\7" "PTM" "\10" "HWP" \ 353 "\11" "HWP_NOTIFY" "\12" "HWP_ACTWIN" "\13" "HWP_EPP" "\14" "HWP_PLR" \ 354 "\16" "HDC" "\17" "TBM3" "\20" "HWP_CAP" \ 355 "\21" "HWP_PECI" "\22" "HWP_FLEX" "\23" "HWP_FAST" "\24HFI" \ 356 "\25" "HWP_IGNIDL" "\30" "TD" \ 357 "\31" "THERMI_HFN" 358 359 /* %ecx */ 360 #define CPUID_DSPM_HWF __BIT(0) /* MSR_APERF/MSR_MPERF available */ 361 #define CPUID_DSPM_EPB __BIT(3) /* Energy Performance Bias */ 362 #define CPUID_DSPM_NTDC __BITS(15, 8) /* Number of Thread Director Classes */ 363 364 #define CPUID_DSPM_FLAGS1 "\177\20" \ 365 "b\0HWF\0" "b\3EPB\0" \ 366 "f\10\10NTDC\0" 367 368 /* 369 * Intel/AMD Structured Extended Feature. 370 * CPUID Fn0000_0007 371 * %ecx == 0: Subleaf 0 372 * %eax: The Maximum input value for supported subleaf. 373 * %ebx: Feature bits. 374 * %ecx: Feature bits. 375 * %edx: Feature bits. 376 * 377 * %ecx == 1: Structure Extendede Feature Enumeration Sub-leaf 378 * %eax: See below. 379 */ 380 381 /* %ecx = 0, %ebx */ 382 #define CPUID_SEF_FSGSBASE __BIT(0) /* {RD,WR}{FS,GS}BASE */ 383 #define CPUID_SEF_TSC_ADJUST __BIT(1) /* IA32_TSC_ADJUST MSR support */ 384 #define CPUID_SEF_SGX __BIT(2) /* Software Guard Extensions */ 385 #define CPUID_SEF_BMI1 __BIT(3) /* Advanced bit manipulation ext. 1st grp */ 386 #define CPUID_SEF_HLE __BIT(4) /* Hardware Lock Elision */ 387 #define CPUID_SEF_AVX2 __BIT(5) /* Advanced Vector Extensions 2 */ 388 #define CPUID_SEF_FDPEXONLY __BIT(6) /* x87FPU Data ptr updated only on x87exp */ 389 #define CPUID_SEF_SMEP __BIT(7) /* Supervisor-Mode Execution Prevention */ 390 #define CPUID_SEF_BMI2 __BIT(8) /* Advanced bit manipulation ext. 2nd grp */ 391 #define CPUID_SEF_ERMS __BIT(9) /* Enhanced REP MOVSB/STOSB */ 392 #define CPUID_SEF_INVPCID __BIT(10) /* INVPCID instruction */ 393 #define CPUID_SEF_RTM __BIT(11) /* Restricted Transactional Memory */ 394 #define CPUID_SEF_QM __BIT(12) /* Resource Director Technology Monitoring */ 395 #define CPUID_SEF_FPUCSDS __BIT(13) /* Deprecate FPU CS and FPU DS values */ 396 #define CPUID_SEF_MPX __BIT(14) /* Memory Protection Extensions */ 397 #define CPUID_SEF_PQE __BIT(15) /* Resource Director Technology Allocation */ 398 #define CPUID_SEF_AVX512F __BIT(16) /* AVX-512 Foundation */ 399 #define CPUID_SEF_AVX512DQ __BIT(17) /* AVX-512 Double/Quadword */ 400 #define CPUID_SEF_RDSEED __BIT(18) /* RDSEED instruction */ 401 #define CPUID_SEF_ADX __BIT(19) /* ADCX/ADOX instructions */ 402 #define CPUID_SEF_SMAP __BIT(20) /* Supervisor-Mode Access Prevention */ 403 #define CPUID_SEF_AVX512_IFMA __BIT(21) /* AVX-512 Integer Fused Multiply Add */ 404 /* Bit 22 was PCOMMIT */ 405 #define CPUID_SEF_CLFLUSHOPT __BIT(23) /* Cache Line FLUSH OPTimized */ 406 #define CPUID_SEF_CLWB __BIT(24) /* Cache Line Write Back */ 407 #define CPUID_SEF_PT __BIT(25) /* Processor Trace */ 408 #define CPUID_SEF_AVX512PF __BIT(26) /* AVX-512 PreFetch */ 409 #define CPUID_SEF_AVX512ER __BIT(27) /* AVX-512 Exponential and Reciprocal */ 410 #define CPUID_SEF_AVX512CD __BIT(28) /* AVX-512 Conflict Detection */ 411 #define CPUID_SEF_SHA __BIT(29) /* SHA Extensions */ 412 #define CPUID_SEF_AVX512BW __BIT(30) /* AVX-512 Byte and Word */ 413 #define CPUID_SEF_AVX512VL __BIT(31) /* AVX-512 Vector Length */ 414 415 #define CPUID_SEF_FLAGS "\20" \ 416 "\1" "FSGSBASE" "\2" "TSCADJUST" "\3" "SGX" "\4" "BMI1" \ 417 "\5" "HLE" "\6" "AVX2" "\7" "FDPEXONLY" "\10" "SMEP" \ 418 "\11" "BMI2" "\12" "ERMS" "\13" "INVPCID" "\14" "RTM" \ 419 "\15" "QM" "\16" "FPUCSDS" "\17" "MPX" "\20" "PQE" \ 420 "\21" "AVX512F" "\22" "AVX512DQ" "\23" "RDSEED" "\24" "ADX" \ 421 "\25" "SMAP" "\26" "AVX512_IFMA" "\30" "CLFLUSHOPT" \ 422 "\31" "CLWB" "\32" "PT" "\33" "AVX512PF" "\34" "AVX512ER" \ 423 "\35" "AVX512CD""\36" "SHA" "\37" "AVX512BW" "\40" "AVX512VL" 424 425 /* %ecx = 0, %ecx */ 426 #define CPUID_SEF_PREFETCHWT1 __BIT(0) /* PREFETCHWT1 instruction */ 427 #define CPUID_SEF_AVX512_VBMI __BIT(1) /* AVX-512 Vector Byte Manipulation */ 428 #define CPUID_SEF_UMIP __BIT(2) /* User-Mode Instruction prevention */ 429 #define CPUID_SEF_PKU __BIT(3) /* Protection Keys for User-mode pages */ 430 #define CPUID_SEF_OSPKE __BIT(4) /* OS has set CR4.PKE to ena. protec. keys */ 431 #define CPUID_SEF_WAITPKG __BIT(5) /* TPAUSE,UMONITOR,UMWAIT */ 432 #define CPUID_SEF_AVX512_VBMI2 __BIT(6) /* AVX-512 Vector Byte Manipulation 2 */ 433 #define CPUID_SEF_CET_SS __BIT(7) /* CET Shadow Stack */ 434 #define CPUID_SEF_GFNI __BIT(8) /* Galois Field instructions */ 435 #define CPUID_SEF_VAES __BIT(9) /* Vector AES instruction set */ 436 #define CPUID_SEF_VPCLMULQDQ __BIT(10) /* CLMUL instruction set */ 437 #define CPUID_SEF_AVX512_VNNI __BIT(11) /* Vector Neural Network Instruction */ 438 #define CPUID_SEF_AVX512_BITALG __BIT(12) /* BITALG instructions */ 439 #define CPUID_SEF_TME_EN __BIT(13) /* Total Memory Encryption */ 440 #define CPUID_SEF_AVX512_VPOPCNTDQ __BIT(14) /* Vector Population Count D/Q */ 441 #define CPUID_SEF_LA57 __BIT(16) /* 57bit linear addr & 5LVL paging */ 442 #define CPUID_SEF_MAWAU __BITS(21, 17) /* MAWAU for BND{LD,ST}X */ 443 #define CPUID_SEF_RDPID __BIT(22) /* RDPID and IA32_TSC_AUX */ 444 #define CPUID_SEF_KL __BIT(23) /* Key Locker */ 445 #define CPUID_SEF_CLDEMOTE __BIT(25) /* Cache line demote */ 446 #define CPUID_SEF_MOVDIRI __BIT(27) /* MOVDIRI instruction */ 447 #define CPUID_SEF_MOVDIR64B __BIT(28) /* MOVDIR64B instruction */ 448 #define CPUID_SEF_ENQCMD __BIT(29) /* Enqueue Stores */ 449 #define CPUID_SEF_SGXLC __BIT(30) /* SGX Launch Configuration */ 450 #define CPUID_SEF_PKS __BIT(31) /* Protection Keys for kern-mode pages */ 451 452 #define CPUID_SEF_FLAGS1 "\177\20" \ 453 "b\0PREFETCHWT1\0" "b\1AVX512_VBMI\0" "b\2UMIP\0" "b\3PKU\0" \ 454 "b\4OSPKE\0" "b\5WAITPKG\0" "b\6AVX512_VBMI2\0" "b\7CET_SS\0" \ 455 "b\10GFNI\0" "b\11VAES\0" "b\12VPCLMULQDQ\0" "b\13AVX512_VNNI\0"\ 456 "b\14AVX512_BITALG\0" "b\15TME_EN\0" "b\16AVX512_VPOPCNTDQ\0" \ 457 "b\20LA57\0" \ 458 "f\21\5MAWAU\0" "b\26RDPID\0" "b\27KL\0" \ 459 "b\31CLDEMOTE\0" "b\33MOVDIRI\0" \ 460 "b\34MOVDIR64B\0" "b\35ENQCMD\0" "b\36SGXLC\0" "b\37PKS\0" 461 462 /* %ecx = 0, %edx */ 463 #define CPUID_SEF_SGX_KEYS __BIT(1) /* Attestation support for SGX */ 464 #define CPUID_SEF_AVX512_4VNNIW __BIT(2) /* AVX512 4-reg Neural Network ins */ 465 #define CPUID_SEF_AVX512_4FMAPS __BIT(3) /* AVX512 4-reg Mult Accum Single precision */ 466 #define CPUID_SEF_FSRM __BIT(4) /* Fast Short Rep Move */ 467 #define CPUID_SEF_UINTR __BIT(5) /* User Interrupts */ 468 #define CPUID_SEF_AVX512_VP2INTERSECT __BIT(8) /* AVX512 VP2INTERSECT */ 469 #define CPUID_SEF_SRBDS_CTRL __BIT(9) /* IA32_MCU_OPT_CTRL */ 470 #define CPUID_SEF_MD_CLEAR __BIT(10) /* VERW clears CPU buffers */ 471 #define CPUID_SEF_RTM_ALWAYS_ABORT __BIT(11) /* XBEGIN immediately abort */ 472 #define CPUID_SEF_RTM_FORCE_ABORT __BIT(13) /* MSR_TSX_FORCE_ABORT bit 0 */ 473 #define CPUID_SEF_SERIALIZE __BIT(14) /* SERIALIZE instruction */ 474 #define CPUID_SEF_HYBRID __BIT(15) /* Hybrid part */ 475 #define CPUID_SEF_TSXLDTRK __BIT(16) /* TSX suspend load addr tracking */ 476 #define CPUID_SEF_PCONFIG __BIT(18) /* Platform CONFIGuration */ 477 #define CPUID_SEF_ARCH_LBR __BIT(19) /* Architectural LBR */ 478 #define CPUID_SEF_CET_IBT __BIT(20) /* CET Indirect Branch Tracking */ 479 #define CPUID_SEF_AMX_BF16 __BIT(22) /* AMX bfloat16 */ 480 #define CPUID_SEF_AVX512_FP16 __BIT(23) /* AVX512 FP16 */ 481 #define CPUID_SEF_AMX_TILE __BIT(24) /* Tile architecture */ 482 #define CPUID_SEF_AMX_INT8 __BIT(25) /* AMX 8bit interger */ 483 #define CPUID_SEF_IBRS __BIT(26) /* IBRS / IBPB Speculation Control */ 484 #define CPUID_SEF_STIBP __BIT(27) /* STIBP Speculation Control */ 485 #define CPUID_SEF_L1D_FLUSH __BIT(28) /* IA32_FLUSH_CMD MSR */ 486 #define CPUID_SEF_ARCH_CAP __BIT(29) /* IA32_ARCH_CAPABILITIES */ 487 #define CPUID_SEF_CORE_CAP __BIT(30) /* IA32_CORE_CAPABILITIES */ 488 #define CPUID_SEF_SSBD __BIT(31) /* Speculative Store Bypass Disable */ 489 490 #define CPUID_SEF_FLAGS2 "\20" \ 491 "\2SGX_KEYS" "\3AVX512_4VNNIW" "\4AVX512_4FMAPS" \ 492 "\5FSRM" "\6UINTR" \ 493 "\11VP2INTERSECT" "\12SRBDS_CTRL" "\13MD_CLEAR" "\14RTM_ALWAYS_ABORT" \ 494 "\16RTM_FORCE_ABORT" "\17SERIALIZE" "\20HYBRID" \ 495 "\21" "TSXLDTRK" "\23" "PCONFIG" "\24" "ARCH_LBR" \ 496 "\25CET_IBT" "\27AMX_BF16" "\30AVX512_FP16" \ 497 "\31AMX_TILE" "\32AMX_INT8" "\33IBRS" "\34STIBP" \ 498 "\35" "L1D_FLUSH" "\36" "ARCH_CAP" "\37CORE_CAP" "\40" "SSBD" 499 500 /* %ecx = 1, %eax */ 501 #define CPUID_SEF_AVXVNNI __BIT(4) /* AVX version of VNNI */ 502 #define CPUID_SEF_AVX512_BF16 __BIT(5) 503 #define CPUID_SEF_FZLRMS __BIT(10) /* fast zero-length REP MOVSB */ 504 #define CPUID_SEF_FSRSB __BIT(11) /* fast short REP STOSB */ 505 #define CPUID_SEF_FSRCS __BIT(12) /* fast short REP CMPSB, REP SCASB */ 506 #define CPUID_SEF_HRESET __BIT(22) /* HREST & IA32_HRESET_ENABLE MSR */ 507 #define CPUID_SEF_LAM __BIT(26) /* Linear Address Masking */ 508 509 #define CPUID_SEF1_FLAGS_A "\20" \ 510 "\5" "AVXVNNI" "\6" "AVX512_BF16" \ 511 "\13" "FZLRMS" "\14" "FSRSB" \ 512 "\15" "FSRCS" "\27" "HRESET" \ 513 "\31" "LAM" 514 515 /* %ecx = 1, %ebx */ 516 #define CPUID_SEF_INTEL_PPIN __BIT(0) /* IA32_PPIN & IA32_PPIN_CTL MSRs */ 517 518 #define CPUID_SEF1_FLAGS_B "\20" \ 519 "\1" "PPIN" 520 521 /* %ecx = 1, %edx */ 522 #define CPUID_SEF_CET_SSS __BIT(18) /* CET Supervisor Shadow Stack */ 523 524 #define CPUID_SEF1_FLAGS_D "\20" \ 525 "\23CET_SSS" 526 527 /* %ecx = 2, %edx */ 528 #define CPUID_SEF_PSFD __BIT(0) /* Fast Forwarding Predictor Dis. */ 529 #define CPUID_SEF_IPRED_CTRL __BIT(1) /* IPRED_DIS */ 530 #define CPUID_SEF_RRSBA_CTRL __BIT(2) /* RRSBA for CPL3 */ 531 #define CPUID_SEF_DDPD_U __BIT(3) /* Data Dependent Prefetcher */ 532 #define CPUID_SEF_BHI_CTRL __BIT(4) /* BHI_DIS_S */ 533 #define CPUID_SEF_MCDT_NO __BIT(5) /* !MXCSR Config Dependent Timing */ 534 535 #define CPUID_SEF2_FLAGS_D "\20" \ 536 "\1PSFD" "\2IPRED_CTRL" "\3RRSBA_CTRL" "\4DDPD_U" \ 537 "\5BHI_CTRL" "\6MCDT_NO" 538 539 /* 540 * Intel CPUID Architectural Performance Monitoring. 541 * CPUID Fn0000000a 542 * 543 * See also src/usr.sbin/tprof/arch/tprof_x86.c 544 */ 545 546 /* %eax */ 547 #define CPUID_PERF_VERSION __BITS(7, 0) /* Version ID */ 548 #define CPUID_PERF_NGPPC __BITS(15, 8) /* Num of G.P. perf counter */ 549 #define CPUID_PERF_NBWGPPC __BITS(23, 16) /* Bit width of G.P. perfcnt */ 550 #define CPUID_PERF_BVECLEN __BITS(31, 24) /* Length of EBX bit vector */ 551 552 #define CPUID_PERF_FLAGS0 "\177\20" \ 553 "f\0\10VERSION\0" "f\10\10GPCounter\0" \ 554 "f\20\10GPBitwidth\0" "f\30\10Vectorlen\0" 555 556 /* %ebx */ 557 #define CPUID_PERF_CORECYCL __BIT(0) /* No core cycle */ 558 #define CPUID_PERF_INSTRETRY __BIT(1) /* No instruction retried */ 559 #define CPUID_PERF_REFCYCL __BIT(2) /* No reference cycles */ 560 #define CPUID_PERF_LLCREF __BIT(3) /* No LLCache reference */ 561 #define CPUID_PERF_LLCMISS __BIT(4) /* No LLCache miss */ 562 #define CPUID_PERF_BRINSRETR __BIT(5) /* No branch inst. retried */ 563 #define CPUID_PERF_BRMISPRRETR __BIT(6) /* No branch mispredict retry */ 564 #define CPUID_PERF_TOPDOWNSLOT __BIT(7) /* No top-down slots */ 565 566 #define CPUID_PERF_FLAGS1 "\177\20" \ 567 "b\0CORECYCL\0" "b\1INST\0" "b\2REFCYCL\0" "b\3LLCREF\0" \ 568 "b\4LLCMISS\0" "b\5BRINST\0" "b\6BRMISPR\0" "b\7TOPDOWNSLOT\0" 569 570 /* %ecx */ 571 572 #define CPUID_PERF_FLAGS2 "\177\20" \ 573 "b\0INST\0" "b\1CLK_CORETHREAD\0" "b\2CLK_REF_TSC\0" "b\3TOPDOWNSLOT\0" 574 575 /* %edx */ 576 #define CPUID_PERF_NFFPC __BITS(4, 0) /* Num of fixed-funct perfcnt */ 577 #define CPUID_PERF_NBWFFPC __BITS(12, 5) /* Bit width of fixed-func pc */ 578 #define CPUID_PERF_ANYTHREADDEPR __BIT(15) /* Any Thread deprecation */ 579 580 #define CPUID_PERF_FLAGS3 "\177\20" \ 581 "f\0\5FixedFunc\0" "f\5\10FFBitwidth\0" "b\17ANYTHREADDEPR\0" 582 583 /* 584 * Intel/AMD CPUID Extended Topology Enumeration. 585 * CPUID Fn0000000b 586 * %ecx == level number 587 * %eax: See below. 588 * %ebx: Number of logical processors at this level. 589 * %ecx: See below. 590 * %edx: x2APIC ID of the current logical processor. 591 */ 592 /* %eax */ 593 #define CPUID_TOP_SHIFTNUM __BITS(4, 0) /* Topology ID shift value */ 594 /* %ecx */ 595 #define CPUID_TOP_LVLNUM __BITS(7, 0) /* Level number */ 596 #define CPUID_TOP_LVLTYPE __BITS(15, 8) /* Level type */ 597 #define CPUID_TOP_LVLTYPE_INVAL 0 /* Invalid */ 598 #define CPUID_TOP_LVLTYPE_SMT 1 /* SMT */ 599 #define CPUID_TOP_LVLTYPE_CORE 2 /* Core */ 600 601 /* 602 * Intel/AMD CPUID Processor extended state Enumeration. 603 * CPUID Fn0000000d 604 * 605 * %ecx == 0: supported features info: 606 * %eax: Valid bits of lower 32bits of XCR0 607 * %ebx: Maximum save area size for features enabled in XCR0 608 * %ecx: Maximum save area size for all cpu features 609 * %edx: Valid bits of upper 32bits of XCR0 610 * 611 * %ecx == 1: 612 * %eax: See below 613 * %ebx: Save area size for features enabled by XCR0 | IA32_XSS 614 * %ecx: Valid bits of lower 32bits of IA32_XSS 615 * %edx: Valid bits of upper 32bits of IA32_XSS 616 * 617 * %ecx >= 2: Save area details for XCR0 bit n 618 * %eax: size of save area for this feature 619 * %ebx: offset of save area for this feature 620 * %ecx, %edx: reserved 621 * All of %eax, %ebx, %ecx and %edx are zero for unsupported features. 622 */ 623 624 /* %ecx = 1, %eax */ 625 #define CPUID_PES1_XSAVEOPT __BIT(0) /* xsaveopt instruction */ 626 #define CPUID_PES1_XSAVEC __BIT(1) /* xsavec & compacted XRSTOR */ 627 #define CPUID_PES1_XGETBV __BIT(2) /* xgetbv with ECX = 1 */ 628 #define CPUID_PES1_XSAVES __BIT(3) /* xsaves/xrstors, IA32_XSS */ 629 #define CPUID_PES1_XFD __BIT(4) /* eXtened Feature Disable */ 630 631 #define CPUID_PES1_FLAGS "\20" \ 632 "\1XSAVEOPT" "\2XSAVEC" "\3XGETBV" "\4XSAVES" \ 633 "\5XFD" 634 635 /* 636 * Intel Deterministic Address Translation Parameter. 637 * CPUID Fn0000_0018 638 */ 639 640 /* %ecx=0 %eax __BITS(31, 0): the maximum input value of supported sub-leaf */ 641 642 /* %ebx */ 643 #define CPUID_DATP_PGSIZE __BITS(3, 0) /* page size */ 644 #define CPUID_DATP_PGSIZE_4KB __BIT(0) /* 4KB page support */ 645 #define CPUID_DATP_PGSIZE_2MB __BIT(1) /* 2MB page support */ 646 #define CPUID_DATP_PGSIZE_4MB __BIT(2) /* 4MB page support */ 647 #define CPUID_DATP_PGSIZE_1GB __BIT(3) /* 1GB page support */ 648 #define CPUID_DATP_PARTITIONING __BITS(10, 8) /* Partitioning */ 649 #define CPUID_DATP_WAYS __BITS(31, 16) /* Ways of associativity */ 650 651 /* Number of sets: %ecx */ 652 653 /* %edx */ 654 #define CPUID_DATP_TCTYPE __BITS(4, 0) /* Translation Cache type */ 655 #define CPUID_DATP_TCTYPE_N 0 /* NULL (not valid) */ 656 #define CPUID_DATP_TCTYPE_D 1 /* Data TLB */ 657 #define CPUID_DATP_TCTYPE_I 2 /* Instruction TLB */ 658 #define CPUID_DATP_TCTYPE_U 3 /* Unified TLB */ 659 #define CPUID_DATP_TCTYPE_L 4 /* Load only TLB */ 660 #define CPUID_DATP_TCTYPE_S 5 /* Store only TLB */ 661 #define CPUID_DATP_TCLEVEL __BITS(7, 5) /* TLB level (start at 1) */ 662 #define CPUID_DATP_FULLASSOC __BIT(8) /* Full associative */ 663 #define CPUID_DATP_SHARING __BITS(25, 14) /* sharing */ 664 665 /* 666 * Intel Native Model ID Information Enumeration. 667 * CPUID Fn0000_001a 668 */ 669 /* %eax */ 670 #define CPUID_HYBRID_NATIVEID __BITS(23, 0) /* Native model ID */ 671 #define CPUID_HYBRID_CORETYPE __BITS(31, 24) /* Core type */ 672 #define CPUID_HYBRID_CORETYPE_ATOM 0x20 /* Atom */ 673 #define CPUID_HYBRID_CORETYPE_CORE 0x40 /* Core */ 674 675 /* 676 * Intel Tile Information 677 * CPUID Fn0000_001d 678 * %ecx == 0: Main leaf 679 * %eax: max_palette 680 * %ecx == 1: Tile Palette1 Sub-leaf 681 * Tile palette 1 682 */ 683 684 /* %ecx */ 685 #define CPUID_TILE_P1_TOTAL_B __BITS(15, 0) 686 #define CPUID_TILE_P1_B_PERTILE __BITS(31, 16) 687 #define CPUID_TILE_P1_B_PERLOW __BITS(15, 0) 688 #define CPUID_TILE_P1_MAXNAMES __BITS(31, 16) 689 #define CPUID_TILE_P1_MAXROWS __BITS(15, 0) 690 691 /* 692 * Intel TMUL Information 693 * CPUID Fn0000_001e 694 */ 695 696 /* %ebx */ 697 #define CPUID_TMUL_MAXK __BITS(7, 0) /* Rows or columns */ 698 #define CPUID_TMUL_MAXN __BITS(23, 8) /* Column bytes */ 699 700 /* 701 * Intel extended features. 702 * CPUID Fn80000001 703 */ 704 /* %edx */ 705 #define CPUID_SYSCALL __BIT(11) /* SYSCALL/SYSRET */ 706 #define CPUID_XD __BIT(20) /* Execute Disable (like CPUID_NOX) */ 707 #define CPUID_PAGE1GB __BIT(26) /* 1GB Large Page Support */ 708 #define CPUID_RDTSCP __BIT(27) /* Read TSC Pair Instruction */ 709 #define CPUID_EM64T __BIT(29) /* Intel EM64T */ 710 711 #define CPUID_INTEL_EXT_FLAGS "\20" \ 712 "\14" "SYSCALL/SYSRET" "\25" "XD" "\33" "P1GB" \ 713 "\34" "RDTSCP" "\36" "EM64T" 714 715 /* %ecx */ 716 #define CPUID_LAHF __BIT(0) /* LAHF/SAHF in IA-32e mode, 64bit sub*/ 717 /* __BIT(5) */ /* LZCNT. Same as AMD's CPUID_ABM */ 718 #define CPUID_PREFETCHW __BIT(8) /* PREFETCHW */ 719 720 #define CPUID_INTEL_FLAGS4 "\20" \ 721 "\1" "LAHF" "\02" "B01" "\03" "B02" \ 722 "\06" "LZCNT" \ 723 "\11" "PREFETCHW" 724 725 726 /* 727 * AMD/VIA extended features. 728 * CPUID Fn80000001 729 */ 730 /* %edx */ 731 /* CPUID_SYSCALL SYSCALL/SYSRET */ 732 #define CPUID_MPC 0x00080000 /* Multiprocessing Capable */ 733 #define CPUID_NOX 0x00100000 /* No Execute Page Protection */ 734 #define CPUID_MMXX 0x00400000 /* AMD MMX Extensions */ 735 /* CPUID_MMX MMX supported */ 736 /* CPUID_FXSR fast FP/MMX save/restore */ 737 #define CPUID_FFXSR 0x02000000 /* FXSAVE/FXSTOR Extensions */ 738 /* CPUID_PAGE1GB 1GB Large Page Support */ 739 /* CPUID_RDTSCP Read TSC Pair Instruction */ 740 /* CPUID_EM64T Long mode */ 741 #define CPUID_3DNOW2 0x40000000 /* 3DNow! Instruction Extension */ 742 #define CPUID_3DNOW 0x80000000 /* 3DNow! Instructions */ 743 744 #define CPUID_EXT_FLAGS "\20" \ 745 "\14" "SYSCALL/SYSRET" \ 746 "\24" "MPC" \ 747 "\25" "NOX" "\27" "MMXX" "\30" "MMX" \ 748 "\31" "FXSR" "\32" "FFXSR" "\33" "P1GB" "\34" "RDTSCP" \ 749 "\36" "LONG" "\37" "3DNOW2" "\40" "3DNOW" 750 751 /* %ecx (AMD) */ 752 /* CPUID_LAHF LAHF/SAHF instruction */ 753 #define CPUID_CMPLEGACY __BIT(1) /* Compare Legacy */ 754 #define CPUID_SVM __BIT(2) /* Secure Virtual Machine */ 755 #define CPUID_EAPIC __BIT(3) /* Extended APIC space */ 756 #define CPUID_ALTMOVCR0 __BIT(4) /* Lock Mov Cr0 */ 757 #define CPUID_ABM __BIT(5) /* LZCNT instruction */ 758 #define CPUID_SSE4A __BIT(6) /* SSE4A instruction set */ 759 #define CPUID_MISALIGNSSE __BIT(7) /* Misaligned SSE */ 760 #define CPUID_3DNOWPF __BIT(8) /* 3DNow Prefetch */ 761 #define CPUID_OSVW __BIT(9) /* OS visible workarounds */ 762 #define CPUID_IBS __BIT(10) /* Instruction Based Sampling */ 763 #define CPUID_XOP __BIT(11) /* XOP instruction set */ 764 #define CPUID_SKINIT __BIT(12) /* SKINIT */ 765 #define CPUID_WDT __BIT(13) /* watchdog timer support */ 766 #define CPUID_LWP __BIT(15) /* Light Weight Profiling */ 767 #define CPUID_FMA4 __BIT(16) /* FMA4 instructions */ 768 #define CPUID_TCE __BIT(17) /* Translation cache Extension */ 769 #define CPUID_NODEID __BIT(19) /* NodeID MSR available */ 770 #define CPUID_TBM __BIT(21) /* TBM instructions */ 771 #define CPUID_TOPOEXT __BIT(22) /* cpuid Topology Extension */ 772 #define CPUID_PCEC __BIT(23) /* Perf Ctr Ext Core */ 773 #define CPUID_PCENB __BIT(24) /* Perf Ctr Ext NB */ 774 #define CPUID_SPM __BIT(25) /* Stream Perf Mon */ 775 #define CPUID_DBE __BIT(26) /* Data Breakpoint Extension */ 776 #define CPUID_PTSC __BIT(27) /* PerfTsc */ 777 #define CPUID_L2IPERFC __BIT(28) /* L2I performance counter Extension */ 778 #define CPUID_MWAITX __BIT(29) /* MWAITX/MONITORX support */ 779 #define CPUID_ADDRMASKEXT __BIT(30) /* Breakpoint Addressing Mask ext. */ 780 781 #define CPUID_AMD_FLAGS4 "\20" \ 782 "\1" "LAHF" "\2" "CMPLEGACY" "\3" "SVM" "\4" "EAPIC" \ 783 "\5" "ALTMOVCR0" "\6" "LZCNT" "\7" "SSE4A" "\10" "MISALIGNSSE" \ 784 "\11" "3DNOWPREFETCH" \ 785 "\12" "OSVW" "\13" "IBS" "\14" "XOP" \ 786 "\15" "SKINIT" "\16" "WDT" "\17" "B14" "\20" "LWP" \ 787 "\21" "FMA4" "\22" "TCE" "\23" "B18" "\24" "NodeID" \ 788 "\25" "B20" "\26" "TBM" "\27" "TopoExt" "\30" "PCExtC" \ 789 "\31" "PCExtNB" "\32" "StrmPM" "\33" "DBExt" "\34" "PerfTsc" \ 790 "\35" "L2IPERFC" "\36" "MWAITX" "\37" "AddrMaskExt" "\40" "B31" 791 792 /* 793 * Advanced Power Management and RAS. 794 * CPUID Fn8000_0007 795 * 796 * Only ITSC is for both Intel and AMD. Others are only for AMD. 797 * 798 * %ebx: RAS capabilities. See below. 799 * %ecx: Processor Power Monitoring Interface. 800 * %edx: See below. 801 * 802 */ 803 /* %ebx */ 804 #define CPUID_RAS_OVFL_RECOV __BIT(0) /* MCA Overflow Recovery */ 805 #define CPUID_RAS_SUCCOR __BIT(1) /* Sw UnCorr. err. COntainment & Recovery */ 806 #define CPUID_RAS_MCAX __BIT(3) /* MCA Extension */ 807 808 #define CPUID_RAS_FLAGS "\20" \ 809 "\1OVFL_RECOV" "\2SUCCOR" "\4" "MCAX" 810 811 /* %edx */ 812 #define CPUID_APM_TS __BIT(0) /* Temperature Sensor */ 813 #define CPUID_APM_FID __BIT(1) /* Frequency ID control */ 814 #define CPUID_APM_VID __BIT(2) /* Voltage ID control */ 815 #define CPUID_APM_TTP __BIT(3) /* THERMTRIP (PCI F3xE4 register) */ 816 #define CPUID_APM_HTC __BIT(4) /* Hardware thermal control (HTC) */ 817 #define CPUID_APM_STC __BIT(5) /* Software thermal control (STC) */ 818 #define CPUID_APM_100 __BIT(6) /* 100MHz multiplier control */ 819 #define CPUID_APM_HWP __BIT(7) /* HW P-State control */ 820 #define CPUID_APM_ITSC __BIT(8) /* Invariant TSC */ 821 #define CPUID_APM_CPB __BIT(9) /* Core Performance Boost */ 822 #define CPUID_APM_EFF __BIT(10) /* Effective Frequency (read-only) */ 823 #define CPUID_APM_PROCFI __BIT(11) /* Processor Feedback Interface */ 824 #define CPUID_APM_PROCPR __BIT(12) /* Processor Power Reporting */ 825 #define CPUID_APM_CONNSTBY __BIT(13) /* Connected Standby */ 826 #define CPUID_APM_RAPL __BIT(14) /* Running Average Power Limit */ 827 828 #define CPUID_APM_FLAGS "\20" \ 829 "\1" "TS" "\2" "FID" "\3" "VID" "\4" "TTP" \ 830 "\5" "HTC" "\6" "STC" "\7" "100" "\10" "HWP" \ 831 "\11" "ITSC" "\12" "CPB" "\13" "EffFreq" "\14" "PROCFI" \ 832 "\15" "PROCPR" "\16" "CONNSTBY" "\17" "RAPL" 833 834 /* 835 * AMD Processor Capacity Parameters and Extended Features. 836 * CPUID Fn8000_0008 837 * %eax: Long Mode Size Identifiers 838 * %ebx: Extended Feature Identifiers 839 * %ecx: Size Identifiers 840 * %edx: RDPRU Register Identifier Range 841 */ 842 843 /* %ebx */ 844 #define CPUID_CAPEX_CLZERO __BIT(0) /* CLZERO instruction */ 845 #define CPUID_CAPEX_IRPERF __BIT(1) /* InstRetCntMsr */ 846 #define CPUID_CAPEX_XSAVEERPTR __BIT(2) /* RstrFpErrPtrs by XRSTOR */ 847 #define CPUID_CAPEX_RDPRU __BIT(4) /* RDPRU instruction */ 848 #define CPUID_CAPEX_MBE __BIT(6) /* Memory Bandwidth Enforcement */ 849 #define CPUID_CAPEX_MCOMMIT __BIT(8) /* MCOMMIT instruction */ 850 #define CPUID_CAPEX_WBNOINVD __BIT(9) /* WBNOINVD instruction */ 851 #define CPUID_CAPEX_IBPB __BIT(12) /* Speculation Control IBPB */ 852 #define CPUID_CAPEX_INT_WBINVD __BIT(13) /* Interruptable WB[NO]INVD */ 853 #define CPUID_CAPEX_IBRS __BIT(14) /* Speculation Control IBRS */ 854 #define CPUID_CAPEX_STIBP __BIT(15) /* Speculation Control STIBP */ 855 #define CPUID_CAPEX_IBRS_ALWAYSON __BIT(16) /* IBRS always on mode */ 856 #define CPUID_CAPEX_STIBP_ALWAYSON __BIT(17) /* STIBP always on mode */ 857 #define CPUID_CAPEX_PREFER_IBRS __BIT(18) /* IBRS preferred */ 858 #define CPUID_CAPEX_IBRS_SAMEMODE __BIT(19) /* IBRS same speculation limits */ 859 #define CPUID_CAPEX_EFER_LSMSLE_UN __BIT(20) /* EFER.LMSLE is unsupported */ 860 #define CPUID_CAPEX_AMD_PPIN __BIT(23) /* Protected Processor Inventory Number */ 861 #define CPUID_CAPEX_SSBD __BIT(24) /* Speculation Control SSBD */ 862 #define CPUID_CAPEX_VIRT_SSBD __BIT(25) /* Virt Spec Control SSBD */ 863 #define CPUID_CAPEX_SSB_NO __BIT(26) /* SSBD not required */ 864 #define CPUID_CAPEX_CPPC __BIT(27) /* Collaborative Processor Perf. Control */ 865 #define CPUID_CAPEX_PSFD __BIT(28) /* Predictive Store Forward Dis */ 866 #define CPUID_CAPEX_BTC_NO __BIT(29) /* Branch Type Confusion NO */ 867 868 #define CPUID_CAPEX_FLAGS "\20" \ 869 "\1CLZERO" "\2IRPERF" "\3XSAVEERPTR" \ 870 "\5RDPRU" "\7MBE" \ 871 "\11MCOMMIT" "\12WBNOINVD" "\13B10" \ 872 "\15IBPB" "\16INT_WBINVD" "\17IBRS" "\20STIBP" \ 873 "\21IBRS_ALWAYSON" "\22STIBP_ALWAYSON" "\23PREFER_IBRS" \ 874 "\24IBRS_SAMEMODE" \ 875 "\25EFER_LSMSLE_UN" "\30PPIN" \ 876 "\31SSBD" "\32VIRT_SSBD" "\33SSB_NO" "\34CPPC" \ 877 "\35PSFD" "\36BTC_NO" 878 879 /* %ecx */ 880 #define CPUID_CAPEX_PerfTscSize __BITS(17,16) /* Perf. tstamp counter size */ 881 #define CPUID_CAPEX_ApicIdSize __BITS(15,12) /* APIC ID Size */ 882 #define CPUID_CAPEX_NC __BITS(7,0) /* Number of threads - 1 */ 883 884 /* 885 * AMD SVM Revision and Feature. 886 * CPUID Fn8000_000a 887 */ 888 889 /* %eax: SVM revision */ 890 #define CPUID_AMD_SVM_REV __BITS(7,0) 891 892 /* %edx: SVM features */ 893 #define CPUID_AMD_SVM_NP __BIT(0) /* Nested Paging */ 894 #define CPUID_AMD_SVM_LbrVirt __BIT(1) /* LBR virtualization */ 895 #define CPUID_AMD_SVM_SVML __BIT(2) /* SVM Lock */ 896 #define CPUID_AMD_SVM_NRIPS __BIT(3) /* NRIP Save on #VMEXIT */ 897 #define CPUID_AMD_SVM_TSCRateCtrl __BIT(4) /* MSR-based TSC rate ctrl */ 898 #define CPUID_AMD_SVM_VMCBCleanBits __BIT(5) /* VMCB Clean Bits support */ 899 #define CPUID_AMD_SVM_FlushByASID __BIT(6) /* Flush by ASID */ 900 #define CPUID_AMD_SVM_DecodeAssist __BIT(7) /* Decode Assists support */ 901 #define CPUID_AMD_SVM_PauseFilter __BIT(10) /* PAUSE intercept filter */ 902 #define CPUID_AMD_SVM_PFThreshold __BIT(12) /* PAUSE filter threshold */ 903 #define CPUID_AMD_SVM_AVIC __BIT(13) /* Advanced Virt. Intr. Ctrl */ 904 #define CPUID_AMD_SVM_V_VMSAVE_VMLOAD __BIT(15) /* Virtual VM{SAVE/LOAD} */ 905 #define CPUID_AMD_SVM_vGIF __BIT(16) /* Virtualized GIF */ 906 #define CPUID_AMD_SVM_GMET __BIT(17) /* Guest Mode Execution Trap */ 907 #define CPUID_AMD_SVM_X2AVIC __BIT(18) /* Virt. Intr. Ctrl 4 x2APIC */ 908 #define CPUID_AMD_SVM_SSSCHECK __BIT(19) /* Shadow Stack restrictions */ 909 #define CPUID_AMD_SVM_SPEC_CTRL __BIT(20) /* SPEC_CTRL virtualization */ 910 #define CPUID_AMD_SVM_ROGPT __BIT(21) /* Read-Only Guest PTable */ 911 #define CPUID_AMD_SVM_HOST_MCE_OVERRIDE __BIT(23) /* #MC intercept */ 912 #define CPUID_AMD_SVM_TLBICTL __BIT(24) /* TLB Intercept Control */ 913 #define CPUID_AMD_SVM_VNMI __BIT(25) /* NMI Virtualization */ 914 #define CPUID_AMD_SVM_IBSVIRT __BIT(26) /* IBS Virtualization */ 915 916 #define CPUID_AMD_SVM_FLAGS "\20" \ 917 "\1" "NP" "\2" "LbrVirt" "\3" "SVML" "\4" "NRIPS" \ 918 "\5" "TSCRate" "\6" "VMCBCleanBits" \ 919 "\7" "FlushByASID" "\10" "DecodeAssist" \ 920 "\11" "B08" "\12" "B09" "\13" "PauseFilter" "\14" "B11" \ 921 "\15" "PFThreshold" "\16" "AVIC" "\17" "B14" \ 922 "\20" "V_VMSAVE_VMLOAD" \ 923 "\21" "VGIF" "\22" "GMET" "\23x2AVIC" "\24SSSCHECK" \ 924 "\25" "SPEC_CTRL" "\26" "ROGPT" "\30HOST_MCE_OVERRIDE" \ 925 "\31" "TLBICTL" "\32VNMI" "\33IBSVIRT" "\34B27" \ 926 "\35B28" 927 928 /* 929 * AMD Instruction-Based Sampling Capabilities. 930 * CPUID Fn8000_001b 931 */ 932 /* %eax */ 933 #define CPUID_IBS_FFV __BIT(0) /* Feature Flags Valid */ 934 #define CPUID_IBS_FETCHSUM __BIT(1) /* Fetch Sampling */ 935 #define CPUID_IBS_OPSAM __BIT(2) /* execution SAMpling */ 936 #define CPUID_IBS_RDWROPCNT __BIT(3) /* Read Write of Op Counter */ 937 #define CPUID_IBS_OPCNT __BIT(4) /* OP CouNTing mode */ 938 #define CPUID_IBS_BRNTRGT __BIT(5) /* Branch Target */ 939 #define CPUID_IBS_OPCNTEXT __BIT(6) /* OpCurCnt and OpMaxCnt extended */ 940 #define CPUID_IBS_RIPINVALIDCHK __BIT(7) /* Invalid RIP indication */ 941 #define CPUID_IBS_OPBRNFUSE __BIT(8) /* Fused branch micro-op indicate */ 942 #define CPUID_IBS_FETCHCTLEXTD __BIT(9) /* IC_IBS_EXTD_CTL MSR */ 943 #define CPUID_IBS_OPDATA4 __BIT(10) /* IBS op data 4 MSR */ 944 #define CPUID_IBS_L3MISSFILT __BIT(11) /* L3 Miss Filtering */ 945 946 #define CPUID_IBS_FLAGS "\20" \ 947 "\1IBSFFV" "\2FetchSam" "\3OpSam" "\4RdWrOpCnt" \ 948 "\5OpCnt" "\6BrnTrgt" "\7OpCntExt" "\10RipInvalidChk" \ 949 "\11OpBrnFuse" "\12IbsFetchCtlExtd" "\13IbsOpData4" \ 950 "\14IbsL3MissFiltering" 951 952 /* 953 * AMD Cache Topology Information. 954 * CPUID Fn8000_001d 955 * It's almost the same as Intel Deterministic Cache Parameter Leaf(0x04) 956 * except the following: 957 * No Cores/package (%eax bit 31..26) 958 * No Complex cache indexing (%edx bit 2) 959 */ 960 961 /* 962 * AMD Processor Topology Information. 963 * CPUID Fn8000_001e 964 * %eax: Extended APIC ID. 965 * %ebx: Core Identifiers. 966 * %ecx: Node Identifiers. 967 */ 968 969 /* %ebx */ 970 #define CPUID_AMD_PROCT_COREID __BITS(7,0) /* Core ID */ 971 #define CPUID_AMD_PROCT_THREADS_PER_CORE __BITS(15,8) /* Threads/Core - 1 */ 972 973 /* %ecx */ 974 #define CPUID_AMD_PROCT_NODEID __BITS(7,0) /* Node ID */ 975 #define CPUID_AMD_PROCT_NODE_PER_PROCESSOR __BITS(10,8) /* Node/Processor -1 */ 976 977 /* 978 * AMD Encrypted Memory Capabilities. 979 * CPUID Fn8000_001f 980 * %eax: flags 981 * %ebx: 5-0: Cbit Position 982 * 11-6: PhysAddrReduction 983 * 15-12: NumVMPL 984 * %ecx: 31-0: NumEncryptedGuests 985 * %edx: 31-0: MinSevNoEsAsid 986 */ 987 #define CPUID_AMD_ENCMEM_SME __BIT(0) /* Secure Memory Encryption */ 988 #define CPUID_AMD_ENCMEM_SEV __BIT(1) /* Secure Encrypted Virtualiz. */ 989 #define CPUID_AMD_ENCMEM_PGFLMSR __BIT(2) /* Page Flush MSR */ 990 #define CPUID_AMD_ENCMEM_SEVES __BIT(3) /* SEV Encrypted State */ 991 #define CPUID_AMD_ENCMEM_SEV_SNP __BIT(4) /* Secure Nested Paging */ 992 #define CPUID_AMD_ENCMEM_VMPL __BIT(5) /* Virtual Machine Privilege Lvl */ 993 #define CPUID_AMD_ENCMEM_RPMQUERY __BIT(6) /* RMPQUERY instruction */ 994 #define CPUID_AMD_ENCMEM_VMPLSSS __BIT(7) /* VMPL Secure Shadow Stack */ 995 #define CPUID_AMD_ENCMEM_SECTSC __BIT(8) /* Secure TSC */ 996 #define CPUID_AMD_ENCMEM_TSCAUX_V __BIT(9) /* TSC AUX Virtualization */ 997 #define CPUID_AMD_ENCMEM_HECC __BIT(10) /* HW Enf Cache Coh across enc dom */ 998 #define CPUID_AMD_ENCMEM_64BH __BIT(11) /* 64Bit Host */ 999 #define CPUID_AMD_ENCMEM_RSTRINJ __BIT(12) /* Restricted Injection */ 1000 #define CPUID_AMD_ENCMEM_ALTINJ __BIT(13) /* Alternate Injection */ 1001 #define CPUID_AMD_ENCMEM_DBGSWAP __BIT(14) /* Debug Swap */ 1002 #define CPUID_AMD_ENCMEM_PREVHOSTIBS __BIT(15) /* Prevent Host IBS */ 1003 #define CPUID_AMD_ENCMEM_VTE __BIT(16) /* Virtual Transparent Encryption */ 1004 1005 #define CPUID_AMD_ENCMEM_VMGEXITP __BIT(17) /* VMGEXIT Parameter */ 1006 #define CPUID_AMD_ENCMEM_VIRTTOM __BIT(18) /* Virtual TOM MSR */ 1007 #define CPUID_AMD_ENCMEM_IBSVGUEST __BIT(19) /* IBS Virt. for SEV-ES guest */ 1008 #define CPUID_AMD_ENCMEM_VMSA_REGPROT __BIT(24) /* VmsaRegProt */ 1009 #define CPUID_AMD_ENCMEM_SMTPROTECT __BIT(25) /* SMT Protection */ 1010 #define CPUID_AMD_ENCMEM_SVSM_COMMPAGE __BIT(28) /* SVSM Communication Page */ 1011 #define CPUID_AMD_ENCMEM_NESTED_VSMP __BIT(29) /* VIRT_{RMPUPDATE,PSMASH} */ 1012 1013 #define CPUID_AMD_ENCMEM_FLAGS "\20" \ 1014 "\1" "SME" "\2" "SEV" "\3" "PageFlushMsr" "\4" "SEV-ES" \ 1015 "\5" "SEV-SNP" "\6" "VMPL" "\7RMPQUERY" "\10VmplSSS" \ 1016 "\11SecureTSC" "\12TscAuxVirt" "\13HwEnfCacheCoh" "\14" "64BitHost" \ 1017 "\15" "RSTRINJ" "\16" "ALTINJ" "\17" "DebugSwap" "\20PreventHostIbs" \ 1018 "\21VTE" "\22VmgexitParam" "\23VirtualTomMsr" "\24IbsVirtGuest" \ 1019 "\31VmsaRegProt" "\32SmtProtection" \ 1020 "\35SvsmCommPageMSR" "\36NestedVirtSnpMsr" 1021 1022 /* 1023 * AMD Extended Features 2. 1024 * CPUID Fn8000_0021 1025 */ 1026 1027 /* %eax */ 1028 #define CPUID_AMDEXT2_NONESTEDDBP __BIT(0) /* No nested data breakpoints */ 1029 #define CPUID_AMDEXT2_LFENCESERIAL __BIT(2) /* LFENCE always serializing */ 1030 #define CPUID_AMDEXT2_SMMPGCFGLCK __BIT(3) /* SMM Paging configuration lock */ 1031 #define CPUID_AMDEXT2_NULLSELCLRB __BIT(6) /* Null segment selector clr base */ 1032 #define CPUID_AMDEXT2_UPADDRIGN __BIT(7) /* Upper Address Ignore */ 1033 #define CPUID_AMDEXT2_AUTOIBRS __BIT(8) /* Automatic IBRS */ 1034 #define CPUID_AMDEXT2_NOSMMCTL __BIT(9) /* SMM_CTL MSR is not supported */ 1035 #define CPUID_AMDEXT2_PREFETCHCTL __BIT(13) /* Prefetch control MSR */ 1036 #define CPUID_AMDEXT2_CPUIDUSRDIS __BIT(17) /* CPUID dis. for non-priv. soft */ 1037 1038 #define CPUID_AMDEXT2_FLAGS "\20" \ 1039 "\1NoNestedDataBp" "\3LfenceAlwaysSerialize" "\4SmmPgCfgLock" \ 1040 "\7NullSelectClearsBase" "\10UpperAddressIgnore" \ 1041 "\11AutomaticIBRS" "\12NoSmmCtlMSR" \ 1042 "\16PrefetchCtlMSR" \ 1043 "\22CpuidUserDis" 1044 1045 /* 1046 * AMD Extended Performance Monitoring and Debug 1047 * CPUID Fn8000_0022 1048 */ 1049 1050 /* %eax */ 1051 #define CPUID_AXPERF_PERFMONV2 __BIT(0) /* Version 2 */ 1052 #define CPUID_AXPERF_LBRSTACK __BIT(1) /* Last Branch Record Stack */ 1053 #define CPUID_AXPERF_LBRPMCFREEZE __BIT(2) /* Freezing LBR and PMC */ 1054 1055 #define CPUID_AXPERF_FLAGS "\20" \ 1056 "\1PerfMonV2" "\2LbrStack" "\3LbrAndPmcFreeze" 1057 1058 /* %ebx */ 1059 #define CPUID_AXPERF_NCPC __BITS(3, 0) /* Num of Core PMC counters */ 1060 #define CPUID_AXPERF_NLBRSTACK __BITS(9, 4) /* Num of LBR Stack entries */ 1061 #define CPUID_AXPERF_NNBPC __BITS(15, 10) /* Num of Northbridge PMC */ 1062 1063 /* 1064 * Centaur Extended Feature flags. 1065 * CPUID FnC000_0001 1066 */ 1067 #define CPUID_VIA_HAS_RNG __BIT(2) /* Random number generator */ 1068 #define CPUID_VIA_DO_RNG __BIT(3) 1069 #define CPUID_VIA_HAS_ACE __BIT(6) /* AES Encryption */ 1070 #define CPUID_VIA_DO_ACE __BIT(7) 1071 #define CPUID_VIA_HAS_ACE2 __BIT(8) /* AES+CTR instructions */ 1072 #define CPUID_VIA_DO_ACE2 __BIT(9) 1073 #define CPUID_VIA_HAS_PHE __BIT(10) /* SHA1+SHA256 HMAC */ 1074 #define CPUID_VIA_DO_PHE __BIT(11) 1075 #define CPUID_VIA_HAS_PMM __BIT(12) /* RSA Instructions */ 1076 #define CPUID_VIA_DO_PMM __BIT(13) 1077 1078 #define CPUID_FLAGS_PADLOCK "\20" \ 1079 "\3" "RNG" "\7" "AES" "\11" "AES/CTR" "\13" "SHA1/SHA256" \ 1080 "\15" "RSA" 1081 1082 /* 1083 * Model-Specific Registers 1084 */ 1085 #define MSR_TSC 0x010 1086 #define MSR_IA32_PLATFORM_ID 0x017 1087 #define MSR_APICBASE 0x01b 1088 #define APICBASE_BSP 0x00000100 /* boot processor */ 1089 #define APICBASE_EXTD 0x00000400 /* x2APIC mode */ 1090 #define APICBASE_EN 0x00000800 /* software enable */ 1091 /* 1092 * APICBASE_PHYSADDR is actually variable-sized on some CPUs. But we're 1093 * only interested in the initial value, which is guaranteed to fit the 1094 * first 32 bits. So this macro is fine. 1095 */ 1096 #define APICBASE_PHYSADDR 0xfffff000 /* physical address */ 1097 #define MSR_EBL_CR_POWERON 0x02a 1098 #define MSR_EBC_FREQUENCY_ID 0x02c /* PIV only */ 1099 #define MSR_IA32_SPEC_CTRL 0x048 1100 #define IA32_SPEC_CTRL_IBRS 0x01 1101 #define IA32_SPEC_CTRL_STIBP 0x02 1102 #define IA32_SPEC_CTRL_SSBD 0x04 1103 #define MSR_IA32_PRED_CMD 0x049 1104 #define IA32_PRED_CMD_IBPB 0x01 1105 #define MSR_BIOS_UPDT_TRIG 0x079 1106 #define MSR_BIOS_SIGN 0x08b 1107 #define MSR_PERFCTR0 0x0c1 1108 #define MSR_PERFCTR1 0x0c2 1109 #define MSR_FSB_FREQ 0x0cd /* Core Duo/Solo only */ 1110 #define MSR_MPERF 0x0e7 1111 #define MSR_APERF 0x0e8 1112 #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ 1113 #define MSR_MTRRcap 0x0fe 1114 #define MSR_IA32_ARCH_CAPABILITIES 0x10a 1115 #define IA32_ARCH_RDCL_NO 0x01 1116 #define IA32_ARCH_IBRS_ALL 0x02 1117 #define IA32_ARCH_RSBA 0x04 1118 #define IA32_ARCH_SKIP_L1DFL_VMENTRY 0x08 1119 #define IA32_ARCH_SSB_NO 0x10 1120 #define IA32_ARCH_MDS_NO 0x20 1121 #define IA32_ARCH_IF_PSCHANGE_MC_NO 0x40 1122 #define IA32_ARCH_TSX_CTRL 0x80 1123 #define IA32_ARCH_TAA_NO 0x100 1124 #define MSR_IA32_FLUSH_CMD 0x10b 1125 #define IA32_FLUSH_CMD_L1D_FLUSH 0x01 1126 #define MSR_TSX_FORCE_ABORT 0x10f 1127 #define MSR_IA32_TSX_CTRL 0x122 1128 #define IA32_TSX_CTRL_RTM_DISABLE __BIT(0) 1129 #define IA32_TSX_CTRL_TSX_CPUID_CLEAR __BIT(1) 1130 #define MSR_SYSENTER_CS 0x174 /* PII+ only */ 1131 #define MSR_SYSENTER_ESP 0x175 /* PII+ only */ 1132 #define MSR_SYSENTER_EIP 0x176 /* PII+ only */ 1133 #define MSR_MCG_CAP 0x179 1134 #define MSR_MCG_STATUS 0x17a 1135 #define MSR_MCG_CTL 0x17b 1136 #define MSR_EVNTSEL0 0x186 1137 #define MSR_EVNTSEL1 0x187 1138 #define MSR_PERF_STATUS 0x198 /* Pentium M */ 1139 #define MSR_PERF_CTL 0x199 /* Pentium M */ 1140 #define MSR_THERM_CONTROL 0x19a 1141 #define MSR_THERM_INTERRUPT 0x19b 1142 #define MSR_THERM_STATUS 0x19c 1143 #define MSR_THERM2_CTL 0x19d /* Pentium M */ 1144 #define MSR_MISC_ENABLE 0x1a0 1145 #define IA32_MISC_MWAIT_EN 0x40000 1146 #define MSR_TEMPERATURE_TARGET 0x1a2 1147 #define MSR_DEBUGCTLMSR 0x1d9 1148 #define MSR_LASTBRANCHFROMIP 0x1db 1149 #define MSR_LASTBRANCHTOIP 0x1dc 1150 #define MSR_LASTINTFROMIP 0x1dd 1151 #define MSR_LASTINTTOIP 0x1de 1152 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 1153 #define MSR_MTRRphysBase0 0x200 1154 #define MSR_MTRRphysMask0 0x201 1155 #define MSR_MTRRphysBase1 0x202 1156 #define MSR_MTRRphysMask1 0x203 1157 #define MSR_MTRRphysBase2 0x204 1158 #define MSR_MTRRphysMask2 0x205 1159 #define MSR_MTRRphysBase3 0x206 1160 #define MSR_MTRRphysMask3 0x207 1161 #define MSR_MTRRphysBase4 0x208 1162 #define MSR_MTRRphysMask4 0x209 1163 #define MSR_MTRRphysBase5 0x20a 1164 #define MSR_MTRRphysMask5 0x20b 1165 #define MSR_MTRRphysBase6 0x20c 1166 #define MSR_MTRRphysMask6 0x20d 1167 #define MSR_MTRRphysBase7 0x20e 1168 #define MSR_MTRRphysMask7 0x20f 1169 #define MSR_MTRRphysBase8 0x210 1170 #define MSR_MTRRphysMask8 0x211 1171 #define MSR_MTRRphysBase9 0x212 1172 #define MSR_MTRRphysMask9 0x213 1173 #define MSR_MTRRphysBase10 0x214 1174 #define MSR_MTRRphysMask10 0x215 1175 #define MSR_MTRRphysBase11 0x216 1176 #define MSR_MTRRphysMask11 0x217 1177 #define MSR_MTRRphysBase12 0x218 1178 #define MSR_MTRRphysMask12 0x219 1179 #define MSR_MTRRphysBase13 0x21a 1180 #define MSR_MTRRphysMask13 0x21b 1181 #define MSR_MTRRphysBase14 0x21c 1182 #define MSR_MTRRphysMask14 0x21d 1183 #define MSR_MTRRphysBase15 0x21e 1184 #define MSR_MTRRphysMask15 0x21f 1185 #define MSR_MTRRfix64K_00000 0x250 1186 #define MSR_MTRRfix16K_80000 0x258 1187 #define MSR_MTRRfix16K_A0000 0x259 1188 #define MSR_MTRRfix4K_C0000 0x268 1189 #define MSR_MTRRfix4K_C8000 0x269 1190 #define MSR_MTRRfix4K_D0000 0x26a 1191 #define MSR_MTRRfix4K_D8000 0x26b 1192 #define MSR_MTRRfix4K_E0000 0x26c 1193 #define MSR_MTRRfix4K_E8000 0x26d 1194 #define MSR_MTRRfix4K_F0000 0x26e 1195 #define MSR_MTRRfix4K_F8000 0x26f 1196 #define MSR_CR_PAT 0x277 1197 #define MSR_MTRRdefType 0x2ff 1198 #define MSR_MC0_CTL 0x400 1199 #define MSR_MC0_STATUS 0x401 1200 #define MSR_MC0_ADDR 0x402 1201 #define MSR_MC0_MISC 0x403 1202 #define MSR_MC1_CTL 0x404 1203 #define MSR_MC1_STATUS 0x405 1204 #define MSR_MC1_ADDR 0x406 1205 #define MSR_MC1_MISC 0x407 1206 #define MSR_MC2_CTL 0x408 1207 #define MSR_MC2_STATUS 0x409 1208 #define MSR_MC2_ADDR 0x40a 1209 #define MSR_MC2_MISC 0x40b 1210 #define MSR_MC3_CTL 0x40c 1211 #define MSR_MC3_STATUS 0x40d 1212 #define MSR_MC3_ADDR 0x40e 1213 #define MSR_MC3_MISC 0x40f 1214 #define MSR_MC4_CTL 0x410 1215 #define MSR_MC4_STATUS 0x411 1216 #define MSR_MC4_ADDR 0x412 1217 #define MSR_MC4_MISC 0x413 1218 /* 0x480 - 0x490 VMX */ 1219 #define MSR_X2APIC_BASE 0x800 /* 0x800 - 0xBFF */ 1220 #define MSR_X2APIC_ID 0x002 /* x2APIC ID. (RO) */ 1221 #define MSR_X2APIC_VERS 0x003 /* Version. (RO) */ 1222 #define MSR_X2APIC_TPRI 0x008 /* Task Prio. (RW) */ 1223 #define MSR_X2APIC_PPRI 0x00a /* Processor prio. (RO) */ 1224 #define MSR_X2APIC_EOI 0x00b /* End Int. (W) */ 1225 #define MSR_X2APIC_LDR 0x00d /* Logical dest. (RO) */ 1226 #define MSR_X2APIC_SVR 0x00f /* Spurious intvec (RW) */ 1227 #define MSR_X2APIC_ISR 0x010 /* In-Service Status (RO) */ 1228 #define MSR_X2APIC_TMR 0x018 /* Trigger Mode (RO) */ 1229 #define MSR_X2APIC_IRR 0x020 /* Interrupt Req (RO) */ 1230 #define MSR_X2APIC_ESR 0x028 /* Err status. (RW) */ 1231 #define MSR_X2APIC_LVT_CMCI 0x02f /* LVT CMCI (RW) */ 1232 #define MSR_X2APIC_ICRLO 0x030 /* Int. cmd. (RW64) */ 1233 #define MSR_X2APIC_LVTT 0x032 /* Loc.vec.(timer) (RW) */ 1234 #define MSR_X2APIC_TMINT 0x033 /* Loc.vec (Thermal) (RW) */ 1235 #define MSR_X2APIC_PCINT 0x034 /* Loc.vec (Perf Mon) (RW) */ 1236 #define MSR_X2APIC_LVINT0 0x035 /* Loc.vec (LINT0) (RW) */ 1237 #define MSR_X2APIC_LVINT1 0x036 /* Loc.vec (LINT1) (RW) */ 1238 #define MSR_X2APIC_LVERR 0x037 /* Loc.vec (ERROR) (RW) */ 1239 #define MSR_X2APIC_ICR_TIMER 0x038 /* Initial count (RW) */ 1240 #define MSR_X2APIC_CCR_TIMER 0x039 /* Current count (RO) */ 1241 #define MSR_X2APIC_DCR_TIMER 0x03e /* Divisor config (RW) */ 1242 #define MSR_X2APIC_SELF_IPI 0x03f /* SELF IPI (W) */ 1243 1244 /* 1245 * VIA "Nehemiah" MSRs 1246 */ 1247 #define MSR_VIA_RNG 0x0000110b 1248 #define MSR_VIA_RNG_ENABLE 0x00000040 1249 #define MSR_VIA_RNG_NOISE_MASK 0x00000300 1250 #define MSR_VIA_RNG_NOISE_A 0x00000000 1251 #define MSR_VIA_RNG_NOISE_B 0x00000100 1252 #define MSR_VIA_RNG_2NOISE 0x00000300 1253 #define MSR_VIA_ACE 0x00001107 1254 #define VIA_ACE_ALTINST 0x00000001 1255 #define VIA_ACE_ECX8 0x00000002 1256 #define VIA_ACE_ENABLE 0x10000000 1257 1258 /* 1259 * VIA "Eden" MSRs 1260 */ 1261 #define MSR_VIA_FCR MSR_VIA_ACE 1262 1263 /* 1264 * AMD K6/K7 MSRs. 1265 */ 1266 #define MSR_K6_UWCCR 0xc0000085 1267 #define MSR_K7_EVNTSEL0 0xc0010000 1268 #define MSR_K7_EVNTSEL1 0xc0010001 1269 #define MSR_K7_EVNTSEL2 0xc0010002 1270 #define MSR_K7_EVNTSEL3 0xc0010003 1271 #define MSR_K7_PERFCTR0 0xc0010004 1272 #define MSR_K7_PERFCTR1 0xc0010005 1273 #define MSR_K7_PERFCTR2 0xc0010006 1274 #define MSR_K7_PERFCTR3 0xc0010007 1275 1276 /* 1277 * AMD K8 (Opteron) MSRs. 1278 */ 1279 #define MSR_SYSCFG 0xc0010010 1280 1281 #define MSR_EFER 0xc0000080 /* Extended feature enable */ 1282 #define EFER_SCE 0x00000001 /* SYSCALL extension */ 1283 #define EFER_LME 0x00000100 /* Long Mode Enable */ 1284 #define EFER_LMA 0x00000400 /* Long Mode Active */ 1285 #define EFER_NXE 0x00000800 /* No-Execute Enabled */ 1286 #define EFER_SVME 0x00001000 /* Secure Virtual Machine En. */ 1287 #define EFER_LMSLE 0x00002000 /* Long Mode Segment Limit E. */ 1288 #define EFER_FFXSR 0x00004000 /* Fast FXSAVE/FXRSTOR En. */ 1289 #define EFER_TCE 0x00008000 /* Translation Cache Ext. */ 1290 1291 #define MSR_STAR 0xc0000081 /* 32 bit syscall gate addr */ 1292 #define MSR_LSTAR 0xc0000082 /* 64 bit syscall gate addr */ 1293 #define MSR_CSTAR 0xc0000083 /* compat syscall gate addr */ 1294 #define MSR_SFMASK 0xc0000084 /* flags to clear on syscall */ 1295 1296 #define MSR_FSBASE 0xc0000100 /* 64bit offset for fs: */ 1297 #define MSR_GSBASE 0xc0000101 /* 64bit offset for gs: */ 1298 #define MSR_KERNELGSBASE 0xc0000102 /* storage for swapgs ins */ 1299 1300 #define MSR_VMCR 0xc0010114 /* Virtual Machine Control Register */ 1301 #define VMCR_DPD 0x00000001 /* Debug port disable */ 1302 #define VMCR_RINIT 0x00000002 /* intercept init */ 1303 #define VMCR_DISA20 0x00000004 /* Disable A20 masking */ 1304 #define VMCR_LOCK 0x00000008 /* SVM Lock */ 1305 #define VMCR_SVMED 0x00000010 /* SVME Disable */ 1306 #define MSR_SVMLOCK 0xc0010118 /* SVM Lock key */ 1307 1308 /* 1309 * These require a 'passcode' for access. See cpufunc.h. 1310 */ 1311 #define MSR_HWCR 0xc0010015 1312 #define HWCR_TLBCACHEDIS 0x00000008 1313 #define HWCR_FFDIS 0x00000040 1314 1315 #define MSR_NB_CFG 0xc001001f 1316 #define NB_CFG_DISIOREQLOCK 0x0000000000000008ULL 1317 #define NB_CFG_DISDATMSK 0x0000001000000000ULL 1318 #define NB_CFG_INITAPICCPUIDLO (1ULL << 54) 1319 1320 #define MSR_LS_CFG 0xc0011020 1321 #define LS_CFG_ERRATA_1033 __BIT(4) 1322 #define LS_CFG_ERRATA_793 __BIT(15) 1323 #define LS_CFG_ERRATA_1095 __BIT(57) 1324 #define LS_CFG_DIS_LS2_SQUISH 0x02000000 1325 #define LS_CFG_DIS_SSB_F15H 0x0040000000000000ULL 1326 #define LS_CFG_DIS_SSB_F16H 0x0000000200000000ULL 1327 #define LS_CFG_DIS_SSB_F17H 0x0000000000000400ULL 1328 1329 #define MSR_IC_CFG 0xc0011021 1330 #define IC_CFG_DIS_SEQ_PREFETCH 0x00000800 1331 #define IC_CFG_DIS_IND 0x00004000 1332 #define IC_CFG_ERRATA_776 __BIT(26) 1333 1334 #define MSR_DC_CFG 0xc0011022 1335 #define DC_CFG_DIS_CNV_WC_SSO 0x00000008 1336 #define DC_CFG_DIS_SMC_CHK_BUF 0x00000400 1337 #define DC_CFG_ERRATA_261 0x01000000 1338 1339 #define MSR_BU_CFG 0xc0011023 1340 #define BU_CFG_ERRATA_298 0x0000000000000002ULL 1341 #define BU_CFG_ERRATA_254 0x0000000000200000ULL 1342 #define BU_CFG_ERRATA_309 0x0000000000800000ULL 1343 #define BU_CFG_THRL2IDXCMPDIS 0x0000080000000000ULL 1344 #define BU_CFG_WBPFSMCCHKDIS 0x0000200000000000ULL 1345 #define BU_CFG_WBENHWSBDIS 0x0001000000000000ULL 1346 1347 #define MSR_FP_CFG 0xc0011028 1348 #define FP_CFG_ERRATA_1049 __BIT(4) 1349 1350 #define MSR_DE_CFG 0xc0011029 1351 #define DE_CFG_ERRATA_721 0x00000001 1352 #define DE_CFG_LFENCE_SERIALIZE __BIT(1) 1353 #define DE_CFG_ERRATA_1021 __BIT(13) 1354 1355 #define MSR_LS_CFG2 0xc001102d 1356 #define LS_CFG2_ERRATA_1091 __BIT(34) 1357 1358 /* AMD Family10h MSRs */ 1359 #define MSR_OSVW_ID_LENGTH 0xc0010140 1360 #define MSR_OSVW_STATUS 0xc0010141 1361 #define MSR_UCODE_AMD_PATCHLEVEL 0x0000008b 1362 #define MSR_UCODE_AMD_PATCHLOADER 0xc0010020 1363 1364 /* X86 MSRs */ 1365 #define MSR_RDTSCP_AUX 0xc0000103 1366 1367 /* 1368 * Constants related to MTRRs 1369 */ 1370 #define MTRR_N64K 8 /* numbers of fixed-size entries */ 1371 #define MTRR_N16K 16 1372 #define MTRR_N4K 64 1373 1374 /* 1375 * the following four 3-byte registers control the non-cacheable regions. 1376 * These registers must be written as three separate bytes. 1377 * 1378 * NCRx+0: A31-A24 of starting address 1379 * NCRx+1: A23-A16 of starting address 1380 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 1381 * 1382 * The non-cacheable region's starting address must be aligned to the 1383 * size indicated by the NCR_SIZE_xx field. 1384 */ 1385 #define NCR1 0xc4 1386 #define NCR2 0xc7 1387 #define NCR3 0xca 1388 #define NCR4 0xcd 1389 1390 #define NCR_SIZE_0K 0 1391 #define NCR_SIZE_4K 1 1392 #define NCR_SIZE_8K 2 1393 #define NCR_SIZE_16K 3 1394 #define NCR_SIZE_32K 4 1395 #define NCR_SIZE_64K 5 1396 #define NCR_SIZE_128K 6 1397 #define NCR_SIZE_256K 7 1398 #define NCR_SIZE_512K 8 1399 #define NCR_SIZE_1M 9 1400 #define NCR_SIZE_2M 10 1401 #define NCR_SIZE_4M 11 1402 #define NCR_SIZE_8M 12 1403 #define NCR_SIZE_16M 13 1404 #define NCR_SIZE_32M 14 1405 #define NCR_SIZE_4G 15 1406 1407 /* 1408 * Performance monitor events. 1409 * 1410 * Note that 586-class and 686-class CPUs have different performance 1411 * monitors available, and they are accessed differently: 1412 * 1413 * 686-class: `rdpmc' instruction 1414 * 586-class: `rdmsr' instruction, CESR MSR 1415 * 1416 * The descriptions of these events are too lengthy to include here. 1417 * See Appendix A of "Intel Architecture Software Developer's 1418 * Manual, Volume 3: System Programming" for more information. 1419 */ 1420 1421 /* 1422 * 586-class CESR MSR format. Lower 16 bits is CTR0, upper 16 bits 1423 * is CTR1. 1424 */ 1425 1426 #define PMC5_CESR_EVENT 0x003f 1427 #define PMC5_CESR_OS 0x0040 1428 #define PMC5_CESR_USR 0x0080 1429 #define PMC5_CESR_E 0x0100 1430 #define PMC5_CESR_P 0x0200 1431 1432 #define PMC5_DATA_READ 0x00 1433 #define PMC5_DATA_WRITE 0x01 1434 #define PMC5_DATA_TLB_MISS 0x02 1435 #define PMC5_DATA_READ_MISS 0x03 1436 #define PMC5_DATA_WRITE_MISS 0x04 1437 #define PMC5_WRITE_M_E 0x05 1438 #define PMC5_DATA_LINES_WBACK 0x06 1439 #define PMC5_DATA_CACHE_SNOOP 0x07 1440 #define PMC5_DATA_CACHE_SNOOP_HIT 0x08 1441 #define PMC5_MEM_ACCESS_BOTH_PIPES 0x09 1442 #define PMC5_BANK_CONFLICTS 0x0a 1443 #define PMC5_MISALIGNED_DATA 0x0b 1444 #define PMC5_INST_READ 0x0c 1445 #define PMC5_INST_TLB_MISS 0x0d 1446 #define PMC5_INST_CACHE_MISS 0x0e 1447 #define PMC5_SEGMENT_REG_LOAD 0x0f 1448 #define PMC5_BRANCHES 0x12 1449 #define PMC5_BTB_HITS 0x13 1450 #define PMC5_BRANCH_TAKEN 0x14 1451 #define PMC5_PIPELINE_FLUSH 0x15 1452 #define PMC5_INST_EXECUTED 0x16 1453 #define PMC5_INST_EXECUTED_V_PIPE 0x17 1454 #define PMC5_BUS_UTILIZATION 0x18 1455 #define PMC5_WRITE_BACKUP_STALL 0x19 1456 #define PMC5_DATA_READ_STALL 0x1a 1457 #define PMC5_WRITE_E_M_STALL 0x1b 1458 #define PMC5_LOCKED_BUS 0x1c 1459 #define PMC5_IO_CYCLE 0x1d 1460 #define PMC5_NONCACHE_MEM_READ 0x1e 1461 #define PMC5_AGI_STALL 0x1f 1462 #define PMC5_FLOPS 0x22 1463 #define PMC5_BP0_MATCH 0x23 1464 #define PMC5_BP1_MATCH 0x24 1465 #define PMC5_BP2_MATCH 0x25 1466 #define PMC5_BP3_MATCH 0x26 1467 #define PMC5_HARDWARE_INTR 0x27 1468 #define PMC5_DATA_RW 0x28 1469 #define PMC5_DATA_RW_MISS 0x29 1470 1471 /* 1472 * 686-class Event Selector MSR format. 1473 */ 1474 1475 #define PMC6_EVTSEL_EVENT 0x000000ff 1476 #define PMC6_EVTSEL_UNIT 0x0000ff00 1477 #define PMC6_EVTSEL_UNIT_SHIFT 8 1478 #define PMC6_EVTSEL_USR (1 << 16) 1479 #define PMC6_EVTSEL_OS (1 << 17) 1480 #define PMC6_EVTSEL_E (1 << 18) 1481 #define PMC6_EVTSEL_PC (1 << 19) 1482 #define PMC6_EVTSEL_INT (1 << 20) 1483 #define PMC6_EVTSEL_EN (1 << 22) /* PerfEvtSel0 only */ 1484 #define PMC6_EVTSEL_INV (1 << 23) 1485 #define PMC6_EVTSEL_COUNTER_MASK 0xff000000 1486 #define PMC6_EVTSEL_COUNTER_MASK_SHIFT 24 1487 1488 /* Data Cache Unit */ 1489 #define PMC6_DATA_MEM_REFS 0x43 1490 #define PMC6_DCU_LINES_IN 0x45 1491 #define PMC6_DCU_M_LINES_IN 0x46 1492 #define PMC6_DCU_M_LINES_OUT 0x47 1493 #define PMC6_DCU_MISS_OUTSTANDING 0x48 1494 1495 /* Instruction Fetch Unit */ 1496 #define PMC6_IFU_IFETCH 0x80 1497 #define PMC6_IFU_IFETCH_MISS 0x81 1498 #define PMC6_ITLB_MISS 0x85 1499 #define PMC6_IFU_MEM_STALL 0x86 1500 #define PMC6_ILD_STALL 0x87 1501 1502 /* L2 Cache */ 1503 #define PMC6_L2_IFETCH 0x28 1504 #define PMC6_L2_LD 0x29 1505 #define PMC6_L2_ST 0x2a 1506 #define PMC6_L2_LINES_IN 0x24 1507 #define PMC6_L2_LINES_OUT 0x26 1508 #define PMC6_L2_M_LINES_INM 0x25 1509 #define PMC6_L2_M_LINES_OUTM 0x27 1510 #define PMC6_L2_RQSTS 0x2e 1511 #define PMC6_L2_ADS 0x21 1512 #define PMC6_L2_DBUS_BUSY 0x22 1513 #define PMC6_L2_DBUS_BUSY_RD 0x23 1514 1515 /* External Bus Logic */ 1516 #define PMC6_BUS_DRDY_CLOCKS 0x62 1517 #define PMC6_BUS_LOCK_CLOCKS 0x63 1518 #define PMC6_BUS_REQ_OUTSTANDING 0x60 1519 #define PMC6_BUS_TRAN_BRD 0x65 1520 #define PMC6_BUS_TRAN_RFO 0x66 1521 #define PMC6_BUS_TRANS_WB 0x67 1522 #define PMC6_BUS_TRAN_IFETCH 0x68 1523 #define PMC6_BUS_TRAN_INVAL 0x69 1524 #define PMC6_BUS_TRAN_PWR 0x6a 1525 #define PMC6_BUS_TRANS_P 0x6b 1526 #define PMC6_BUS_TRANS_IO 0x6c 1527 #define PMC6_BUS_TRAN_DEF 0x6d 1528 #define PMC6_BUS_TRAN_BURST 0x6e 1529 #define PMC6_BUS_TRAN_ANY 0x70 1530 #define PMC6_BUS_TRAN_MEM 0x6f 1531 #define PMC6_BUS_DATA_RCV 0x64 1532 #define PMC6_BUS_BNR_DRV 0x61 1533 #define PMC6_BUS_HIT_DRV 0x7a 1534 #define PMC6_BUS_HITM_DRDV 0x7b 1535 #define PMC6_BUS_SNOOP_STALL 0x7e 1536 1537 /* Floating Point Unit */ 1538 #define PMC6_FLOPS 0xc1 1539 #define PMC6_FP_COMP_OPS_EXE 0x10 1540 #define PMC6_FP_ASSIST 0x11 1541 #define PMC6_MUL 0x12 1542 #define PMC6_DIV 0x12 1543 #define PMC6_CYCLES_DIV_BUSY 0x14 1544 1545 /* Memory Ordering */ 1546 #define PMC6_LD_BLOCKS 0x03 1547 #define PMC6_SB_DRAINS 0x04 1548 #define PMC6_MISALIGN_MEM_REF 0x05 1549 #define PMC6_EMON_KNI_PREF_DISPATCHED 0x07 /* P-III only */ 1550 #define PMC6_EMON_KNI_PREF_MISS 0x4b /* P-III only */ 1551 1552 /* Instruction Decoding and Retirement */ 1553 #define PMC6_INST_RETIRED 0xc0 1554 #define PMC6_UOPS_RETIRED 0xc2 1555 #define PMC6_INST_DECODED 0xd0 1556 #define PMC6_EMON_KNI_INST_RETIRED 0xd8 1557 #define PMC6_EMON_KNI_COMP_INST_RET 0xd9 1558 1559 /* Interrupts */ 1560 #define PMC6_HW_INT_RX 0xc8 1561 #define PMC6_CYCLES_INT_MASKED 0xc6 1562 #define PMC6_CYCLES_INT_PENDING_AND_MASKED 0xc7 1563 1564 /* Branches */ 1565 #define PMC6_BR_INST_RETIRED 0xc4 1566 #define PMC6_BR_MISS_PRED_RETIRED 0xc5 1567 #define PMC6_BR_TAKEN_RETIRED 0xc9 1568 #define PMC6_BR_MISS_PRED_TAKEN_RET 0xca 1569 #define PMC6_BR_INST_DECODED 0xe0 1570 #define PMC6_BTB_MISSES 0xe2 1571 #define PMC6_BR_BOGUS 0xe4 1572 #define PMC6_BACLEARS 0xe6 1573 1574 /* Stalls */ 1575 #define PMC6_RESOURCE_STALLS 0xa2 1576 #define PMC6_PARTIAL_RAT_STALLS 0xd2 1577 1578 /* Segment Register Loads */ 1579 #define PMC6_SEGMENT_REG_LOADS 0x06 1580 1581 /* Clocks */ 1582 #define PMC6_CPU_CLK_UNHALTED 0x79 1583 1584 /* MMX Unit */ 1585 #define PMC6_MMX_INSTR_EXEC 0xb0 /* Celeron, P-II, P-IIX only */ 1586 #define PMC6_MMX_SAT_INSTR_EXEC 0xb1 /* P-II and P-III only */ 1587 #define PMC6_MMX_UOPS_EXEC 0xb2 /* P-II and P-III only */ 1588 #define PMC6_MMX_INSTR_TYPE_EXEC 0xb3 /* P-II and P-III only */ 1589 #define PMC6_FP_MMX_TRANS 0xcc /* P-II and P-III only */ 1590 #define PMC6_MMX_ASSIST 0xcd /* P-II and P-III only */ 1591 #define PMC6_MMX_INSTR_RET 0xc3 /* P-II only */ 1592 1593 /* Segment Register Renaming */ 1594 #define PMC6_SEG_RENAME_STALLS 0xd4 /* P-II and P-III only */ 1595 #define PMC6_SEG_REG_RENAMES 0xd5 /* P-II and P-III only */ 1596 #define PMC6_RET_SEG_RENAMES 0xd6 /* P-II and P-III only */ 1597 1598 /* 1599 * AMD K7. [Doc: 22007K.pdf, Feb 2002] 1600 */ 1601 /* Event Selector MSR format */ 1602 #define K7_EVTSEL_EVENT 0x000000ff 1603 #define K7_EVTSEL_UNIT 0x0000ff00 1604 #define K7_EVTSEL_UNIT_SHIFT 8 1605 #define K7_EVTSEL_USR __BIT(16) 1606 #define K7_EVTSEL_OS __BIT(17) 1607 #define K7_EVTSEL_E __BIT(18) 1608 #define K7_EVTSEL_PC __BIT(19) 1609 #define K7_EVTSEL_INT __BIT(20) 1610 #define K7_EVTSEL_EN __BIT(22) 1611 #define K7_EVTSEL_INV __BIT(23) 1612 #define K7_EVTSEL_COUNTER_MASK 0xff000000 1613 #define K7_EVTSEL_COUNTER_MASK_SHIFT 24 1614 /* Data Cache Unit */ 1615 #define K7_DATA_CACHE_ACCESS 0x40 1616 #define K7_DATA_CACHE_MISS 0x41 1617 #define K7_DATA_CACHE_REFILL 0x42 1618 #define K7_DATA_CACHE_REFILL_SYSTEM 0x43 1619 #define K7_DATA_CACHE_WBACK 0x44 1620 #define K7_L1_DTLB_MISS 0x45 1621 #define K7_L2_DTLB_MISS 0x46 1622 #define K7_MISALIGNED_DATA_REF 0x47 1623 /* Instruction Fetch Unit */ 1624 #define K7_IFU_IFETCH 0x80 1625 #define K7_IFU_IFETCH_MISS 0x81 1626 #define K7_IFU_REFILL_FROM_L2 0x82 1627 #define K7_IFU_REFILL_FROM_SYSTEM 0x83 1628 #define K7_L1_ITLB_MISS 0x84 1629 #define K7_L2_ITLB_MISS 0x85 1630 /* Retired */ 1631 #define K7_RETIRED_INST 0xc0 1632 #define K7_RETIRED_OPS 0xc1 1633 #define K7_RETIRED_BRANCH 0xc2 1634 #define K7_RETIRED_BRANCH_MISPREDICTED 0xc3 1635 #define K7_RETIRED_TAKEN_BRANCH 0xc4 1636 #define K7_RETIRED_TAKEN_BRANCH_MISPREDICTED 0xc5 1637 #define K7_RETIRED_FAR_CONTROL_TRANSFER 0xc6 1638 #define K7_RETIRED_RESYNC_BRANCH 0xc7 1639 /* Interrupts */ 1640 #define K7_CYCLES_INT_MASKED 0xcd 1641 #define K7_CYCLES_INT_PENDING_AND_MASKED 0xce 1642 #define K7_HW_INTR_RECV 0xcf 1643 1644 /* 1645 * AMD 10h family PMCs. [Doc: 31116.pdf, Jan 2013] 1646 */ 1647 /* Register MSRs */ 1648 #define MSR_F10H_EVNTSEL0 0xc0010000 1649 #define MSR_F10H_EVNTSEL1 0xc0010001 1650 #define MSR_F10H_EVNTSEL2 0xc0010002 1651 #define MSR_F10H_EVNTSEL3 0xc0010003 1652 #define MSR_F10H_PERFCTR0 0xc0010004 1653 #define MSR_F10H_PERFCTR1 0xc0010005 1654 #define MSR_F10H_PERFCTR2 0xc0010006 1655 #define MSR_F10H_PERFCTR3 0xc0010007 1656 /* Event Selector MSR format */ 1657 #define F10H_EVTSEL_EVENT_MASK 0x000F000000FF 1658 #define F10H_EVTSEL_EVENT_SHIFT_LOW 0 1659 #define F10H_EVTSEL_EVENT_SHIFT_HIGH 32 1660 #define F10H_EVTSEL_UNIT_MASK 0x0000FF00 1661 #define F10H_EVTSEL_UNIT_SHIFT 8 1662 #define F10H_EVTSEL_USR __BIT(16) 1663 #define F10H_EVTSEL_OS __BIT(17) 1664 #define F10H_EVTSEL_EDGE __BIT(18) 1665 #define F10H_EVTSEL_RSVD1 __BIT(19) 1666 #define F10H_EVTSEL_INT __BIT(20) 1667 #define F10H_EVTSEL_RSVD2 __BIT(21) 1668 #define F10H_EVTSEL_EN __BIT(22) 1669 #define F10H_EVTSEL_INV __BIT(23) 1670 #define F10H_EVTSEL_COUNTER_MASK 0xFF000000 1671 #define F10H_EVTSEL_COUNTER_MASK_SHIFT 24 1672 /* Floating Point Events */ 1673 #define F10H_FP_DISPATCHED_FPU_OPS 0x00 1674 #define F10H_FP_CYCLES_EMPTY_FPU_OPS 0x01 1675 #define F10H_FP_DISPATCHED_FASTFLAG_OPS 0x02 1676 #define F10H_FP_RETIRED_SSE_OPS 0x03 1677 #define F10H_FP_RETIRED_MOVE_OPS 0x04 1678 #define F10H_FP_RETIRED_SERIALIZING_OPS 0x05 1679 #define F10H_FP_CYCLES_SERIALIZING_OP_SCHEDULER 0x06 1680 /* Load/Store and TLB Events */ 1681 #define F10H_SEGMENT_REG_LOADS 0x20 1682 #define F10H_PIPELINE_RESTART_SELFMOD_CODE 0x21 1683 #define F10H_PIPELINE_RESTART_PROBE_HIT 0x22 1684 #define F10H_LS_BUFFER_2_FILL 0x23 1685 #define F10H_LOCKED_OPERATIONS 0x24 1686 #define F10H_RETIRED_CLFLUSH_INSTRUCTIONS 0x26 1687 #define F10H_RETIRED_CPUID_INSTRUCTIONS 0x27 1688 #define F10H_CANCELLED_STORE_LOAD_FORWARD_OPS 0x2A 1689 #define F10H_SMI_RECEIVED 0x2B 1690 /* Data Cache Events */ 1691 #define F10H_DATA_CACHE_ACCESS 0x40 1692 #define F10H_DATA_CACHE_MISS 0x41 1693 #define F10H_DATA_CACHE_REFILL_FROM_L2 0x42 1694 #define F10H_DATA_CACHE_REFILL_FROM_NORTHBRIDGE 0x43 1695 #define F10H_CACHE_LINES_EVICTED 0x44 1696 #define F10H_L1_DTLB_MISS 0x45 1697 #define F10H_L2_DTLB_MISS 0x46 1698 #define F10H_MISALIGNED_ACCESS 0x47 1699 #define F10H_MICROARCH_LATE_CANCEL_OF_ACCESS 0x48 1700 #define F10H_MICROARCH_EARLY_CANCEL_OF_ACCESS 0x49 1701 #define F10H_SINGLE_BIT_ECC_ERRORS_RECORDED 0x4A 1702 #define F10H_PREFETCH_INSTRUCTIONS_DISPATCHED 0x4B 1703 #define F10H_DCACHE_MISSES_LOCKED_INSTRUCTIONS 0x4C 1704 #define F10H_L1_DTLB_HIT 0x4D 1705 #define F10H_INEFFECTIVE_SOFTWARE_PREFETCHS 0x52 1706 #define F10H_GLOBAL_TLB_FLUSHES 0x54 1707 #define F10H_MEMORY_REQUESTS_BY_TYPE 0x65 1708 #define F10H_DATA_PREFETCHER 0x67 1709 #define F10H_MAB_REQUESTS 0x68 1710 #define F10H_MAB_WAIT_CYCLES 0x69 1711 #define F10H_NORTHBRIDGE_READ_RESP_BY_COH_STATE 0x6C 1712 #define F10H_OCTWORDS_WRITTEN_TO_SYSTEM 0x6D 1713 #define F10H_CPU_CLOCKS_NOT_HALTED 0x76 1714 #define F10H_REQUESTS_TO_L2_CACHE 0x7D 1715 #define F10H_L2_CACHE_MISSES 0x7E 1716 #define F10H_L2_FILL 0x7F 1717 /* F10H_PAGE_SIZE_MISMATCHES (0x01C0): reserved on some revisions */ 1718 /* Instruction Cache Events */ 1719 #define F10H_INSTRUCTION_CACHE_FETCH 0x80 1720 #define F10H_INSTRUCTION_CACHE_MISS 0x81 1721 #define F10H_INSTRUCTION_CACHE_REFILL_FROM_L2 0x82 1722 #define F10H_INSTRUCTION_CACHE_REFILL_FROM_SYS 0x83 1723 #define F10H_L1_ITLB_MISS 0x84 1724 #define F10H_L2_ITLB_MISS 0x85 1725 #define F10H_PIPELINE_RESTART_INSTR_STREAM_PROBE 0x86 1726 #define F10H_INSTRUCTION_FETCH_STALL 0x87 1727 #define F10H_RETURN_STACK_HITS 0x88 1728 #define F10H_RETURN_STACK_OVERFLOWS 0x89 1729 #define F10H_INSTRUCTION_CACHE_VICTIMS 0x8B 1730 #define F10H_INSTRUCTION_CACHE_LINES_INVALIDATED 0x8C 1731 #define F10H_ITLD_RELOADS 0x99 1732 #define F10H_ITLD_RELOADS_ABORTED 0x9A 1733 /* Execution Unit Events */ 1734 #define F10H_RETIRED_INSTRUCTIONS 0xC0 1735 #define F10H_RETIRED_UOPS 0xC1 1736 #define F10H_RETIRED_BRANCH 0xC2 1737 #define F10H_RETIRED_MISPREDICTED_BRANCH 0xC3 1738 #define F10H_RETIRED_TAKEN_BRANCH 0xC4 1739 #define F10H_RETIRED_TAKEN_BRANCH_MISPREDICTED 0xC5 1740 #define F10H_RETIRED_FAR_CONTROL_TRANSFER 0xC6 1741 #define F10H_RETIRED_BRANCH_RESYNC 0xC7 1742 #define F10H_RETIRED_NEAR_RETURNS 0xC8 1743 #define F10H_RETIRED_NEAR_RETURNS_MISPREDICTED 0xC9 1744 #define F10H_RETIRED_INDIRECT_BRANCH_MISPREDICTED 0xCA 1745 #define F10H_RETIRED_MMX_FP_INSTRUCTIONS 0xCB 1746 #define F10H_RETIRED_FASTPATH_DOUBLE_OP_INSTR 0xCC 1747 #define F10H_INTERRUPTS_MASKED_CYCLES 0xCD 1748 #define F10H_INTERRUPTS_MASKED_CYCLES_INTERRUPT_PENDING 0xCE 1749 #define F10H_INTERRUPTS_TAKEN 0xCF 1750 #define F10H_DECODER_EMPTY 0xD0 1751 #define F10H_DISPATCH_STALLS 0xD1 1752 #define F10H_DISPATCH_STALLS_BRANCH_ABORT_RETIRE 0xD2 1753 #define F10H_DISPATCH_STALLS_SERIALIZATION 0xD3 1754 #define F10H_DISPATCH_STALLS_SEGMENT_LOAD 0xD4 1755 #define F10H_DISPATCH_STALLS_REORDER_BUF_FULL 0xD5 1756 #define F10H_DISPATCH_STALLS_RSV_STATION_FULL 0xD6 1757 #define F10H_DISPATCH_STALLS_FPU_FULL 0xD7 1758 #define F10H_DISPATCH_STALLS_LS_FULL 0xD8 1759 #define F10H_DISPATCH_STALLS_WAITING_ALL_QUITE 0xD9 1760 #define F10H_DISPATCH_STALLS_FAR_TRANSFER 0xDA 1761 #define F10H_FPU_EXCEPTIONS 0xDB 1762 #define F10H_DR0_BREAKPOINT_MATCHES 0xDC 1763 #define F10H_DR1_BREAKPOINT_MATCHES 0xDD 1764 #define F10H_DR2_BREAKPOINT_MATCHES 0xDE 1765 #define F10H_DR3_BREAKPOINT_MATCHES 0xDF 1766 /* F10H_RETIRED_X87_FP_OPERATIONS (0x01C0): reserved on some revisions */ 1767 /* F10H_IBS_OPS_TAGGED (0x1CF): reserved on some revisions */ 1768 /* F10H_LFENCE_INSTRUCTIONS_RETIRED (0x01D3): reserved on some revisions */ 1769 /* F10H_SFENCE_INSTRUCTIONS_RETIRED (0x01D4): reserved on some revisions */ 1770 /* F10H_MFENCE_INSTRUCTIONS_RETIRED (0x01D5): reserved on some revisions */ 1771 /* Memory Controller Events */ 1772 #define F10H_DRAM_ACCESSES 0xE0 1773 #define F10H_DRAM_CONTROLLER_PT_OVERFLOWS 0xE1 1774 #define F10H_MEM_CONTROLLER_DRAM_COMMAND_SLOTS_MISSED 0xE2 1775 #define F10H_MEM_CONTROLLER_TURNAROUNDS 0xE3 1776 #define F10H_MEM_CONTROLLER_BYPASS_COUNTER_SATURATION 0xE4 1777 #define F10H_THERMAL_STATUS 0xE8 1778 #define F10H_CPU_IO_REQUESTS_TO_MEMORY_IO 0xE9 1779 #define F10H_CACHE_BLOCK_COMMANDS 0xEA 1780 #define F10H_SIZED_COMMANDS 0xEB 1781 #define F10H_PROBE_RESPONSES_AND_UPSTREAM_REQUESTS 0xEC 1782 #define F10H_GART_EVENTS 0xEE 1783 #define F10H_MEMORY_CONTROLLER_REQUESTS 0x01F0 1784 #define F10H_CPU_TO_DRAM_REQUESTS_TO_TARGET_NODE 0x01E0 1785 #define F10H_IO_TO_DRAM_REQUESTS_TO_TARGET_NODE 0x01E1 1786 #define F10H_CPU_READ_CMD_LATENCY_TARGET_NODE_03 0x01E2 1787 #define F10H_CPU_READ_CMD_REQUESTS_TARGET_NODE_03 0x01E3 1788 #define F10H_CPU_READ_CMD_LATENCY_TARGET_NODE_47 0x01E4 1789 #define F10H_CPU_READ_CMD_REQUESTS_TARGET_NODE_47 0x01E5 1790 #define F10H_CPU_CMD_LATENCY_TO_TARGET_NODE_0347 0x01E6 1791 #define F10H_CPU_REQUESTS_TO_TARGET_NODE_0347 0x01E7 1792 /* Link Events */ 1793 #define F10H_HYPERTRANSPORT_LINK0_TRANSMIT_BANDWIDTH 0xF6 1794 #define F10H_HYPERTRANSPORT_LINK1_TRANSMIT_BANDWIDTH 0xF7 1795 #define F10H_HYPERTRANSPORT_LINK2_TRANSMIT_BANDWIDTH 0xF8 1796 #define F10H_HYPERTRANSPORT_LINK3_TRANSMIT_BANDWIDTH 0x01F9 1797 /* L3 Cache Events */ 1798 /* F10H_READ_READ_REQUEST_TO_L3_CACHE (0x04E0): depends on the revision */ 1799 /* F10H_L3_CACHE_MISSES (0x04E1): depends on the revision */ 1800 /* F10H_L3_FILLS_FROM_L2_EVICTIONS (0x04E2): depends on the revision */ 1801 #define F10H_L3_EVICTIONS 0x04E3 1802 /* F10H_NONCANCELLED_L3_READ_REQUESTS (0x04ED): depends on the revision */ 1803 1804
Indexes created Tue Oct 21 07:10:13 GMT 2025