msipic.c revision 1.4.2.3
1 1.4.2.3 skrll /* $NetBSD: msipic.c,v 1.4.2.3 2015/09/22 12:05:54 skrll Exp $ */ 2 1.4.2.2 skrll 3 1.4.2.2 skrll /* 4 1.4.2.2 skrll * Copyright (c) 2015 Internet Initiative Japan Inc. 5 1.4.2.2 skrll * All rights reserved. 6 1.4.2.2 skrll * 7 1.4.2.2 skrll * Redistribution and use in source and binary forms, with or without 8 1.4.2.2 skrll * modification, are permitted provided that the following conditions 9 1.4.2.2 skrll * are met: 10 1.4.2.2 skrll * 1. Redistributions of source code must retain the above copyright 11 1.4.2.2 skrll * notice, this list of conditions and the following disclaimer. 12 1.4.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 13 1.4.2.2 skrll * notice, this list of conditions and the following disclaimer in the 14 1.4.2.2 skrll * documentation and/or other materials provided with the distribution. 15 1.4.2.2 skrll * 16 1.4.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 1.4.2.2 skrll * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 1.4.2.2 skrll * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 1.4.2.2 skrll * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 1.4.2.2 skrll * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 1.4.2.2 skrll * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 1.4.2.2 skrll * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 1.4.2.2 skrll * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 1.4.2.2 skrll * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 1.4.2.2 skrll * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 1.4.2.2 skrll * POSSIBILITY OF SUCH DAMAGE. 27 1.4.2.2 skrll */ 28 1.4.2.2 skrll 29 1.4.2.2 skrll #include <sys/cdefs.h> 30 1.4.2.3 skrll __KERNEL_RCSID(0, "$NetBSD: msipic.c,v 1.4.2.3 2015/09/22 12:05:54 skrll Exp $"); 31 1.4.2.3 skrll 32 1.4.2.3 skrll #include "opt_intrdebug.h" 33 1.4.2.2 skrll 34 1.4.2.2 skrll #include <sys/types.h> 35 1.4.2.2 skrll #include <sys/param.h> 36 1.4.2.2 skrll #include <sys/systm.h> 37 1.4.2.2 skrll #include <sys/errno.h> 38 1.4.2.2 skrll #include <sys/kmem.h> 39 1.4.2.2 skrll #include <sys/malloc.h> 40 1.4.2.2 skrll #include <sys/mutex.h> 41 1.4.2.2 skrll 42 1.4.2.2 skrll #include <dev/pci/pcivar.h> 43 1.4.2.2 skrll 44 1.4.2.2 skrll #include <machine/i82489reg.h> 45 1.4.2.2 skrll #include <machine/i82093reg.h> 46 1.4.2.2 skrll #include <machine/i82093var.h> 47 1.4.2.2 skrll #include <machine/pic.h> 48 1.4.2.2 skrll #include <machine/lock.h> 49 1.4.2.2 skrll 50 1.4.2.2 skrll #include <x86/pci/msipic.h> 51 1.4.2.2 skrll 52 1.4.2.2 skrll #ifdef INTRDEBUG 53 1.4.2.2 skrll #define MSIPICDEBUG 54 1.4.2.2 skrll #endif 55 1.4.2.2 skrll 56 1.4.2.2 skrll #ifdef MSIPICDEBUG 57 1.4.2.2 skrll #define DPRINTF(msg) printf msg 58 1.4.2.2 skrll #else 59 1.4.2.2 skrll #define DPRINTF(msg) 60 1.4.2.2 skrll #endif 61 1.4.2.2 skrll 62 1.4.2.2 skrll #define BUS_SPACE_WRITE_FLUSH(pc, tag) (void)bus_space_read_4(pc, tag, 0) 63 1.4.2.2 skrll 64 1.4.2.2 skrll #define MSIPICNAMEBUF 16 65 1.4.2.2 skrll 66 1.4.2.2 skrll /* 67 1.4.2.2 skrll * A Pseudo pic for single MSI/MSI-X device. 68 1.4.2.2 skrll * The pic and MSI/MSI-X device are distinbuished by "devid". The "devid" 69 1.4.2.2 skrll * is managed by below "dev_seqs". 70 1.4.2.2 skrll */ 71 1.4.2.2 skrll struct msipic { 72 1.4.2.2 skrll int mp_bus; 73 1.4.2.2 skrll int mp_dev; 74 1.4.2.2 skrll int mp_fun; 75 1.4.2.2 skrll 76 1.4.2.2 skrll int mp_devid; /* The device id for the MSI/MSI-X device. */ 77 1.4.2.2 skrll int mp_veccnt; /* The number of MSI/MSI-X vectors. */ 78 1.4.2.2 skrll 79 1.4.2.2 skrll char mp_pic_name[MSIPICNAMEBUF]; /* The MSI/MSI-X device's name. */ 80 1.4.2.2 skrll 81 1.4.2.2 skrll struct pci_attach_args mp_pa; 82 1.4.2.2 skrll bus_space_tag_t mp_bstag; 83 1.4.2.2 skrll bus_space_handle_t mp_bshandle; 84 1.4.2.2 skrll bus_size_t mp_bssize; 85 1.4.2.2 skrll struct pic *mp_pic; 86 1.4.2.2 skrll 87 1.4.2.2 skrll LIST_ENTRY(msipic) mp_list; 88 1.4.2.2 skrll }; 89 1.4.2.2 skrll 90 1.4.2.2 skrll static kmutex_t msipic_list_lock; 91 1.4.2.2 skrll 92 1.4.2.2 skrll static LIST_HEAD(, msipic) msipic_list = 93 1.4.2.2 skrll LIST_HEAD_INITIALIZER(msipic_list); 94 1.4.2.2 skrll 95 1.4.2.2 skrll /* 96 1.4.2.2 skrll * This struct managements "devid" to use the same "devid" for the device 97 1.4.2.2 skrll * re-attached. If the device's bus number and device numer and function 98 1.4.2.2 skrll * number are equal, it is assumed re-attached. 99 1.4.2.2 skrll */ 100 1.4.2.2 skrll struct dev_last_used_seq { 101 1.4.2.2 skrll bool ds_using; 102 1.4.2.2 skrll int ds_bus; 103 1.4.2.2 skrll int ds_dev; 104 1.4.2.2 skrll int ds_fun; 105 1.4.2.2 skrll }; 106 1.4.2.2 skrll /* The number of MSI/MSI-X devices supported by system. */ 107 1.4.2.2 skrll #define NUM_MSI_DEVS 256 108 1.4.2.2 skrll /* Record devids to use the same devid when the device is re-attached. */ 109 1.4.2.2 skrll static struct dev_last_used_seq dev_seqs[NUM_MSI_DEVS]; 110 1.4.2.2 skrll 111 1.4.2.2 skrll static int msipic_allocate_common_msi_devid(const struct pci_attach_args *); 112 1.4.2.2 skrll static void msipic_release_common_msi_devid(int); 113 1.4.2.2 skrll 114 1.4.2.2 skrll static struct pic *msipic_find_msi_pic_locked(int); 115 1.4.2.2 skrll static struct pic *msipic_construct_common_msi_pic(const struct pci_attach_args *, 116 1.4.2.2 skrll struct pic *); 117 1.4.2.2 skrll static void msipic_destruct_common_msi_pic(struct pic *); 118 1.4.2.2 skrll 119 1.4.2.2 skrll static void msi_set_msictl_enablebit(struct pic *, int, int); 120 1.4.2.2 skrll static void msi_hwmask(struct pic *, int); 121 1.4.2.2 skrll static void msi_hwunmask(struct pic *, int); 122 1.4.2.2 skrll static void msi_addroute(struct pic *, struct cpu_info *, int, int, int); 123 1.4.2.2 skrll static void msi_delroute(struct pic *, struct cpu_info *, int, int, int); 124 1.4.2.2 skrll 125 1.4.2.2 skrll static void msix_set_vecctl_mask(struct pic *, int, int); 126 1.4.2.2 skrll static void msix_hwmask(struct pic *, int); 127 1.4.2.2 skrll static void msix_hwunmask(struct pic *, int); 128 1.4.2.2 skrll static void msix_addroute(struct pic *, struct cpu_info *, int, int, int); 129 1.4.2.2 skrll static void msix_delroute(struct pic *, struct cpu_info *, int, int, int); 130 1.4.2.2 skrll 131 1.4.2.2 skrll /* 132 1.4.2.2 skrll * Return new "devid" for the device attached first. 133 1.4.2.2 skrll * Return the same "devid" for the device re-attached after dettached once. 134 1.4.2.2 skrll * Return -1 if the number of attached MSI/MSI-X devices is over NUM_MSI_DEVS. 135 1.4.2.2 skrll */ 136 1.4.2.2 skrll static int 137 1.4.2.2 skrll msipic_allocate_common_msi_devid(const struct pci_attach_args *pa) 138 1.4.2.2 skrll { 139 1.4.2.2 skrll pci_chipset_tag_t pc; 140 1.4.2.2 skrll pcitag_t tag; 141 1.4.2.2 skrll int bus, dev, fun, i; 142 1.4.2.2 skrll 143 1.4.2.2 skrll KASSERT(mutex_owned(&msipic_list_lock)); 144 1.4.2.2 skrll 145 1.4.2.2 skrll pc = pa->pa_pc; 146 1.4.2.2 skrll tag = pa->pa_tag; 147 1.4.2.2 skrll pci_decompose_tag(pc, tag, &bus, &dev, &fun); 148 1.4.2.2 skrll 149 1.4.2.2 skrll /* if the device was once attached, use same devid */ 150 1.4.2.2 skrll for (i = 0; i < NUM_MSI_DEVS; i++) { 151 1.4.2.2 skrll /* skip host bridge */ 152 1.4.2.2 skrll if (dev_seqs[i].ds_bus == 0 153 1.4.2.2 skrll && dev_seqs[i].ds_dev == 0 154 1.4.2.2 skrll && dev_seqs[i].ds_fun == 0) 155 1.4.2.2 skrll break; 156 1.4.2.2 skrll 157 1.4.2.2 skrll if (dev_seqs[i].ds_bus == bus 158 1.4.2.2 skrll && dev_seqs[i].ds_dev == dev 159 1.4.2.2 skrll && dev_seqs[i].ds_fun == fun) { 160 1.4.2.2 skrll dev_seqs[i].ds_using = true; 161 1.4.2.2 skrll return i; 162 1.4.2.2 skrll } 163 1.4.2.2 skrll } 164 1.4.2.2 skrll 165 1.4.2.2 skrll for (i = 0; i < NUM_MSI_DEVS; i++) { 166 1.4.2.2 skrll if (dev_seqs[i].ds_using == 0) { 167 1.4.2.2 skrll dev_seqs[i].ds_using = true; 168 1.4.2.2 skrll dev_seqs[i].ds_bus = bus; 169 1.4.2.2 skrll dev_seqs[i].ds_dev = dev; 170 1.4.2.2 skrll dev_seqs[i].ds_fun = fun; 171 1.4.2.2 skrll return i; 172 1.4.2.2 skrll } 173 1.4.2.2 skrll } 174 1.4.2.2 skrll 175 1.4.2.2 skrll DPRINTF(("too many MSI devices.\n")); 176 1.4.2.2 skrll return -1; 177 1.4.2.2 skrll } 178 1.4.2.2 skrll 179 1.4.2.2 skrll /* 180 1.4.2.2 skrll * Set the "devid" unused, but keep reserving the "devid" to reuse when 181 1.4.2.2 skrll * the device is re-attached. 182 1.4.2.2 skrll */ 183 1.4.2.2 skrll static void 184 1.4.2.2 skrll msipic_release_common_msi_devid(int devid) 185 1.4.2.2 skrll { 186 1.4.2.2 skrll 187 1.4.2.2 skrll KASSERT(mutex_owned(&msipic_list_lock)); 188 1.4.2.2 skrll 189 1.4.2.2 skrll if (devid < 0 || NUM_MSI_DEVS <= devid) { 190 1.4.2.2 skrll DPRINTF(("%s: invalid devid.\n", __func__)); 191 1.4.2.2 skrll return; 192 1.4.2.2 skrll } 193 1.4.2.2 skrll 194 1.4.2.2 skrll dev_seqs[devid].ds_using = false; 195 1.4.2.2 skrll /* Keep ds_* to reuse the same devid for the same device. */ 196 1.4.2.2 skrll } 197 1.4.2.2 skrll 198 1.4.2.2 skrll static struct pic * 199 1.4.2.2 skrll msipic_find_msi_pic_locked(int devid) 200 1.4.2.2 skrll { 201 1.4.2.2 skrll struct msipic *mpp; 202 1.4.2.2 skrll 203 1.4.2.2 skrll KASSERT(mutex_owned(&msipic_list_lock)); 204 1.4.2.2 skrll 205 1.4.2.2 skrll LIST_FOREACH(mpp, &msipic_list, mp_list) { 206 1.4.2.2 skrll if(mpp->mp_devid == devid) 207 1.4.2.2 skrll return mpp->mp_pic; 208 1.4.2.2 skrll } 209 1.4.2.2 skrll return NULL; 210 1.4.2.2 skrll } 211 1.4.2.2 skrll 212 1.4.2.2 skrll /* 213 1.4.2.2 skrll * Return the msi_pic whose device is already registered. 214 1.4.2.2 skrll * If the device is not registered yet, return NULL. 215 1.4.2.2 skrll */ 216 1.4.2.2 skrll struct pic * 217 1.4.2.2 skrll msipic_find_msi_pic(int devid) 218 1.4.2.2 skrll { 219 1.4.2.2 skrll struct pic *msipic; 220 1.4.2.2 skrll 221 1.4.2.2 skrll mutex_enter(&msipic_list_lock); 222 1.4.2.2 skrll msipic = msipic_find_msi_pic_locked(devid); 223 1.4.2.2 skrll mutex_exit(&msipic_list_lock); 224 1.4.2.2 skrll 225 1.4.2.2 skrll return msipic; 226 1.4.2.2 skrll } 227 1.4.2.2 skrll 228 1.4.2.2 skrll /* 229 1.4.2.2 skrll * A common construct process of MSI and MSI-X. 230 1.4.2.2 skrll */ 231 1.4.2.2 skrll static struct pic * 232 1.4.2.2 skrll msipic_construct_common_msi_pic(const struct pci_attach_args *pa, 233 1.4.2.2 skrll struct pic *pic_tmpl) 234 1.4.2.2 skrll { 235 1.4.2.2 skrll struct pic *pic; 236 1.4.2.2 skrll struct msipic *msipic; 237 1.4.2.2 skrll int devid; 238 1.4.2.2 skrll 239 1.4.2.2 skrll pic = kmem_alloc(sizeof(*pic), KM_SLEEP); 240 1.4.2.2 skrll if (pic == NULL) 241 1.4.2.2 skrll return NULL; 242 1.4.2.2 skrll 243 1.4.2.2 skrll msipic = kmem_zalloc(sizeof(*msipic), KM_SLEEP); 244 1.4.2.2 skrll if (msipic == NULL) { 245 1.4.2.2 skrll kmem_free(pic, sizeof(*pic)); 246 1.4.2.2 skrll return NULL; 247 1.4.2.2 skrll } 248 1.4.2.2 skrll 249 1.4.2.2 skrll mutex_enter(&msipic_list_lock); 250 1.4.2.2 skrll 251 1.4.2.2 skrll devid = msipic_allocate_common_msi_devid(pa); 252 1.4.2.2 skrll if (devid == -1) { 253 1.4.2.2 skrll mutex_exit(&msipic_list_lock); 254 1.4.2.2 skrll kmem_free(pic, sizeof(*pic)); 255 1.4.2.2 skrll kmem_free(msipic, sizeof(*msipic)); 256 1.4.2.2 skrll return NULL; 257 1.4.2.2 skrll } 258 1.4.2.2 skrll 259 1.4.2.2 skrll memcpy(pic, pic_tmpl, sizeof(*pic)); 260 1.4.2.2 skrll pic->pic_msipic = msipic; 261 1.4.2.2 skrll msipic->mp_pic = pic; 262 1.4.2.2 skrll pci_decompose_tag(pa->pa_pc, pa->pa_tag, 263 1.4.2.2 skrll &msipic->mp_bus, &msipic->mp_dev, &msipic->mp_fun); 264 1.4.2.2 skrll memcpy(&msipic->mp_pa, pa, sizeof(msipic->mp_pa)); 265 1.4.2.2 skrll msipic->mp_devid = devid; 266 1.4.2.2 skrll /* 267 1.4.2.2 skrll * pci_msi{,x}_alloc() must be called only once in the device driver. 268 1.4.2.2 skrll */ 269 1.4.2.2 skrll KASSERT(msipic_find_msi_pic_locked(msipic->mp_devid) == NULL); 270 1.4.2.2 skrll 271 1.4.2.2 skrll LIST_INSERT_HEAD(&msipic_list, msipic, mp_list); 272 1.4.2.2 skrll 273 1.4.2.2 skrll mutex_exit(&msipic_list_lock); 274 1.4.2.2 skrll 275 1.4.2.2 skrll return pic; 276 1.4.2.2 skrll } 277 1.4.2.2 skrll 278 1.4.2.2 skrll static void 279 1.4.2.2 skrll msipic_destruct_common_msi_pic(struct pic *msi_pic) 280 1.4.2.2 skrll { 281 1.4.2.2 skrll struct msipic *msipic; 282 1.4.2.2 skrll 283 1.4.2.2 skrll if (msi_pic == NULL) 284 1.4.2.2 skrll return; 285 1.4.2.2 skrll 286 1.4.2.2 skrll msipic = msi_pic->pic_msipic; 287 1.4.2.2 skrll mutex_enter(&msipic_list_lock); 288 1.4.2.2 skrll LIST_REMOVE(msipic, mp_list); 289 1.4.2.2 skrll msipic_release_common_msi_devid(msipic->mp_devid); 290 1.4.2.2 skrll mutex_exit(&msipic_list_lock); 291 1.4.2.2 skrll 292 1.4.2.2 skrll kmem_free(msipic, sizeof(*msipic)); 293 1.4.2.2 skrll kmem_free(msi_pic, sizeof(*msi_pic)); 294 1.4.2.2 skrll } 295 1.4.2.2 skrll 296 1.4.2.2 skrll /* 297 1.4.2.2 skrll * The pic is MSI/MSI-X pic or not. 298 1.4.2.2 skrll */ 299 1.4.2.2 skrll bool 300 1.4.2.2 skrll msipic_is_msi_pic(struct pic *pic) 301 1.4.2.2 skrll { 302 1.4.2.2 skrll 303 1.4.2.2 skrll return (pic->pic_msipic != NULL); 304 1.4.2.2 skrll } 305 1.4.2.2 skrll 306 1.4.2.2 skrll /* 307 1.4.2.2 skrll * Return the MSI/MSI-X devid which is unique for each devices. 308 1.4.2.2 skrll */ 309 1.4.2.2 skrll int 310 1.4.2.2 skrll msipic_get_devid(struct pic *pic) 311 1.4.2.2 skrll { 312 1.4.2.2 skrll 313 1.4.2.2 skrll KASSERT(msipic_is_msi_pic(pic)); 314 1.4.2.2 skrll 315 1.4.2.2 skrll return pic->pic_msipic->mp_devid; 316 1.4.2.2 skrll } 317 1.4.2.2 skrll 318 1.4.2.2 skrll #define MSI_MSICTL_ENABLE 1 319 1.4.2.2 skrll #define MSI_MSICTL_DISABLE 0 320 1.4.2.2 skrll static void 321 1.4.2.2 skrll msi_set_msictl_enablebit(struct pic *pic, int msi_vec, int flag) 322 1.4.2.2 skrll { 323 1.4.2.2 skrll pci_chipset_tag_t pc; 324 1.4.2.2 skrll struct pci_attach_args *pa; 325 1.4.2.2 skrll pcitag_t tag; 326 1.4.2.2 skrll pcireg_t ctl; 327 1.4.2.2 skrll int off, err __diagused; 328 1.4.2.2 skrll 329 1.4.2.2 skrll pc = NULL; 330 1.4.2.2 skrll pa = &pic->pic_msipic->mp_pa; 331 1.4.2.2 skrll tag = pa->pa_tag; 332 1.4.2.2 skrll err = pci_get_capability(pc, tag, PCI_CAP_MSI, &off, NULL); 333 1.4.2.2 skrll KASSERT(err != 0); 334 1.4.2.2 skrll 335 1.4.2.2 skrll /* 336 1.4.2.2 skrll * MSI can establish only one vector at once. 337 1.4.2.2 skrll * So, use whole device mask bit instead of a vector mask bit. 338 1.4.2.2 skrll */ 339 1.4.2.2 skrll ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL); 340 1.4.2.2 skrll if (flag == MSI_MSICTL_ENABLE) 341 1.4.2.2 skrll ctl |= PCI_MSI_CTL_MSI_ENABLE; 342 1.4.2.2 skrll else 343 1.4.2.2 skrll ctl &= ~PCI_MSI_CTL_MSI_ENABLE; 344 1.4.2.2 skrll 345 1.4.2.2 skrll pci_conf_write(pc, tag, off, ctl); 346 1.4.2.2 skrll } 347 1.4.2.2 skrll 348 1.4.2.2 skrll static void 349 1.4.2.2 skrll msi_hwmask(struct pic *pic, int msi_vec) 350 1.4.2.2 skrll { 351 1.4.2.2 skrll 352 1.4.2.2 skrll msi_set_msictl_enablebit(pic, msi_vec, MSI_MSICTL_DISABLE); 353 1.4.2.2 skrll } 354 1.4.2.2 skrll 355 1.4.2.2 skrll /* 356 1.4.2.2 skrll * Do not use pic->hwunmask() immediately after pic->delroute(). 357 1.4.2.2 skrll * It is required to use pic->addroute() before pic->hwunmask(). 358 1.4.2.2 skrll */ 359 1.4.2.2 skrll static void 360 1.4.2.2 skrll msi_hwunmask(struct pic *pic, int msi_vec) 361 1.4.2.2 skrll { 362 1.4.2.2 skrll 363 1.4.2.2 skrll msi_set_msictl_enablebit(pic, msi_vec, MSI_MSICTL_ENABLE); 364 1.4.2.2 skrll } 365 1.4.2.2 skrll 366 1.4.2.2 skrll static void 367 1.4.2.2 skrll msi_addroute(struct pic *pic, struct cpu_info *ci, 368 1.4.2.2 skrll int unused, int idt_vec, int type) 369 1.4.2.2 skrll { 370 1.4.2.2 skrll pci_chipset_tag_t pc; 371 1.4.2.2 skrll struct pci_attach_args *pa; 372 1.4.2.2 skrll pcitag_t tag; 373 1.4.2.2 skrll pcireg_t addr, data, ctl; 374 1.4.2.2 skrll int off, err __diagused; 375 1.4.2.2 skrll 376 1.4.2.2 skrll pc = NULL; 377 1.4.2.2 skrll pa = &pic->pic_msipic->mp_pa; 378 1.4.2.2 skrll tag = pa->pa_tag; 379 1.4.2.2 skrll err = pci_get_capability(pc, tag, PCI_CAP_MSI, &off, NULL); 380 1.4.2.2 skrll KASSERT(err != 0); 381 1.4.2.2 skrll 382 1.4.2.2 skrll /* 383 1.4.2.2 skrll * See Intel 64 and IA-32 Architectures Software Developer's Manual 384 1.4.2.2 skrll * Volume 3 10.11 Message Signalled Interrupts. 385 1.4.2.2 skrll */ 386 1.4.2.2 skrll /* 387 1.4.2.2 skrll * "cpuid" for MSI address is local APIC ID. In NetBSD, the ID is 388 1.4.2.2 skrll * the same as ci->ci_cpuid. 389 1.4.2.2 skrll */ 390 1.4.2.2 skrll addr = LAPIC_MSIADDR_BASE | __SHIFTIN(ci->ci_cpuid, 391 1.4.2.2 skrll LAPIC_MSIADDR_DSTID_MASK); 392 1.4.2.2 skrll /* If trigger mode is edge, it don't care level for trigger mode. */ 393 1.4.2.2 skrll data = __SHIFTIN(idt_vec, LAPIC_MSIDATA_VECTOR_MASK) 394 1.4.2.2 skrll | LAPIC_MSIDATA_TRGMODE_EDGE | LAPIC_MSIDATA_DM_FIXED; 395 1.4.2.2 skrll 396 1.4.2.2 skrll ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL); 397 1.4.2.2 skrll if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 398 1.4.2.2 skrll pci_conf_write(pc, tag, off + PCI_MSI_MADDR64_LO, addr); 399 1.4.2.2 skrll pci_conf_write(pc, tag, off + PCI_MSI_MADDR64_HI, 0); 400 1.4.2.2 skrll pci_conf_write(pc, tag, off + PCI_MSI_MDATA64, data); 401 1.4.2.2 skrll } else { 402 1.4.2.2 skrll pci_conf_write(pc, tag, off + PCI_MSI_MADDR, addr); 403 1.4.2.2 skrll pci_conf_write(pc, tag, off + PCI_MSI_MDATA, data); 404 1.4.2.2 skrll } 405 1.4.2.2 skrll ctl |= PCI_MSI_CTL_MSI_ENABLE; 406 1.4.2.2 skrll pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl); 407 1.4.2.2 skrll } 408 1.4.2.2 skrll 409 1.4.2.2 skrll /* 410 1.4.2.2 skrll * Do not use pic->hwunmask() immediately after pic->delroute(). 411 1.4.2.2 skrll * It is required to use pic->addroute() before pic->hwunmask(). 412 1.4.2.2 skrll */ 413 1.4.2.2 skrll static void 414 1.4.2.2 skrll msi_delroute(struct pic *pic, struct cpu_info *ci, 415 1.4.2.2 skrll int msi_vec, int idt_vec, int type) 416 1.4.2.2 skrll { 417 1.4.2.2 skrll 418 1.4.2.2 skrll msi_hwmask(pic, msi_vec); 419 1.4.2.2 skrll } 420 1.4.2.2 skrll 421 1.4.2.2 skrll /* 422 1.4.2.2 skrll * Template for MSI pic. 423 1.4.2.2 skrll * .pic_msipic is set later in construct_msi_pic(). 424 1.4.2.2 skrll */ 425 1.4.2.2 skrll static struct pic msi_pic_tmpl = { 426 1.4.2.2 skrll .pic_type = PIC_MSI, 427 1.4.2.2 skrll .pic_vecbase = 0, 428 1.4.2.2 skrll .pic_apicid = 0, 429 1.4.2.2 skrll .pic_lock = __SIMPLELOCK_UNLOCKED, /* not used for msi_pic */ 430 1.4.2.2 skrll .pic_hwmask = msi_hwmask, 431 1.4.2.2 skrll .pic_hwunmask = msi_hwunmask, 432 1.4.2.2 skrll .pic_addroute = msi_addroute, 433 1.4.2.2 skrll .pic_delroute = msi_delroute, 434 1.4.2.2 skrll .pic_edge_stubs = ioapic_edge_stubs, 435 1.4.2.2 skrll .pic_ioapic = NULL, 436 1.4.2.2 skrll }; 437 1.4.2.2 skrll 438 1.4.2.2 skrll /* 439 1.4.2.2 skrll * Create pseudo pic for a MSI device. 440 1.4.2.2 skrll */ 441 1.4.2.2 skrll struct pic * 442 1.4.2.2 skrll msipic_construct_msi_pic(const struct pci_attach_args *pa) 443 1.4.2.2 skrll { 444 1.4.2.2 skrll struct pic *msi_pic; 445 1.4.2.2 skrll char pic_name_buf[MSIPICNAMEBUF]; 446 1.4.2.2 skrll 447 1.4.2.2 skrll msi_pic = msipic_construct_common_msi_pic(pa, &msi_pic_tmpl); 448 1.4.2.2 skrll if (msi_pic == NULL) { 449 1.4.2.2 skrll DPRINTF(("cannot allocate MSI pic.\n")); 450 1.4.2.2 skrll return NULL; 451 1.4.2.2 skrll } 452 1.4.2.2 skrll 453 1.4.2.2 skrll memset(pic_name_buf, 0, MSIPICNAMEBUF); 454 1.4.2.2 skrll snprintf(pic_name_buf, MSIPICNAMEBUF, "msi%d", 455 1.4.2.2 skrll msi_pic->pic_msipic->mp_devid); 456 1.4.2.2 skrll strncpy(msi_pic->pic_msipic->mp_pic_name, pic_name_buf, 457 1.4.2.2 skrll MSIPICNAMEBUF - 1); 458 1.4.2.2 skrll msi_pic->pic_name = msi_pic->pic_msipic->mp_pic_name; 459 1.4.2.2 skrll 460 1.4.2.2 skrll return msi_pic; 461 1.4.2.2 skrll } 462 1.4.2.2 skrll 463 1.4.2.2 skrll /* 464 1.4.2.2 skrll * Delete pseudo pic for a MSI device. 465 1.4.2.2 skrll */ 466 1.4.2.2 skrll void 467 1.4.2.2 skrll msipic_destruct_msi_pic(struct pic *msi_pic) 468 1.4.2.2 skrll { 469 1.4.2.2 skrll 470 1.4.2.2 skrll msipic_destruct_common_msi_pic(msi_pic); 471 1.4.2.2 skrll } 472 1.4.2.2 skrll 473 1.4.2.2 skrll #define MSIX_VECCTL_HWMASK 1 474 1.4.2.2 skrll #define MSIX_VECCTL_HWUNMASK 0 475 1.4.2.2 skrll static void 476 1.4.2.2 skrll msix_set_vecctl_mask(struct pic *pic, int msix_vec, int flag) 477 1.4.2.2 skrll { 478 1.4.2.2 skrll bus_space_tag_t bstag; 479 1.4.2.2 skrll bus_space_handle_t bshandle; 480 1.4.2.2 skrll uint64_t entry_base; 481 1.4.2.2 skrll uint32_t vecctl; 482 1.4.2.2 skrll 483 1.4.2.2 skrll if (msix_vec < 0) { 484 1.4.2.2 skrll DPRINTF(("%s: invalid MSI-X table index, devid=%d vecid=%d", 485 1.4.2.2 skrll __func__, msipic_get_devid(pic), msix_vec)); 486 1.4.2.2 skrll return; 487 1.4.2.2 skrll } 488 1.4.2.2 skrll 489 1.4.2.2 skrll entry_base = PCI_MSIX_TABLE_ENTRY_SIZE * msix_vec; 490 1.4.2.2 skrll 491 1.4.2.2 skrll bstag = pic->pic_msipic->mp_bstag; 492 1.4.2.2 skrll bshandle = pic->pic_msipic->mp_bshandle; 493 1.4.2.2 skrll vecctl = bus_space_read_4(bstag, bshandle, 494 1.4.2.2 skrll entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL); 495 1.4.2.2 skrll if (flag == MSIX_VECCTL_HWMASK) 496 1.4.2.2 skrll vecctl |= PCI_MSIX_VECTCTL_HWMASK_MASK; 497 1.4.2.2 skrll else 498 1.4.2.2 skrll vecctl &= ~PCI_MSIX_VECTCTL_HWMASK_MASK; 499 1.4.2.2 skrll 500 1.4.2.2 skrll bus_space_write_4(bstag, bshandle, 501 1.4.2.2 skrll entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL, vecctl); 502 1.4.2.2 skrll BUS_SPACE_WRITE_FLUSH(bstag, bshandle); 503 1.4.2.2 skrll } 504 1.4.2.2 skrll 505 1.4.2.2 skrll static void 506 1.4.2.2 skrll msix_hwmask(struct pic *pic, int msix_vec) 507 1.4.2.2 skrll { 508 1.4.2.2 skrll 509 1.4.2.2 skrll msix_set_vecctl_mask(pic, msix_vec, MSIX_VECCTL_HWMASK); 510 1.4.2.2 skrll } 511 1.4.2.2 skrll 512 1.4.2.2 skrll /* 513 1.4.2.2 skrll * Do not use pic->hwunmask() immediately after pic->delroute(). 514 1.4.2.2 skrll * It is required to use pic->addroute() before pic->hwunmask(). 515 1.4.2.2 skrll */ 516 1.4.2.2 skrll static void 517 1.4.2.2 skrll msix_hwunmask(struct pic *pic, int msix_vec) 518 1.4.2.2 skrll { 519 1.4.2.2 skrll 520 1.4.2.2 skrll msix_set_vecctl_mask(pic, msix_vec, MSIX_VECCTL_HWUNMASK); 521 1.4.2.2 skrll } 522 1.4.2.2 skrll 523 1.4.2.2 skrll static void 524 1.4.2.2 skrll msix_addroute(struct pic *pic, struct cpu_info *ci, 525 1.4.2.2 skrll int msix_vec, int idt_vec, int type) 526 1.4.2.2 skrll { 527 1.4.2.2 skrll pci_chipset_tag_t pc; 528 1.4.2.2 skrll struct pci_attach_args *pa; 529 1.4.2.2 skrll pcitag_t tag; 530 1.4.2.2 skrll bus_space_tag_t bstag; 531 1.4.2.2 skrll bus_space_handle_t bshandle; 532 1.4.2.2 skrll uint64_t entry_base; 533 1.4.2.2 skrll pcireg_t addr, data, ctl; 534 1.4.2.2 skrll int off, err __diagused; 535 1.4.2.2 skrll 536 1.4.2.2 skrll if (msix_vec < 0) { 537 1.4.2.2 skrll DPRINTF(("%s: invalid MSI-X table index, devid=%d vecid=%d", 538 1.4.2.2 skrll __func__, msipic_get_devid(pic), msix_vec)); 539 1.4.2.2 skrll return; 540 1.4.2.2 skrll } 541 1.4.2.2 skrll 542 1.4.2.2 skrll pa = &pic->pic_msipic->mp_pa; 543 1.4.2.2 skrll pc = pa->pa_pc; 544 1.4.2.2 skrll tag = pa->pa_tag; 545 1.4.2.2 skrll err = pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, NULL); 546 1.4.2.2 skrll KASSERT(err != 0); 547 1.4.2.2 skrll 548 1.4.2.2 skrll entry_base = PCI_MSIX_TABLE_ENTRY_SIZE * msix_vec; 549 1.4.2.2 skrll 550 1.4.2.2 skrll /* 551 1.4.2.2 skrll * See Intel 64 and IA-32 Architectures Software Developer's Manual 552 1.4.2.2 skrll * Volume 3 10.11 Message Signalled Interrupts. 553 1.4.2.2 skrll */ 554 1.4.2.2 skrll /* 555 1.4.2.2 skrll * "cpuid" for MSI-X address is local APIC ID. In NetBSD, the ID is 556 1.4.2.2 skrll * the same as ci->ci_cpuid. 557 1.4.2.2 skrll */ 558 1.4.2.2 skrll addr = LAPIC_MSIADDR_BASE | __SHIFTIN(ci->ci_cpuid, 559 1.4.2.2 skrll LAPIC_MSIADDR_DSTID_MASK); 560 1.4.2.2 skrll /* If trigger mode is edge, it don't care level for trigger mode. */ 561 1.4.2.2 skrll data = __SHIFTIN(idt_vec, LAPIC_MSIDATA_VECTOR_MASK) 562 1.4.2.2 skrll | LAPIC_MSIDATA_TRGMODE_EDGE | LAPIC_MSIDATA_DM_FIXED; 563 1.4.2.2 skrll 564 1.4.2.2 skrll bstag = pic->pic_msipic->mp_bstag; 565 1.4.2.2 skrll bshandle = pic->pic_msipic->mp_bshandle; 566 1.4.2.2 skrll bus_space_write_4(bstag, bshandle, 567 1.4.2.2 skrll entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_LO, addr); 568 1.4.2.2 skrll bus_space_write_4(bstag, bshandle, 569 1.4.2.2 skrll entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_HI, 0); 570 1.4.2.2 skrll bus_space_write_4(bstag, bshandle, 571 1.4.2.2 skrll entry_base + PCI_MSIX_TABLE_ENTRY_DATA, data); 572 1.4.2.2 skrll bus_space_write_4(bstag, bshandle, 573 1.4.2.2 skrll entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL, 0); 574 1.4.2.2 skrll BUS_SPACE_WRITE_FLUSH(bstag, bshandle); 575 1.4.2.2 skrll 576 1.4.2.2 skrll ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL); 577 1.4.2.2 skrll ctl |= PCI_MSIX_CTL_ENABLE; 578 1.4.2.2 skrll pci_conf_write(pc, tag, off + PCI_MSIX_CTL, ctl); 579 1.4.2.2 skrll } 580 1.4.2.2 skrll 581 1.4.2.2 skrll /* 582 1.4.2.2 skrll * Do not use pic->hwunmask() immediately after pic->delroute(). 583 1.4.2.2 skrll * It is required to use pic->addroute() before pic->hwunmask(). 584 1.4.2.2 skrll */ 585 1.4.2.2 skrll static void 586 1.4.2.2 skrll msix_delroute(struct pic *pic, struct cpu_info *ci, 587 1.4.2.2 skrll int msix_vec, int vec, int type) 588 1.4.2.2 skrll { 589 1.4.2.2 skrll 590 1.4.2.2 skrll msix_hwmask(pic, msix_vec); 591 1.4.2.2 skrll } 592 1.4.2.2 skrll 593 1.4.2.2 skrll /* 594 1.4.2.2 skrll * Template for MSI-X pic. 595 1.4.2.2 skrll * .pic_msipic is set later in construct_msix_pic(). 596 1.4.2.2 skrll */ 597 1.4.2.2 skrll static struct pic msix_pic_tmpl = { 598 1.4.2.2 skrll .pic_type = PIC_MSIX, 599 1.4.2.2 skrll .pic_vecbase = 0, 600 1.4.2.2 skrll .pic_apicid = 0, 601 1.4.2.2 skrll .pic_lock = __SIMPLELOCK_UNLOCKED, /* not used for msix_pic */ 602 1.4.2.2 skrll .pic_hwmask = msix_hwmask, 603 1.4.2.2 skrll .pic_hwunmask = msix_hwunmask, 604 1.4.2.2 skrll .pic_addroute = msix_addroute, 605 1.4.2.2 skrll .pic_delroute = msix_delroute, 606 1.4.2.2 skrll .pic_edge_stubs = ioapic_edge_stubs, 607 1.4.2.2 skrll }; 608 1.4.2.2 skrll 609 1.4.2.2 skrll struct pic * 610 1.4.2.2 skrll msipic_construct_msix_pic(const struct pci_attach_args *pa) 611 1.4.2.2 skrll { 612 1.4.2.2 skrll struct pic *msix_pic; 613 1.4.2.2 skrll pci_chipset_tag_t pc; 614 1.4.2.2 skrll pcitag_t tag; 615 1.4.2.2 skrll pcireg_t tbl; 616 1.4.2.2 skrll bus_space_tag_t bstag; 617 1.4.2.2 skrll bus_space_handle_t bshandle; 618 1.4.2.2 skrll bus_size_t bssize; 619 1.4.2.2 skrll size_t table_size; 620 1.4.2.2 skrll uint32_t table_offset; 621 1.4.2.2 skrll u_int memtype; 622 1.4.2.3 skrll bus_addr_t memaddr; 623 1.4.2.3 skrll int flags; 624 1.4.2.2 skrll int bir, bar, err, off, table_nentry; 625 1.4.2.2 skrll char pic_name_buf[MSIPICNAMEBUF]; 626 1.4.2.2 skrll 627 1.4.2.3 skrll table_nentry = pci_msix_count(pa->pa_pc, pa->pa_tag); 628 1.4.2.2 skrll if (table_nentry == 0) { 629 1.4.2.2 skrll DPRINTF(("MSI-X table entry is 0.\n")); 630 1.4.2.2 skrll return NULL; 631 1.4.2.2 skrll } 632 1.4.2.2 skrll 633 1.4.2.2 skrll pc = pa->pa_pc; 634 1.4.2.2 skrll tag = pa->pa_tag; 635 1.4.2.2 skrll if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, NULL) == 0) { 636 1.4.2.2 skrll DPRINTF(("%s: no msix capability", __func__)); 637 1.4.2.2 skrll return NULL; 638 1.4.2.2 skrll } 639 1.4.2.2 skrll 640 1.4.2.2 skrll msix_pic = msipic_construct_common_msi_pic(pa, &msix_pic_tmpl); 641 1.4.2.2 skrll if (msix_pic == NULL) { 642 1.4.2.2 skrll DPRINTF(("cannot allocate MSI-X pic.\n")); 643 1.4.2.2 skrll return NULL; 644 1.4.2.2 skrll } 645 1.4.2.2 skrll 646 1.4.2.2 skrll memset(pic_name_buf, 0, MSIPICNAMEBUF); 647 1.4.2.2 skrll snprintf(pic_name_buf, MSIPICNAMEBUF, "msix%d", 648 1.4.2.2 skrll msix_pic->pic_msipic->mp_devid); 649 1.4.2.2 skrll strncpy(msix_pic->pic_msipic->mp_pic_name, pic_name_buf, 650 1.4.2.2 skrll MSIPICNAMEBUF - 1); 651 1.4.2.2 skrll msix_pic->pic_name = msix_pic->pic_msipic->mp_pic_name; 652 1.4.2.2 skrll 653 1.4.2.2 skrll tbl = pci_conf_read(pc, tag, off + PCI_MSIX_TBLOFFSET); 654 1.4.2.2 skrll table_offset = tbl & PCI_MSIX_TBLOFFSET_MASK; 655 1.4.2.2 skrll bir = tbl & PCI_MSIX_PBABIR_MASK; 656 1.4.2.2 skrll switch(bir) { 657 1.4.2.2 skrll case 0: 658 1.4.2.2 skrll bar = PCI_BAR0; 659 1.4.2.2 skrll break; 660 1.4.2.2 skrll case 1: 661 1.4.2.2 skrll bar = PCI_BAR1; 662 1.4.2.2 skrll break; 663 1.4.2.2 skrll case 2: 664 1.4.2.2 skrll bar = PCI_BAR2; 665 1.4.2.2 skrll break; 666 1.4.2.2 skrll case 3: 667 1.4.2.2 skrll bar = PCI_BAR3; 668 1.4.2.2 skrll break; 669 1.4.2.2 skrll case 4: 670 1.4.2.2 skrll bar = PCI_BAR4; 671 1.4.2.2 skrll break; 672 1.4.2.2 skrll case 5: 673 1.4.2.2 skrll bar = PCI_BAR5; 674 1.4.2.2 skrll break; 675 1.4.2.2 skrll default: 676 1.4.2.2 skrll aprint_error("detect an illegal device! The device use reserved BIR values.\n"); 677 1.4.2.2 skrll msipic_destruct_common_msi_pic(msix_pic); 678 1.4.2.2 skrll return NULL; 679 1.4.2.2 skrll } 680 1.4.2.2 skrll memtype = pci_mapreg_type(pc, tag, bar); 681 1.4.2.2 skrll /* 682 1.4.2.2 skrll * PCI_MSIX_TABLE_ENTRY_SIZE consists below 683 1.4.2.2 skrll * - Vector Control (32bit) 684 1.4.2.2 skrll * - Message Data (32bit) 685 1.4.2.2 skrll * - Message Upper Address (32bit) 686 1.4.2.2 skrll * - Message Lower Address (32bit) 687 1.4.2.2 skrll */ 688 1.4.2.2 skrll table_size = table_nentry * PCI_MSIX_TABLE_ENTRY_SIZE; 689 1.4.2.3 skrll #if 0 690 1.4.2.2 skrll err = pci_mapreg_submap(pa, bar, memtype, BUS_SPACE_MAP_LINEAR, 691 1.4.2.2 skrll roundup(table_size, PAGE_SIZE), table_offset, 692 1.4.2.2 skrll &bstag, &bshandle, NULL, &bssize); 693 1.4.2.3 skrll #else 694 1.4.2.3 skrll /* 695 1.4.2.3 skrll * Workaround for PCI prefetchable bit. Some chips (e.g. Intel 82599) 696 1.4.2.3 skrll * report SERR and MSI-X doesn't work. This problem might not be the 697 1.4.2.3 skrll * driver's bug but our PCI common part or VMs' bug. Until we find a 698 1.4.2.3 skrll * real reason, we ignore the prefetchable bit. 699 1.4.2.3 skrll */ 700 1.4.2.3 skrll if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, bar, memtype, 701 1.4.2.3 skrll &memaddr, NULL, &flags) != 0) { 702 1.4.2.3 skrll DPRINTF(("cannot get a map info.\n")); 703 1.4.2.3 skrll msipic_destruct_common_msi_pic(msix_pic); 704 1.4.2.3 skrll return NULL; 705 1.4.2.3 skrll } 706 1.4.2.3 skrll if ((flags & BUS_SPACE_MAP_PREFETCHABLE) != 0) { 707 1.4.2.3 skrll DPRINTF(( "clear prefetchable bit\n")); 708 1.4.2.3 skrll flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 709 1.4.2.3 skrll } 710 1.4.2.3 skrll bssize = roundup(table_size, PAGE_SIZE); 711 1.4.2.3 skrll err = bus_space_map(pa->pa_memt, memaddr + table_offset, bssize, flags, 712 1.4.2.3 skrll &bshandle); 713 1.4.2.3 skrll bstag = pa->pa_memt; 714 1.4.2.3 skrll #endif 715 1.4.2.2 skrll if (err) { 716 1.4.2.2 skrll DPRINTF(("cannot map msix table.\n")); 717 1.4.2.2 skrll msipic_destruct_common_msi_pic(msix_pic); 718 1.4.2.2 skrll return NULL; 719 1.4.2.2 skrll } 720 1.4.2.2 skrll msix_pic->pic_msipic->mp_bstag = bstag; 721 1.4.2.2 skrll msix_pic->pic_msipic->mp_bshandle = bshandle; 722 1.4.2.2 skrll msix_pic->pic_msipic->mp_bssize = bssize; 723 1.4.2.2 skrll 724 1.4.2.2 skrll return msix_pic; 725 1.4.2.2 skrll } 726 1.4.2.2 skrll 727 1.4.2.2 skrll /* 728 1.4.2.2 skrll * Delete pseudo pic for a MSI-X device. 729 1.4.2.2 skrll */ 730 1.4.2.2 skrll void 731 1.4.2.2 skrll msipic_destruct_msix_pic(struct pic *msix_pic) 732 1.4.2.2 skrll { 733 1.4.2.2 skrll struct msipic *msipic; 734 1.4.2.2 skrll 735 1.4.2.2 skrll KASSERT(msipic_is_msi_pic(msix_pic)); 736 1.4.2.2 skrll KASSERT(msix_pic->pic_type == PIC_MSIX); 737 1.4.2.2 skrll 738 1.4.2.2 skrll msipic = msix_pic->pic_msipic; 739 1.4.2.2 skrll bus_space_unmap(msipic->mp_bstag, msipic->mp_bshandle, 740 1.4.2.2 skrll msipic->mp_bssize); 741 1.4.2.2 skrll 742 1.4.2.2 skrll msipic_destruct_common_msi_pic(msix_pic); 743 1.4.2.2 skrll } 744 1.4.2.2 skrll 745 1.4.2.2 skrll /* 746 1.4.2.2 skrll * Set the number of MSI vectors for pseudo MSI pic. 747 1.4.2.2 skrll */ 748 1.4.2.2 skrll int 749 1.4.2.2 skrll msipic_set_msi_vectors(struct pic *msi_pic, pci_intr_handle_t *pihs, 750 1.4.2.2 skrll int count) 751 1.4.2.2 skrll { 752 1.4.2.2 skrll 753 1.4.2.2 skrll KASSERT(msipic_is_msi_pic(msi_pic)); 754 1.4.2.2 skrll 755 1.4.2.2 skrll msi_pic->pic_msipic->mp_veccnt = count; 756 1.4.2.2 skrll return 0; 757 1.4.2.2 skrll } 758 1.4.2.2 skrll 759 1.4.2.2 skrll /* 760 1.4.2.2 skrll * Initialize the system to use MSI/MSI-X. 761 1.4.2.2 skrll */ 762 1.4.2.2 skrll void 763 1.4.2.2 skrll msipic_init(void) 764 1.4.2.2 skrll { 765 1.4.2.2 skrll 766 1.4.2.2 skrll mutex_init(&msipic_list_lock, MUTEX_DEFAULT, IPL_NONE); 767 1.4.2.2 skrll } 768
Indexes created Thu Oct 23 22:10:10 GMT 2025