cpu.c revision 1.115
1 /* $NetBSD: cpu.c,v 1.115 2017/11/11 09:10:19 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * Copyright (c) 2002, 2006, 2007 YAMAMOTO Takashi, 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by RedBack Networks Inc. 10 * 11 * Author: Bill Sommerfeld 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * Copyright (c) 1999 Stefan Grefen 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by the NetBSD 49 * Foundation, Inc. and its contributors. 50 * 4. Neither the name of The NetBSD Foundation nor the names of its 51 * contributors may be used to endorse or promote products derived 52 * from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 55 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 56 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 57 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE 58 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 59 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 60 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 62 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 63 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.115 2017/11/11 09:10:19 bouyer Exp $"); 69 70 #include "opt_ddb.h" 71 #include "opt_multiprocessor.h" 72 #include "opt_mpbios.h" /* for MPDEBUG */ 73 #include "opt_mtrr.h" 74 #include "opt_xen.h" 75 76 #include "lapic.h" 77 #include "ioapic.h" 78 79 #include <sys/param.h> 80 #include <sys/proc.h> 81 #include <sys/systm.h> 82 #include <sys/device.h> 83 #include <sys/kmem.h> 84 #include <sys/cpu.h> 85 #include <sys/cpufreq.h> 86 #include <sys/atomic.h> 87 #include <sys/reboot.h> 88 #include <sys/idle.h> 89 90 #include <uvm/uvm.h> 91 92 #include <machine/cpu.h> 93 #include <machine/cpufunc.h> 94 #include <machine/cpuvar.h> 95 #include <machine/pmap.h> 96 #include <machine/vmparam.h> 97 #include <machine/mpbiosvar.h> 98 #include <machine/pcb.h> 99 #include <machine/specialreg.h> 100 #include <machine/segments.h> 101 #include <machine/gdt.h> 102 #include <machine/mtrr.h> 103 #include <machine/pio.h> 104 105 #include <x86/fpu.h> 106 107 #include <xen/xen.h> 108 #include <xen/xen-public/vcpu.h> 109 #include <xen/vcpuvar.h> 110 111 #if NLAPIC > 0 112 #include <machine/apicvar.h> 113 #include <machine/i82489reg.h> 114 #include <machine/i82489var.h> 115 #endif 116 117 #include <dev/ic/mc146818reg.h> 118 #include <dev/isa/isareg.h> 119 120 static int cpu_match(device_t, cfdata_t, void *); 121 static void cpu_attach(device_t, device_t, void *); 122 static void cpu_defer(device_t); 123 static int cpu_rescan(device_t, const char *, const int *); 124 static void cpu_childdetached(device_t, device_t); 125 static int vcpu_match(device_t, cfdata_t, void *); 126 static void vcpu_attach(device_t, device_t, void *); 127 static void cpu_attach_common(device_t, device_t, void *); 128 void cpu_offline_md(void); 129 130 struct cpu_softc { 131 device_t sc_dev; /* device tree glue */ 132 struct cpu_info *sc_info; /* pointer to CPU info */ 133 bool sc_wasonline; 134 }; 135 136 int mp_cpu_start(struct cpu_info *, vaddr_t); 137 void mp_cpu_start_cleanup(struct cpu_info *); 138 const struct cpu_functions mp_cpu_funcs = { mp_cpu_start, NULL, 139 mp_cpu_start_cleanup }; 140 141 CFATTACH_DECL2_NEW(cpu, sizeof(struct cpu_softc), 142 cpu_match, cpu_attach, NULL, NULL, cpu_rescan, cpu_childdetached); 143 144 CFATTACH_DECL_NEW(vcpu, sizeof(struct cpu_softc), 145 vcpu_match, vcpu_attach, NULL, NULL); 146 147 /* 148 * Statically-allocated CPU info for the primary CPU (or the only 149 * CPU, on uniprocessors). The CPU info list is initialized to 150 * point at it. 151 */ 152 struct cpu_info cpu_info_primary __aligned(CACHE_LINE_SIZE) = { 153 .ci_dev = 0, 154 .ci_self = &cpu_info_primary, 155 .ci_idepth = -1, 156 .ci_curlwp = &lwp0, 157 .ci_curldt = -1, 158 }; 159 struct cpu_info phycpu_info_primary __aligned(CACHE_LINE_SIZE) = { 160 .ci_dev = 0, 161 .ci_self = &phycpu_info_primary, 162 }; 163 164 struct cpu_info *cpu_info_list = &cpu_info_primary; 165 struct cpu_info *phycpu_info_list = &phycpu_info_primary; 166 167 uint32_t cpu_feature[7] __read_mostly; /* X86 CPUID feature bits 168 * [0] basic features %edx 169 * [1] basic features %ecx 170 * [2] extended features %edx 171 * [3] extended features %ecx 172 * [4] VIA padlock features 173 * [5] structured extended features cpuid.7:%ebx 174 * [6] structured extended features cpuid.7:%ecx 175 */ 176 177 bool x86_mp_online; 178 paddr_t mp_trampoline_paddr = MP_TRAMPOLINE; 179 180 #if defined(MULTIPROCESSOR) 181 void cpu_hatch(void *); 182 static void cpu_boot_secondary(struct cpu_info *ci); 183 static void cpu_start_secondary(struct cpu_info *ci); 184 #endif /* MULTIPROCESSOR */ 185 186 static int 187 cpu_match(device_t parent, cfdata_t match, void *aux) 188 { 189 190 return 1; 191 } 192 193 static void 194 cpu_attach(device_t parent, device_t self, void *aux) 195 { 196 struct cpu_softc *sc = device_private(self); 197 struct cpu_attach_args *caa = aux; 198 struct cpu_info *ci; 199 uintptr_t ptr; 200 static int nphycpu = 0; 201 202 sc->sc_dev = self; 203 204 /* 205 * If we're an Application Processor, allocate a cpu_info 206 * If we're the first attached CPU use the primary cpu_info, 207 * otherwise allocate a new one 208 */ 209 aprint_naive("\n"); 210 aprint_normal("\n"); 211 if (nphycpu > 0) { 212 struct cpu_info *tmp; 213 ptr = (uintptr_t)kmem_zalloc(sizeof(*ci) + CACHE_LINE_SIZE - 1, 214 KM_SLEEP); 215 ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE); 216 ci->ci_curldt = -1; 217 218 tmp = phycpu_info_list; 219 while (tmp->ci_next) 220 tmp = tmp->ci_next; 221 222 tmp->ci_next = ci; 223 } else { 224 ci = &phycpu_info_primary; 225 } 226 227 ci->ci_self = ci; 228 sc->sc_info = ci; 229 230 ci->ci_dev = self; 231 ci->ci_acpiid = caa->cpu_id; 232 ci->ci_cpuid = caa->cpu_number; 233 ci->ci_vcpu = NULL; 234 ci->ci_index = nphycpu++; 235 236 if (!pmf_device_register(self, NULL, NULL)) 237 aprint_error_dev(self, "couldn't establish power handler\n"); 238 239 (void)config_defer(self, cpu_defer); 240 } 241 242 static void 243 cpu_defer(device_t self) 244 { 245 cpu_rescan(self, NULL, NULL); 246 } 247 248 static int 249 cpu_rescan(device_t self, const char *ifattr, const int *locators) 250 { 251 struct cpu_softc *sc = device_private(self); 252 struct cpufeature_attach_args cfaa; 253 struct cpu_info *ci = sc->sc_info; 254 255 memset(&cfaa, 0, sizeof(cfaa)); 256 cfaa.ci = ci; 257 258 if (ifattr_match(ifattr, "cpufeaturebus")) { 259 260 if (ci->ci_frequency == NULL) { 261 cfaa.name = "frequency"; 262 ci->ci_frequency = config_found_ia(self, 263 "cpufeaturebus", &cfaa, NULL); 264 } 265 } 266 267 return 0; 268 } 269 270 static void 271 cpu_childdetached(device_t self, device_t child) 272 { 273 struct cpu_softc *sc = device_private(self); 274 struct cpu_info *ci = sc->sc_info; 275 276 if (ci->ci_frequency == child) 277 ci->ci_frequency = NULL; 278 } 279 280 static int 281 vcpu_match(device_t parent, cfdata_t match, void *aux) 282 { 283 struct vcpu_attach_args *vcaa = aux; 284 struct vcpu_runstate_info vcr; 285 int error; 286 287 if (strcmp(vcaa->vcaa_name, match->cf_name) == 0) { 288 error = HYPERVISOR_vcpu_op(VCPUOP_get_runstate_info, 289 vcaa->vcaa_caa.cpu_number, &vcr); 290 switch (error) { 291 case 0: 292 return 1; 293 case -ENOENT: 294 return 0; 295 default: 296 panic("Unknown hypervisor error %d returned on vcpu runstate probe\n", error); 297 } 298 } 299 300 return 0; 301 } 302 303 static void 304 vcpu_attach(device_t parent, device_t self, void *aux) 305 { 306 struct vcpu_attach_args *vcaa = aux; 307 308 KASSERT(vcaa->vcaa_caa.cpu_func == NULL); 309 vcaa->vcaa_caa.cpu_func = &mp_cpu_funcs; 310 cpu_attach_common(parent, self, &vcaa->vcaa_caa); 311 312 if (!pmf_device_register(self, NULL, NULL)) 313 aprint_error_dev(self, "couldn't establish power handler\n"); 314 } 315 316 static int 317 vcpu_is_up(struct cpu_info *ci) 318 { 319 KASSERT(ci != NULL); 320 return HYPERVISOR_vcpu_op(VCPUOP_is_up, ci->ci_cpuid, NULL); 321 } 322 323 static void 324 cpu_vm_init(struct cpu_info *ci) 325 { 326 int ncolors = 2, i; 327 328 for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) { 329 struct x86_cache_info *cai; 330 int tcolors; 331 332 cai = &ci->ci_cinfo[i]; 333 334 tcolors = atop(cai->cai_totalsize); 335 switch (cai->cai_associativity) { 336 case 0xff: 337 tcolors = 1; /* fully associative */ 338 break; 339 case 0: 340 case 1: 341 break; 342 default: 343 tcolors /= cai->cai_associativity; 344 } 345 ncolors = max(ncolors, tcolors); 346 } 347 348 /* 349 * Knowing the size of the largest cache on this CPU, potentially 350 * re-color our pages. 351 */ 352 aprint_debug_dev(ci->ci_dev, "%d page colors\n", ncolors); 353 uvm_page_recolor(ncolors); 354 pmap_tlb_cpu_init(ci); 355 #ifndef __HAVE_DIRECT_MAP 356 pmap_vpage_cpu_init(ci); 357 #endif 358 } 359 360 static void 361 cpu_attach_common(device_t parent, device_t self, void *aux) 362 { 363 struct cpu_softc *sc = device_private(self); 364 struct cpu_attach_args *caa = aux; 365 struct cpu_info *ci; 366 uintptr_t ptr; 367 int cpunum = caa->cpu_number; 368 static bool again = false; 369 370 sc->sc_dev = self; 371 372 /* 373 * If we're an Application Processor, allocate a cpu_info 374 * structure, otherwise use the primary's. 375 */ 376 if (caa->cpu_role == CPU_ROLE_AP) { 377 aprint_naive(": Application Processor\n"); 378 ptr = (uintptr_t)kmem_alloc(sizeof(*ci) + CACHE_LINE_SIZE - 1, 379 KM_SLEEP); 380 ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE); 381 memset(ci, 0, sizeof(*ci)); 382 } else { 383 aprint_naive(": %s Processor\n", 384 caa->cpu_role == CPU_ROLE_SP ? "Single" : "Boot"); 385 ci = &cpu_info_primary; 386 } 387 388 ci->ci_self = ci; 389 sc->sc_info = ci; 390 ci->ci_dev = self; 391 ci->ci_cpuid = cpunum; 392 393 KASSERT(HYPERVISOR_shared_info != NULL); 394 KASSERT(cpunum < XEN_LEGACY_MAX_VCPUS); 395 ci->ci_vcpu = &HYPERVISOR_shared_info->vcpu_info[cpunum]; 396 397 KASSERT(ci->ci_func == 0); 398 ci->ci_func = caa->cpu_func; 399 aprint_normal("\n"); 400 401 /* Must be called before mi_cpu_attach(). */ 402 cpu_vm_init(ci); 403 404 if (caa->cpu_role == CPU_ROLE_AP) { 405 int error; 406 407 error = mi_cpu_attach(ci); 408 409 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 410 if (error != 0) { 411 aprint_error_dev(self, 412 "mi_cpu_attach failed with %d\n", error); 413 return; 414 } 415 416 } else { 417 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 418 } 419 420 KASSERT(ci->ci_cpuid == ci->ci_index); 421 #ifdef __x86_64__ 422 /* No user PGD mapped for this CPU yet */ 423 ci->ci_xen_current_user_pgd = 0; 424 #endif 425 #if defined(__x86_64__) || defined(PAE) 426 mutex_init(&ci->ci_kpm_mtx, MUTEX_DEFAULT, IPL_VM); 427 #endif 428 pmap_reference(pmap_kernel()); 429 ci->ci_pmap = pmap_kernel(); 430 ci->ci_tlbstate = TLBSTATE_STALE; 431 432 /* 433 * Boot processor may not be attached first, but the below 434 * must be done to allow booting other processors. 435 */ 436 if (!again) { 437 atomic_or_32(&ci->ci_flags, CPUF_PRESENT | CPUF_PRIMARY); 438 /* Basic init. */ 439 cpu_intr_init(ci); 440 cpu_get_tsc_freq(ci); 441 cpu_init(ci); 442 pmap_cpu_init_late(ci); 443 444 /* Every processor needs to init its own ipi h/w (similar to lapic) */ 445 xen_ipi_init(); 446 447 /* Make sure DELAY() is initialized. */ 448 DELAY(1); 449 again = true; 450 } 451 452 /* further PCB init done later. */ 453 454 switch (caa->cpu_role) { 455 case CPU_ROLE_SP: 456 atomic_or_32(&ci->ci_flags, CPUF_SP); 457 cpu_identify(ci); 458 x86_cpu_idle_init(); 459 break; 460 461 case CPU_ROLE_BP: 462 atomic_or_32(&ci->ci_flags, CPUF_BSP); 463 cpu_identify(ci); 464 x86_cpu_idle_init(); 465 break; 466 467 case CPU_ROLE_AP: 468 atomic_or_32(&ci->ci_flags, CPUF_AP); 469 470 /* 471 * report on an AP 472 */ 473 474 #if defined(MULTIPROCESSOR) 475 /* interrupt handler stack */ 476 cpu_intr_init(ci); 477 478 /* Setup per-cpu memory for gdt */ 479 gdt_alloc_cpu(ci); 480 481 pmap_cpu_init_late(ci); 482 cpu_start_secondary(ci); 483 484 if (ci->ci_flags & CPUF_PRESENT) { 485 struct cpu_info *tmp; 486 487 cpu_identify(ci); 488 tmp = cpu_info_list; 489 while (tmp->ci_next) 490 tmp = tmp->ci_next; 491 492 tmp->ci_next = ci; 493 } 494 #else 495 aprint_error_dev(ci->ci_dev, "not started\n"); 496 #endif 497 break; 498 499 default: 500 panic("unknown processor type??\n"); 501 } 502 503 #ifdef MPVERBOSE 504 if (mp_verbose) { 505 struct lwp *l = ci->ci_data.cpu_idlelwp; 506 struct pcb *pcb = lwp_getpcb(l); 507 508 aprint_verbose_dev(self, 509 "idle lwp at %p, idle sp at 0x%p\n", 510 l, 511 #ifdef i386 512 (void *)pcb->pcb_esp 513 #else 514 (void *)pcb->pcb_rsp 515 #endif 516 ); 517 518 } 519 #endif /* MPVERBOSE */ 520 } 521 522 /* 523 * Initialize the processor appropriately. 524 */ 525 526 void 527 cpu_init(struct cpu_info *ci) 528 { 529 530 /* 531 * If we have FXSAVE/FXRESTOR, use them. 532 */ 533 if (cpu_feature[0] & CPUID_FXSR) { 534 lcr4(rcr4() | CR4_OSFXSR); 535 536 /* 537 * If we have SSE/SSE2, enable XMM exceptions. 538 */ 539 if (cpu_feature[0] & (CPUID_SSE|CPUID_SSE2)) 540 lcr4(rcr4() | CR4_OSXMMEXCPT); 541 } 542 543 atomic_or_32(&ci->ci_flags, CPUF_RUNNING); 544 } 545 546 547 #ifdef MULTIPROCESSOR 548 549 void 550 cpu_boot_secondary_processors(void) 551 { 552 struct cpu_info *ci; 553 u_long i; 554 for (i = 0; i < maxcpus; i++) { 555 ci = cpu_lookup(i); 556 if (ci == NULL) 557 continue; 558 if (ci->ci_data.cpu_idlelwp == NULL) 559 continue; 560 if ((ci->ci_flags & CPUF_PRESENT) == 0) 561 continue; 562 if (ci->ci_flags & (CPUF_BSP|CPUF_SP|CPUF_PRIMARY)) 563 continue; 564 cpu_boot_secondary(ci); 565 } 566 567 x86_mp_online = true; 568 } 569 570 static void 571 cpu_init_idle_lwp(struct cpu_info *ci) 572 { 573 struct lwp *l = ci->ci_data.cpu_idlelwp; 574 struct pcb *pcb = lwp_getpcb(l); 575 576 pcb->pcb_cr0 = rcr0(); 577 } 578 579 void 580 cpu_init_idle_lwps(void) 581 { 582 struct cpu_info *ci; 583 u_long i; 584 585 for (i = 0; i < maxcpus; i++) { 586 ci = cpu_lookup(i); 587 if (ci == NULL) 588 continue; 589 if (ci->ci_data.cpu_idlelwp == NULL) 590 continue; 591 if ((ci->ci_flags & CPUF_PRESENT) == 0) 592 continue; 593 cpu_init_idle_lwp(ci); 594 } 595 } 596 597 static void 598 cpu_start_secondary(struct cpu_info *ci) 599 { 600 int i; 601 602 aprint_debug_dev(ci->ci_dev, "starting\n"); 603 604 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 605 606 if (CPU_STARTUP(ci, (vaddr_t) cpu_hatch) != 0) { 607 return; 608 } 609 610 /* 611 * wait for it to become ready 612 */ 613 for (i = 100000; (!(ci->ci_flags & CPUF_PRESENT)) && i > 0; i--) { 614 delay(10); 615 } 616 if ((ci->ci_flags & CPUF_PRESENT) == 0) { 617 aprint_error_dev(ci->ci_dev, "failed to become ready\n"); 618 #if defined(MPDEBUG) && defined(DDB) 619 printf("dropping into debugger; continue from here to resume boot\n"); 620 Debugger(); 621 #endif 622 } 623 624 CPU_START_CLEANUP(ci); 625 } 626 627 void 628 cpu_boot_secondary(struct cpu_info *ci) 629 { 630 int i; 631 atomic_or_32(&ci->ci_flags, CPUF_GO); 632 for (i = 100000; (!(ci->ci_flags & CPUF_RUNNING)) && i > 0; i--) { 633 delay(10); 634 } 635 if ((ci->ci_flags & CPUF_RUNNING) == 0) { 636 aprint_error_dev(ci->ci_dev, "CPU failed to start\n"); 637 #if defined(MPDEBUG) && defined(DDB) 638 printf("dropping into debugger; continue from here to resume boot\n"); 639 Debugger(); 640 #endif 641 } 642 } 643 644 /* 645 * APs end up here immediately after initialisation and VCPUOP_up in 646 * mp_cpu_start(). 647 * At this point, we are running in the idle pcb/idle stack of the new 648 * CPU. This function jumps to the idle loop and starts looking for 649 * work. 650 */ 651 extern void x86_64_tls_switch(struct lwp *); 652 void 653 cpu_hatch(void *v) 654 { 655 struct cpu_info *ci = (struct cpu_info *)v; 656 struct pcb *pcb; 657 int s, i; 658 659 /* Setup TLS and kernel GS/FS */ 660 cpu_init_msrs(ci, true); 661 cpu_init_idt(); 662 gdt_init_cpu(ci); 663 664 cpu_probe(ci); 665 666 atomic_or_32(&ci->ci_flags, CPUF_PRESENT); 667 668 while ((ci->ci_flags & CPUF_GO) == 0) { 669 /* Don't use delay, boot CPU may be patching the text. */ 670 for (i = 10000; i != 0; i--) 671 x86_pause(); 672 } 673 674 /* Because the text may have been patched in x86_patch(). */ 675 x86_flush(); 676 tlbflushg(); 677 678 KASSERT((ci->ci_flags & CPUF_RUNNING) == 0); 679 680 pcb = lwp_getpcb(curlwp); 681 pcb->pcb_cr3 = pmap_pdirpa(pmap_kernel(), 0); 682 pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp); 683 684 xen_ipi_init(); 685 686 xen_initclocks(); 687 688 #ifdef __x86_64__ 689 fpuinit(ci); 690 #endif 691 692 lldt(GSEL(GLDT_SEL, SEL_KPL)); 693 694 cpu_init(ci); 695 cpu_get_tsc_freq(ci); 696 697 s = splhigh(); 698 x86_enable_intr(); 699 splx(s); 700 701 aprint_debug_dev(ci->ci_dev, "running\n"); 702 703 cpu_switchto(NULL, ci->ci_data.cpu_idlelwp, true); 704 705 idle_loop(NULL); 706 KASSERT(false); 707 } 708 709 #if defined(DDB) 710 711 #include <ddb/db_output.h> 712 #include <machine/db_machdep.h> 713 714 /* 715 * Dump CPU information from ddb. 716 */ 717 void 718 cpu_debug_dump(void) 719 { 720 struct cpu_info *ci; 721 CPU_INFO_ITERATOR cii; 722 723 db_printf("addr dev id flags ipis curlwp fpcurlwp\n"); 724 for (CPU_INFO_FOREACH(cii, ci)) { 725 db_printf("%p %s %ld %x %x %10p %10p\n", 726 ci, 727 ci->ci_dev == NULL ? "BOOT" : device_xname(ci->ci_dev), 728 (long)ci->ci_cpuid, 729 ci->ci_flags, ci->ci_ipis, 730 ci->ci_curlwp, 731 ci->ci_fpcurlwp); 732 } 733 } 734 #endif /* DDB */ 735 736 #endif /* MULTIPROCESSOR */ 737 738 extern void hypervisor_callback(void); 739 extern void failsafe_callback(void); 740 #ifdef __x86_64__ 741 typedef void (vector)(void); 742 extern vector Xsyscall, Xsyscall32; 743 #endif 744 745 /* 746 * Setup the "trampoline". On Xen, we setup nearly all cpu context 747 * outside a trampoline, so we prototype and call targetip like so: 748 * void targetip(struct cpu_info *); 749 */ 750 751 static void 752 gdt_prepframes(paddr_t *frames, vaddr_t base, uint32_t entries) 753 { 754 int i; 755 for (i = 0; i < entries; i++) { 756 frames[i] = ((paddr_t)xpmap_ptetomach( 757 (pt_entry_t *)(base + (i << PAGE_SHIFT)))) >> PAGE_SHIFT; 758 759 /* Mark Read-only */ 760 pmap_pte_clearbits(kvtopte(base + (i << PAGE_SHIFT)), 761 PG_RW); 762 } 763 } 764 765 #ifdef __x86_64__ 766 extern char *ldtstore; 767 768 static void 769 xen_init_amd64_vcpuctxt(struct cpu_info *ci, struct vcpu_guest_context *initctx, 770 void targetrip(struct cpu_info *)) 771 { 772 /* page frames to point at GDT */ 773 extern int gdt_size; 774 paddr_t frames[16]; 775 psize_t gdt_ents; 776 777 struct lwp *l; 778 struct pcb *pcb; 779 780 volatile struct vcpu_info *vci; 781 782 KASSERT(ci != NULL); 783 KASSERT(ci != &cpu_info_primary); 784 KASSERT(initctx != NULL); 785 KASSERT(targetrip != NULL); 786 787 memset(initctx, 0, sizeof(*initctx)); 788 789 gdt_ents = roundup(gdt_size, PAGE_SIZE) >> PAGE_SHIFT; 790 KASSERT(gdt_ents <= 16); 791 792 gdt_prepframes(frames, (vaddr_t)ci->ci_gdt, gdt_ents); 793 794 /* Initialise the vcpu context: We use idle_loop()'s pcb context. */ 795 796 l = ci->ci_data.cpu_idlelwp; 797 798 KASSERT(l != NULL); 799 pcb = lwp_getpcb(l); 800 KASSERT(pcb != NULL); 801 802 /* resume with interrupts off */ 803 vci = ci->ci_vcpu; 804 vci->evtchn_upcall_mask = 1; 805 xen_mb(); 806 807 /* resume in kernel-mode */ 808 initctx->flags = VGCF_in_kernel | VGCF_online; 809 810 /* Stack and entry points: 811 * We arrange for the stack frame for cpu_hatch() to 812 * appear as a callee frame of lwp_trampoline(). Being a 813 * leaf frame prevents trampling on any of the MD stack setup 814 * that x86/vm_machdep.c:cpu_lwp_fork() does for idle_loop() 815 */ 816 817 initctx->user_regs.rdi = (uint64_t) ci; /* targetrip(ci); */ 818 initctx->user_regs.rip = (vaddr_t) targetrip; 819 820 initctx->user_regs.cs = GSEL(GCODE_SEL, SEL_KPL); 821 822 initctx->user_regs.rflags = pcb->pcb_flags; 823 initctx->user_regs.rsp = pcb->pcb_rsp; 824 825 /* Data segments */ 826 initctx->user_regs.ss = GSEL(GDATA_SEL, SEL_KPL); 827 initctx->user_regs.es = GSEL(GDATA_SEL, SEL_KPL); 828 initctx->user_regs.ds = GSEL(GDATA_SEL, SEL_KPL); 829 830 /* GDT */ 831 memcpy(initctx->gdt_frames, frames, sizeof(frames)); 832 initctx->gdt_ents = gdt_ents; 833 834 /* LDT */ 835 initctx->ldt_base = (unsigned long)ldtstore; 836 initctx->ldt_ents = LDT_SIZE >> 3; 837 838 /* Kernel context state */ 839 initctx->kernel_ss = GSEL(GDATA_SEL, SEL_KPL); 840 initctx->kernel_sp = pcb->pcb_rsp0; 841 initctx->ctrlreg[0] = pcb->pcb_cr0; 842 initctx->ctrlreg[1] = 0; /* "resuming" from kernel - no User cr3. */ 843 initctx->ctrlreg[2] = (vaddr_t)targetrip; 844 /* 845 * Use pmap_kernel() L4 PD directly, until we setup the 846 * per-cpu L4 PD in pmap_cpu_init_late() 847 */ 848 initctx->ctrlreg[3] = xen_pfn_to_cr3(x86_btop(xpmap_ptom(ci->ci_kpm_pdirpa))); 849 initctx->ctrlreg[4] = CR4_PAE | CR4_OSFXSR | CR4_OSXMMEXCPT; 850 851 /* Xen callbacks */ 852 initctx->event_callback_eip = (unsigned long)hypervisor_callback; 853 initctx->failsafe_callback_eip = (unsigned long)failsafe_callback; 854 initctx->syscall_callback_eip = (unsigned long)Xsyscall; 855 856 return; 857 } 858 #else /* i386 */ 859 extern union descriptor *ldtstore; 860 extern void Xsyscall(void); 861 862 static void 863 xen_init_i386_vcpuctxt(struct cpu_info *ci, struct vcpu_guest_context *initctx, 864 void targeteip(struct cpu_info *)) 865 { 866 /* page frames to point at GDT */ 867 extern int gdt_size; 868 paddr_t frames[16]; 869 psize_t gdt_ents; 870 871 struct lwp *l; 872 struct pcb *pcb; 873 874 volatile struct vcpu_info *vci; 875 876 KASSERT(ci != NULL); 877 KASSERT(ci != &cpu_info_primary); 878 KASSERT(initctx != NULL); 879 KASSERT(targeteip != NULL); 880 881 memset(initctx, 0, sizeof(*initctx)); 882 883 gdt_ents = roundup(gdt_size, PAGE_SIZE) >> PAGE_SHIFT; 884 KASSERT(gdt_ents <= 16); 885 886 gdt_prepframes(frames, (vaddr_t)ci->ci_gdt, gdt_ents); 887 888 /* 889 * Initialise the vcpu context: 890 * We use this cpu's idle_loop() pcb context. 891 */ 892 893 l = ci->ci_data.cpu_idlelwp; 894 895 KASSERT(l != NULL); 896 pcb = lwp_getpcb(l); 897 KASSERT(pcb != NULL); 898 899 /* resume with interrupts off */ 900 vci = ci->ci_vcpu; 901 vci->evtchn_upcall_mask = 1; 902 xen_mb(); 903 904 /* resume in kernel-mode */ 905 initctx->flags = VGCF_in_kernel | VGCF_online; 906 907 /* Stack frame setup for cpu_hatch(): 908 * We arrange for the stack frame for cpu_hatch() to 909 * appear as a callee frame of lwp_trampoline(). Being a 910 * leaf frame prevents trampling on any of the MD stack setup 911 * that x86/vm_machdep.c:cpu_lwp_fork() does for idle_loop() 912 */ 913 914 initctx->user_regs.esp = pcb->pcb_esp - 4; /* Leave word for 915 arg1 */ 916 { 917 /* targeteip(ci); */ 918 uint32_t *arg = (uint32_t *)initctx->user_regs.esp; 919 arg[1] = (uint32_t)ci; /* arg1 */ 920 } 921 922 initctx->user_regs.eip = (vaddr_t)targeteip; 923 initctx->user_regs.cs = GSEL(GCODE_SEL, SEL_KPL); 924 initctx->user_regs.eflags |= pcb->pcb_iopl; 925 926 /* Data segments */ 927 initctx->user_regs.ss = GSEL(GDATA_SEL, SEL_KPL); 928 initctx->user_regs.es = GSEL(GDATA_SEL, SEL_KPL); 929 initctx->user_regs.ds = GSEL(GDATA_SEL, SEL_KPL); 930 initctx->user_regs.fs = GSEL(GDATA_SEL, SEL_KPL); 931 932 /* GDT */ 933 memcpy(initctx->gdt_frames, frames, sizeof(frames)); 934 initctx->gdt_ents = gdt_ents; 935 936 /* LDT */ 937 initctx->ldt_base = (unsigned long)ldtstore; 938 initctx->ldt_ents = NLDT; 939 940 /* Kernel context state */ 941 initctx->kernel_ss = GSEL(GDATA_SEL, SEL_KPL); 942 initctx->kernel_sp = pcb->pcb_esp0; 943 initctx->ctrlreg[0] = pcb->pcb_cr0; 944 initctx->ctrlreg[1] = 0; /* "resuming" from kernel - no User cr3. */ 945 initctx->ctrlreg[2] = (vaddr_t)targeteip; 946 #ifdef PAE 947 initctx->ctrlreg[3] = xen_pfn_to_cr3(x86_btop(xpmap_ptom(ci->ci_pae_l3_pdirpa))); 948 #else 949 initctx->ctrlreg[3] = xen_pfn_to_cr3(x86_btop(xpmap_ptom(pcb->pcb_cr3))); 950 #endif 951 initctx->ctrlreg[4] = /* CR4_PAE | */CR4_OSFXSR | CR4_OSXMMEXCPT; 952 953 /* Xen callbacks */ 954 initctx->event_callback_eip = (unsigned long)hypervisor_callback; 955 initctx->event_callback_cs = GSEL(GCODE_SEL, SEL_KPL); 956 initctx->failsafe_callback_eip = (unsigned long)failsafe_callback; 957 initctx->failsafe_callback_cs = GSEL(GCODE_SEL, SEL_KPL); 958 959 return; 960 } 961 #endif /* __x86_64__ */ 962 963 int 964 mp_cpu_start(struct cpu_info *ci, vaddr_t target) 965 { 966 int hyperror; 967 struct vcpu_guest_context vcpuctx; 968 969 KASSERT(ci != NULL); 970 KASSERT(ci != &cpu_info_primary); 971 KASSERT(ci->ci_flags & CPUF_AP); 972 973 #ifdef __x86_64__ 974 xen_init_amd64_vcpuctxt(ci, &vcpuctx, (void (*)(struct cpu_info *))target); 975 #else 976 xen_init_i386_vcpuctxt(ci, &vcpuctx, (void (*)(struct cpu_info *))target); 977 #endif 978 979 /* Initialise the given vcpu to execute cpu_hatch(ci); */ 980 if ((hyperror = HYPERVISOR_vcpu_op(VCPUOP_initialise, ci->ci_cpuid, &vcpuctx))) { 981 aprint_error(": context initialisation failed. errno = %d\n", hyperror); 982 return hyperror; 983 } 984 985 /* Start it up */ 986 987 /* First bring it down */ 988 if ((hyperror = HYPERVISOR_vcpu_op(VCPUOP_down, ci->ci_cpuid, NULL))) { 989 aprint_error(": VCPUOP_down hypervisor command failed. errno = %d\n", hyperror); 990 return hyperror; 991 } 992 993 if ((hyperror = HYPERVISOR_vcpu_op(VCPUOP_up, ci->ci_cpuid, NULL))) { 994 aprint_error(": VCPUOP_up hypervisor command failed. errno = %d\n", hyperror); 995 return hyperror; 996 } 997 998 if (!vcpu_is_up(ci)) { 999 aprint_error(": did not come up\n"); 1000 return -1; 1001 } 1002 1003 return 0; 1004 } 1005 1006 void 1007 mp_cpu_start_cleanup(struct cpu_info *ci) 1008 { 1009 if (vcpu_is_up(ci)) { 1010 aprint_debug_dev(ci->ci_dev, "is started.\n"); 1011 } else { 1012 aprint_error_dev(ci->ci_dev, "did not start up.\n"); 1013 } 1014 } 1015 1016 void 1017 cpu_init_msrs(struct cpu_info *ci, bool full) 1018 { 1019 #ifdef __x86_64__ 1020 if (full) { 1021 HYPERVISOR_set_segment_base(SEGBASE_FS, 0); 1022 HYPERVISOR_set_segment_base(SEGBASE_GS_KERNEL, (uint64_t)ci); 1023 HYPERVISOR_set_segment_base(SEGBASE_GS_USER, 0); 1024 } 1025 #endif 1026 1027 if (cpu_feature[2] & CPUID_NOX) 1028 wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_NXE); 1029 } 1030 1031 void 1032 cpu_offline_md(void) 1033 { 1034 int s; 1035 1036 s = splhigh(); 1037 fpusave_cpu(true); 1038 splx(s); 1039 } 1040 1041 void 1042 cpu_get_tsc_freq(struct cpu_info *ci) 1043 { 1044 uint32_t vcpu_tversion; 1045 const volatile vcpu_time_info_t *tinfo = &ci->ci_vcpu->time; 1046 1047 vcpu_tversion = tinfo->version; 1048 while (tinfo->version == vcpu_tversion); /* Wait for a time update. XXX: timeout ? */ 1049 1050 uint64_t freq = 1000000000ULL << 32; 1051 freq = freq / (uint64_t)tinfo->tsc_to_system_mul; 1052 if (tinfo->tsc_shift < 0) 1053 freq = freq << -tinfo->tsc_shift; 1054 else 1055 freq = freq >> tinfo->tsc_shift; 1056 ci->ci_data.cpu_cc_freq = freq; 1057 } 1058 1059 void 1060 x86_cpu_idle_xen(void) 1061 { 1062 struct cpu_info *ci = curcpu(); 1063 1064 KASSERT(ci->ci_ilevel == IPL_NONE); 1065 1066 x86_disable_intr(); 1067 if (!__predict_false(ci->ci_want_resched)) { 1068 idle_block(); 1069 } else { 1070 x86_enable_intr(); 1071 } 1072 } 1073 1074 /* 1075 * Loads pmap for the current CPU. 1076 */ 1077 void 1078 cpu_load_pmap(struct pmap *pmap, struct pmap *oldpmap) 1079 { 1080 KASSERT(pmap != pmap_kernel()); 1081 1082 #if defined(__x86_64__) || defined(PAE) 1083 struct cpu_info *ci = curcpu(); 1084 cpuid_t cid = cpu_index(ci); 1085 1086 mutex_enter(&ci->ci_kpm_mtx); 1087 /* make new pmap visible to xen_kpm_sync() */ 1088 kcpuset_atomic_set(pmap->pm_xen_ptp_cpus, cid); 1089 #endif 1090 1091 #ifdef i386 1092 #ifdef PAE 1093 { 1094 int i; 1095 paddr_t l3_pd = xpmap_ptom_masked(ci->ci_pae_l3_pdirpa); 1096 /* don't update the kernel L3 slot */ 1097 for (i = 0 ; i < PDP_SIZE - 1; i++) { 1098 xpq_queue_pte_update(l3_pd + i * sizeof(pd_entry_t), 1099 xpmap_ptom(pmap->pm_pdirpa[i]) | PG_V); 1100 } 1101 tlbflush(); 1102 } 1103 #else /* PAE */ 1104 lcr3(pmap_pdirpa(pmap, 0)); 1105 #endif /* PAE */ 1106 #endif /* i386 */ 1107 1108 #ifdef __x86_64__ 1109 { 1110 int i; 1111 pd_entry_t *new_pgd; 1112 paddr_t l4_pd_ma; 1113 1114 l4_pd_ma = xpmap_ptom_masked(ci->ci_kpm_pdirpa); 1115 1116 /* 1117 * Map user space address in kernel space and load 1118 * user cr3 1119 */ 1120 new_pgd = pmap->pm_pdir; 1121 KASSERT(pmap == ci->ci_pmap); 1122 1123 /* Copy user pmap L4 PDEs (in user addr. range) to per-cpu L4 */ 1124 for (i = 0; i < PDIR_SLOT_PTE; i++) { 1125 KASSERT(pmap != pmap_kernel() || new_pgd[i] == 0); 1126 if (ci->ci_kpm_pdir[i] != new_pgd[i]) { 1127 xpq_queue_pte_update( 1128 l4_pd_ma + i * sizeof(pd_entry_t), 1129 new_pgd[i]); 1130 } 1131 } 1132 1133 xen_set_user_pgd(pmap_pdirpa(pmap, 0)); 1134 ci->ci_xen_current_user_pgd = pmap_pdirpa(pmap, 0); 1135 1136 tlbflush(); 1137 } 1138 #endif /* __x86_64__ */ 1139 1140 #if defined(__x86_64__) || defined(PAE) 1141 /* old pmap no longer visible to xen_kpm_sync() */ 1142 if (oldpmap != pmap_kernel()) { 1143 kcpuset_atomic_clear(oldpmap->pm_xen_ptp_cpus, cid); 1144 } 1145 mutex_exit(&ci->ci_kpm_mtx); 1146 #endif 1147 } 1148 1149 /* 1150 * pmap_cpu_init_late: perform late per-CPU initialization. 1151 * 1152 * Short note about percpu PDIR pages. Both the PAE and __x86_64__ architectures 1153 * have per-cpu PDIR tables, for two different reasons: 1154 * - on PAE, this is to get around Xen's pagetable setup constraints (multiple 1155 * L3[3]s cannot point to the same L2 - Xen will refuse to pin a table set up 1156 * this way). 1157 * - on __x86_64__, this is for multiple CPUs to map in different user pmaps 1158 * (see cpu_load_pmap()). 1159 * 1160 * What this means for us is that the PDIR of the pmap_kernel() is considered 1161 * to be a canonical "SHADOW" PDIR with the following properties: 1162 * - its recursive mapping points to itself 1163 * - per-cpu recursive mappings point to themselves on __x86_64__ 1164 * - per-cpu L4 pages' kernel entries are expected to be in sync with 1165 * the shadow 1166 */ 1167 1168 void 1169 pmap_cpu_init_late(struct cpu_info *ci) 1170 { 1171 #if defined(PAE) || defined(__x86_64__) 1172 /* 1173 * The BP has already its own PD page allocated during early 1174 * MD startup. 1175 */ 1176 1177 #if defined(__x86_64__) 1178 /* Setup per-cpu normal_pdes */ 1179 int i; 1180 extern pd_entry_t * const normal_pdes[]; 1181 for (i = 0;i < PTP_LEVELS - 1;i++) { 1182 ci->ci_normal_pdes[i] = normal_pdes[i]; 1183 } 1184 #endif /* __x86_64__ */ 1185 1186 if (ci == &cpu_info_primary) 1187 return; 1188 1189 KASSERT(ci != NULL); 1190 1191 #if defined(PAE) 1192 cpu_alloc_l3_page(ci); 1193 KASSERT(ci->ci_pae_l3_pdirpa != 0); 1194 1195 /* Initialise L2 entries 0 - 2: Point them to pmap_kernel() */ 1196 int i; 1197 for (i = 0 ; i < PDP_SIZE - 1; i++) { 1198 ci->ci_pae_l3_pdir[i] = 1199 xpmap_ptom_masked(pmap_kernel()->pm_pdirpa[i]) | PG_V; 1200 } 1201 #endif /* PAE */ 1202 1203 ci->ci_kpm_pdir = (pd_entry_t *)uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 1204 UVM_KMF_WIRED | UVM_KMF_ZERO | UVM_KMF_NOWAIT); 1205 1206 if (ci->ci_kpm_pdir == NULL) { 1207 panic("%s: failed to allocate L4 per-cpu PD for CPU %d\n", 1208 __func__, cpu_index(ci)); 1209 } 1210 ci->ci_kpm_pdirpa = vtophys((vaddr_t)ci->ci_kpm_pdir); 1211 KASSERT(ci->ci_kpm_pdirpa != 0); 1212 1213 #if defined(__x86_64__) 1214 extern pt_entry_t xpmap_pg_nx; 1215 1216 /* Copy over the pmap_kernel() shadow L4 entries */ 1217 memcpy(ci->ci_kpm_pdir, pmap_kernel()->pm_pdir, PAGE_SIZE); 1218 1219 /* Recursive kernel mapping */ 1220 ci->ci_kpm_pdir[PDIR_SLOT_PTE] = xpmap_ptom_masked(ci->ci_kpm_pdirpa) 1221 | PG_V | xpmap_pg_nx; 1222 #elif defined(PAE) 1223 /* Copy over the pmap_kernel() shadow L2 entries */ 1224 memcpy(ci->ci_kpm_pdir, pmap_kernel()->pm_pdir + PDIR_SLOT_KERN, 1225 nkptp[PTP_LEVELS - 1] * sizeof(pd_entry_t)); 1226 #endif 1227 1228 /* Xen wants a RO pdir. */ 1229 pmap_protect(pmap_kernel(), (vaddr_t)ci->ci_kpm_pdir, 1230 (vaddr_t)ci->ci_kpm_pdir + PAGE_SIZE, VM_PROT_READ); 1231 pmap_update(pmap_kernel()); 1232 #if defined(PAE) 1233 /* 1234 * Initialize L3 entry 3. This mapping is shared across all pmaps and is 1235 * static, ie: loading a new pmap will not update this entry. 1236 */ 1237 ci->ci_pae_l3_pdir[3] = xpmap_ptom_masked(ci->ci_kpm_pdirpa) | PG_V; 1238 1239 /* Xen wants a RO L3. */ 1240 pmap_protect(pmap_kernel(), (vaddr_t)ci->ci_pae_l3_pdir, 1241 (vaddr_t)ci->ci_pae_l3_pdir + PAGE_SIZE, VM_PROT_READ); 1242 pmap_update(pmap_kernel()); 1243 1244 xpq_queue_pin_l3_table(xpmap_ptom_masked(ci->ci_pae_l3_pdirpa)); 1245 1246 #elif defined(__x86_64__) 1247 xpq_queue_pin_l4_table(xpmap_ptom_masked(ci->ci_kpm_pdirpa)); 1248 #endif /* PAE , __x86_64__ */ 1249 #endif /* defined(PAE) || defined(__x86_64__) */ 1250 } 1251 1252 /* 1253 * Notify all other cpus to halt. 1254 */ 1255 1256 void 1257 cpu_broadcast_halt(void) 1258 { 1259 xen_broadcast_ipi(XEN_IPI_HALT); 1260 } 1261 1262 /* 1263 * Send a dummy ipi to a cpu. 1264 */ 1265 1266 void 1267 cpu_kick(struct cpu_info *ci) 1268 { 1269 (void)xen_send_ipi(ci, XEN_IPI_KICK); 1270 } 1271
Indexes created Fri Oct 03 17:10:05 GMT 2025