cpu.c revision 1.123
1 /* $NetBSD: cpu.c,v 1.123 2018/07/24 12:24:45 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * Copyright (c) 2002, 2006, 2007 YAMAMOTO Takashi, 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by RedBack Networks Inc. 10 * 11 * Author: Bill Sommerfeld 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * Copyright (c) 1999 Stefan Grefen 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by the NetBSD 49 * Foundation, Inc. and its contributors. 50 * 4. Neither the name of The NetBSD Foundation nor the names of its 51 * contributors may be used to endorse or promote products derived 52 * from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 55 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 56 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 57 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE 58 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 59 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 60 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 62 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 63 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.123 2018/07/24 12:24:45 bouyer Exp $"); 69 70 #include "opt_ddb.h" 71 #include "opt_multiprocessor.h" 72 #include "opt_mpbios.h" /* for MPDEBUG */ 73 #include "opt_mtrr.h" 74 #include "opt_xen.h" 75 76 #include "lapic.h" 77 #include "ioapic.h" 78 79 #include <sys/param.h> 80 #include <sys/proc.h> 81 #include <sys/systm.h> 82 #include <sys/device.h> 83 #include <sys/kmem.h> 84 #include <sys/cpu.h> 85 #include <sys/cpufreq.h> 86 #include <sys/atomic.h> 87 #include <sys/reboot.h> 88 #include <sys/idle.h> 89 90 #include <uvm/uvm.h> 91 92 #include <machine/cpu.h> 93 #include <machine/cpufunc.h> 94 #include <machine/cpuvar.h> 95 #include <machine/pmap.h> 96 #include <machine/vmparam.h> 97 #include <machine/mpbiosvar.h> 98 #include <machine/pcb.h> 99 #include <machine/specialreg.h> 100 #include <machine/segments.h> 101 #include <machine/gdt.h> 102 #include <machine/mtrr.h> 103 #include <machine/pio.h> 104 105 #include <x86/fpu.h> 106 107 #include <xen/xen.h> 108 #include <xen/xen-public/vcpu.h> 109 #include <xen/vcpuvar.h> 110 111 #if NLAPIC > 0 112 #include <machine/apicvar.h> 113 #include <machine/i82489reg.h> 114 #include <machine/i82489var.h> 115 #endif 116 117 #include <dev/ic/mc146818reg.h> 118 #include <dev/isa/isareg.h> 119 120 static int cpu_match(device_t, cfdata_t, void *); 121 static void cpu_attach(device_t, device_t, void *); 122 static void cpu_defer(device_t); 123 static int cpu_rescan(device_t, const char *, const int *); 124 static void cpu_childdetached(device_t, device_t); 125 static int vcpu_match(device_t, cfdata_t, void *); 126 static void vcpu_attach(device_t, device_t, void *); 127 static void cpu_attach_common(device_t, device_t, void *); 128 void cpu_offline_md(void); 129 130 struct cpu_softc { 131 device_t sc_dev; /* device tree glue */ 132 struct cpu_info *sc_info; /* pointer to CPU info */ 133 bool sc_wasonline; 134 }; 135 136 int mp_cpu_start(struct cpu_info *, vaddr_t); 137 void mp_cpu_start_cleanup(struct cpu_info *); 138 const struct cpu_functions mp_cpu_funcs = { mp_cpu_start, NULL, 139 mp_cpu_start_cleanup }; 140 141 CFATTACH_DECL2_NEW(cpu, sizeof(struct cpu_softc), 142 cpu_match, cpu_attach, NULL, NULL, cpu_rescan, cpu_childdetached); 143 144 CFATTACH_DECL_NEW(vcpu, sizeof(struct cpu_softc), 145 vcpu_match, vcpu_attach, NULL, NULL); 146 147 /* 148 * Statically-allocated CPU info for the primary CPU (or the only 149 * CPU, on uniprocessors). The CPU info list is initialized to 150 * point at it. 151 */ 152 struct cpu_info cpu_info_primary __aligned(CACHE_LINE_SIZE) = { 153 .ci_dev = 0, 154 .ci_self = &cpu_info_primary, 155 .ci_idepth = -1, 156 .ci_curlwp = &lwp0, 157 .ci_curldt = -1, 158 }; 159 struct cpu_info phycpu_info_primary __aligned(CACHE_LINE_SIZE) = { 160 .ci_dev = 0, 161 .ci_self = &phycpu_info_primary, 162 }; 163 164 struct cpu_info *cpu_info_list = &cpu_info_primary; 165 struct cpu_info *phycpu_info_list = &phycpu_info_primary; 166 167 uint32_t cpu_feature[7] __read_mostly; /* X86 CPUID feature bits 168 * [0] basic features %edx 169 * [1] basic features %ecx 170 * [2] extended features %edx 171 * [3] extended features %ecx 172 * [4] VIA padlock features 173 * [5] structured extended features cpuid.7:%ebx 174 * [6] structured extended features cpuid.7:%ecx 175 */ 176 177 bool x86_mp_online; 178 paddr_t mp_trampoline_paddr = MP_TRAMPOLINE; 179 180 #if defined(MULTIPROCESSOR) 181 void cpu_hatch(void *); 182 static void cpu_boot_secondary(struct cpu_info *ci); 183 static void cpu_start_secondary(struct cpu_info *ci); 184 #endif /* MULTIPROCESSOR */ 185 186 static int 187 cpu_match(device_t parent, cfdata_t match, void *aux) 188 { 189 190 return 1; 191 } 192 193 static void 194 cpu_attach(device_t parent, device_t self, void *aux) 195 { 196 struct cpu_softc *sc = device_private(self); 197 struct cpu_attach_args *caa = aux; 198 struct cpu_info *ci; 199 uintptr_t ptr; 200 static int nphycpu = 0; 201 202 sc->sc_dev = self; 203 204 /* 205 * If we're an Application Processor, allocate a cpu_info 206 * If we're the first attached CPU use the primary cpu_info, 207 * otherwise allocate a new one 208 */ 209 aprint_naive("\n"); 210 aprint_normal("\n"); 211 if (nphycpu > 0) { 212 struct cpu_info *tmp; 213 ptr = (uintptr_t)kmem_zalloc(sizeof(*ci) + CACHE_LINE_SIZE - 1, 214 KM_SLEEP); 215 ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE); 216 ci->ci_curldt = -1; 217 218 tmp = phycpu_info_list; 219 while (tmp->ci_next) 220 tmp = tmp->ci_next; 221 222 tmp->ci_next = ci; 223 } else { 224 ci = &phycpu_info_primary; 225 } 226 227 ci->ci_self = ci; 228 sc->sc_info = ci; 229 230 ci->ci_dev = self; 231 ci->ci_acpiid = caa->cpu_id; 232 ci->ci_cpuid = caa->cpu_number; 233 ci->ci_vcpu = NULL; 234 ci->ci_index = nphycpu++; 235 236 if (!pmf_device_register(self, NULL, NULL)) 237 aprint_error_dev(self, "couldn't establish power handler\n"); 238 239 (void)config_defer(self, cpu_defer); 240 } 241 242 static void 243 cpu_defer(device_t self) 244 { 245 cpu_rescan(self, NULL, NULL); 246 } 247 248 static int 249 cpu_rescan(device_t self, const char *ifattr, const int *locators) 250 { 251 struct cpu_softc *sc = device_private(self); 252 struct cpufeature_attach_args cfaa; 253 struct cpu_info *ci = sc->sc_info; 254 255 memset(&cfaa, 0, sizeof(cfaa)); 256 cfaa.ci = ci; 257 258 if (ifattr_match(ifattr, "cpufeaturebus")) { 259 260 if (ci->ci_frequency == NULL) { 261 cfaa.name = "frequency"; 262 ci->ci_frequency = config_found_ia(self, 263 "cpufeaturebus", &cfaa, NULL); 264 } 265 } 266 267 return 0; 268 } 269 270 static void 271 cpu_childdetached(device_t self, device_t child) 272 { 273 struct cpu_softc *sc = device_private(self); 274 struct cpu_info *ci = sc->sc_info; 275 276 if (ci->ci_frequency == child) 277 ci->ci_frequency = NULL; 278 } 279 280 static int 281 vcpu_match(device_t parent, cfdata_t match, void *aux) 282 { 283 struct vcpu_attach_args *vcaa = aux; 284 struct vcpu_runstate_info vcr; 285 int error; 286 287 if (strcmp(vcaa->vcaa_name, match->cf_name) == 0) { 288 error = HYPERVISOR_vcpu_op(VCPUOP_get_runstate_info, 289 vcaa->vcaa_caa.cpu_number, &vcr); 290 switch (error) { 291 case 0: 292 return 1; 293 case -ENOENT: 294 return 0; 295 default: 296 panic("Unknown hypervisor error %d returned on vcpu runstate probe\n", error); 297 } 298 } 299 300 return 0; 301 } 302 303 static void 304 vcpu_attach(device_t parent, device_t self, void *aux) 305 { 306 struct vcpu_attach_args *vcaa = aux; 307 308 KASSERT(vcaa->vcaa_caa.cpu_func == NULL); 309 vcaa->vcaa_caa.cpu_func = &mp_cpu_funcs; 310 cpu_attach_common(parent, self, &vcaa->vcaa_caa); 311 312 if (!pmf_device_register(self, NULL, NULL)) 313 aprint_error_dev(self, "couldn't establish power handler\n"); 314 } 315 316 static int 317 vcpu_is_up(struct cpu_info *ci) 318 { 319 KASSERT(ci != NULL); 320 return HYPERVISOR_vcpu_op(VCPUOP_is_up, ci->ci_cpuid, NULL); 321 } 322 323 static void 324 cpu_vm_init(struct cpu_info *ci) 325 { 326 int ncolors = 2, i; 327 328 for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) { 329 struct x86_cache_info *cai; 330 int tcolors; 331 332 cai = &ci->ci_cinfo[i]; 333 334 tcolors = atop(cai->cai_totalsize); 335 switch (cai->cai_associativity) { 336 case 0xff: 337 tcolors = 1; /* fully associative */ 338 break; 339 case 0: 340 case 1: 341 break; 342 default: 343 tcolors /= cai->cai_associativity; 344 } 345 ncolors = max(ncolors, tcolors); 346 } 347 348 /* 349 * Knowing the size of the largest cache on this CPU, potentially 350 * re-color our pages. 351 */ 352 aprint_debug_dev(ci->ci_dev, "%d page colors\n", ncolors); 353 uvm_page_recolor(ncolors); 354 pmap_tlb_cpu_init(ci); 355 #ifndef __HAVE_DIRECT_MAP 356 pmap_vpage_cpu_init(ci); 357 #endif 358 } 359 360 static void 361 cpu_attach_common(device_t parent, device_t self, void *aux) 362 { 363 struct cpu_softc *sc = device_private(self); 364 struct cpu_attach_args *caa = aux; 365 struct cpu_info *ci; 366 uintptr_t ptr; 367 int cpunum = caa->cpu_number; 368 static bool again = false; 369 370 sc->sc_dev = self; 371 372 /* 373 * If we're an Application Processor, allocate a cpu_info 374 * structure, otherwise use the primary's. 375 */ 376 if (caa->cpu_role == CPU_ROLE_AP) { 377 aprint_naive(": Application Processor\n"); 378 ptr = (uintptr_t)kmem_alloc(sizeof(*ci) + CACHE_LINE_SIZE - 1, 379 KM_SLEEP); 380 ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE); 381 memset(ci, 0, sizeof(*ci)); 382 cpu_init_tss(ci); 383 } else { 384 aprint_naive(": %s Processor\n", 385 caa->cpu_role == CPU_ROLE_SP ? "Single" : "Boot"); 386 ci = &cpu_info_primary; 387 } 388 389 ci->ci_self = ci; 390 sc->sc_info = ci; 391 ci->ci_dev = self; 392 ci->ci_cpuid = cpunum; 393 394 KASSERT(HYPERVISOR_shared_info != NULL); 395 KASSERT(cpunum < XEN_LEGACY_MAX_VCPUS); 396 ci->ci_vcpu = &HYPERVISOR_shared_info->vcpu_info[cpunum]; 397 398 KASSERT(ci->ci_func == 0); 399 ci->ci_func = caa->cpu_func; 400 aprint_normal("\n"); 401 402 /* Must be called before mi_cpu_attach(). */ 403 cpu_vm_init(ci); 404 405 if (caa->cpu_role == CPU_ROLE_AP) { 406 int error; 407 408 error = mi_cpu_attach(ci); 409 410 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 411 if (error != 0) { 412 aprint_error_dev(self, 413 "mi_cpu_attach failed with %d\n", error); 414 return; 415 } 416 417 } else { 418 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 419 } 420 421 KASSERT(ci->ci_cpuid == ci->ci_index); 422 #ifdef __x86_64__ 423 /* No user PGD mapped for this CPU yet */ 424 ci->ci_xen_current_user_pgd = 0; 425 #endif 426 #if defined(__x86_64__) || defined(PAE) 427 mutex_init(&ci->ci_kpm_mtx, MUTEX_DEFAULT, IPL_VM); 428 #endif 429 pmap_reference(pmap_kernel()); 430 ci->ci_pmap = pmap_kernel(); 431 ci->ci_tlbstate = TLBSTATE_STALE; 432 433 /* 434 * Boot processor may not be attached first, but the below 435 * must be done to allow booting other processors. 436 */ 437 if (!again) { 438 atomic_or_32(&ci->ci_flags, CPUF_PRESENT | CPUF_PRIMARY); 439 /* Basic init. */ 440 cpu_intr_init(ci); 441 cpu_get_tsc_freq(ci); 442 cpu_init(ci); 443 pmap_cpu_init_late(ci); 444 445 /* Every processor needs to init its own ipi h/w (similar to lapic) */ 446 xen_ipi_init(); 447 448 /* Make sure DELAY() is initialized. */ 449 DELAY(1); 450 again = true; 451 } 452 453 /* further PCB init done later. */ 454 455 switch (caa->cpu_role) { 456 case CPU_ROLE_SP: 457 atomic_or_32(&ci->ci_flags, CPUF_SP); 458 cpu_identify(ci); 459 x86_cpu_idle_init(); 460 break; 461 462 case CPU_ROLE_BP: 463 atomic_or_32(&ci->ci_flags, CPUF_BSP); 464 cpu_identify(ci); 465 x86_cpu_idle_init(); 466 break; 467 468 case CPU_ROLE_AP: 469 atomic_or_32(&ci->ci_flags, CPUF_AP); 470 471 /* 472 * report on an AP 473 */ 474 475 #if defined(MULTIPROCESSOR) 476 /* interrupt handler stack */ 477 cpu_intr_init(ci); 478 479 /* Setup per-cpu memory for gdt */ 480 gdt_alloc_cpu(ci); 481 482 pmap_cpu_init_late(ci); 483 cpu_start_secondary(ci); 484 485 if (ci->ci_flags & CPUF_PRESENT) { 486 struct cpu_info *tmp; 487 488 cpu_identify(ci); 489 tmp = cpu_info_list; 490 while (tmp->ci_next) 491 tmp = tmp->ci_next; 492 493 tmp->ci_next = ci; 494 } 495 #else 496 aprint_error_dev(ci->ci_dev, "not started\n"); 497 #endif 498 break; 499 500 default: 501 panic("unknown processor type??\n"); 502 } 503 504 #ifdef MPVERBOSE 505 if (mp_verbose) { 506 struct lwp *l = ci->ci_data.cpu_idlelwp; 507 struct pcb *pcb = lwp_getpcb(l); 508 509 aprint_verbose_dev(self, 510 "idle lwp at %p, idle sp at 0x%p\n", 511 l, 512 #ifdef i386 513 (void *)pcb->pcb_esp 514 #else 515 (void *)pcb->pcb_rsp 516 #endif 517 ); 518 519 } 520 #endif /* MPVERBOSE */ 521 } 522 523 /* 524 * Initialize the processor appropriately. 525 */ 526 527 void 528 cpu_init(struct cpu_info *ci) 529 { 530 uint32_t cr4 = 0; 531 532 /* 533 * If we have FXSAVE/FXRESTOR, use them. 534 */ 535 if (cpu_feature[0] & CPUID_FXSR) { 536 cr4 |= CR4_OSFXSR; 537 538 /* 539 * If we have SSE/SSE2, enable XMM exceptions. 540 */ 541 if (cpu_feature[0] & (CPUID_SSE|CPUID_SSE2)) 542 cr4 |= CR4_OSXMMEXCPT; 543 } 544 545 /* If xsave is supported, enable it */ 546 if (cpu_feature[1] & CPUID2_XSAVE && x86_fpu_save >= FPU_SAVE_XSAVE) 547 cr4 |= CR4_OSXSAVE; 548 549 if (cr4) { 550 cr4 |= rcr4(); 551 lcr4(cr4); 552 } 553 554 if (x86_fpu_save >= FPU_SAVE_FXSAVE) { 555 fpuinit_mxcsr_mask(); 556 } 557 558 /* 559 * Changing CR4 register may change cpuid values. For example, setting 560 * CR4_OSXSAVE sets CPUID2_OSXSAVE. The CPUID2_OSXSAVE is in 561 * ci_feat_val[1], so update it. 562 * XXX Other than ci_feat_val[1] might be changed. 563 */ 564 if (cpuid_level >= 1) { 565 u_int descs[4]; 566 567 x86_cpuid(1, descs); 568 ci->ci_feat_val[1] = descs[2]; 569 } 570 571 /* If xsave is enabled, enable all fpu features */ 572 if (cr4 & CR4_OSXSAVE) { 573 wrxcr(0, x86_xsave_features & XCR0_FPU); 574 } 575 576 atomic_or_32(&ci->ci_flags, CPUF_RUNNING); 577 } 578 579 580 #ifdef MULTIPROCESSOR 581 582 void 583 cpu_boot_secondary_processors(void) 584 { 585 struct cpu_info *ci; 586 kcpuset_t *cpus; 587 u_long i; 588 589 kcpuset_create(&cpus, true); 590 kcpuset_set(cpus, cpu_index(curcpu())); 591 for (i = 0; i < maxcpus; i++) { 592 ci = cpu_lookup(i); 593 if (ci == NULL) 594 continue; 595 if (ci->ci_data.cpu_idlelwp == NULL) 596 continue; 597 if ((ci->ci_flags & CPUF_PRESENT) == 0) 598 continue; 599 if (ci->ci_flags & (CPUF_BSP|CPUF_SP|CPUF_PRIMARY)) 600 continue; 601 cpu_boot_secondary(ci); 602 kcpuset_set(cpus, cpu_index(ci)); 603 } 604 while (!kcpuset_match(cpus, kcpuset_running)) 605 ; 606 kcpuset_destroy(cpus); 607 608 x86_mp_online = true; 609 } 610 611 static void 612 cpu_init_idle_lwp(struct cpu_info *ci) 613 { 614 struct lwp *l = ci->ci_data.cpu_idlelwp; 615 struct pcb *pcb = lwp_getpcb(l); 616 617 pcb->pcb_cr0 = rcr0(); 618 } 619 620 void 621 cpu_init_idle_lwps(void) 622 { 623 struct cpu_info *ci; 624 u_long i; 625 626 for (i = 0; i < maxcpus; i++) { 627 ci = cpu_lookup(i); 628 if (ci == NULL) 629 continue; 630 if (ci->ci_data.cpu_idlelwp == NULL) 631 continue; 632 if ((ci->ci_flags & CPUF_PRESENT) == 0) 633 continue; 634 cpu_init_idle_lwp(ci); 635 } 636 } 637 638 static void 639 cpu_start_secondary(struct cpu_info *ci) 640 { 641 int i; 642 643 aprint_debug_dev(ci->ci_dev, "starting\n"); 644 645 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 646 647 if (CPU_STARTUP(ci, (vaddr_t) cpu_hatch) != 0) { 648 return; 649 } 650 651 /* 652 * wait for it to become ready 653 */ 654 for (i = 100000; (!(ci->ci_flags & CPUF_PRESENT)) && i > 0; i--) { 655 delay(10); 656 } 657 if ((ci->ci_flags & CPUF_PRESENT) == 0) { 658 aprint_error_dev(ci->ci_dev, "failed to become ready\n"); 659 #if defined(MPDEBUG) && defined(DDB) 660 printf("dropping into debugger; continue from here to resume boot\n"); 661 Debugger(); 662 #endif 663 } 664 665 CPU_START_CLEANUP(ci); 666 } 667 668 void 669 cpu_boot_secondary(struct cpu_info *ci) 670 { 671 int i; 672 atomic_or_32(&ci->ci_flags, CPUF_GO); 673 for (i = 100000; (!(ci->ci_flags & CPUF_RUNNING)) && i > 0; i--) { 674 delay(10); 675 } 676 if ((ci->ci_flags & CPUF_RUNNING) == 0) { 677 aprint_error_dev(ci->ci_dev, "CPU failed to start\n"); 678 #if defined(MPDEBUG) && defined(DDB) 679 printf("dropping into debugger; continue from here to resume boot\n"); 680 Debugger(); 681 #endif 682 } 683 } 684 685 /* 686 * APs end up here immediately after initialisation and VCPUOP_up in 687 * mp_cpu_start(). 688 * At this point, we are running in the idle pcb/idle stack of the new 689 * CPU. This function jumps to the idle loop and starts looking for 690 * work. 691 */ 692 extern void x86_64_tls_switch(struct lwp *); 693 void 694 cpu_hatch(void *v) 695 { 696 struct cpu_info *ci = (struct cpu_info *)v; 697 struct pcb *pcb; 698 int s, i; 699 700 /* Setup TLS and kernel GS/FS */ 701 cpu_init_msrs(ci, true); 702 cpu_init_idt(); 703 gdt_init_cpu(ci); 704 705 cpu_probe(ci); 706 707 atomic_or_32(&ci->ci_flags, CPUF_PRESENT); 708 709 while ((ci->ci_flags & CPUF_GO) == 0) { 710 /* Don't use delay, boot CPU may be patching the text. */ 711 for (i = 10000; i != 0; i--) 712 x86_pause(); 713 } 714 715 /* Because the text may have been patched in x86_patch(). */ 716 x86_flush(); 717 tlbflushg(); 718 719 KASSERT((ci->ci_flags & CPUF_RUNNING) == 0); 720 721 pcb = lwp_getpcb(curlwp); 722 pcb->pcb_cr3 = pmap_pdirpa(pmap_kernel(), 0); 723 pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp); 724 725 xen_ipi_init(); 726 727 xen_initclocks(); 728 729 #ifdef __x86_64__ 730 fpuinit(ci); 731 #endif 732 733 lldt(GSEL(GLDT_SEL, SEL_KPL)); 734 735 cpu_init(ci); 736 cpu_get_tsc_freq(ci); 737 738 s = splhigh(); 739 x86_enable_intr(); 740 splx(s); 741 742 aprint_debug_dev(ci->ci_dev, "running\n"); 743 744 cpu_switchto(NULL, ci->ci_data.cpu_idlelwp, true); 745 746 idle_loop(NULL); 747 KASSERT(false); 748 } 749 750 #if defined(DDB) 751 752 #include <ddb/db_output.h> 753 #include <machine/db_machdep.h> 754 755 /* 756 * Dump CPU information from ddb. 757 */ 758 void 759 cpu_debug_dump(void) 760 { 761 struct cpu_info *ci; 762 CPU_INFO_ITERATOR cii; 763 764 db_printf("addr dev id flags ipis curlwp fpcurlwp\n"); 765 for (CPU_INFO_FOREACH(cii, ci)) { 766 db_printf("%p %s %ld %x %x %10p %10p\n", 767 ci, 768 ci->ci_dev == NULL ? "BOOT" : device_xname(ci->ci_dev), 769 (long)ci->ci_cpuid, 770 ci->ci_flags, ci->ci_ipis, 771 ci->ci_curlwp, 772 ci->ci_fpcurlwp); 773 } 774 } 775 #endif /* DDB */ 776 777 #endif /* MULTIPROCESSOR */ 778 779 extern void hypervisor_callback(void); 780 extern void failsafe_callback(void); 781 #ifdef __x86_64__ 782 typedef void (vector)(void); 783 extern vector Xsyscall, Xsyscall32; 784 #endif 785 786 /* 787 * Setup the "trampoline". On Xen, we setup nearly all cpu context 788 * outside a trampoline, so we prototype and call targetip like so: 789 * void targetip(struct cpu_info *); 790 */ 791 792 static void 793 gdt_prepframes(paddr_t *frames, vaddr_t base, uint32_t entries) 794 { 795 int i; 796 for (i = 0; i < entries; i++) { 797 frames[i] = ((paddr_t)xpmap_ptetomach( 798 (pt_entry_t *)(base + (i << PAGE_SHIFT)))) >> PAGE_SHIFT; 799 800 /* Mark Read-only */ 801 pmap_pte_clearbits(kvtopte(base + (i << PAGE_SHIFT)), 802 PG_RW); 803 } 804 } 805 806 #ifdef __x86_64__ 807 extern char *ldtstore; 808 809 static void 810 xen_init_amd64_vcpuctxt(struct cpu_info *ci, struct vcpu_guest_context *initctx, 811 void targetrip(struct cpu_info *)) 812 { 813 /* page frames to point at GDT */ 814 extern int gdt_size; 815 paddr_t frames[16]; 816 psize_t gdt_ents; 817 818 struct lwp *l; 819 struct pcb *pcb; 820 821 volatile struct vcpu_info *vci; 822 823 KASSERT(ci != NULL); 824 KASSERT(ci != &cpu_info_primary); 825 KASSERT(initctx != NULL); 826 KASSERT(targetrip != NULL); 827 828 memset(initctx, 0, sizeof(*initctx)); 829 830 gdt_ents = roundup(gdt_size, PAGE_SIZE) >> PAGE_SHIFT; 831 KASSERT(gdt_ents <= 16); 832 833 gdt_prepframes(frames, (vaddr_t)ci->ci_gdt, gdt_ents); 834 835 /* Initialise the vcpu context: We use idle_loop()'s pcb context. */ 836 837 l = ci->ci_data.cpu_idlelwp; 838 839 KASSERT(l != NULL); 840 pcb = lwp_getpcb(l); 841 KASSERT(pcb != NULL); 842 843 /* resume with interrupts off */ 844 vci = ci->ci_vcpu; 845 vci->evtchn_upcall_mask = 1; 846 xen_mb(); 847 848 /* resume in kernel-mode */ 849 initctx->flags = VGCF_in_kernel | VGCF_online; 850 851 /* Stack and entry points: 852 * We arrange for the stack frame for cpu_hatch() to 853 * appear as a callee frame of lwp_trampoline(). Being a 854 * leaf frame prevents trampling on any of the MD stack setup 855 * that x86/vm_machdep.c:cpu_lwp_fork() does for idle_loop() 856 */ 857 858 initctx->user_regs.rdi = (uint64_t) ci; /* targetrip(ci); */ 859 initctx->user_regs.rip = (vaddr_t) targetrip; 860 861 initctx->user_regs.cs = GSEL(GCODE_SEL, SEL_KPL); 862 863 initctx->user_regs.rflags = pcb->pcb_flags; 864 initctx->user_regs.rsp = pcb->pcb_rsp; 865 866 /* Data segments */ 867 initctx->user_regs.ss = GSEL(GDATA_SEL, SEL_KPL); 868 initctx->user_regs.es = GSEL(GDATA_SEL, SEL_KPL); 869 initctx->user_regs.ds = GSEL(GDATA_SEL, SEL_KPL); 870 871 /* GDT */ 872 memcpy(initctx->gdt_frames, frames, sizeof(frames)); 873 initctx->gdt_ents = gdt_ents; 874 875 /* LDT */ 876 initctx->ldt_base = (unsigned long)ldtstore; 877 initctx->ldt_ents = LDT_SIZE >> 3; 878 879 /* Kernel context state */ 880 initctx->kernel_ss = GSEL(GDATA_SEL, SEL_KPL); 881 initctx->kernel_sp = pcb->pcb_rsp0; 882 initctx->ctrlreg[0] = pcb->pcb_cr0; 883 initctx->ctrlreg[1] = 0; /* "resuming" from kernel - no User cr3. */ 884 initctx->ctrlreg[2] = (vaddr_t)targetrip; 885 /* 886 * Use pmap_kernel() L4 PD directly, until we setup the 887 * per-cpu L4 PD in pmap_cpu_init_late() 888 */ 889 initctx->ctrlreg[3] = xen_pfn_to_cr3(x86_btop(xpmap_ptom(ci->ci_kpm_pdirpa))); 890 initctx->ctrlreg[4] = CR4_PAE | CR4_OSFXSR | CR4_OSXMMEXCPT; 891 892 /* Xen callbacks */ 893 initctx->event_callback_eip = (unsigned long)hypervisor_callback; 894 initctx->failsafe_callback_eip = (unsigned long)failsafe_callback; 895 initctx->syscall_callback_eip = (unsigned long)Xsyscall; 896 897 return; 898 } 899 #else /* i386 */ 900 extern union descriptor *ldtstore; 901 extern void Xsyscall(void); 902 903 static void 904 xen_init_i386_vcpuctxt(struct cpu_info *ci, struct vcpu_guest_context *initctx, 905 void targeteip(struct cpu_info *)) 906 { 907 /* page frames to point at GDT */ 908 extern int gdt_size; 909 paddr_t frames[16]; 910 psize_t gdt_ents; 911 912 struct lwp *l; 913 struct pcb *pcb; 914 915 volatile struct vcpu_info *vci; 916 917 KASSERT(ci != NULL); 918 KASSERT(ci != &cpu_info_primary); 919 KASSERT(initctx != NULL); 920 KASSERT(targeteip != NULL); 921 922 memset(initctx, 0, sizeof(*initctx)); 923 924 gdt_ents = roundup(gdt_size, PAGE_SIZE) >> PAGE_SHIFT; 925 KASSERT(gdt_ents <= 16); 926 927 gdt_prepframes(frames, (vaddr_t)ci->ci_gdt, gdt_ents); 928 929 /* 930 * Initialise the vcpu context: 931 * We use this cpu's idle_loop() pcb context. 932 */ 933 934 l = ci->ci_data.cpu_idlelwp; 935 936 KASSERT(l != NULL); 937 pcb = lwp_getpcb(l); 938 KASSERT(pcb != NULL); 939 940 /* resume with interrupts off */ 941 vci = ci->ci_vcpu; 942 vci->evtchn_upcall_mask = 1; 943 xen_mb(); 944 945 /* resume in kernel-mode */ 946 initctx->flags = VGCF_in_kernel | VGCF_online; 947 948 /* Stack frame setup for cpu_hatch(): 949 * We arrange for the stack frame for cpu_hatch() to 950 * appear as a callee frame of lwp_trampoline(). Being a 951 * leaf frame prevents trampling on any of the MD stack setup 952 * that x86/vm_machdep.c:cpu_lwp_fork() does for idle_loop() 953 */ 954 955 initctx->user_regs.esp = pcb->pcb_esp - 4; /* Leave word for 956 arg1 */ 957 { 958 /* targeteip(ci); */ 959 uint32_t *arg = (uint32_t *)initctx->user_regs.esp; 960 arg[1] = (uint32_t)ci; /* arg1 */ 961 } 962 963 initctx->user_regs.eip = (vaddr_t)targeteip; 964 initctx->user_regs.cs = GSEL(GCODE_SEL, SEL_KPL); 965 initctx->user_regs.eflags |= pcb->pcb_iopl; 966 967 /* Data segments */ 968 initctx->user_regs.ss = GSEL(GDATA_SEL, SEL_KPL); 969 initctx->user_regs.es = GSEL(GDATA_SEL, SEL_KPL); 970 initctx->user_regs.ds = GSEL(GDATA_SEL, SEL_KPL); 971 initctx->user_regs.fs = GSEL(GDATA_SEL, SEL_KPL); 972 973 /* GDT */ 974 memcpy(initctx->gdt_frames, frames, sizeof(frames)); 975 initctx->gdt_ents = gdt_ents; 976 977 /* LDT */ 978 initctx->ldt_base = (unsigned long)ldtstore; 979 initctx->ldt_ents = NLDT; 980 981 /* Kernel context state */ 982 initctx->kernel_ss = GSEL(GDATA_SEL, SEL_KPL); 983 initctx->kernel_sp = pcb->pcb_esp0; 984 initctx->ctrlreg[0] = pcb->pcb_cr0; 985 initctx->ctrlreg[1] = 0; /* "resuming" from kernel - no User cr3. */ 986 initctx->ctrlreg[2] = (vaddr_t)targeteip; 987 #ifdef PAE 988 initctx->ctrlreg[3] = xen_pfn_to_cr3(x86_btop(xpmap_ptom(ci->ci_pae_l3_pdirpa))); 989 #else 990 initctx->ctrlreg[3] = xen_pfn_to_cr3(x86_btop(xpmap_ptom(pcb->pcb_cr3))); 991 #endif 992 initctx->ctrlreg[4] = /* CR4_PAE | */CR4_OSFXSR | CR4_OSXMMEXCPT; 993 994 /* Xen callbacks */ 995 initctx->event_callback_eip = (unsigned long)hypervisor_callback; 996 initctx->event_callback_cs = GSEL(GCODE_SEL, SEL_KPL); 997 initctx->failsafe_callback_eip = (unsigned long)failsafe_callback; 998 initctx->failsafe_callback_cs = GSEL(GCODE_SEL, SEL_KPL); 999 1000 return; 1001 } 1002 #endif /* __x86_64__ */ 1003 1004 int 1005 mp_cpu_start(struct cpu_info *ci, vaddr_t target) 1006 { 1007 int hyperror; 1008 struct vcpu_guest_context vcpuctx; 1009 1010 KASSERT(ci != NULL); 1011 KASSERT(ci != &cpu_info_primary); 1012 KASSERT(ci->ci_flags & CPUF_AP); 1013 1014 #ifdef __x86_64__ 1015 xen_init_amd64_vcpuctxt(ci, &vcpuctx, (void (*)(struct cpu_info *))target); 1016 #else 1017 xen_init_i386_vcpuctxt(ci, &vcpuctx, (void (*)(struct cpu_info *))target); 1018 #endif 1019 1020 /* Initialise the given vcpu to execute cpu_hatch(ci); */ 1021 if ((hyperror = HYPERVISOR_vcpu_op(VCPUOP_initialise, ci->ci_cpuid, &vcpuctx))) { 1022 aprint_error(": context initialisation failed. errno = %d\n", hyperror); 1023 return hyperror; 1024 } 1025 1026 /* Start it up */ 1027 1028 /* First bring it down */ 1029 if ((hyperror = HYPERVISOR_vcpu_op(VCPUOP_down, ci->ci_cpuid, NULL))) { 1030 aprint_error(": VCPUOP_down hypervisor command failed. errno = %d\n", hyperror); 1031 return hyperror; 1032 } 1033 1034 if ((hyperror = HYPERVISOR_vcpu_op(VCPUOP_up, ci->ci_cpuid, NULL))) { 1035 aprint_error(": VCPUOP_up hypervisor command failed. errno = %d\n", hyperror); 1036 return hyperror; 1037 } 1038 1039 if (!vcpu_is_up(ci)) { 1040 aprint_error(": did not come up\n"); 1041 return -1; 1042 } 1043 1044 return 0; 1045 } 1046 1047 void 1048 mp_cpu_start_cleanup(struct cpu_info *ci) 1049 { 1050 if (vcpu_is_up(ci)) { 1051 aprint_debug_dev(ci->ci_dev, "is started.\n"); 1052 } else { 1053 aprint_error_dev(ci->ci_dev, "did not start up.\n"); 1054 } 1055 } 1056 1057 void 1058 cpu_init_msrs(struct cpu_info *ci, bool full) 1059 { 1060 #ifdef __x86_64__ 1061 if (full) { 1062 HYPERVISOR_set_segment_base(SEGBASE_FS, 0); 1063 HYPERVISOR_set_segment_base(SEGBASE_GS_KERNEL, (uint64_t)ci); 1064 HYPERVISOR_set_segment_base(SEGBASE_GS_USER, 0); 1065 } 1066 #endif 1067 1068 if (cpu_feature[2] & CPUID_NOX) 1069 wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_NXE); 1070 } 1071 1072 void 1073 cpu_offline_md(void) 1074 { 1075 int s; 1076 1077 s = splhigh(); 1078 fpusave_cpu(true); 1079 splx(s); 1080 } 1081 1082 void 1083 cpu_get_tsc_freq(struct cpu_info *ci) 1084 { 1085 uint32_t vcpu_tversion; 1086 const volatile vcpu_time_info_t *tinfo = &ci->ci_vcpu->time; 1087 1088 vcpu_tversion = tinfo->version; 1089 while (tinfo->version == vcpu_tversion); /* Wait for a time update. XXX: timeout ? */ 1090 1091 uint64_t freq = 1000000000ULL << 32; 1092 freq = freq / (uint64_t)tinfo->tsc_to_system_mul; 1093 if (tinfo->tsc_shift < 0) 1094 freq = freq << -tinfo->tsc_shift; 1095 else 1096 freq = freq >> tinfo->tsc_shift; 1097 ci->ci_data.cpu_cc_freq = freq; 1098 } 1099 1100 void 1101 x86_cpu_idle_xen(void) 1102 { 1103 struct cpu_info *ci = curcpu(); 1104 1105 KASSERT(ci->ci_ilevel == IPL_NONE); 1106 1107 x86_disable_intr(); 1108 if (!__predict_false(ci->ci_want_resched)) { 1109 idle_block(); 1110 } else { 1111 x86_enable_intr(); 1112 } 1113 } 1114 1115 /* 1116 * Loads pmap for the current CPU. 1117 */ 1118 void 1119 cpu_load_pmap(struct pmap *pmap, struct pmap *oldpmap) 1120 { 1121 KASSERT(pmap != pmap_kernel()); 1122 1123 #if defined(__x86_64__) || defined(PAE) 1124 struct cpu_info *ci = curcpu(); 1125 cpuid_t cid = cpu_index(ci); 1126 1127 mutex_enter(&ci->ci_kpm_mtx); 1128 /* make new pmap visible to xen_kpm_sync() */ 1129 kcpuset_atomic_set(pmap->pm_xen_ptp_cpus, cid); 1130 #endif 1131 1132 #ifdef i386 1133 #ifdef PAE 1134 { 1135 int i; 1136 paddr_t l3_pd = xpmap_ptom_masked(ci->ci_pae_l3_pdirpa); 1137 /* don't update the kernel L3 slot */ 1138 for (i = 0 ; i < PDP_SIZE - 1; i++) { 1139 xpq_queue_pte_update(l3_pd + i * sizeof(pd_entry_t), 1140 xpmap_ptom(pmap->pm_pdirpa[i]) | PG_V); 1141 } 1142 tlbflush(); 1143 } 1144 #else /* PAE */ 1145 lcr3(pmap_pdirpa(pmap, 0)); 1146 #endif /* PAE */ 1147 #endif /* i386 */ 1148 1149 #ifdef __x86_64__ 1150 { 1151 int i; 1152 pd_entry_t *new_pgd; 1153 paddr_t l4_pd_ma; 1154 1155 l4_pd_ma = xpmap_ptom_masked(ci->ci_kpm_pdirpa); 1156 1157 /* 1158 * Map user space address in kernel space and load 1159 * user cr3 1160 */ 1161 new_pgd = pmap->pm_pdir; 1162 KASSERT(pmap == ci->ci_pmap); 1163 1164 /* Copy user pmap L4 PDEs (in user addr. range) to per-cpu L4 */ 1165 for (i = 0; i < PDIR_SLOT_PTE; i++) { 1166 KASSERT(pmap != pmap_kernel() || new_pgd[i] == 0); 1167 if (ci->ci_kpm_pdir[i] != new_pgd[i]) { 1168 xpq_queue_pte_update( 1169 l4_pd_ma + i * sizeof(pd_entry_t), 1170 new_pgd[i]); 1171 } 1172 } 1173 1174 xen_set_user_pgd(pmap_pdirpa(pmap, 0)); 1175 ci->ci_xen_current_user_pgd = pmap_pdirpa(pmap, 0); 1176 1177 tlbflush(); 1178 } 1179 #endif /* __x86_64__ */ 1180 1181 #if defined(__x86_64__) || defined(PAE) 1182 /* old pmap no longer visible to xen_kpm_sync() */ 1183 if (oldpmap != pmap_kernel()) { 1184 kcpuset_atomic_clear(oldpmap->pm_xen_ptp_cpus, cid); 1185 } 1186 mutex_exit(&ci->ci_kpm_mtx); 1187 #endif 1188 } 1189 1190 /* 1191 * pmap_cpu_init_late: perform late per-CPU initialization. 1192 * 1193 * Short note about percpu PDIR pages. Both the PAE and __x86_64__ architectures 1194 * have per-cpu PDIR tables, for two different reasons: 1195 * - on PAE, this is to get around Xen's pagetable setup constraints (multiple 1196 * L3[3]s cannot point to the same L2 - Xen will refuse to pin a table set up 1197 * this way). 1198 * - on __x86_64__, this is for multiple CPUs to map in different user pmaps 1199 * (see cpu_load_pmap()). 1200 * 1201 * What this means for us is that the PDIR of the pmap_kernel() is considered 1202 * to be a canonical "SHADOW" PDIR with the following properties: 1203 * - its recursive mapping points to itself 1204 * - per-cpu recursive mappings point to themselves on __x86_64__ 1205 * - per-cpu L4 pages' kernel entries are expected to be in sync with 1206 * the shadow 1207 */ 1208 1209 void 1210 pmap_cpu_init_late(struct cpu_info *ci) 1211 { 1212 #if defined(PAE) || defined(__x86_64__) 1213 /* 1214 * The BP has already its own PD page allocated during early 1215 * MD startup. 1216 */ 1217 1218 #if defined(__x86_64__) 1219 /* Setup per-cpu normal_pdes */ 1220 int i; 1221 extern pd_entry_t * const normal_pdes[]; 1222 for (i = 0;i < PTP_LEVELS - 1;i++) { 1223 ci->ci_normal_pdes[i] = normal_pdes[i]; 1224 } 1225 #endif /* __x86_64__ */ 1226 1227 if (ci == &cpu_info_primary) 1228 return; 1229 1230 KASSERT(ci != NULL); 1231 1232 #if defined(PAE) 1233 cpu_alloc_l3_page(ci); 1234 KASSERT(ci->ci_pae_l3_pdirpa != 0); 1235 1236 /* Initialise L2 entries 0 - 2: Point them to pmap_kernel() */ 1237 int i; 1238 for (i = 0 ; i < PDP_SIZE - 1; i++) { 1239 ci->ci_pae_l3_pdir[i] = 1240 xpmap_ptom_masked(pmap_kernel()->pm_pdirpa[i]) | PG_V; 1241 } 1242 #endif /* PAE */ 1243 1244 ci->ci_kpm_pdir = (pd_entry_t *)uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 1245 UVM_KMF_WIRED | UVM_KMF_ZERO | UVM_KMF_NOWAIT); 1246 1247 if (ci->ci_kpm_pdir == NULL) { 1248 panic("%s: failed to allocate L4 per-cpu PD for CPU %d\n", 1249 __func__, cpu_index(ci)); 1250 } 1251 ci->ci_kpm_pdirpa = vtophys((vaddr_t)ci->ci_kpm_pdir); 1252 KASSERT(ci->ci_kpm_pdirpa != 0); 1253 1254 #if defined(__x86_64__) 1255 extern pt_entry_t xpmap_pg_nx; 1256 1257 /* Copy over the pmap_kernel() shadow L4 entries */ 1258 memcpy(ci->ci_kpm_pdir, pmap_kernel()->pm_pdir, PAGE_SIZE); 1259 1260 /* Recursive kernel mapping */ 1261 ci->ci_kpm_pdir[PDIR_SLOT_PTE] = xpmap_ptom_masked(ci->ci_kpm_pdirpa) 1262 | PG_V | xpmap_pg_nx; 1263 #elif defined(PAE) 1264 /* Copy over the pmap_kernel() shadow L2 entries */ 1265 memcpy(ci->ci_kpm_pdir, pmap_kernel()->pm_pdir + PDIR_SLOT_KERN, 1266 nkptp[PTP_LEVELS - 1] * sizeof(pd_entry_t)); 1267 #endif 1268 1269 /* Xen wants a RO pdir. */ 1270 pmap_protect(pmap_kernel(), (vaddr_t)ci->ci_kpm_pdir, 1271 (vaddr_t)ci->ci_kpm_pdir + PAGE_SIZE, VM_PROT_READ); 1272 pmap_update(pmap_kernel()); 1273 #if defined(PAE) 1274 /* 1275 * Initialize L3 entry 3. This mapping is shared across all pmaps and is 1276 * static, ie: loading a new pmap will not update this entry. 1277 */ 1278 ci->ci_pae_l3_pdir[3] = xpmap_ptom_masked(ci->ci_kpm_pdirpa) | PG_V; 1279 1280 /* Xen wants a RO L3. */ 1281 pmap_protect(pmap_kernel(), (vaddr_t)ci->ci_pae_l3_pdir, 1282 (vaddr_t)ci->ci_pae_l3_pdir + PAGE_SIZE, VM_PROT_READ); 1283 pmap_update(pmap_kernel()); 1284 1285 xpq_queue_pin_l3_table(xpmap_ptom_masked(ci->ci_pae_l3_pdirpa)); 1286 1287 #elif defined(__x86_64__) 1288 xpq_queue_pin_l4_table(xpmap_ptom_masked(ci->ci_kpm_pdirpa)); 1289 #endif /* PAE , __x86_64__ */ 1290 #endif /* defined(PAE) || defined(__x86_64__) */ 1291 } 1292 1293 /* 1294 * Notify all other cpus to halt. 1295 */ 1296 1297 void 1298 cpu_broadcast_halt(void) 1299 { 1300 xen_broadcast_ipi(XEN_IPI_HALT); 1301 } 1302 1303 /* 1304 * Send a dummy ipi to a cpu. 1305 */ 1306 1307 void 1308 cpu_kick(struct cpu_info *ci) 1309 { 1310 (void)xen_send_ipi(ci, XEN_IPI_KICK); 1311 } 1312
Indexes created Wed Sep 24 05:09:52 GMT 2025