cpu.c revision 1.131
1 /* $NetBSD: cpu.c,v 1.131 2019/11/23 19:40:38 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * Copyright (c) 2002, 2006, 2007 YAMAMOTO Takashi, 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by RedBack Networks Inc. 10 * 11 * Author: Bill Sommerfeld 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * Copyright (c) 1999 Stefan Grefen 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by the NetBSD 49 * Foundation, Inc. and its contributors. 50 * 4. Neither the name of The NetBSD Foundation nor the names of its 51 * contributors may be used to endorse or promote products derived 52 * from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 55 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 56 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 57 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE 58 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 59 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 60 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 62 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 63 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.131 2019/11/23 19:40:38 ad Exp $"); 69 70 #include "opt_ddb.h" 71 #include "opt_multiprocessor.h" 72 #include "opt_mpbios.h" /* for MPDEBUG */ 73 #include "opt_mtrr.h" 74 #include "opt_xen.h" 75 76 #include "lapic.h" 77 #include "ioapic.h" 78 79 #include <sys/param.h> 80 #include <sys/proc.h> 81 #include <sys/systm.h> 82 #include <sys/device.h> 83 #include <sys/kmem.h> 84 #include <sys/cpu.h> 85 #include <sys/cpufreq.h> 86 #include <sys/atomic.h> 87 #include <sys/reboot.h> 88 #include <sys/idle.h> 89 90 #include <uvm/uvm.h> 91 92 #include <machine/cpu.h> 93 #include <machine/cpufunc.h> 94 #include <machine/cpuvar.h> 95 #include <machine/pmap.h> 96 #include <machine/vmparam.h> 97 #include <machine/mpbiosvar.h> 98 #include <machine/pcb.h> 99 #include <machine/specialreg.h> 100 #include <machine/segments.h> 101 #include <machine/gdt.h> 102 #include <machine/mtrr.h> 103 #include <machine/pio.h> 104 105 #include <x86/fpu.h> 106 107 #include <xen/xen.h> 108 #include <xen/include/public/vcpu.h> 109 #include <xen/vcpuvar.h> 110 111 #if NLAPIC > 0 112 #include <machine/apicvar.h> 113 #include <machine/i82489reg.h> 114 #include <machine/i82489var.h> 115 #endif 116 117 #include <dev/ic/mc146818reg.h> 118 #include <dev/isa/isareg.h> 119 120 static int cpu_match(device_t, cfdata_t, void *); 121 static void cpu_attach(device_t, device_t, void *); 122 static void cpu_defer(device_t); 123 static int cpu_rescan(device_t, const char *, const int *); 124 static void cpu_childdetached(device_t, device_t); 125 static int vcpu_match(device_t, cfdata_t, void *); 126 static void vcpu_attach(device_t, device_t, void *); 127 static void cpu_attach_common(device_t, device_t, void *); 128 void cpu_offline_md(void); 129 130 struct cpu_softc { 131 device_t sc_dev; /* device tree glue */ 132 struct cpu_info *sc_info; /* pointer to CPU info */ 133 bool sc_wasonline; 134 }; 135 136 int mp_cpu_start(struct cpu_info *, vaddr_t); 137 void mp_cpu_start_cleanup(struct cpu_info *); 138 const struct cpu_functions mp_cpu_funcs = { mp_cpu_start, NULL, 139 mp_cpu_start_cleanup }; 140 141 CFATTACH_DECL2_NEW(cpu, sizeof(struct cpu_softc), 142 cpu_match, cpu_attach, NULL, NULL, cpu_rescan, cpu_childdetached); 143 144 CFATTACH_DECL_NEW(vcpu, sizeof(struct cpu_softc), 145 vcpu_match, vcpu_attach, NULL, NULL); 146 147 /* 148 * Statically-allocated CPU info for the primary CPU (or the only 149 * CPU, on uniprocessors). The CPU info list is initialized to 150 * point at it. 151 */ 152 struct cpu_info cpu_info_primary __aligned(CACHE_LINE_SIZE) = { 153 .ci_dev = 0, 154 .ci_self = &cpu_info_primary, 155 .ci_idepth = -1, 156 .ci_curlwp = &lwp0, 157 .ci_curldt = -1, 158 }; 159 struct cpu_info phycpu_info_primary __aligned(CACHE_LINE_SIZE) = { 160 .ci_dev = 0, 161 .ci_self = &phycpu_info_primary, 162 }; 163 164 struct cpu_info *cpu_info_list = &cpu_info_primary; 165 struct cpu_info *phycpu_info_list = &phycpu_info_primary; 166 167 uint32_t cpu_feature[7] __read_mostly; /* X86 CPUID feature bits 168 * [0] basic features %edx 169 * [1] basic features %ecx 170 * [2] extended features %edx 171 * [3] extended features %ecx 172 * [4] VIA padlock features 173 * [5] structured extended features cpuid.7:%ebx 174 * [6] structured extended features cpuid.7:%ecx 175 */ 176 177 bool x86_mp_online; 178 paddr_t mp_trampoline_paddr = MP_TRAMPOLINE; 179 180 #if defined(MULTIPROCESSOR) 181 void cpu_hatch(void *); 182 static void cpu_boot_secondary(struct cpu_info *ci); 183 static void cpu_start_secondary(struct cpu_info *ci); 184 #endif /* MULTIPROCESSOR */ 185 186 static int 187 cpu_match(device_t parent, cfdata_t match, void *aux) 188 { 189 190 return 1; 191 } 192 193 static void 194 cpu_attach(device_t parent, device_t self, void *aux) 195 { 196 struct cpu_softc *sc = device_private(self); 197 struct cpu_attach_args *caa = aux; 198 struct cpu_info *ci; 199 uintptr_t ptr; 200 static int nphycpu = 0; 201 202 sc->sc_dev = self; 203 204 /* 205 * If we're an Application Processor, allocate a cpu_info 206 * If we're the first attached CPU use the primary cpu_info, 207 * otherwise allocate a new one 208 */ 209 aprint_naive("\n"); 210 aprint_normal("\n"); 211 if (nphycpu > 0) { 212 struct cpu_info *tmp; 213 ptr = (uintptr_t)kmem_zalloc(sizeof(*ci) + CACHE_LINE_SIZE - 1, 214 KM_SLEEP); 215 ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE); 216 ci->ci_curldt = -1; 217 218 tmp = phycpu_info_list; 219 while (tmp->ci_next) 220 tmp = tmp->ci_next; 221 222 tmp->ci_next = ci; 223 } else { 224 ci = &phycpu_info_primary; 225 } 226 227 ci->ci_self = ci; 228 sc->sc_info = ci; 229 230 ci->ci_dev = self; 231 ci->ci_acpiid = caa->cpu_id; 232 ci->ci_cpuid = caa->cpu_number; 233 ci->ci_vcpu = NULL; 234 ci->ci_index = nphycpu++; 235 236 if (!pmf_device_register(self, NULL, NULL)) 237 aprint_error_dev(self, "couldn't establish power handler\n"); 238 239 (void)config_defer(self, cpu_defer); 240 } 241 242 static void 243 cpu_defer(device_t self) 244 { 245 cpu_rescan(self, NULL, NULL); 246 } 247 248 static int 249 cpu_rescan(device_t self, const char *ifattr, const int *locators) 250 { 251 struct cpu_softc *sc = device_private(self); 252 struct cpufeature_attach_args cfaa; 253 struct cpu_info *ci = sc->sc_info; 254 255 memset(&cfaa, 0, sizeof(cfaa)); 256 cfaa.ci = ci; 257 258 if (ifattr_match(ifattr, "cpufeaturebus")) { 259 260 if (ci->ci_frequency == NULL) { 261 cfaa.name = "frequency"; 262 ci->ci_frequency = config_found_ia(self, 263 "cpufeaturebus", &cfaa, NULL); 264 } 265 } 266 267 return 0; 268 } 269 270 static void 271 cpu_childdetached(device_t self, device_t child) 272 { 273 struct cpu_softc *sc = device_private(self); 274 struct cpu_info *ci = sc->sc_info; 275 276 if (ci->ci_frequency == child) 277 ci->ci_frequency = NULL; 278 } 279 280 static int 281 vcpu_match(device_t parent, cfdata_t match, void *aux) 282 { 283 struct vcpu_attach_args *vcaa = aux; 284 struct vcpu_runstate_info vcr; 285 int error; 286 287 if (strcmp(vcaa->vcaa_name, match->cf_name) == 0) { 288 error = HYPERVISOR_vcpu_op(VCPUOP_get_runstate_info, 289 vcaa->vcaa_caa.cpu_number, &vcr); 290 switch (error) { 291 case 0: 292 return 1; 293 case -ENOENT: 294 return 0; 295 default: 296 panic("Unknown hypervisor error %d returned on vcpu runstate probe\n", error); 297 } 298 } 299 300 return 0; 301 } 302 303 static void 304 vcpu_attach(device_t parent, device_t self, void *aux) 305 { 306 struct vcpu_attach_args *vcaa = aux; 307 308 KASSERT(vcaa->vcaa_caa.cpu_func == NULL); 309 vcaa->vcaa_caa.cpu_func = &mp_cpu_funcs; 310 cpu_attach_common(parent, self, &vcaa->vcaa_caa); 311 312 if (!pmf_device_register(self, NULL, NULL)) 313 aprint_error_dev(self, "couldn't establish power handler\n"); 314 } 315 316 static int 317 vcpu_is_up(struct cpu_info *ci) 318 { 319 KASSERT(ci != NULL); 320 return HYPERVISOR_vcpu_op(VCPUOP_is_up, ci->ci_cpuid, NULL); 321 } 322 323 static void 324 cpu_vm_init(struct cpu_info *ci) 325 { 326 int ncolors = 2, i; 327 328 for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) { 329 struct x86_cache_info *cai; 330 int tcolors; 331 332 cai = &ci->ci_cinfo[i]; 333 334 tcolors = atop(cai->cai_totalsize); 335 switch (cai->cai_associativity) { 336 case 0xff: 337 tcolors = 1; /* fully associative */ 338 break; 339 case 0: 340 case 1: 341 break; 342 default: 343 tcolors /= cai->cai_associativity; 344 } 345 ncolors = uimax(ncolors, tcolors); 346 } 347 348 /* 349 * Knowing the size of the largest cache on this CPU, potentially 350 * re-color our pages. 351 */ 352 aprint_debug_dev(ci->ci_dev, "%d page colors\n", ncolors); 353 uvm_page_recolor(ncolors); 354 pmap_tlb_cpu_init(ci); 355 #ifndef __HAVE_DIRECT_MAP 356 pmap_vpage_cpu_init(ci); 357 #endif 358 } 359 360 static void 361 cpu_attach_common(device_t parent, device_t self, void *aux) 362 { 363 struct cpu_softc *sc = device_private(self); 364 struct cpu_attach_args *caa = aux; 365 struct cpu_info *ci; 366 uintptr_t ptr; 367 int cpunum = caa->cpu_number; 368 static bool again = false; 369 370 sc->sc_dev = self; 371 372 /* 373 * If we're an Application Processor, allocate a cpu_info 374 * structure, otherwise use the primary's. 375 */ 376 if (caa->cpu_role == CPU_ROLE_AP) { 377 aprint_naive(": Application Processor\n"); 378 ptr = (uintptr_t)kmem_alloc(sizeof(*ci) + CACHE_LINE_SIZE - 1, 379 KM_SLEEP); 380 ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE); 381 memset(ci, 0, sizeof(*ci)); 382 cpu_init_tss(ci); 383 } else { 384 aprint_naive(": %s Processor\n", 385 caa->cpu_role == CPU_ROLE_SP ? "Single" : "Boot"); 386 ci = &cpu_info_primary; 387 } 388 389 ci->ci_self = ci; 390 sc->sc_info = ci; 391 ci->ci_dev = self; 392 ci->ci_cpuid = cpunum; 393 394 KASSERT(HYPERVISOR_shared_info != NULL); 395 KASSERT(cpunum < XEN_LEGACY_MAX_VCPUS); 396 ci->ci_vcpu = &HYPERVISOR_shared_info->vcpu_info[cpunum]; 397 398 KASSERT(ci->ci_func == 0); 399 ci->ci_func = caa->cpu_func; 400 aprint_normal("\n"); 401 402 /* Must be called before mi_cpu_attach(). */ 403 cpu_vm_init(ci); 404 405 if (caa->cpu_role == CPU_ROLE_AP) { 406 int error; 407 408 error = mi_cpu_attach(ci); 409 410 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 411 if (error != 0) { 412 aprint_error_dev(self, 413 "mi_cpu_attach failed with %d\n", error); 414 return; 415 } 416 417 } else { 418 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 419 } 420 421 KASSERT(ci->ci_cpuid == ci->ci_index); 422 #ifdef __x86_64__ 423 /* No user PGD mapped for this CPU yet */ 424 ci->ci_xen_current_user_pgd = 0; 425 #endif 426 mutex_init(&ci->ci_kpm_mtx, MUTEX_DEFAULT, IPL_VM); 427 pmap_reference(pmap_kernel()); 428 ci->ci_pmap = pmap_kernel(); 429 ci->ci_tlbstate = TLBSTATE_STALE; 430 431 /* 432 * Boot processor may not be attached first, but the below 433 * must be done to allow booting other processors. 434 */ 435 if (!again) { 436 atomic_or_32(&ci->ci_flags, CPUF_PRESENT | CPUF_PRIMARY); 437 /* Basic init. */ 438 cpu_intr_init(ci); 439 cpu_get_tsc_freq(ci); 440 cpu_init(ci); 441 pmap_cpu_init_late(ci); 442 443 /* Every processor needs to init its own ipi h/w (similar to lapic) */ 444 xen_ipi_init(); 445 446 /* Make sure DELAY() is initialized. */ 447 DELAY(1); 448 again = true; 449 } 450 451 /* further PCB init done later. */ 452 453 switch (caa->cpu_role) { 454 case CPU_ROLE_SP: 455 atomic_or_32(&ci->ci_flags, CPUF_SP); 456 cpu_identify(ci); 457 x86_cpu_idle_init(); 458 break; 459 460 case CPU_ROLE_BP: 461 atomic_or_32(&ci->ci_flags, CPUF_BSP); 462 cpu_identify(ci); 463 x86_cpu_idle_init(); 464 break; 465 466 case CPU_ROLE_AP: 467 atomic_or_32(&ci->ci_flags, CPUF_AP); 468 469 /* 470 * report on an AP 471 */ 472 473 #if defined(MULTIPROCESSOR) 474 /* interrupt handler stack */ 475 cpu_intr_init(ci); 476 477 /* Setup per-cpu memory for gdt */ 478 gdt_alloc_cpu(ci); 479 480 pmap_cpu_init_late(ci); 481 cpu_start_secondary(ci); 482 483 if (ci->ci_flags & CPUF_PRESENT) { 484 struct cpu_info *tmp; 485 486 cpu_identify(ci); 487 tmp = cpu_info_list; 488 while (tmp->ci_next) 489 tmp = tmp->ci_next; 490 491 tmp->ci_next = ci; 492 } 493 #else 494 aprint_error_dev(ci->ci_dev, "not started\n"); 495 #endif 496 break; 497 498 default: 499 panic("unknown processor type??\n"); 500 } 501 502 #ifdef MPVERBOSE 503 if (mp_verbose) { 504 struct lwp *l = ci->ci_data.cpu_idlelwp; 505 struct pcb *pcb = lwp_getpcb(l); 506 507 aprint_verbose_dev(self, 508 "idle lwp at %p, idle sp at 0x%p\n", 509 l, 510 #ifdef i386 511 (void *)pcb->pcb_esp 512 #else 513 (void *)pcb->pcb_rsp 514 #endif 515 ); 516 517 } 518 #endif /* MPVERBOSE */ 519 } 520 521 /* 522 * Initialize the processor appropriately. 523 */ 524 525 void 526 cpu_init(struct cpu_info *ci) 527 { 528 uint32_t cr4 = 0; 529 530 /* 531 * If we have FXSAVE/FXRESTOR, use them. 532 */ 533 if (cpu_feature[0] & CPUID_FXSR) { 534 cr4 |= CR4_OSFXSR; 535 536 /* 537 * If we have SSE/SSE2, enable XMM exceptions. 538 */ 539 if (cpu_feature[0] & (CPUID_SSE|CPUID_SSE2)) 540 cr4 |= CR4_OSXMMEXCPT; 541 } 542 543 /* If xsave is supported, enable it */ 544 if (cpu_feature[1] & CPUID2_XSAVE && x86_fpu_save >= FPU_SAVE_XSAVE) 545 cr4 |= CR4_OSXSAVE; 546 547 if (cr4) { 548 cr4 |= rcr4(); 549 lcr4(cr4); 550 } 551 552 if (x86_fpu_save >= FPU_SAVE_FXSAVE) { 553 fpuinit_mxcsr_mask(); 554 } 555 556 /* 557 * Changing CR4 register may change cpuid values. For example, setting 558 * CR4_OSXSAVE sets CPUID2_OSXSAVE. The CPUID2_OSXSAVE is in 559 * ci_feat_val[1], so update it. 560 * XXX Other than ci_feat_val[1] might be changed. 561 */ 562 if (cpuid_level >= 1) { 563 u_int descs[4]; 564 565 x86_cpuid(1, descs); 566 ci->ci_feat_val[1] = descs[2]; 567 } 568 569 /* If xsave is enabled, enable all fpu features */ 570 if (cr4 & CR4_OSXSAVE) { 571 wrxcr(0, x86_xsave_features & XCR0_FPU); 572 } 573 574 atomic_or_32(&ci->ci_flags, CPUF_RUNNING); 575 } 576 577 578 #ifdef MULTIPROCESSOR 579 580 void 581 cpu_boot_secondary_processors(void) 582 { 583 struct cpu_info *ci; 584 kcpuset_t *cpus; 585 u_long i; 586 587 kcpuset_create(&cpus, true); 588 kcpuset_set(cpus, cpu_index(curcpu())); 589 for (i = 0; i < maxcpus; i++) { 590 ci = cpu_lookup(i); 591 if (ci == NULL) 592 continue; 593 if (ci->ci_data.cpu_idlelwp == NULL) 594 continue; 595 if ((ci->ci_flags & CPUF_PRESENT) == 0) 596 continue; 597 if (ci->ci_flags & (CPUF_BSP|CPUF_SP|CPUF_PRIMARY)) 598 continue; 599 cpu_boot_secondary(ci); 600 kcpuset_set(cpus, cpu_index(ci)); 601 } 602 while (!kcpuset_match(cpus, kcpuset_running)) 603 ; 604 kcpuset_destroy(cpus); 605 606 x86_mp_online = true; 607 } 608 609 static void 610 cpu_init_idle_lwp(struct cpu_info *ci) 611 { 612 struct lwp *l = ci->ci_data.cpu_idlelwp; 613 struct pcb *pcb = lwp_getpcb(l); 614 615 pcb->pcb_cr0 = rcr0(); 616 } 617 618 void 619 cpu_init_idle_lwps(void) 620 { 621 struct cpu_info *ci; 622 u_long i; 623 624 for (i = 0; i < maxcpus; i++) { 625 ci = cpu_lookup(i); 626 if (ci == NULL) 627 continue; 628 if (ci->ci_data.cpu_idlelwp == NULL) 629 continue; 630 if ((ci->ci_flags & CPUF_PRESENT) == 0) 631 continue; 632 cpu_init_idle_lwp(ci); 633 } 634 } 635 636 static void 637 cpu_start_secondary(struct cpu_info *ci) 638 { 639 int i; 640 641 aprint_debug_dev(ci->ci_dev, "starting\n"); 642 643 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 644 645 if (CPU_STARTUP(ci, (vaddr_t) cpu_hatch) != 0) { 646 return; 647 } 648 649 /* 650 * wait for it to become ready 651 */ 652 for (i = 100000; (!(ci->ci_flags & CPUF_PRESENT)) && i > 0; i--) { 653 delay(10); 654 } 655 if ((ci->ci_flags & CPUF_PRESENT) == 0) { 656 aprint_error_dev(ci->ci_dev, "failed to become ready\n"); 657 #if defined(MPDEBUG) && defined(DDB) 658 printf("dropping into debugger; continue from here to resume boot\n"); 659 Debugger(); 660 #endif 661 } 662 663 CPU_START_CLEANUP(ci); 664 } 665 666 void 667 cpu_boot_secondary(struct cpu_info *ci) 668 { 669 int i; 670 atomic_or_32(&ci->ci_flags, CPUF_GO); 671 for (i = 100000; (!(ci->ci_flags & CPUF_RUNNING)) && i > 0; i--) { 672 delay(10); 673 } 674 if ((ci->ci_flags & CPUF_RUNNING) == 0) { 675 aprint_error_dev(ci->ci_dev, "CPU failed to start\n"); 676 #if defined(MPDEBUG) && defined(DDB) 677 printf("dropping into debugger; continue from here to resume boot\n"); 678 Debugger(); 679 #endif 680 } 681 } 682 683 /* 684 * APs end up here immediately after initialisation and VCPUOP_up in 685 * mp_cpu_start(). 686 * At this point, we are running in the idle pcb/idle stack of the new 687 * CPU. This function jumps to the idle loop and starts looking for 688 * work. 689 */ 690 extern void x86_64_tls_switch(struct lwp *); 691 void 692 cpu_hatch(void *v) 693 { 694 struct cpu_info *ci = (struct cpu_info *)v; 695 struct pcb *pcb; 696 int s, i; 697 698 /* Setup TLS and kernel GS/FS */ 699 cpu_init_msrs(ci, true); 700 cpu_init_idt(); 701 gdt_init_cpu(ci); 702 703 cpu_probe(ci); 704 705 atomic_or_32(&ci->ci_flags, CPUF_PRESENT); 706 707 while ((ci->ci_flags & CPUF_GO) == 0) { 708 /* Don't use delay, boot CPU may be patching the text. */ 709 for (i = 10000; i != 0; i--) 710 x86_pause(); 711 } 712 713 /* Because the text may have been patched in x86_patch(). */ 714 x86_flush(); 715 tlbflushg(); 716 717 KASSERT((ci->ci_flags & CPUF_RUNNING) == 0); 718 719 pcb = lwp_getpcb(curlwp); 720 pcb->pcb_cr3 = pmap_pdirpa(pmap_kernel(), 0); 721 pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp); 722 723 xen_ipi_init(); 724 725 xen_initclocks(); 726 727 #ifdef __x86_64__ 728 fpuinit(ci); 729 #endif 730 731 lldt(GSEL(GLDT_SEL, SEL_KPL)); 732 733 cpu_init(ci); 734 cpu_get_tsc_freq(ci); 735 736 s = splhigh(); 737 x86_enable_intr(); 738 splx(s); 739 740 aprint_debug_dev(ci->ci_dev, "running\n"); 741 742 cpu_switchto(NULL, ci->ci_data.cpu_idlelwp, true); 743 744 idle_loop(NULL); 745 KASSERT(false); 746 } 747 748 #if defined(DDB) 749 750 #include <ddb/db_output.h> 751 #include <machine/db_machdep.h> 752 753 /* 754 * Dump CPU information from ddb. 755 */ 756 void 757 cpu_debug_dump(void) 758 { 759 struct cpu_info *ci; 760 CPU_INFO_ITERATOR cii; 761 762 db_printf("addr dev id flags ipis curlwp\n"); 763 for (CPU_INFO_FOREACH(cii, ci)) { 764 db_printf("%p %s %ld %x %x %10p\n", 765 ci, 766 ci->ci_dev == NULL ? "BOOT" : device_xname(ci->ci_dev), 767 (long)ci->ci_cpuid, 768 ci->ci_flags, ci->ci_ipis, 769 ci->ci_curlwp); 770 } 771 } 772 #endif /* DDB */ 773 774 #endif /* MULTIPROCESSOR */ 775 776 extern void hypervisor_callback(void); 777 extern void failsafe_callback(void); 778 #ifdef __x86_64__ 779 typedef void (vector)(void); 780 extern vector Xsyscall, Xsyscall32; 781 #endif 782 783 /* 784 * Setup the "trampoline". On Xen, we setup nearly all cpu context 785 * outside a trampoline, so we prototype and call targetip like so: 786 * void targetip(struct cpu_info *); 787 */ 788 789 static void 790 gdt_prepframes(paddr_t *frames, vaddr_t base, uint32_t entries) 791 { 792 int i; 793 for (i = 0; i < entries; i++) { 794 frames[i] = ((paddr_t)xpmap_ptetomach( 795 (pt_entry_t *)(base + (i << PAGE_SHIFT)))) >> PAGE_SHIFT; 796 797 /* Mark Read-only */ 798 pmap_pte_clearbits(kvtopte(base + (i << PAGE_SHIFT)), 799 PTE_W); 800 } 801 } 802 803 #ifdef __x86_64__ 804 extern char *ldtstore; 805 806 static void 807 xen_init_amd64_vcpuctxt(struct cpu_info *ci, struct vcpu_guest_context *initctx, 808 void targetrip(struct cpu_info *)) 809 { 810 /* page frames to point at GDT */ 811 extern int gdt_size; 812 paddr_t frames[16]; 813 psize_t gdt_ents; 814 815 struct lwp *l; 816 struct pcb *pcb; 817 818 volatile struct vcpu_info *vci; 819 820 KASSERT(ci != NULL); 821 KASSERT(ci != &cpu_info_primary); 822 KASSERT(initctx != NULL); 823 KASSERT(targetrip != NULL); 824 825 memset(initctx, 0, sizeof(*initctx)); 826 827 gdt_ents = roundup(gdt_size, PAGE_SIZE) >> PAGE_SHIFT; 828 KASSERT(gdt_ents <= 16); 829 830 gdt_prepframes(frames, (vaddr_t)ci->ci_gdt, gdt_ents); 831 832 /* Initialise the vcpu context: We use idle_loop()'s pcb context. */ 833 834 l = ci->ci_data.cpu_idlelwp; 835 836 KASSERT(l != NULL); 837 pcb = lwp_getpcb(l); 838 KASSERT(pcb != NULL); 839 840 /* resume with interrupts off */ 841 vci = ci->ci_vcpu; 842 vci->evtchn_upcall_mask = 1; 843 xen_mb(); 844 845 /* resume in kernel-mode */ 846 initctx->flags = VGCF_in_kernel | VGCF_online; 847 848 /* Stack and entry points: 849 * We arrange for the stack frame for cpu_hatch() to 850 * appear as a callee frame of lwp_trampoline(). Being a 851 * leaf frame prevents trampling on any of the MD stack setup 852 * that x86/vm_machdep.c:cpu_lwp_fork() does for idle_loop() 853 */ 854 855 initctx->user_regs.rdi = (uint64_t) ci; /* targetrip(ci); */ 856 initctx->user_regs.rip = (vaddr_t) targetrip; 857 858 initctx->user_regs.cs = GSEL(GCODE_SEL, SEL_KPL); 859 860 initctx->user_regs.rflags = pcb->pcb_flags; 861 initctx->user_regs.rsp = pcb->pcb_rsp; 862 863 /* Data segments */ 864 initctx->user_regs.ss = GSEL(GDATA_SEL, SEL_KPL); 865 initctx->user_regs.es = GSEL(GDATA_SEL, SEL_KPL); 866 initctx->user_regs.ds = GSEL(GDATA_SEL, SEL_KPL); 867 868 /* GDT */ 869 memcpy(initctx->gdt_frames, frames, sizeof(frames)); 870 initctx->gdt_ents = gdt_ents; 871 872 /* LDT */ 873 initctx->ldt_base = (unsigned long)ldtstore; 874 initctx->ldt_ents = LDT_SIZE >> 3; 875 876 /* Kernel context state */ 877 initctx->kernel_ss = GSEL(GDATA_SEL, SEL_KPL); 878 initctx->kernel_sp = pcb->pcb_rsp0; 879 initctx->ctrlreg[0] = pcb->pcb_cr0; 880 initctx->ctrlreg[1] = 0; /* "resuming" from kernel - no User cr3. */ 881 initctx->ctrlreg[2] = (vaddr_t)targetrip; 882 /* 883 * Use pmap_kernel() L4 PD directly, until we setup the 884 * per-cpu L4 PD in pmap_cpu_init_late() 885 */ 886 initctx->ctrlreg[3] = xen_pfn_to_cr3(x86_btop(xpmap_ptom(ci->ci_kpm_pdirpa))); 887 initctx->ctrlreg[4] = CR4_PAE | CR4_OSFXSR | CR4_OSXMMEXCPT; 888 889 /* Xen callbacks */ 890 initctx->event_callback_eip = (unsigned long)hypervisor_callback; 891 initctx->failsafe_callback_eip = (unsigned long)failsafe_callback; 892 initctx->syscall_callback_eip = (unsigned long)Xsyscall; 893 894 return; 895 } 896 #else /* i386 */ 897 extern union descriptor *ldtstore; 898 extern void Xsyscall(void); 899 900 static void 901 xen_init_i386_vcpuctxt(struct cpu_info *ci, struct vcpu_guest_context *initctx, 902 void targeteip(struct cpu_info *)) 903 { 904 /* page frames to point at GDT */ 905 extern int gdt_size; 906 paddr_t frames[16]; 907 psize_t gdt_ents; 908 909 struct lwp *l; 910 struct pcb *pcb; 911 912 volatile struct vcpu_info *vci; 913 914 KASSERT(ci != NULL); 915 KASSERT(ci != &cpu_info_primary); 916 KASSERT(initctx != NULL); 917 KASSERT(targeteip != NULL); 918 919 memset(initctx, 0, sizeof(*initctx)); 920 921 gdt_ents = roundup(gdt_size, PAGE_SIZE) >> PAGE_SHIFT; 922 KASSERT(gdt_ents <= 16); 923 924 gdt_prepframes(frames, (vaddr_t)ci->ci_gdt, gdt_ents); 925 926 /* 927 * Initialise the vcpu context: 928 * We use this cpu's idle_loop() pcb context. 929 */ 930 931 l = ci->ci_data.cpu_idlelwp; 932 933 KASSERT(l != NULL); 934 pcb = lwp_getpcb(l); 935 KASSERT(pcb != NULL); 936 937 /* resume with interrupts off */ 938 vci = ci->ci_vcpu; 939 vci->evtchn_upcall_mask = 1; 940 xen_mb(); 941 942 /* resume in kernel-mode */ 943 initctx->flags = VGCF_in_kernel | VGCF_online; 944 945 /* Stack frame setup for cpu_hatch(): 946 * We arrange for the stack frame for cpu_hatch() to 947 * appear as a callee frame of lwp_trampoline(). Being a 948 * leaf frame prevents trampling on any of the MD stack setup 949 * that x86/vm_machdep.c:cpu_lwp_fork() does for idle_loop() 950 */ 951 952 initctx->user_regs.esp = pcb->pcb_esp - 4; /* Leave word for 953 arg1 */ 954 { 955 /* targeteip(ci); */ 956 uint32_t *arg = (uint32_t *)initctx->user_regs.esp; 957 arg[1] = (uint32_t)ci; /* arg1 */ 958 } 959 960 initctx->user_regs.eip = (vaddr_t)targeteip; 961 initctx->user_regs.cs = GSEL(GCODE_SEL, SEL_KPL); 962 initctx->user_regs.eflags |= pcb->pcb_iopl; 963 964 /* Data segments */ 965 initctx->user_regs.ss = GSEL(GDATA_SEL, SEL_KPL); 966 initctx->user_regs.es = GSEL(GDATA_SEL, SEL_KPL); 967 initctx->user_regs.ds = GSEL(GDATA_SEL, SEL_KPL); 968 initctx->user_regs.fs = GSEL(GDATA_SEL, SEL_KPL); 969 970 /* GDT */ 971 memcpy(initctx->gdt_frames, frames, sizeof(frames)); 972 initctx->gdt_ents = gdt_ents; 973 974 /* LDT */ 975 initctx->ldt_base = (unsigned long)ldtstore; 976 initctx->ldt_ents = NLDT; 977 978 /* Kernel context state */ 979 initctx->kernel_ss = GSEL(GDATA_SEL, SEL_KPL); 980 initctx->kernel_sp = pcb->pcb_esp0; 981 initctx->ctrlreg[0] = pcb->pcb_cr0; 982 initctx->ctrlreg[1] = 0; /* "resuming" from kernel - no User cr3. */ 983 initctx->ctrlreg[2] = (vaddr_t)targeteip; 984 initctx->ctrlreg[3] = xen_pfn_to_cr3(x86_btop(xpmap_ptom(ci->ci_pae_l3_pdirpa))); 985 initctx->ctrlreg[4] = /* CR4_PAE | */CR4_OSFXSR | CR4_OSXMMEXCPT; 986 987 /* Xen callbacks */ 988 initctx->event_callback_eip = (unsigned long)hypervisor_callback; 989 initctx->event_callback_cs = GSEL(GCODE_SEL, SEL_KPL); 990 initctx->failsafe_callback_eip = (unsigned long)failsafe_callback; 991 initctx->failsafe_callback_cs = GSEL(GCODE_SEL, SEL_KPL); 992 993 return; 994 } 995 #endif /* __x86_64__ */ 996 997 int 998 mp_cpu_start(struct cpu_info *ci, vaddr_t target) 999 { 1000 int hyperror; 1001 struct vcpu_guest_context vcpuctx; 1002 1003 KASSERT(ci != NULL); 1004 KASSERT(ci != &cpu_info_primary); 1005 KASSERT(ci->ci_flags & CPUF_AP); 1006 1007 #ifdef __x86_64__ 1008 xen_init_amd64_vcpuctxt(ci, &vcpuctx, (void (*)(struct cpu_info *))target); 1009 #else 1010 xen_init_i386_vcpuctxt(ci, &vcpuctx, (void (*)(struct cpu_info *))target); 1011 #endif 1012 1013 /* Initialise the given vcpu to execute cpu_hatch(ci); */ 1014 if ((hyperror = HYPERVISOR_vcpu_op(VCPUOP_initialise, ci->ci_cpuid, &vcpuctx))) { 1015 aprint_error(": context initialisation failed. errno = %d\n", hyperror); 1016 return hyperror; 1017 } 1018 1019 /* Start it up */ 1020 1021 /* First bring it down */ 1022 if ((hyperror = HYPERVISOR_vcpu_op(VCPUOP_down, ci->ci_cpuid, NULL))) { 1023 aprint_error(": VCPUOP_down hypervisor command failed. errno = %d\n", hyperror); 1024 return hyperror; 1025 } 1026 1027 if ((hyperror = HYPERVISOR_vcpu_op(VCPUOP_up, ci->ci_cpuid, NULL))) { 1028 aprint_error(": VCPUOP_up hypervisor command failed. errno = %d\n", hyperror); 1029 return hyperror; 1030 } 1031 1032 if (!vcpu_is_up(ci)) { 1033 aprint_error(": did not come up\n"); 1034 return -1; 1035 } 1036 1037 return 0; 1038 } 1039 1040 void 1041 mp_cpu_start_cleanup(struct cpu_info *ci) 1042 { 1043 if (vcpu_is_up(ci)) { 1044 aprint_debug_dev(ci->ci_dev, "is started.\n"); 1045 } else { 1046 aprint_error_dev(ci->ci_dev, "did not start up.\n"); 1047 } 1048 } 1049 1050 void 1051 cpu_init_msrs(struct cpu_info *ci, bool full) 1052 { 1053 #ifdef __x86_64__ 1054 if (full) { 1055 HYPERVISOR_set_segment_base(SEGBASE_FS, 0); 1056 HYPERVISOR_set_segment_base(SEGBASE_GS_KERNEL, (uint64_t)ci); 1057 HYPERVISOR_set_segment_base(SEGBASE_GS_USER, 0); 1058 } 1059 #endif 1060 1061 if (cpu_feature[2] & CPUID_NOX) 1062 wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_NXE); 1063 } 1064 1065 void 1066 cpu_offline_md(void) 1067 { 1068 return; 1069 } 1070 1071 void 1072 cpu_get_tsc_freq(struct cpu_info *ci) 1073 { 1074 uint32_t vcpu_tversion; 1075 const volatile vcpu_time_info_t *tinfo = &ci->ci_vcpu->time; 1076 1077 vcpu_tversion = tinfo->version; 1078 while (tinfo->version == vcpu_tversion); /* Wait for a time update. XXX: timeout ? */ 1079 1080 uint64_t freq = 1000000000ULL << 32; 1081 freq = freq / (uint64_t)tinfo->tsc_to_system_mul; 1082 if (tinfo->tsc_shift < 0) 1083 freq = freq << -tinfo->tsc_shift; 1084 else 1085 freq = freq >> tinfo->tsc_shift; 1086 ci->ci_data.cpu_cc_freq = freq; 1087 } 1088 1089 void 1090 x86_cpu_idle_xen(void) 1091 { 1092 struct cpu_info *ci = curcpu(); 1093 1094 KASSERT(ci->ci_ilevel == IPL_NONE); 1095 1096 x86_disable_intr(); 1097 if (!__predict_false(ci->ci_want_resched)) { 1098 idle_block(); 1099 } else { 1100 x86_enable_intr(); 1101 } 1102 } 1103 1104 /* 1105 * Loads pmap for the current CPU. 1106 */ 1107 void 1108 cpu_load_pmap(struct pmap *pmap, struct pmap *oldpmap) 1109 { 1110 struct cpu_info *ci = curcpu(); 1111 cpuid_t cid = cpu_index(ci); 1112 int i; 1113 1114 KASSERT(pmap != pmap_kernel()); 1115 1116 mutex_enter(&ci->ci_kpm_mtx); 1117 /* make new pmap visible to xen_kpm_sync() */ 1118 kcpuset_atomic_set(pmap->pm_xen_ptp_cpus, cid); 1119 1120 #ifdef __x86_64__ 1121 pd_entry_t *new_pgd; 1122 paddr_t l4_pd_ma; 1123 1124 l4_pd_ma = xpmap_ptom_masked(ci->ci_kpm_pdirpa); 1125 1126 /* 1127 * Map user space address in kernel space and load 1128 * user cr3 1129 */ 1130 new_pgd = pmap->pm_pdir; 1131 KASSERT(pmap == ci->ci_pmap); 1132 1133 /* Copy user pmap L4 PDEs (in user addr. range) to per-cpu L4 */ 1134 for (i = 0; i < PDIR_SLOT_USERLIM; i++) { 1135 KASSERT(pmap != pmap_kernel() || new_pgd[i] == 0); 1136 if (ci->ci_kpm_pdir[i] != new_pgd[i]) { 1137 xpq_queue_pte_update(l4_pd_ma + i * sizeof(pd_entry_t), 1138 new_pgd[i]); 1139 } 1140 } 1141 1142 xen_set_user_pgd(pmap_pdirpa(pmap, 0)); 1143 ci->ci_xen_current_user_pgd = pmap_pdirpa(pmap, 0); 1144 #else 1145 paddr_t l3_pd = xpmap_ptom_masked(ci->ci_pae_l3_pdirpa); 1146 /* don't update the kernel L3 slot */ 1147 for (i = 0; i < PDP_SIZE - 1; i++) { 1148 xpq_queue_pte_update(l3_pd + i * sizeof(pd_entry_t), 1149 xpmap_ptom(pmap->pm_pdirpa[i]) | PTE_P); 1150 } 1151 #endif 1152 1153 tlbflush(); 1154 1155 /* old pmap no longer visible to xen_kpm_sync() */ 1156 if (oldpmap != pmap_kernel()) { 1157 kcpuset_atomic_clear(oldpmap->pm_xen_ptp_cpus, cid); 1158 } 1159 mutex_exit(&ci->ci_kpm_mtx); 1160 } 1161 1162 /* 1163 * pmap_cpu_init_late: perform late per-CPU initialization. 1164 * 1165 * Short note about percpu PDIR pages. Both the PAE and __x86_64__ architectures 1166 * have per-cpu PDIR tables, for two different reasons: 1167 * - on PAE, this is to get around Xen's pagetable setup constraints (multiple 1168 * L3[3]s cannot point to the same L2 - Xen will refuse to pin a table set up 1169 * this way). 1170 * - on __x86_64__, this is for multiple CPUs to map in different user pmaps 1171 * (see cpu_load_pmap()). 1172 * 1173 * What this means for us is that the PDIR of the pmap_kernel() is considered 1174 * to be a canonical "SHADOW" PDIR with the following properties: 1175 * - its recursive mapping points to itself 1176 * - per-cpu recursive mappings point to themselves on __x86_64__ 1177 * - per-cpu L4 pages' kernel entries are expected to be in sync with 1178 * the shadow 1179 */ 1180 1181 void 1182 pmap_cpu_init_late(struct cpu_info *ci) 1183 { 1184 int i; 1185 1186 /* 1187 * The BP has already its own PD page allocated during early 1188 * MD startup. 1189 */ 1190 1191 #ifdef __x86_64__ 1192 /* Setup per-cpu normal_pdes */ 1193 extern pd_entry_t * const normal_pdes[]; 1194 for (i = 0;i < PTP_LEVELS - 1;i++) { 1195 ci->ci_normal_pdes[i] = normal_pdes[i]; 1196 } 1197 #endif 1198 1199 if (ci == &cpu_info_primary) 1200 return; 1201 1202 KASSERT(ci != NULL); 1203 1204 #if defined(i386) 1205 cpu_alloc_l3_page(ci); 1206 KASSERT(ci->ci_pae_l3_pdirpa != 0); 1207 1208 /* Initialise L2 entries 0 - 2: Point them to pmap_kernel() */ 1209 for (i = 0; i < PDP_SIZE - 1; i++) { 1210 ci->ci_pae_l3_pdir[i] = 1211 xpmap_ptom_masked(pmap_kernel()->pm_pdirpa[i]) | PTE_P; 1212 } 1213 #endif 1214 1215 ci->ci_kpm_pdir = (pd_entry_t *)uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 1216 UVM_KMF_WIRED | UVM_KMF_ZERO | UVM_KMF_NOWAIT); 1217 1218 if (ci->ci_kpm_pdir == NULL) { 1219 panic("%s: failed to allocate L4 per-cpu PD for CPU %d\n", 1220 __func__, cpu_index(ci)); 1221 } 1222 ci->ci_kpm_pdirpa = vtophys((vaddr_t)ci->ci_kpm_pdir); 1223 KASSERT(ci->ci_kpm_pdirpa != 0); 1224 1225 #ifdef __x86_64__ 1226 extern pt_entry_t xpmap_pg_nx; 1227 1228 /* Copy over the pmap_kernel() shadow L4 entries */ 1229 memcpy(ci->ci_kpm_pdir, pmap_kernel()->pm_pdir, PAGE_SIZE); 1230 1231 /* Recursive kernel mapping */ 1232 ci->ci_kpm_pdir[PDIR_SLOT_PTE] = xpmap_ptom_masked(ci->ci_kpm_pdirpa) 1233 | PTE_P | xpmap_pg_nx; 1234 #else 1235 /* Copy over the pmap_kernel() shadow L2 entries */ 1236 memcpy(ci->ci_kpm_pdir, pmap_kernel()->pm_pdir + PDIR_SLOT_KERN, 1237 nkptp[PTP_LEVELS - 1] * sizeof(pd_entry_t)); 1238 #endif 1239 1240 /* Xen wants a RO pdir. */ 1241 pmap_protect(pmap_kernel(), (vaddr_t)ci->ci_kpm_pdir, 1242 (vaddr_t)ci->ci_kpm_pdir + PAGE_SIZE, VM_PROT_READ); 1243 pmap_update(pmap_kernel()); 1244 1245 #ifdef __x86_64__ 1246 xpq_queue_pin_l4_table(xpmap_ptom_masked(ci->ci_kpm_pdirpa)); 1247 #else 1248 /* 1249 * Initialize L3 entry 3. This mapping is shared across all pmaps and is 1250 * static, ie: loading a new pmap will not update this entry. 1251 */ 1252 ci->ci_pae_l3_pdir[3] = xpmap_ptom_masked(ci->ci_kpm_pdirpa) | PTE_P; 1253 1254 /* Xen wants a RO L3. */ 1255 pmap_protect(pmap_kernel(), (vaddr_t)ci->ci_pae_l3_pdir, 1256 (vaddr_t)ci->ci_pae_l3_pdir + PAGE_SIZE, VM_PROT_READ); 1257 pmap_update(pmap_kernel()); 1258 1259 xpq_queue_pin_l3_table(xpmap_ptom_masked(ci->ci_pae_l3_pdirpa)); 1260 #endif 1261 } 1262 1263 /* 1264 * Notify all other cpus to halt. 1265 */ 1266 1267 void 1268 cpu_broadcast_halt(void) 1269 { 1270 xen_broadcast_ipi(XEN_IPI_HALT); 1271 } 1272 1273 /* 1274 * Send a dummy ipi to a cpu, and raise an AST on the running LWP. 1275 */ 1276 1277 void 1278 cpu_kick(struct cpu_info *ci) 1279 { 1280 (void)xen_send_ipi(ci, XEN_IPI_AST); 1281 } 1282
Indexes created Mon Sep 22 13:09:51 GMT 2025