cpu.c revision 1.141
1 /* $NetBSD: cpu.c,v 1.141 2021/08/07 16:19:08 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * Copyright (c) 2002, 2006, 2007 YAMAMOTO Takashi, 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by RedBack Networks Inc. 10 * 11 * Author: Bill Sommerfeld 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * Copyright (c) 1999 Stefan Grefen 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by the NetBSD 49 * Foundation, Inc. and its contributors. 50 * 4. Neither the name of The NetBSD Foundation nor the names of its 51 * contributors may be used to endorse or promote products derived 52 * from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 55 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 56 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 57 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE 58 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 59 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 60 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 62 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 63 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.141 2021/08/07 16:19:08 thorpej Exp $"); 69 70 #include "opt_ddb.h" 71 #include "opt_multiprocessor.h" 72 #include "opt_mpbios.h" /* for MPDEBUG */ 73 #include "opt_mtrr.h" 74 #include "opt_xen.h" 75 76 #include "lapic.h" 77 #include "ioapic.h" 78 79 #include <sys/param.h> 80 #include <sys/proc.h> 81 #include <sys/systm.h> 82 #include <sys/device.h> 83 #include <sys/kmem.h> 84 #include <sys/cpu.h> 85 #include <sys/cpufreq.h> 86 #include <sys/atomic.h> 87 #include <sys/reboot.h> 88 #include <sys/idle.h> 89 90 #include <uvm/uvm.h> 91 92 #include <machine/cpu.h> 93 #include <machine/cpufunc.h> 94 #include <machine/cpuvar.h> 95 #include <machine/pmap.h> 96 #include <machine/vmparam.h> 97 #include <machine/mpbiosvar.h> 98 #include <machine/pcb.h> 99 #include <machine/specialreg.h> 100 #include <machine/segments.h> 101 #include <machine/gdt.h> 102 #include <machine/mtrr.h> 103 #include <machine/pio.h> 104 105 #include <x86/fpu.h> 106 107 #include <xen/xen.h> 108 #include <xen/include/public/vcpu.h> 109 #include <xen/vcpuvar.h> 110 111 #if NLAPIC > 0 112 #include <machine/apicvar.h> 113 #include <machine/i82489reg.h> 114 #include <machine/i82489var.h> 115 #endif 116 117 #include <dev/ic/mc146818reg.h> 118 #include <dev/isa/isareg.h> 119 120 static int cpu_match(device_t, cfdata_t, void *); 121 static void cpu_attach(device_t, device_t, void *); 122 static void cpu_defer(device_t); 123 static int cpu_rescan(device_t, const char *, const int *); 124 static void cpu_childdetached(device_t, device_t); 125 static int vcpu_match(device_t, cfdata_t, void *); 126 static void vcpu_attach(device_t, device_t, void *); 127 static void cpu_attach_common(device_t, device_t, void *); 128 void cpu_offline_md(void); 129 130 struct cpu_softc { 131 device_t sc_dev; /* device tree glue */ 132 struct cpu_info *sc_info; /* pointer to CPU info */ 133 bool sc_wasonline; 134 }; 135 136 int mp_cpu_start(struct cpu_info *, vaddr_t); 137 void mp_cpu_start_cleanup(struct cpu_info *); 138 const struct cpu_functions mp_cpu_funcs = { mp_cpu_start, NULL, 139 mp_cpu_start_cleanup }; 140 141 CFATTACH_DECL2_NEW(cpu, sizeof(struct cpu_softc), 142 cpu_match, cpu_attach, NULL, NULL, cpu_rescan, cpu_childdetached); 143 144 CFATTACH_DECL_NEW(vcpu, sizeof(struct cpu_softc), 145 vcpu_match, vcpu_attach, NULL, NULL); 146 147 /* 148 * Statically-allocated CPU info for the primary CPU (or the only 149 * CPU, on uniprocessors). The CPU info list is initialized to 150 * point at it. 151 */ 152 struct cpu_info cpu_info_primary __aligned(CACHE_LINE_SIZE) = { 153 .ci_dev = 0, 154 .ci_self = &cpu_info_primary, 155 .ci_idepth = -1, 156 .ci_curlwp = &lwp0, 157 .ci_curldt = -1, 158 }; 159 struct cpu_info phycpu_info_primary __aligned(CACHE_LINE_SIZE) = { 160 .ci_dev = 0, 161 .ci_self = &phycpu_info_primary, 162 }; 163 164 struct cpu_info *cpu_info_list = &cpu_info_primary; 165 struct cpu_info *phycpu_info_list = &phycpu_info_primary; 166 167 uint32_t cpu_feature[7] __read_mostly; /* X86 CPUID feature bits 168 * [0] basic features %edx 169 * [1] basic features %ecx 170 * [2] extended features %edx 171 * [3] extended features %ecx 172 * [4] VIA padlock features 173 * [5] structured extended features cpuid.7:%ebx 174 * [6] structured extended features cpuid.7:%ecx 175 */ 176 177 bool x86_mp_online; 178 paddr_t mp_trampoline_paddr = MP_TRAMPOLINE; 179 180 #if defined(MULTIPROCESSOR) 181 void cpu_hatch(void *); 182 static void cpu_boot_secondary(struct cpu_info *ci); 183 static void cpu_start_secondary(struct cpu_info *ci); 184 #endif /* MULTIPROCESSOR */ 185 186 static int 187 cpu_match(device_t parent, cfdata_t match, void *aux) 188 { 189 190 return 1; 191 } 192 193 static void 194 cpu_attach(device_t parent, device_t self, void *aux) 195 { 196 struct cpu_softc *sc = device_private(self); 197 struct cpu_attach_args *caa = aux; 198 struct cpu_info *ci; 199 uintptr_t ptr; 200 static int nphycpu = 0; 201 202 sc->sc_dev = self; 203 204 /* 205 * If we're an Application Processor, allocate a cpu_info 206 * If we're the first attached CPU use the primary cpu_info, 207 * otherwise allocate a new one 208 */ 209 aprint_naive("\n"); 210 aprint_normal("\n"); 211 if (nphycpu > 0) { 212 struct cpu_info *tmp; 213 ptr = (uintptr_t)kmem_zalloc(sizeof(*ci) + CACHE_LINE_SIZE - 1, 214 KM_SLEEP); 215 ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE); 216 ci->ci_curldt = -1; 217 218 tmp = phycpu_info_list; 219 while (tmp->ci_next) 220 tmp = tmp->ci_next; 221 222 tmp->ci_next = ci; 223 } else { 224 ci = &phycpu_info_primary; 225 } 226 227 ci->ci_self = ci; 228 sc->sc_info = ci; 229 230 ci->ci_dev = self; 231 ci->ci_acpiid = caa->cpu_id; 232 ci->ci_cpuid = caa->cpu_number; 233 ci->ci_vcpu = NULL; 234 ci->ci_index = nphycpu++; 235 ci->ci_kfpu_spl = -1; 236 237 if (!pmf_device_register(self, NULL, NULL)) 238 aprint_error_dev(self, "couldn't establish power handler\n"); 239 240 (void)config_defer(self, cpu_defer); 241 } 242 243 static void 244 cpu_defer(device_t self) 245 { 246 cpu_rescan(self, NULL, NULL); 247 } 248 249 static int 250 cpu_rescan(device_t self, const char *ifattr, const int *locators) 251 { 252 struct cpu_softc *sc = device_private(self); 253 struct cpufeature_attach_args cfaa; 254 struct cpu_info *ci = sc->sc_info; 255 256 memset(&cfaa, 0, sizeof(cfaa)); 257 cfaa.ci = ci; 258 259 if (ifattr_match(ifattr, "cpufeaturebus")) { 260 261 if (ci->ci_frequency == NULL) { 262 cfaa.name = "frequency"; 263 ci->ci_frequency = 264 config_found(self, &cfaa, NULL, 265 CFARGS(.iattr = "cpufeaturebus")); 266 } 267 } 268 269 return 0; 270 } 271 272 static void 273 cpu_childdetached(device_t self, device_t child) 274 { 275 struct cpu_softc *sc = device_private(self); 276 struct cpu_info *ci = sc->sc_info; 277 278 if (ci->ci_frequency == child) 279 ci->ci_frequency = NULL; 280 } 281 282 static int 283 vcpu_match(device_t parent, cfdata_t match, void *aux) 284 { 285 struct vcpu_attach_args *vcaa = aux; 286 struct vcpu_runstate_info vcr; 287 int error; 288 289 if (strcmp(vcaa->vcaa_name, match->cf_name) == 0) { 290 error = HYPERVISOR_vcpu_op(VCPUOP_get_runstate_info, 291 vcaa->vcaa_caa.cpu_number, &vcr); 292 switch (error) { 293 case 0: 294 return 1; 295 case -ENOENT: 296 return 0; 297 default: 298 panic("Unknown hypervisor error %d returned on vcpu runstate probe\n", error); 299 } 300 } 301 302 return 0; 303 } 304 305 static void 306 vcpu_attach(device_t parent, device_t self, void *aux) 307 { 308 struct vcpu_attach_args *vcaa = aux; 309 310 KASSERT(vcaa->vcaa_caa.cpu_func == NULL); 311 vcaa->vcaa_caa.cpu_func = &mp_cpu_funcs; 312 cpu_attach_common(parent, self, &vcaa->vcaa_caa); 313 314 if (!pmf_device_register(self, NULL, NULL)) 315 aprint_error_dev(self, "couldn't establish power handler\n"); 316 } 317 318 static int 319 vcpu_is_up(struct cpu_info *ci) 320 { 321 KASSERT(ci != NULL); 322 return HYPERVISOR_vcpu_op(VCPUOP_is_up, ci->ci_vcpuid, NULL); 323 } 324 325 static void 326 cpu_vm_init(struct cpu_info *ci) 327 { 328 int ncolors = 2, i; 329 330 for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) { 331 struct x86_cache_info *cai; 332 int tcolors; 333 334 cai = &ci->ci_cinfo[i]; 335 336 tcolors = atop(cai->cai_totalsize); 337 switch (cai->cai_associativity) { 338 case 0xff: 339 tcolors = 1; /* fully associative */ 340 break; 341 case 0: 342 case 1: 343 break; 344 default: 345 tcolors /= cai->cai_associativity; 346 } 347 ncolors = uimax(ncolors, tcolors); 348 } 349 350 /* 351 * Knowing the size of the largest cache on this CPU, potentially 352 * re-color our pages. 353 */ 354 aprint_debug_dev(ci->ci_dev, "%d page colors\n", ncolors); 355 uvm_page_recolor(ncolors); 356 pmap_tlb_cpu_init(ci); 357 #ifndef __HAVE_DIRECT_MAP 358 pmap_vpage_cpu_init(ci); 359 #endif 360 } 361 362 static void 363 cpu_attach_common(device_t parent, device_t self, void *aux) 364 { 365 struct cpu_softc *sc = device_private(self); 366 struct cpu_attach_args *caa = aux; 367 struct cpu_info *ci; 368 uintptr_t ptr; 369 int cpunum = caa->cpu_number; 370 static bool again = false; 371 372 sc->sc_dev = self; 373 374 /* 375 * If we're an Application Processor, allocate a cpu_info 376 * structure, otherwise use the primary's. 377 */ 378 if (caa->cpu_role == CPU_ROLE_AP) { 379 aprint_naive(": Application Processor\n"); 380 ptr = (uintptr_t)kmem_alloc(sizeof(*ci) + CACHE_LINE_SIZE - 1, 381 KM_SLEEP); 382 ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE); 383 memset(ci, 0, sizeof(*ci)); 384 cpu_init_tss(ci); 385 } else { 386 aprint_naive(": %s Processor\n", 387 caa->cpu_role == CPU_ROLE_SP ? "Single" : "Boot"); 388 ci = &cpu_info_primary; 389 } 390 391 ci->ci_self = ci; 392 sc->sc_info = ci; 393 ci->ci_dev = self; 394 ci->ci_cpuid = cpunum; 395 ci->ci_vcpuid = cpunum; 396 ci->ci_kfpu_spl = -1; 397 398 KASSERT(HYPERVISOR_shared_info != NULL); 399 KASSERT(cpunum < XEN_LEGACY_MAX_VCPUS); 400 ci->ci_vcpu = &HYPERVISOR_shared_info->vcpu_info[cpunum]; 401 402 KASSERT(ci->ci_func == 0); 403 ci->ci_func = caa->cpu_func; 404 aprint_normal("\n"); 405 406 /* Must be called before mi_cpu_attach(). */ 407 cpu_vm_init(ci); 408 409 if (caa->cpu_role == CPU_ROLE_AP) { 410 int error; 411 412 error = mi_cpu_attach(ci); 413 414 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 415 if (error != 0) { 416 aprint_error_dev(self, 417 "mi_cpu_attach failed with %d\n", error); 418 return; 419 } 420 421 } else { 422 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 423 } 424 425 KASSERT(ci->ci_cpuid == ci->ci_index); 426 #ifdef __x86_64__ 427 /* No user PGD mapped for this CPU yet */ 428 ci->ci_xen_current_user_pgd = 0; 429 #endif 430 mutex_init(&ci->ci_kpm_mtx, MUTEX_DEFAULT, IPL_VM); 431 pmap_reference(pmap_kernel()); 432 ci->ci_pmap = pmap_kernel(); 433 ci->ci_tlbstate = TLBSTATE_STALE; 434 435 /* 436 * Boot processor may not be attached first, but the below 437 * must be done to allow booting other processors. 438 */ 439 if (!again) { 440 atomic_or_32(&ci->ci_flags, CPUF_PRESENT | CPUF_PRIMARY); 441 /* Basic init. */ 442 cpu_intr_init(ci); 443 cpu_get_tsc_freq(ci); 444 cpu_init(ci); 445 pmap_cpu_init_late(ci); 446 447 /* Every processor needs to init its own ipi h/w (similar to lapic) */ 448 xen_ipi_init(); 449 450 /* Make sure DELAY() is initialized. */ 451 DELAY(1); 452 again = true; 453 } 454 455 /* further PCB init done later. */ 456 457 switch (caa->cpu_role) { 458 case CPU_ROLE_SP: 459 atomic_or_32(&ci->ci_flags, CPUF_SP); 460 cpu_identify(ci); 461 x86_cpu_idle_init(); 462 break; 463 464 case CPU_ROLE_BP: 465 atomic_or_32(&ci->ci_flags, CPUF_BSP); 466 cpu_identify(ci); 467 x86_cpu_idle_init(); 468 break; 469 470 case CPU_ROLE_AP: 471 atomic_or_32(&ci->ci_flags, CPUF_AP); 472 473 /* 474 * report on an AP 475 */ 476 477 #if defined(MULTIPROCESSOR) 478 /* interrupt handler stack */ 479 cpu_intr_init(ci); 480 481 /* Setup per-cpu memory for idt */ 482 idt_vec_init_cpu_md(&ci->ci_idtvec, cpu_index(ci)); 483 484 /* Setup per-cpu memory for gdt */ 485 gdt_alloc_cpu(ci); 486 487 pmap_cpu_init_late(ci); 488 cpu_start_secondary(ci); 489 490 if (ci->ci_flags & CPUF_PRESENT) { 491 struct cpu_info *tmp; 492 493 cpu_identify(ci); 494 tmp = cpu_info_list; 495 while (tmp->ci_next) 496 tmp = tmp->ci_next; 497 498 tmp->ci_next = ci; 499 } 500 #else 501 aprint_error_dev(ci->ci_dev, "not started\n"); 502 #endif 503 break; 504 505 default: 506 panic("unknown processor type??\n"); 507 } 508 509 #ifdef MPVERBOSE 510 if (mp_verbose) { 511 struct lwp *l = ci->ci_data.cpu_idlelwp; 512 struct pcb *pcb = lwp_getpcb(l); 513 514 aprint_verbose_dev(self, 515 "idle lwp at %p, idle sp at %p\n", 516 l, 517 #ifdef i386 518 (void *)pcb->pcb_esp 519 #else 520 (void *)pcb->pcb_rsp 521 #endif 522 ); 523 524 } 525 #endif /* MPVERBOSE */ 526 } 527 528 /* 529 * Initialize the processor appropriately. 530 */ 531 532 void 533 cpu_init(struct cpu_info *ci) 534 { 535 uint32_t cr4 = 0; 536 537 /* 538 * If we have FXSAVE/FXRESTOR, use them. 539 */ 540 if (cpu_feature[0] & CPUID_FXSR) { 541 cr4 |= CR4_OSFXSR; 542 543 /* 544 * If we have SSE/SSE2, enable XMM exceptions. 545 */ 546 if (cpu_feature[0] & (CPUID_SSE|CPUID_SSE2)) 547 cr4 |= CR4_OSXMMEXCPT; 548 } 549 550 /* If xsave is supported, enable it */ 551 if (cpu_feature[1] & CPUID2_XSAVE && x86_fpu_save >= FPU_SAVE_XSAVE) 552 cr4 |= CR4_OSXSAVE; 553 554 if (cr4) { 555 cr4 |= rcr4(); 556 lcr4(cr4); 557 } 558 559 if (x86_fpu_save >= FPU_SAVE_FXSAVE) { 560 fpuinit_mxcsr_mask(); 561 } 562 563 /* 564 * Changing CR4 register may change cpuid values. For example, setting 565 * CR4_OSXSAVE sets CPUID2_OSXSAVE. The CPUID2_OSXSAVE is in 566 * ci_feat_val[1], so update it. 567 * XXX Other than ci_feat_val[1] might be changed. 568 */ 569 if (cpuid_level >= 1) { 570 u_int descs[4]; 571 572 x86_cpuid(1, descs); 573 ci->ci_feat_val[1] = descs[2]; 574 } 575 576 /* If xsave is enabled, enable all fpu features */ 577 if (cr4 & CR4_OSXSAVE) { 578 wrxcr(0, x86_xsave_features & XCR0_FPU); 579 } 580 581 atomic_or_32(&ci->ci_flags, CPUF_RUNNING); 582 } 583 584 585 #ifdef MULTIPROCESSOR 586 587 void 588 cpu_boot_secondary_processors(void) 589 { 590 struct cpu_info *ci; 591 kcpuset_t *cpus; 592 u_long i; 593 594 kcpuset_create(&cpus, true); 595 kcpuset_set(cpus, cpu_index(curcpu())); 596 for (i = 0; i < maxcpus; i++) { 597 ci = cpu_lookup(i); 598 if (ci == NULL) 599 continue; 600 if (ci->ci_data.cpu_idlelwp == NULL) 601 continue; 602 if ((ci->ci_flags & CPUF_PRESENT) == 0) 603 continue; 604 if (ci->ci_flags & (CPUF_BSP|CPUF_SP|CPUF_PRIMARY)) 605 continue; 606 cpu_boot_secondary(ci); 607 kcpuset_set(cpus, cpu_index(ci)); 608 } 609 while (!kcpuset_match(cpus, kcpuset_running)) 610 ; 611 kcpuset_destroy(cpus); 612 613 x86_mp_online = true; 614 } 615 616 static void 617 cpu_init_idle_lwp(struct cpu_info *ci) 618 { 619 struct lwp *l = ci->ci_data.cpu_idlelwp; 620 struct pcb *pcb = lwp_getpcb(l); 621 622 pcb->pcb_cr0 = rcr0(); 623 } 624 625 void 626 cpu_init_idle_lwps(void) 627 { 628 struct cpu_info *ci; 629 u_long i; 630 631 for (i = 0; i < maxcpus; i++) { 632 ci = cpu_lookup(i); 633 if (ci == NULL) 634 continue; 635 if (ci->ci_data.cpu_idlelwp == NULL) 636 continue; 637 if ((ci->ci_flags & CPUF_PRESENT) == 0) 638 continue; 639 cpu_init_idle_lwp(ci); 640 } 641 } 642 643 static void 644 cpu_start_secondary(struct cpu_info *ci) 645 { 646 int i; 647 648 aprint_debug_dev(ci->ci_dev, "starting\n"); 649 650 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 651 652 if (CPU_STARTUP(ci, (vaddr_t) cpu_hatch) != 0) { 653 return; 654 } 655 656 /* 657 * wait for it to become ready 658 */ 659 for (i = 100000; (!(ci->ci_flags & CPUF_PRESENT)) && i > 0; i--) { 660 delay(10); 661 } 662 if ((ci->ci_flags & CPUF_PRESENT) == 0) { 663 aprint_error_dev(ci->ci_dev, "failed to become ready\n"); 664 #if defined(MPDEBUG) && defined(DDB) 665 printf("dropping into debugger; continue from here to resume boot\n"); 666 Debugger(); 667 #endif 668 } 669 670 CPU_START_CLEANUP(ci); 671 } 672 673 void 674 cpu_boot_secondary(struct cpu_info *ci) 675 { 676 int i; 677 atomic_or_32(&ci->ci_flags, CPUF_GO); 678 for (i = 100000; (!(ci->ci_flags & CPUF_RUNNING)) && i > 0; i--) { 679 delay(10); 680 } 681 if ((ci->ci_flags & CPUF_RUNNING) == 0) { 682 aprint_error_dev(ci->ci_dev, "CPU failed to start\n"); 683 #if defined(MPDEBUG) && defined(DDB) 684 printf("dropping into debugger; continue from here to resume boot\n"); 685 Debugger(); 686 #endif 687 } 688 } 689 690 /* 691 * APs end up here immediately after initialisation and VCPUOP_up in 692 * mp_cpu_start(). 693 * At this point, we are running in the idle pcb/idle stack of the new 694 * CPU. This function jumps to the idle loop and starts looking for 695 * work. 696 */ 697 extern void x86_64_tls_switch(struct lwp *); 698 void 699 cpu_hatch(void *v) 700 { 701 struct cpu_info *ci = (struct cpu_info *)v; 702 struct pcb *pcb; 703 int s, i; 704 705 /* Setup TLS and kernel GS/FS */ 706 cpu_init_msrs(ci, true); 707 cpu_init_idt(ci); 708 gdt_init_cpu(ci); 709 710 cpu_probe(ci); 711 712 atomic_or_32(&ci->ci_flags, CPUF_PRESENT); 713 714 while ((ci->ci_flags & CPUF_GO) == 0) { 715 /* Don't use delay, boot CPU may be patching the text. */ 716 for (i = 10000; i != 0; i--) 717 x86_pause(); 718 } 719 720 /* Because the text may have been patched in x86_patch(). */ 721 x86_flush(); 722 tlbflushg(); 723 724 KASSERT((ci->ci_flags & CPUF_RUNNING) == 0); 725 726 KASSERT(ci->ci_curlwp == ci->ci_data.cpu_idlelwp); 727 KASSERT(curlwp == ci->ci_data.cpu_idlelwp); 728 pcb = lwp_getpcb(curlwp); 729 pcb->pcb_cr3 = pmap_pdirpa(pmap_kernel(), 0); 730 731 xen_ipi_init(); 732 733 xen_initclocks(); 734 735 #ifdef __x86_64__ 736 fpuinit(ci); 737 #endif 738 739 lldt(GSEL(GLDT_SEL, SEL_KPL)); 740 741 cpu_init(ci); 742 cpu_get_tsc_freq(ci); 743 744 s = splhigh(); 745 x86_enable_intr(); 746 splx(s); 747 748 aprint_debug_dev(ci->ci_dev, "running\n"); 749 750 KASSERT(ci->ci_curlwp == ci->ci_data.cpu_idlelwp); 751 idle_loop(NULL); 752 KASSERT(false); 753 } 754 755 #if defined(DDB) 756 757 #include <ddb/db_output.h> 758 #include <machine/db_machdep.h> 759 760 /* 761 * Dump CPU information from ddb. 762 */ 763 void 764 cpu_debug_dump(void) 765 { 766 struct cpu_info *ci; 767 CPU_INFO_ITERATOR cii; 768 769 db_printf("addr dev id flags ipis curlwp\n"); 770 for (CPU_INFO_FOREACH(cii, ci)) { 771 db_printf("%p %s %ld %x %x %10p\n", 772 ci, 773 ci->ci_dev == NULL ? "BOOT" : device_xname(ci->ci_dev), 774 (long)ci->ci_vcpuid, 775 ci->ci_flags, ci->ci_ipis, 776 ci->ci_curlwp); 777 } 778 } 779 #endif /* DDB */ 780 781 #endif /* MULTIPROCESSOR */ 782 783 extern void hypervisor_callback(void); 784 extern void failsafe_callback(void); 785 #ifdef __x86_64__ 786 typedef void (vector)(void); 787 extern vector Xsyscall, Xsyscall32; 788 #endif 789 790 /* 791 * Setup the "trampoline". On Xen, we setup nearly all cpu context 792 * outside a trampoline, so we prototype and call targetip like so: 793 * void targetip(struct cpu_info *); 794 */ 795 796 static void 797 gdt_prepframes(paddr_t *frames, vaddr_t base, uint32_t entries) 798 { 799 int i; 800 for (i = 0; i < entries; i++) { 801 frames[i] = ((paddr_t)xpmap_ptetomach( 802 (pt_entry_t *)(base + (i << PAGE_SHIFT)))) >> PAGE_SHIFT; 803 804 /* Mark Read-only */ 805 pmap_pte_clearbits(kvtopte(base + (i << PAGE_SHIFT)), 806 PTE_W); 807 } 808 } 809 810 #ifdef __x86_64__ 811 extern char *ldtstore; 812 813 static void 814 xen_init_amd64_vcpuctxt(struct cpu_info *ci, struct vcpu_guest_context *initctx, 815 void targetrip(struct cpu_info *)) 816 { 817 /* page frames to point at GDT */ 818 extern int gdt_size; 819 paddr_t frames[16]; 820 psize_t gdt_ents; 821 822 struct lwp *l; 823 struct pcb *pcb; 824 825 volatile struct vcpu_info *vci; 826 827 KASSERT(ci != NULL); 828 KASSERT(ci != &cpu_info_primary); 829 KASSERT(initctx != NULL); 830 KASSERT(targetrip != NULL); 831 832 memset(initctx, 0, sizeof(*initctx)); 833 834 gdt_ents = roundup(gdt_size, PAGE_SIZE) >> PAGE_SHIFT; 835 KASSERT(gdt_ents <= 16); 836 837 gdt_prepframes(frames, (vaddr_t)ci->ci_gdt, gdt_ents); 838 839 /* Initialise the vcpu context: We use idle_loop()'s pcb context. */ 840 841 l = ci->ci_data.cpu_idlelwp; 842 843 KASSERT(l != NULL); 844 pcb = lwp_getpcb(l); 845 KASSERT(pcb != NULL); 846 847 /* resume with interrupts off */ 848 vci = ci->ci_vcpu; 849 vci->evtchn_upcall_mask = 1; 850 xen_mb(); 851 852 /* resume in kernel-mode */ 853 initctx->flags = VGCF_in_kernel | VGCF_online; 854 855 /* Stack and entry points: 856 * We arrange for the stack frame for cpu_hatch() to 857 * appear as a callee frame of lwp_trampoline(). Being a 858 * leaf frame prevents trampling on any of the MD stack setup 859 * that x86/vm_machdep.c:cpu_lwp_fork() does for idle_loop() 860 */ 861 862 initctx->user_regs.rdi = (uint64_t) ci; /* targetrip(ci); */ 863 initctx->user_regs.rip = (vaddr_t) targetrip; 864 865 initctx->user_regs.cs = GSEL(GCODE_SEL, SEL_KPL); 866 867 initctx->user_regs.rflags = pcb->pcb_flags; 868 initctx->user_regs.rsp = pcb->pcb_rsp; 869 870 /* Data segments */ 871 initctx->user_regs.ss = GSEL(GDATA_SEL, SEL_KPL); 872 initctx->user_regs.es = GSEL(GDATA_SEL, SEL_KPL); 873 initctx->user_regs.ds = GSEL(GDATA_SEL, SEL_KPL); 874 875 /* GDT */ 876 memcpy(initctx->gdt_frames, frames, sizeof(frames)); 877 initctx->gdt_ents = gdt_ents; 878 879 /* LDT */ 880 initctx->ldt_base = (unsigned long)ldtstore; 881 initctx->ldt_ents = LDT_SIZE >> 3; 882 883 /* Kernel context state */ 884 initctx->kernel_ss = GSEL(GDATA_SEL, SEL_KPL); 885 initctx->kernel_sp = pcb->pcb_rsp0; 886 initctx->ctrlreg[0] = pcb->pcb_cr0; 887 initctx->ctrlreg[1] = 0; /* "resuming" from kernel - no User cr3. */ 888 initctx->ctrlreg[2] = (vaddr_t)targetrip; 889 /* 890 * Use pmap_kernel() L4 PD directly, until we setup the 891 * per-cpu L4 PD in pmap_cpu_init_late() 892 */ 893 initctx->ctrlreg[3] = xen_pfn_to_cr3(x86_btop(xpmap_ptom(ci->ci_kpm_pdirpa))); 894 initctx->ctrlreg[4] = CR4_PAE | CR4_OSFXSR | CR4_OSXMMEXCPT; 895 896 /* Xen callbacks */ 897 initctx->event_callback_eip = (unsigned long)hypervisor_callback; 898 initctx->failsafe_callback_eip = (unsigned long)failsafe_callback; 899 initctx->syscall_callback_eip = (unsigned long)Xsyscall; 900 901 return; 902 } 903 #else /* i386 */ 904 extern union descriptor *ldtstore; 905 extern void Xsyscall(void); 906 907 static void 908 xen_init_i386_vcpuctxt(struct cpu_info *ci, struct vcpu_guest_context *initctx, 909 void targeteip(struct cpu_info *)) 910 { 911 /* page frames to point at GDT */ 912 extern int gdt_size; 913 paddr_t frames[16]; 914 psize_t gdt_ents; 915 916 struct lwp *l; 917 struct pcb *pcb; 918 919 volatile struct vcpu_info *vci; 920 921 KASSERT(ci != NULL); 922 KASSERT(ci != &cpu_info_primary); 923 KASSERT(initctx != NULL); 924 KASSERT(targeteip != NULL); 925 926 memset(initctx, 0, sizeof(*initctx)); 927 928 gdt_ents = roundup(gdt_size, PAGE_SIZE) >> PAGE_SHIFT; 929 KASSERT(gdt_ents <= 16); 930 931 gdt_prepframes(frames, (vaddr_t)ci->ci_gdt, gdt_ents); 932 933 /* 934 * Initialise the vcpu context: 935 * We use this cpu's idle_loop() pcb context. 936 */ 937 938 l = ci->ci_data.cpu_idlelwp; 939 940 KASSERT(l != NULL); 941 pcb = lwp_getpcb(l); 942 KASSERT(pcb != NULL); 943 944 /* resume with interrupts off */ 945 vci = ci->ci_vcpu; 946 vci->evtchn_upcall_mask = 1; 947 xen_mb(); 948 949 /* resume in kernel-mode */ 950 initctx->flags = VGCF_in_kernel | VGCF_online; 951 952 /* Stack frame setup for cpu_hatch(): 953 * We arrange for the stack frame for cpu_hatch() to 954 * appear as a callee frame of lwp_trampoline(). Being a 955 * leaf frame prevents trampling on any of the MD stack setup 956 * that x86/vm_machdep.c:cpu_lwp_fork() does for idle_loop() 957 */ 958 959 initctx->user_regs.esp = pcb->pcb_esp - 4; /* Leave word for 960 arg1 */ 961 { 962 /* targeteip(ci); */ 963 uint32_t *arg = (uint32_t *)initctx->user_regs.esp; 964 arg[1] = (uint32_t)ci; /* arg1 */ 965 } 966 967 initctx->user_regs.eip = (vaddr_t)targeteip; 968 initctx->user_regs.cs = GSEL(GCODE_SEL, SEL_KPL); 969 initctx->user_regs.eflags |= pcb->pcb_iopl; 970 971 /* Data segments */ 972 initctx->user_regs.ss = GSEL(GDATA_SEL, SEL_KPL); 973 initctx->user_regs.es = GSEL(GDATA_SEL, SEL_KPL); 974 initctx->user_regs.ds = GSEL(GDATA_SEL, SEL_KPL); 975 initctx->user_regs.fs = GSEL(GDATA_SEL, SEL_KPL); 976 977 /* GDT */ 978 memcpy(initctx->gdt_frames, frames, sizeof(frames)); 979 initctx->gdt_ents = gdt_ents; 980 981 /* LDT */ 982 initctx->ldt_base = (unsigned long)ldtstore; 983 initctx->ldt_ents = NLDT; 984 985 /* Kernel context state */ 986 initctx->kernel_ss = GSEL(GDATA_SEL, SEL_KPL); 987 initctx->kernel_sp = pcb->pcb_esp0; 988 initctx->ctrlreg[0] = pcb->pcb_cr0; 989 initctx->ctrlreg[1] = 0; /* "resuming" from kernel - no User cr3. */ 990 initctx->ctrlreg[2] = (vaddr_t)targeteip; 991 initctx->ctrlreg[3] = xen_pfn_to_cr3(x86_btop(xpmap_ptom(ci->ci_pae_l3_pdirpa))); 992 initctx->ctrlreg[4] = /* CR4_PAE | */CR4_OSFXSR | CR4_OSXMMEXCPT; 993 994 /* Xen callbacks */ 995 initctx->event_callback_eip = (unsigned long)hypervisor_callback; 996 initctx->event_callback_cs = GSEL(GCODE_SEL, SEL_KPL); 997 initctx->failsafe_callback_eip = (unsigned long)failsafe_callback; 998 initctx->failsafe_callback_cs = GSEL(GCODE_SEL, SEL_KPL); 999 1000 return; 1001 } 1002 #endif /* __x86_64__ */ 1003 1004 int 1005 mp_cpu_start(struct cpu_info *ci, vaddr_t target) 1006 { 1007 int hyperror; 1008 struct vcpu_guest_context *vcpuctx; 1009 1010 KASSERT(ci != NULL); 1011 KASSERT(ci != &cpu_info_primary); 1012 KASSERT(ci->ci_flags & CPUF_AP); 1013 1014 vcpuctx = kmem_alloc(sizeof(*vcpuctx), KM_SLEEP); 1015 1016 #ifdef __x86_64__ 1017 xen_init_amd64_vcpuctxt(ci, vcpuctx, (void (*)(struct cpu_info *))target); 1018 #else 1019 xen_init_i386_vcpuctxt(ci, vcpuctx, (void (*)(struct cpu_info *))target); 1020 #endif 1021 1022 /* Initialise the given vcpu to execute cpu_hatch(ci); */ 1023 if ((hyperror = HYPERVISOR_vcpu_op(VCPUOP_initialise, ci->ci_vcpuid, vcpuctx))) { 1024 aprint_error(": context initialisation failed. errno = %d\n", hyperror); 1025 goto out; 1026 } 1027 1028 /* Start it up */ 1029 1030 /* First bring it down */ 1031 if ((hyperror = HYPERVISOR_vcpu_op(VCPUOP_down, ci->ci_vcpuid, NULL))) { 1032 aprint_error(": VCPUOP_down hypervisor command failed. errno = %d\n", hyperror); 1033 goto out; 1034 } 1035 1036 if ((hyperror = HYPERVISOR_vcpu_op(VCPUOP_up, ci->ci_vcpuid, NULL))) { 1037 aprint_error(": VCPUOP_up hypervisor command failed. errno = %d\n", hyperror); 1038 goto out; 1039 } 1040 1041 if (!vcpu_is_up(ci)) { 1042 aprint_error(": did not come up\n"); 1043 hyperror = -1; 1044 goto out; 1045 } 1046 1047 out: 1048 kmem_free(vcpuctx, sizeof(*vcpuctx)); 1049 return hyperror; 1050 } 1051 1052 void 1053 mp_cpu_start_cleanup(struct cpu_info *ci) 1054 { 1055 if (vcpu_is_up(ci)) { 1056 aprint_debug_dev(ci->ci_dev, "is started.\n"); 1057 } else { 1058 aprint_error_dev(ci->ci_dev, "did not start up.\n"); 1059 } 1060 } 1061 1062 void 1063 cpu_init_msrs(struct cpu_info *ci, bool full) 1064 { 1065 #ifdef __x86_64__ 1066 if (full) { 1067 HYPERVISOR_set_segment_base(SEGBASE_FS, 0); 1068 HYPERVISOR_set_segment_base(SEGBASE_GS_KERNEL, (uint64_t)ci); 1069 HYPERVISOR_set_segment_base(SEGBASE_GS_USER, 0); 1070 } 1071 #endif 1072 1073 if (cpu_feature[2] & CPUID_NOX) 1074 wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_NXE); 1075 } 1076 1077 void 1078 cpu_offline_md(void) 1079 { 1080 return; 1081 } 1082 1083 void 1084 cpu_get_tsc_freq(struct cpu_info *ci) 1085 { 1086 uint32_t vcpu_tversion; 1087 const volatile vcpu_time_info_t *tinfo = &ci->ci_vcpu->time; 1088 1089 vcpu_tversion = tinfo->version; 1090 while (tinfo->version == vcpu_tversion); /* Wait for a time update. XXX: timeout ? */ 1091 1092 uint64_t freq = 1000000000ULL << 32; 1093 freq = freq / (uint64_t)tinfo->tsc_to_system_mul; 1094 if (tinfo->tsc_shift < 0) 1095 freq = freq << -tinfo->tsc_shift; 1096 else 1097 freq = freq >> tinfo->tsc_shift; 1098 ci->ci_data.cpu_cc_freq = freq; 1099 } 1100 1101 /* 1102 * Loads pmap for the current CPU. 1103 */ 1104 void 1105 cpu_load_pmap(struct pmap *pmap, struct pmap *oldpmap) 1106 { 1107 struct cpu_info *ci = curcpu(); 1108 cpuid_t cid = cpu_index(ci); 1109 int i; 1110 1111 KASSERT(pmap != pmap_kernel()); 1112 1113 mutex_enter(&ci->ci_kpm_mtx); 1114 /* make new pmap visible to xen_kpm_sync() */ 1115 kcpuset_atomic_set(pmap->pm_xen_ptp_cpus, cid); 1116 1117 #ifdef __x86_64__ 1118 pd_entry_t *new_pgd; 1119 paddr_t l4_pd_ma; 1120 1121 l4_pd_ma = xpmap_ptom_masked(ci->ci_kpm_pdirpa); 1122 1123 /* 1124 * Map user space address in kernel space and load 1125 * user cr3 1126 */ 1127 new_pgd = pmap->pm_pdir; 1128 KASSERT(pmap == ci->ci_pmap); 1129 1130 /* Copy user pmap L4 PDEs (in user addr. range) to per-cpu L4 */ 1131 for (i = 0; i < PDIR_SLOT_USERLIM; i++) { 1132 KASSERT(pmap != pmap_kernel() || new_pgd[i] == 0); 1133 if (ci->ci_kpm_pdir[i] != new_pgd[i]) { 1134 xpq_queue_pte_update(l4_pd_ma + i * sizeof(pd_entry_t), 1135 new_pgd[i]); 1136 } 1137 } 1138 1139 xen_set_user_pgd(pmap_pdirpa(pmap, 0)); 1140 ci->ci_xen_current_user_pgd = pmap_pdirpa(pmap, 0); 1141 #else 1142 paddr_t l3_pd = xpmap_ptom_masked(ci->ci_pae_l3_pdirpa); 1143 /* don't update the kernel L3 slot */ 1144 for (i = 0; i < PDP_SIZE - 1; i++) { 1145 xpq_queue_pte_update(l3_pd + i * sizeof(pd_entry_t), 1146 xpmap_ptom(pmap->pm_pdirpa[i]) | PTE_P); 1147 } 1148 #endif 1149 1150 tlbflush(); 1151 1152 /* old pmap no longer visible to xen_kpm_sync() */ 1153 if (oldpmap != pmap_kernel()) { 1154 kcpuset_atomic_clear(oldpmap->pm_xen_ptp_cpus, cid); 1155 } 1156 mutex_exit(&ci->ci_kpm_mtx); 1157 } 1158 1159 /* 1160 * pmap_cpu_init_late: perform late per-CPU initialization. 1161 * 1162 * Short note about percpu PDIR pages. Both the PAE and __x86_64__ architectures 1163 * have per-cpu PDIR tables, for two different reasons: 1164 * - on PAE, this is to get around Xen's pagetable setup constraints (multiple 1165 * L3[3]s cannot point to the same L2 - Xen will refuse to pin a table set up 1166 * this way). 1167 * - on __x86_64__, this is for multiple CPUs to map in different user pmaps 1168 * (see cpu_load_pmap()). 1169 * 1170 * What this means for us is that the PDIR of the pmap_kernel() is considered 1171 * to be a canonical "SHADOW" PDIR with the following properties: 1172 * - its recursive mapping points to itself 1173 * - per-cpu recursive mappings point to themselves on __x86_64__ 1174 * - per-cpu L4 pages' kernel entries are expected to be in sync with 1175 * the shadow 1176 */ 1177 1178 void 1179 pmap_cpu_init_late(struct cpu_info *ci) 1180 { 1181 int i; 1182 1183 /* 1184 * The BP has already its own PD page allocated during early 1185 * MD startup. 1186 */ 1187 1188 #ifdef __x86_64__ 1189 /* Setup per-cpu normal_pdes */ 1190 extern pd_entry_t * const normal_pdes[]; 1191 for (i = 0;i < PTP_LEVELS - 1;i++) { 1192 ci->ci_normal_pdes[i] = normal_pdes[i]; 1193 } 1194 #endif 1195 1196 if (ci == &cpu_info_primary) 1197 return; 1198 1199 KASSERT(ci != NULL); 1200 1201 #if defined(i386) 1202 cpu_alloc_l3_page(ci); 1203 KASSERT(ci->ci_pae_l3_pdirpa != 0); 1204 1205 /* Initialise L2 entries 0 - 2: Point them to pmap_kernel() */ 1206 for (i = 0; i < PDP_SIZE - 1; i++) { 1207 ci->ci_pae_l3_pdir[i] = 1208 xpmap_ptom_masked(pmap_kernel()->pm_pdirpa[i]) | PTE_P; 1209 } 1210 #endif 1211 1212 ci->ci_kpm_pdir = (pd_entry_t *)uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 1213 UVM_KMF_WIRED | UVM_KMF_ZERO | UVM_KMF_NOWAIT); 1214 1215 if (ci->ci_kpm_pdir == NULL) { 1216 panic("%s: failed to allocate L4 per-cpu PD for CPU %d\n", 1217 __func__, cpu_index(ci)); 1218 } 1219 ci->ci_kpm_pdirpa = vtophys((vaddr_t)ci->ci_kpm_pdir); 1220 KASSERT(ci->ci_kpm_pdirpa != 0); 1221 1222 #ifdef __x86_64__ 1223 extern pt_entry_t xpmap_pg_nx; 1224 1225 /* Copy over the pmap_kernel() shadow L4 entries */ 1226 memcpy(ci->ci_kpm_pdir, pmap_kernel()->pm_pdir, PAGE_SIZE); 1227 1228 /* Recursive kernel mapping */ 1229 ci->ci_kpm_pdir[PDIR_SLOT_PTE] = xpmap_ptom_masked(ci->ci_kpm_pdirpa) 1230 | PTE_P | xpmap_pg_nx; 1231 #else 1232 /* Copy over the pmap_kernel() shadow L2 entries */ 1233 memcpy(ci->ci_kpm_pdir, pmap_kernel()->pm_pdir + PDIR_SLOT_KERN, 1234 nkptp[PTP_LEVELS - 1] * sizeof(pd_entry_t)); 1235 #endif 1236 1237 /* Xen wants a RO pdir. */ 1238 pmap_protect(pmap_kernel(), (vaddr_t)ci->ci_kpm_pdir, 1239 (vaddr_t)ci->ci_kpm_pdir + PAGE_SIZE, VM_PROT_READ); 1240 pmap_update(pmap_kernel()); 1241 1242 #ifdef __x86_64__ 1243 xpq_queue_pin_l4_table(xpmap_ptom_masked(ci->ci_kpm_pdirpa)); 1244 #else 1245 /* 1246 * Initialize L3 entry 3. This mapping is shared across all pmaps and is 1247 * static, ie: loading a new pmap will not update this entry. 1248 */ 1249 ci->ci_pae_l3_pdir[3] = xpmap_ptom_masked(ci->ci_kpm_pdirpa) | PTE_P; 1250 1251 /* Xen wants a RO L3. */ 1252 pmap_protect(pmap_kernel(), (vaddr_t)ci->ci_pae_l3_pdir, 1253 (vaddr_t)ci->ci_pae_l3_pdir + PAGE_SIZE, VM_PROT_READ); 1254 pmap_update(pmap_kernel()); 1255 1256 xpq_queue_pin_l3_table(xpmap_ptom_masked(ci->ci_pae_l3_pdirpa)); 1257 #endif 1258 } 1259 1260 /* 1261 * Notify all other cpus to halt. 1262 */ 1263 1264 void 1265 cpu_broadcast_halt(void) 1266 { 1267 xen_broadcast_ipi(XEN_IPI_HALT); 1268 } 1269 1270 /* 1271 * Send a dummy ipi to a cpu, and raise an AST on the running LWP. 1272 */ 1273 1274 void 1275 cpu_kick(struct cpu_info *ci) 1276 { 1277 (void)xen_send_ipi(ci, XEN_IPI_AST); 1278 } 1279
Indexes created Tue Sep 23 21:09:50 GMT 2025