cpu.c revision 1.56.2.11
1 /* $NetBSD: cpu.c,v 1.56.2.11 2011/09/09 11:53:43 cherry Exp $ */ 2 /* NetBSD: cpu.c,v 1.18 2004/02/20 17:35:01 yamt Exp */ 3 4 /*- 5 * Copyright (c) 2000 The NetBSD Foundation, Inc. 6 * Copyright (c) 2002, 2006, 2007 YAMAMOTO Takashi, 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to The NetBSD Foundation 10 * by RedBack Networks Inc. 11 * 12 * Author: Bill Sommerfeld 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * Copyright (c) 1999 Stefan Grefen 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 56 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.56.2.11 2011/09/09 11:53:43 cherry Exp $"); 70 71 #include "opt_ddb.h" 72 #include "opt_multiprocessor.h" 73 #include "opt_mpbios.h" /* for MPDEBUG */ 74 #include "opt_mtrr.h" 75 #include "opt_xen.h" 76 77 #include "lapic.h" 78 #include "ioapic.h" 79 80 #include <sys/param.h> 81 #include <sys/proc.h> 82 #include <sys/systm.h> 83 #include <sys/device.h> 84 #include <sys/kmem.h> 85 #include <sys/cpu.h> 86 #include <sys/atomic.h> 87 #include <sys/reboot.h> 88 #include <sys/idle.h> 89 90 #include <uvm/uvm.h> 91 92 #include <machine/cpufunc.h> 93 #include <machine/cpuvar.h> 94 #include <machine/pmap.h> 95 #include <machine/vmparam.h> 96 #include <machine/mpbiosvar.h> 97 #include <machine/pcb.h> 98 #include <machine/specialreg.h> 99 #include <machine/segments.h> 100 #include <machine/gdt.h> 101 #include <machine/mtrr.h> 102 #include <machine/pio.h> 103 104 #ifdef i386 105 #include <machine/npx.h> 106 #else 107 #include <machine/fpu.h> 108 #endif 109 110 #include <xen/xen.h> 111 #include <xen/xen3-public/vcpu.h> 112 #include <xen/vcpuvar.h> 113 114 #if NLAPIC > 0 115 #include <machine/apicvar.h> 116 #include <machine/i82489reg.h> 117 #include <machine/i82489var.h> 118 #endif 119 120 #include <dev/ic/mc146818reg.h> 121 #include <dev/isa/isareg.h> 122 123 #if MAXCPUS > 32 124 #error cpu_info contains 32bit bitmasks 125 #endif 126 127 static int cpu_match(device_t, cfdata_t, void *); 128 static void cpu_attach(device_t, device_t, void *); 129 static void cpu_defer(device_t); 130 static int cpu_rescan(device_t, const char *, const int *); 131 static void cpu_childdetached(device_t, device_t); 132 static int vcpu_match(device_t, cfdata_t, void *); 133 static void vcpu_attach(device_t, device_t, void *); 134 static void cpu_attach_common(device_t, device_t, void *); 135 void cpu_offline_md(void); 136 137 struct cpu_softc { 138 device_t sc_dev; /* device tree glue */ 139 struct cpu_info *sc_info; /* pointer to CPU info */ 140 bool sc_wasonline; 141 }; 142 143 int mp_cpu_start(struct cpu_info *, vaddr_t); 144 void mp_cpu_start_cleanup(struct cpu_info *); 145 const struct cpu_functions mp_cpu_funcs = { mp_cpu_start, NULL, 146 mp_cpu_start_cleanup }; 147 148 CFATTACH_DECL2_NEW(cpu, sizeof(struct cpu_softc), 149 cpu_match, cpu_attach, NULL, NULL, cpu_rescan, cpu_childdetached); 150 151 CFATTACH_DECL_NEW(vcpu, sizeof(struct cpu_softc), 152 vcpu_match, vcpu_attach, NULL, NULL); 153 154 /* 155 * Statically-allocated CPU info for the primary CPU (or the only 156 * CPU, on uniprocessors). The CPU info list is initialized to 157 * point at it. 158 */ 159 #ifdef TRAPLOG 160 #include <machine/tlog.h> 161 struct tlog tlog_primary; 162 #endif 163 struct cpu_info cpu_info_primary __aligned(CACHE_LINE_SIZE) = { 164 .ci_dev = 0, 165 .ci_self = &cpu_info_primary, 166 .ci_idepth = -1, 167 .ci_curlwp = &lwp0, 168 .ci_curldt = -1, 169 .ci_cpumask = 1, 170 #ifdef TRAPLOG 171 .ci_tlog = &tlog_primary, 172 #endif 173 174 }; 175 struct cpu_info phycpu_info_primary __aligned(CACHE_LINE_SIZE) = { 176 .ci_dev = 0, 177 .ci_self = &phycpu_info_primary, 178 }; 179 180 struct cpu_info *cpu_info_list = &cpu_info_primary; 181 struct cpu_info *phycpu_info_list = &phycpu_info_primary; 182 183 uint32_t cpus_attached = 1; 184 uint32_t cpus_running = 0; 185 186 uint32_t phycpus_attached = 0; 187 uint32_t phycpus_running = 0; 188 189 uint32_t cpu_feature[5]; /* X86 CPUID feature bits 190 * [0] basic features %edx 191 * [1] basic features %ecx 192 * [2] extended features %edx 193 * [3] extended features %ecx 194 * [4] VIA padlock features 195 */ 196 197 bool x86_mp_online; 198 paddr_t mp_trampoline_paddr = MP_TRAMPOLINE; 199 200 #if defined(MULTIPROCESSOR) 201 void cpu_hatch(void *); 202 static void cpu_boot_secondary(struct cpu_info *ci); 203 static void cpu_start_secondary(struct cpu_info *ci); 204 #endif /* MULTIPROCESSOR */ 205 206 static int 207 cpu_match(device_t parent, cfdata_t match, void *aux) 208 { 209 210 return 1; 211 } 212 213 static void 214 cpu_attach(device_t parent, device_t self, void *aux) 215 { 216 struct cpu_softc *sc = device_private(self); 217 struct cpu_attach_args *caa = aux; 218 struct cpu_info *ci; 219 uintptr_t ptr; 220 static int nphycpu = 0; 221 222 sc->sc_dev = self; 223 224 if (phycpus_attached == ~0) { 225 aprint_error(": increase MAXCPUS\n"); 226 return; 227 } 228 229 /* 230 * If we're an Application Processor, allocate a cpu_info 231 * If we're the first attached CPU use the primary cpu_info, 232 * otherwise allocate a new one 233 */ 234 aprint_naive("\n"); 235 aprint_normal("\n"); 236 if (nphycpu > 0) { 237 struct cpu_info *tmp; 238 ptr = (uintptr_t)kmem_zalloc(sizeof(*ci) + CACHE_LINE_SIZE - 1, 239 KM_SLEEP); 240 ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE); 241 ci->ci_curldt = -1; 242 243 tmp = phycpu_info_list; 244 while (tmp->ci_next) 245 tmp = tmp->ci_next; 246 247 tmp->ci_next = ci; 248 } else { 249 ci = &phycpu_info_primary; 250 } 251 252 ci->ci_self = ci; 253 sc->sc_info = ci; 254 255 ci->ci_dev = self; 256 ci->ci_acpiid = caa->cpu_id; 257 ci->ci_cpuid = caa->cpu_number; 258 ci->ci_vcpu = NULL; 259 ci->ci_index = nphycpu++; 260 ci->ci_cpumask = (1 << cpu_index(ci)); 261 262 atomic_or_32(&phycpus_attached, ci->ci_cpumask); 263 264 if (!pmf_device_register(self, NULL, NULL)) 265 aprint_error_dev(self, "couldn't establish power handler\n"); 266 267 (void)config_defer(self, cpu_defer); 268 } 269 270 static void 271 cpu_defer(device_t self) 272 { 273 cpu_rescan(self, NULL, NULL); 274 } 275 276 static int 277 cpu_rescan(device_t self, const char *ifattr, const int *locators) 278 { 279 struct cpu_softc *sc = device_private(self); 280 struct cpufeature_attach_args cfaa; 281 struct cpu_info *ci = sc->sc_info; 282 283 memset(&cfaa, 0, sizeof(cfaa)); 284 cfaa.ci = ci; 285 286 if (ifattr_match(ifattr, "cpufeaturebus")) { 287 288 if (ci->ci_frequency == NULL) { 289 cfaa.name = "frequency"; 290 ci->ci_frequency = config_found_ia(self, 291 "cpufeaturebus", &cfaa, NULL); 292 } 293 } 294 295 return 0; 296 } 297 298 static void 299 cpu_childdetached(device_t self, device_t child) 300 { 301 struct cpu_softc *sc = device_private(self); 302 struct cpu_info *ci = sc->sc_info; 303 304 if (ci->ci_frequency == child) 305 ci->ci_frequency = NULL; 306 } 307 308 static int 309 vcpu_match(device_t parent, cfdata_t match, void *aux) 310 { 311 struct vcpu_attach_args *vcaa = aux; 312 struct vcpu_runstate_info vcr; 313 int error; 314 315 if (strcmp(vcaa->vcaa_name, match->cf_name) == 0) { 316 error = HYPERVISOR_vcpu_op(VCPUOP_get_runstate_info, 317 vcaa->vcaa_caa.cpu_number, 318 &vcr); 319 switch (error) { 320 case 0: 321 return 1; 322 case -ENOENT: 323 return 0; 324 default: 325 panic("Unknown hypervisor error %d returned on vcpu runstate probe\n", error); 326 } 327 } 328 329 return 0; 330 } 331 332 static void 333 vcpu_attach(device_t parent, device_t self, void *aux) 334 { 335 struct vcpu_attach_args *vcaa = aux; 336 337 KASSERT(vcaa->vcaa_caa.cpu_func == NULL); 338 vcaa->vcaa_caa.cpu_func = &mp_cpu_funcs; 339 cpu_attach_common(parent, self, &vcaa->vcaa_caa); 340 } 341 342 static int 343 vcpu_is_up(struct cpu_info *ci) 344 { 345 KASSERT(ci != NULL); 346 return HYPERVISOR_vcpu_op(VCPUOP_is_up, ci->ci_cpuid, NULL); 347 } 348 349 static void 350 cpu_vm_init(struct cpu_info *ci) 351 { 352 int ncolors = 2, i; 353 354 for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) { 355 struct x86_cache_info *cai; 356 int tcolors; 357 358 cai = &ci->ci_cinfo[i]; 359 360 tcolors = atop(cai->cai_totalsize); 361 switch(cai->cai_associativity) { 362 case 0xff: 363 tcolors = 1; /* fully associative */ 364 break; 365 case 0: 366 case 1: 367 break; 368 default: 369 tcolors /= cai->cai_associativity; 370 } 371 ncolors = max(ncolors, tcolors); 372 } 373 374 /* 375 * Knowing the size of the largest cache on this CPU, re-color 376 * our pages. 377 */ 378 if (ncolors <= uvmexp.ncolors) 379 return; 380 aprint_debug_dev(ci->ci_dev, "%d page colors\n", ncolors); 381 uvm_page_recolor(ncolors); 382 } 383 384 static void 385 cpu_attach_common(device_t parent, device_t self, void *aux) 386 { 387 struct cpu_softc *sc = device_private(self); 388 struct cpu_attach_args *caa = aux; 389 struct cpu_info *ci; 390 uintptr_t ptr; 391 int cpunum = caa->cpu_number; 392 static bool again = false; 393 394 sc->sc_dev = self; 395 396 /* 397 * If we're an Application Processor, allocate a cpu_info 398 * structure, otherwise use the primary's. 399 */ 400 if (caa->cpu_role == CPU_ROLE_AP) { 401 aprint_naive(": Application Processor\n"); 402 ptr = (uintptr_t)kmem_alloc(sizeof(*ci) + CACHE_LINE_SIZE - 1, 403 KM_SLEEP); 404 ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE); 405 memset(ci, 0, sizeof(*ci)); 406 #ifdef TRAPLOG 407 ci->ci_tlog_base = kmem_zalloc(sizeof(struct tlog), KM_SLEEP); 408 #endif 409 } else { 410 aprint_naive(": %s Processor\n", 411 caa->cpu_role == CPU_ROLE_SP ? "Single" : "Boot"); 412 ci = &cpu_info_primary; 413 } 414 415 ci->ci_self = ci; 416 sc->sc_info = ci; 417 ci->ci_dev = self; 418 ci->ci_cpuid = cpunum; 419 420 KASSERT(HYPERVISOR_shared_info != NULL); 421 ci->ci_vcpu = &HYPERVISOR_shared_info->vcpu_info[cpunum]; 422 423 KASSERT(ci->ci_func == 0); 424 ci->ci_func = caa->cpu_func; 425 426 /* Must be called before mi_cpu_attach(). */ 427 cpu_vm_init(ci); 428 429 if (caa->cpu_role == CPU_ROLE_AP) { 430 int error; 431 432 error = mi_cpu_attach(ci); 433 434 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 435 if (error != 0) { 436 aprint_normal("\n"); 437 aprint_error_dev(self, 438 "mi_cpu_attach failed with %d\n", error); 439 return; 440 } 441 442 } else { 443 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 444 } 445 446 ci->ci_cpumask = (1 << cpu_index(ci)); 447 pmap_reference(pmap_kernel()); 448 ci->ci_pmap = pmap_kernel(); 449 ci->ci_tlbstate = TLBSTATE_STALE; 450 451 /* 452 * Boot processor may not be attached first, but the below 453 * must be done to allow booting other processors. 454 */ 455 if (!again) { 456 atomic_or_32(&ci->ci_flags, CPUF_PRESENT | CPUF_PRIMARY); 457 /* Basic init. */ 458 cpu_intr_init(ci); 459 cpu_get_tsc_freq(ci); 460 cpu_init(ci); 461 pmap_cpu_init_late(ci); /* XXX: cosmetic */ 462 463 /* Every processor needs to init it's own ipi h/w (similar to lapic) */ 464 xen_ipi_init(); 465 /* XXX: clock_init() */ 466 467 /* Make sure DELAY() is initialized. */ 468 DELAY(1); 469 again = true; 470 } 471 472 /* further PCB init done later. */ 473 474 switch (caa->cpu_role) { 475 case CPU_ROLE_SP: 476 atomic_or_32(&ci->ci_flags, CPUF_SP); 477 cpu_identify(ci); 478 #if 0 479 x86_errata(); 480 #endif 481 x86_cpu_idle_init(); 482 483 break; 484 485 case CPU_ROLE_BP: 486 atomic_or_32(&ci->ci_flags, CPUF_BSP); 487 cpu_identify(ci); 488 cpu_init(ci); 489 #if 0 490 x86_errata(); 491 #endif 492 x86_cpu_idle_init(); 493 494 break; 495 496 case CPU_ROLE_AP: 497 atomic_or_32(&ci->ci_flags, CPUF_AP); 498 499 /* 500 * report on an AP 501 */ 502 503 #if defined(MULTIPROCESSOR) 504 /* interrupt handler stack */ 505 cpu_intr_init(ci); 506 507 /* Setup per-cpu memory for gdt */ 508 gdt_alloc_cpu(ci); 509 510 pmap_cpu_init_late(ci); 511 cpu_start_secondary(ci); 512 513 if (ci->ci_flags & CPUF_PRESENT) { 514 struct cpu_info *tmp; 515 516 cpu_identify(ci); 517 tmp = cpu_info_list; 518 while (tmp->ci_next) 519 tmp = tmp->ci_next; 520 521 tmp->ci_next = ci; 522 } 523 #else 524 aprint_error(": not started\n"); 525 #endif 526 break; 527 528 default: 529 aprint_normal("\n"); 530 panic("unknown processor type??\n"); 531 } 532 533 pat_init(ci); 534 atomic_or_32(&cpus_attached, ci->ci_cpumask); 535 536 #if 0 537 if (!pmf_device_register(self, cpu_suspend, cpu_resume)) 538 aprint_error_dev(self, "couldn't establish power handler\n"); 539 #endif 540 541 #ifdef MPVERBOSE 542 if (mp_verbose) { 543 struct lwp *l = ci->ci_data.cpu_idlelwp; 544 struct pcb *pcb = lwp_getpcb(l); 545 546 aprint_verbose_dev(self, 547 "idle lwp at %p, idle sp at 0x%p\n", 548 l, 549 #ifdef i386 550 (void *)pcb->pcb_esp 551 #else /* i386 */ 552 (void *)pcb->pcb_rsp 553 #endif /* i386 */ 554 ); 555 556 } 557 #endif /* MPVERBOSE */ 558 } 559 560 /* 561 * Initialize the processor appropriately. 562 */ 563 564 void 565 cpu_init(struct cpu_info *ci) 566 { 567 568 /* 569 * On a P6 or above, enable global TLB caching if the 570 * hardware supports it. 571 */ 572 if (cpu_feature[0] & CPUID_PGE) 573 lcr4(rcr4() | CR4_PGE); /* enable global TLB caching */ 574 575 #ifdef XXXMTRR 576 /* 577 * On a P6 or above, initialize MTRR's if the hardware supports them. 578 */ 579 if (cpu_feature[0] & CPUID_MTRR) { 580 if ((ci->ci_flags & CPUF_AP) == 0) 581 i686_mtrr_init_first(); 582 mtrr_init_cpu(ci); 583 } 584 #endif 585 /* 586 * If we have FXSAVE/FXRESTOR, use them. 587 */ 588 if (cpu_feature[0] & CPUID_FXSR) { 589 lcr4(rcr4() | CR4_OSFXSR); 590 591 /* 592 * If we have SSE/SSE2, enable XMM exceptions. 593 */ 594 if (cpu_feature[0] & (CPUID_SSE|CPUID_SSE2)) 595 lcr4(rcr4() | CR4_OSXMMEXCPT); 596 } 597 598 #ifdef __x86_64__ 599 /* No user PGD mapped for this CPU yet */ 600 ci->ci_xen_current_user_pgd = 0; 601 #endif 602 603 atomic_or_32(&cpus_running, ci->ci_cpumask); 604 atomic_or_32(&ci->ci_flags, CPUF_RUNNING); 605 606 /* XXX: register vcpu_register_runstate_memory_area, and figure out how to make sure this VCPU is running ? */ 607 } 608 609 610 #ifdef MULTIPROCESSOR 611 612 void 613 cpu_boot_secondary_processors(void) 614 { 615 struct cpu_info *ci; 616 u_long i; 617 for (i = 0; i < maxcpus; i++) { 618 ci = cpu_lookup(i); 619 if (ci == NULL) 620 continue; 621 if (ci->ci_data.cpu_idlelwp == NULL) 622 continue; 623 if ((ci->ci_flags & CPUF_PRESENT) == 0) 624 continue; 625 if (ci->ci_flags & (CPUF_BSP|CPUF_SP|CPUF_PRIMARY)) 626 continue; 627 cpu_boot_secondary(ci); 628 } 629 630 x86_mp_online = true; 631 } 632 633 static void 634 cpu_init_idle_lwp(struct cpu_info *ci) 635 { 636 struct lwp *l = ci->ci_data.cpu_idlelwp; 637 struct pcb *pcb = lwp_getpcb(l); 638 639 pcb->pcb_cr0 = rcr0(); 640 } 641 642 void 643 cpu_init_idle_lwps(void) 644 { 645 struct cpu_info *ci; 646 u_long i; 647 648 for (i = 0; i < maxcpus; i++) { 649 ci = cpu_lookup(i); 650 if (ci == NULL) 651 continue; 652 if (ci->ci_data.cpu_idlelwp == NULL) 653 continue; 654 if ((ci->ci_flags & CPUF_PRESENT) == 0) 655 continue; 656 cpu_init_idle_lwp(ci); 657 } 658 } 659 660 static void 661 cpu_start_secondary(struct cpu_info *ci) 662 { 663 int i; 664 665 aprint_debug_dev(ci->ci_dev, "starting\n"); 666 667 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 668 669 if (CPU_STARTUP(ci, (vaddr_t) cpu_hatch) != 0) { 670 return; 671 } 672 673 /* 674 * wait for it to become ready 675 */ 676 for (i = 100000; (!(ci->ci_flags & CPUF_PRESENT)) && i > 0; i--) { 677 delay(10); 678 } 679 if ((ci->ci_flags & CPUF_PRESENT) == 0) { 680 aprint_error_dev(ci->ci_dev, "failed to become ready\n"); 681 #if defined(MPDEBUG) && defined(DDB) 682 printf("dropping into debugger; continue from here to resume boot\n"); 683 Debugger(); 684 #endif 685 } 686 687 CPU_START_CLEANUP(ci); 688 } 689 690 void 691 cpu_boot_secondary(struct cpu_info *ci) 692 { 693 int i; 694 atomic_or_32(&ci->ci_flags, CPUF_GO); 695 for (i = 100000; (!(ci->ci_flags & CPUF_RUNNING)) && i > 0; i--) { 696 delay(10); 697 } 698 if ((ci->ci_flags & CPUF_RUNNING) == 0) { 699 aprint_error_dev(ci->ci_dev, "CPU failed to start\n"); 700 #if defined(MPDEBUG) && defined(DDB) 701 printf("dropping into debugger; continue from here to resume boot\n"); 702 Debugger(); 703 #endif 704 } 705 } 706 707 /* 708 * APs end up here immediately after initialisation and VCPUOP_up in 709 * mp_cpu_start(). 710 * At this point, we are running in the idle pcb/idle stack of the new 711 * CPU. This function jumps to the idle loop and starts looking for 712 * work. 713 */ 714 extern void x86_64_tls_switch(struct lwp *); 715 716 void 717 cpu_hatch(void *v) 718 { 719 struct cpu_info *ci = (struct cpu_info *)v; 720 struct pcb *pcb; 721 int s, i; 722 723 /* Setup TLS and kernel GS/FS */ 724 cpu_init_msrs(ci, true); 725 cpu_init_idt(); 726 gdt_init_cpu(ci); 727 728 cpu_probe(ci); 729 730 atomic_or_32(&ci->ci_flags, CPUF_PRESENT); 731 732 while ((ci->ci_flags & CPUF_GO) == 0) { 733 /* Don't use delay, boot CPU may be patching the text. */ 734 for (i = 10000; i != 0; i--) 735 x86_pause(); 736 } 737 738 /* Because the text may have been patched in x86_patch(). */ 739 x86_flush(); 740 tlbflushg(); 741 742 KASSERT((ci->ci_flags & CPUF_RUNNING) == 0); 743 744 pcb = lwp_getpcb(curlwp); 745 pcb->pcb_cr3 = pmap_pdirpa(pmap_kernel(), 0); /* XXX: consider using pmap_load() ? */ 746 pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp); 747 748 xen_ipi_init(); 749 750 xen_initclocks(); 751 752 /* XXX: lapic_initclocks(); */ 753 754 #ifdef __x86_64__ 755 fpuinit(ci); 756 #endif 757 758 lldt(GSEL(GLDT_SEL, SEL_KPL)); 759 760 cpu_init(ci); 761 cpu_get_tsc_freq(ci); 762 763 s = splhigh(); 764 x86_enable_intr(); 765 splx(s); 766 #if 0 767 x86_errata(); 768 #endif 769 770 aprint_debug_dev(ci->ci_dev, "running\n"); 771 772 cpu_switchto(NULL, ci->ci_data.cpu_idlelwp, true); 773 774 panic("switch to idle_loop context returned!\n"); 775 /* NOTREACHED */ 776 } 777 778 #if defined(DDB) 779 780 #include <ddb/db_output.h> 781 #include <machine/db_machdep.h> 782 783 /* 784 * Dump CPU information from ddb. 785 */ 786 void 787 cpu_debug_dump(void) 788 { 789 struct cpu_info *ci; 790 CPU_INFO_ITERATOR cii; 791 792 db_printf("addr dev id flags ipis curlwp fpcurlwp\n"); 793 for (CPU_INFO_FOREACH(cii, ci)) { 794 db_printf("%p %s %ld %x %x %10p %10p\n", 795 ci, 796 ci->ci_dev == NULL ? "BOOT" : device_xname(ci->ci_dev), 797 (long)ci->ci_cpuid, 798 ci->ci_flags, ci->ci_ipis, 799 ci->ci_curlwp, 800 ci->ci_fpcurlwp); 801 } 802 } 803 #endif /* DDB */ 804 805 #endif /* MULTIPROCESSOR */ 806 807 extern void hypervisor_callback(void); 808 extern void failsafe_callback(void); 809 #ifdef __x86_64__ 810 typedef void (vector)(void); 811 extern vector Xsyscall, Xsyscall32; 812 #endif 813 814 /* 815 * Setup the "trampoline". On Xen, we setup nearly all cpu context 816 * outside a trampoline, so we prototype and call targetip like so: 817 * void targetip(struct cpu_info *); 818 */ 819 820 static void 821 gdt_prepframes(paddr_t *frames, vaddr_t base, uint32_t entries) 822 { 823 int i; 824 for (i = 0; i < roundup(entries, PAGE_SIZE) >> PAGE_SHIFT; i++) { 825 826 frames[i] = ((paddr_t) xpmap_ptetomach( 827 (pt_entry_t *) (base + (i << PAGE_SHIFT)))) 828 >> PAGE_SHIFT; 829 830 /* Mark Read-only */ 831 pmap_pte_clearbits(kvtopte(base + (i << PAGE_SHIFT)), 832 PG_RW); 833 } 834 } 835 836 #ifdef __x86_64__ 837 extern char *ldtstore; /* XXX: Xen MP todo */ 838 839 static void 840 xen_init_amd64_vcpuctxt(struct cpu_info *ci, 841 struct vcpu_guest_context *initctx, 842 void targetrip(struct cpu_info *)) 843 { 844 /* page frames to point at GDT */ 845 extern int gdt_size; 846 paddr_t frames[16]; 847 psize_t gdt_ents; 848 849 struct lwp *l; 850 struct pcb *pcb; 851 852 volatile struct vcpu_info *vci; 853 854 KASSERT(ci != NULL); 855 KASSERT(ci != &cpu_info_primary); 856 KASSERT(initctx != NULL); 857 KASSERT(targetrip != NULL); 858 859 memset(initctx, 0, sizeof *initctx); 860 861 gdt_ents = roundup(gdt_size, PAGE_SIZE) >> PAGE_SHIFT; /* XXX: re-investigate roundup(gdt_size... ) for gdt_ents. */ 862 KASSERT(gdt_ents <= 16); 863 864 gdt_prepframes(frames, (vaddr_t) ci->ci_gdt, gdt_ents); 865 866 /* XXX: The stuff in here is amd64 specific. move to mptramp.[Sc] ? */ 867 868 /* Initialise the vcpu context: We use idle_loop()'s pcb context. */ 869 870 l = ci->ci_data.cpu_idlelwp; 871 872 KASSERT(l != NULL); 873 pcb = lwp_getpcb(l); 874 KASSERT(pcb != NULL); 875 876 /* resume with interrupts off */ 877 vci = ci->ci_vcpu; 878 vci->evtchn_upcall_mask = 1; 879 xen_mb(); 880 881 /* resume in kernel-mode */ 882 initctx->flags = VGCF_in_kernel | VGCF_online; 883 884 /* Stack and entry points: 885 * We arrange for the stack frame for cpu_hatch() to 886 * appear as a callee frame of lwp_trampoline(). Being a 887 * leaf frame prevents trampling on any of the MD stack setup 888 * that x86/vm_machdep.c:cpu_lwp_fork() does for idle_loop() 889 */ 890 891 initctx->user_regs.rdi = (uint64_t) ci; /* targetrip(ci); */ 892 initctx->user_regs.rip = (vaddr_t) targetrip; 893 894 initctx->user_regs.cs = GSEL(GCODE_SEL, SEL_KPL); 895 896 initctx->user_regs.rflags = pcb->pcb_flags; 897 initctx->user_regs.rsp = pcb->pcb_rsp; 898 899 /* Data segments */ 900 initctx->user_regs.ss = GSEL(GDATA_SEL, SEL_KPL); 901 initctx->user_regs.es = GSEL(GDATA_SEL, SEL_KPL); 902 initctx->user_regs.ds = GSEL(GDATA_SEL, SEL_KPL); 903 904 /* GDT */ 905 memcpy(initctx->gdt_frames, frames, sizeof frames); 906 initctx->gdt_ents = gdt_ents; 907 908 /* LDT */ 909 initctx->ldt_base = (unsigned long) ldtstore; 910 initctx->ldt_ents = LDT_SIZE >> 3; 911 912 /* Kernel context state */ 913 initctx->kernel_ss = GSEL(GDATA_SEL, SEL_KPL); 914 initctx->kernel_sp = pcb->pcb_rsp0; 915 initctx->ctrlreg[0] = pcb->pcb_cr0; 916 initctx->ctrlreg[1] = 0; /* "resuming" from kernel - no User cr3. */ 917 initctx->ctrlreg[2] = pcb->pcb_cr2; /* XXX: */ 918 /* 919 * Use pmap_kernel() L4 PD directly, until we setup the 920 * per-cpu L4 PD in pmap_cpu_init_late() 921 */ 922 923 initctx->ctrlreg[3] = xen_pfn_to_cr3(x86_btop(xpmap_ptom(ci->ci_kpm_pdirpa))); 924 initctx->ctrlreg[4] = CR4_PAE | CR4_OSFXSR | CR4_OSXMMEXCPT; 925 926 927 /* Xen callbacks */ 928 initctx->event_callback_eip = (unsigned long) hypervisor_callback; 929 initctx->failsafe_callback_eip = (unsigned long) failsafe_callback; 930 initctx->syscall_callback_eip = (unsigned long) Xsyscall; 931 932 return; 933 } 934 #else /* i386 */ 935 extern union descriptor *ldt; 936 extern void Xsyscall(void); 937 938 static void 939 xen_init_i386_vcpuctxt(struct cpu_info *ci, 940 struct vcpu_guest_context *initctx, 941 void targeteip(struct cpu_info *)) 942 { 943 /* page frames to point at GDT */ 944 extern int gdt_size; 945 paddr_t frames[16]; 946 psize_t gdt_ents; 947 948 struct lwp *l; 949 struct pcb *pcb; 950 951 volatile struct vcpu_info *vci; 952 953 KASSERT(ci != NULL); 954 KASSERT(ci != &cpu_info_primary); 955 KASSERT(initctx != NULL); 956 KASSERT(targeteip != NULL); 957 958 memset(initctx, 0, sizeof *initctx); 959 960 gdt_ents = roundup(gdt_size, PAGE_SIZE) >> PAGE_SHIFT; /* XXX: re-investigate roundup(gdt_size... ) for gdt_ents. */ 961 KASSERT(gdt_ents <= 16); 962 963 gdt_prepframes(frames, (vaddr_t) ci->ci_gdt, gdt_ents); 964 965 /* 966 * Initialise the vcpu context: 967 * We use this cpu's idle_loop() pcb context. 968 */ 969 970 l = ci->ci_data.cpu_idlelwp; 971 972 KASSERT(l != NULL); 973 pcb = lwp_getpcb(l); 974 KASSERT(pcb != NULL); 975 976 /* resume with interrupts off */ 977 vci = ci->ci_vcpu; 978 vci->evtchn_upcall_mask = 1; 979 xen_mb(); 980 981 /* resume in kernel-mode */ 982 initctx->flags = VGCF_in_kernel | VGCF_online; 983 984 /* Stack frame setup for cpu_hatch(): 985 * We arrange for the stack frame for cpu_hatch() to 986 * appear as a callee frame of lwp_trampoline(). Being a 987 * leaf frame prevents trampling on any of the MD stack setup 988 * that x86/vm_machdep.c:cpu_lwp_fork() does for idle_loop() 989 */ 990 991 initctx->user_regs.esp = pcb->pcb_esp - 4; /* Leave word for 992 arg1 */ 993 { /* targeteip(ci); */ 994 uint32_t *arg = (uint32_t *) initctx->user_regs.esp; 995 arg[1] = (uint32_t) ci; /* arg1 */ 996 997 } 998 999 initctx->user_regs.eip = (vaddr_t) targeteip; 1000 initctx->user_regs.cs = GSEL(GCODE_SEL, SEL_KPL); 1001 initctx->user_regs.eflags |= pcb->pcb_iopl; 1002 1003 /* Data segments */ 1004 initctx->user_regs.ss = GSEL(GDATA_SEL, SEL_KPL); 1005 initctx->user_regs.es = GSEL(GDATA_SEL, SEL_KPL); 1006 initctx->user_regs.ds = GSEL(GDATA_SEL, SEL_KPL); 1007 initctx->user_regs.fs = GSEL(GDATA_SEL, SEL_KPL); 1008 1009 /* GDT */ 1010 memcpy(initctx->gdt_frames, frames, sizeof frames); 1011 initctx->gdt_ents = gdt_ents; 1012 1013 /* LDT */ 1014 initctx->ldt_base = (unsigned long) ldt; 1015 initctx->ldt_ents = NLDT; 1016 1017 /* Kernel context state */ 1018 initctx->kernel_ss = GSEL(GDATA_SEL, SEL_KPL); 1019 initctx->kernel_sp = pcb->pcb_esp0; 1020 initctx->ctrlreg[0] = pcb->pcb_cr0; 1021 initctx->ctrlreg[1] = 0; /* "resuming" from kernel - no User cr3. */ 1022 initctx->ctrlreg[2] = pcb->pcb_cr2; /* XXX: */ 1023 /* 1024 * Use pmap_kernel() L4 PD directly, until we setup the 1025 * per-cpu L4 PD in pmap_cpu_init_late() 1026 */ 1027 #ifdef PAE 1028 initctx->ctrlreg[3] = xen_pfn_to_cr3(x86_btop(xpmap_ptom(ci->ci_pae_l3_pdirpa))); 1029 #else /* PAE */ 1030 initctx->ctrlreg[3] = xen_pfn_to_cr3(x86_btop(xpmap_ptom(pcb->pcb_cr3))); 1031 #endif /* PAE */ 1032 initctx->ctrlreg[4] = /* CR4_PAE | */CR4_OSFXSR | CR4_OSXMMEXCPT; 1033 1034 1035 /* Xen callbacks */ 1036 initctx->event_callback_eip = (unsigned long) hypervisor_callback; 1037 initctx->event_callback_cs = GSEL(GCODE_SEL, SEL_KPL); 1038 initctx->failsafe_callback_eip = (unsigned long) failsafe_callback; 1039 initctx->failsafe_callback_cs = GSEL(GCODE_SEL, SEL_KPL); 1040 1041 return; 1042 } 1043 #endif /* __x86_64__ */ 1044 1045 int 1046 mp_cpu_start(struct cpu_info *ci, vaddr_t target) 1047 { 1048 1049 int hyperror; 1050 struct vcpu_guest_context vcpuctx; 1051 1052 KASSERT(ci != NULL); 1053 KASSERT(ci != &cpu_info_primary); 1054 KASSERT(ci->ci_flags & CPUF_AP); 1055 1056 #ifdef __x86_64__ 1057 xen_init_amd64_vcpuctxt(ci, &vcpuctx, (void (*)(struct cpu_info *))target); 1058 #else /* i386 */ 1059 xen_init_i386_vcpuctxt(ci, &vcpuctx, (void (*)(struct cpu_info *))target); 1060 #endif /* __x86_64__ */ 1061 1062 /* Initialise the given vcpu to execute cpu_hatch(ci); */ 1063 if ((hyperror = HYPERVISOR_vcpu_op(VCPUOP_initialise, ci->ci_cpuid, &vcpuctx))) { 1064 aprint_error(": context initialisation failed. errno = %d\n", hyperror); 1065 return hyperror; 1066 } 1067 1068 /* Start it up */ 1069 1070 /* First bring it down - yay, thanks Xen documentation for omitting this slight detail - lost only about 1 week reading through crap */ 1071 if ((hyperror = HYPERVISOR_vcpu_op(VCPUOP_down, ci->ci_cpuid, NULL))) { 1072 aprint_error(": VCPUOP_down hypervisor command failed. errno = %d\n", hyperror); 1073 return hyperror; 1074 } 1075 1076 if ((hyperror = HYPERVISOR_vcpu_op(VCPUOP_up, ci->ci_cpuid, NULL))) { 1077 aprint_error(": VCPUOP_up hypervisor command failed. errno = %d\n", hyperror); 1078 return hyperror; 1079 } 1080 1081 if (!vcpu_is_up(ci)) { 1082 aprint_error(": did not come up\n"); 1083 return -1; 1084 } 1085 1086 return 0; 1087 } 1088 1089 void 1090 mp_cpu_start_cleanup(struct cpu_info *ci) 1091 { 1092 #if 0 1093 /* 1094 * Ensure the NVRAM reset byte contains something vaguely sane. 1095 */ 1096 1097 outb(IO_RTC, NVRAM_RESET); 1098 outb(IO_RTC+1, NVRAM_RESET_RST); 1099 #endif 1100 if (vcpu_is_up(ci)) { 1101 aprint_debug_dev(ci->ci_dev, "is started.\n"); 1102 } 1103 else { 1104 aprint_error_dev(ci->ci_dev, "did not start up.\n"); 1105 } 1106 1107 } 1108 1109 /* curcpu() uses %fs - shim for until cpu_init_msrs(), below */ 1110 static struct cpu_info *cpu_primary(void) 1111 { 1112 return &cpu_info_primary; 1113 } 1114 struct cpu_info * (*xpq_cpu)(void) = cpu_primary; 1115 1116 void 1117 cpu_init_msrs(struct cpu_info *ci, bool full) 1118 { 1119 #ifdef __x86_64__ 1120 if (full) { 1121 HYPERVISOR_set_segment_base (SEGBASE_FS, 0); 1122 HYPERVISOR_set_segment_base (SEGBASE_GS_KERNEL, (uint64_t) ci); 1123 HYPERVISOR_set_segment_base (SEGBASE_GS_USER, 0); 1124 xpq_cpu = x86_curcpu; 1125 } 1126 #endif /* __x86_64__ */ 1127 1128 if (cpu_feature[2] & CPUID_NOX) 1129 wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_NXE); 1130 1131 } 1132 1133 void 1134 cpu_offline_md(void) 1135 { 1136 int s; 1137 1138 s = splhigh(); 1139 #ifdef __i386__ 1140 npxsave_cpu(true); 1141 #else 1142 fpusave_cpu(true); 1143 #endif 1144 splx(s); 1145 } 1146 1147 #if 0 1148 /* XXX joerg restructure and restart CPUs individually */ 1149 static bool 1150 cpu_suspend(device_t dv, const pmf_qual_t *qual) 1151 { 1152 struct cpu_softc *sc = device_private(dv); 1153 struct cpu_info *ci = sc->sc_info; 1154 int err; 1155 1156 if (ci->ci_flags & CPUF_PRIMARY) 1157 return true; 1158 if (ci->ci_data.cpu_idlelwp == NULL) 1159 return true; 1160 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1161 return true; 1162 1163 sc->sc_wasonline = !(ci->ci_schedstate.spc_flags & SPCF_OFFLINE); 1164 1165 if (sc->sc_wasonline) { 1166 mutex_enter(&cpu_lock); 1167 err = cpu_setstate(ci, false); 1168 mutex_exit(&cpu_lock); 1169 1170 if (err) 1171 return false; 1172 } 1173 1174 return true; 1175 } 1176 1177 static bool 1178 cpu_resume(device_t dv, const pmf_qual_t *qual) 1179 { 1180 struct cpu_softc *sc = device_private(dv); 1181 struct cpu_info *ci = sc->sc_info; 1182 int err = 0; 1183 1184 if (ci->ci_flags & CPUF_PRIMARY) 1185 return true; 1186 if (ci->ci_data.cpu_idlelwp == NULL) 1187 return true; 1188 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1189 return true; 1190 1191 if (sc->sc_wasonline) { 1192 mutex_enter(&cpu_lock); 1193 err = cpu_setstate(ci, true); 1194 mutex_exit(&cpu_lock); 1195 } 1196 1197 return err == 0; 1198 } 1199 #endif 1200 1201 void 1202 cpu_get_tsc_freq(struct cpu_info *ci) 1203 { 1204 uint32_t vcpu_tversion; 1205 const volatile vcpu_time_info_t *tinfo = &ci->ci_vcpu->time; 1206 1207 vcpu_tversion = tinfo->version; 1208 while (tinfo->version == vcpu_tversion); /* Wait for a time update. XXX: timeout ? */ 1209 1210 uint64_t freq = 1000000000ULL << 32; 1211 freq = freq / (uint64_t)tinfo->tsc_to_system_mul; 1212 if ( tinfo->tsc_shift < 0 ) 1213 freq = freq << -tinfo->tsc_shift; 1214 else 1215 freq = freq >> tinfo->tsc_shift; 1216 ci->ci_data.cpu_cc_freq = freq; 1217 } 1218 1219 void 1220 x86_cpu_idle_xen(void) 1221 { 1222 struct cpu_info *ci = curcpu(); 1223 1224 KASSERT(ci->ci_ilevel == IPL_NONE); 1225 1226 x86_disable_intr(); 1227 if (!__predict_false(ci->ci_want_resched)) { 1228 idle_block(); 1229 } else { 1230 x86_enable_intr(); 1231 } 1232 } 1233 1234 /* 1235 * Loads pmap for the current CPU. 1236 */ 1237 void 1238 cpu_load_pmap(struct pmap *pmap) 1239 { 1240 #ifdef i386 1241 #ifdef PAE 1242 int i, s; 1243 struct cpu_info *ci; 1244 1245 s = splvm(); /* just to be safe */ 1246 xpq_queue_lock(); 1247 ci = curcpu(); 1248 paddr_t l3_pd = xpmap_ptom_masked(ci->ci_pae_l3_pdirpa); 1249 /* don't update the kernel L3 slot */ 1250 for (i = 0 ; i < PDP_SIZE - 1; i++) { 1251 xpq_queue_pte_update(l3_pd + i * sizeof(pd_entry_t), 1252 xpmap_ptom(pmap->pm_pdirpa[i]) | PG_V); 1253 } 1254 xpq_queue_unlock(); 1255 splx(s); 1256 tlbflush(); 1257 #else /* PAE */ 1258 lcr3(pmap_pdirpa(pmap, 0)); 1259 #endif /* PAE */ 1260 #endif /* i386 */ 1261 1262 #ifdef __x86_64__ 1263 int i, s; 1264 pd_entry_t *new_pgd; 1265 struct cpu_info *ci; 1266 paddr_t l4_pd_ma; 1267 1268 ci = curcpu(); 1269 l4_pd_ma = xpmap_ptom_masked(ci->ci_kpm_pdirpa); 1270 1271 /* 1272 * Map user space address in kernel space and load 1273 * user cr3 1274 */ 1275 s = splvm(); 1276 new_pgd = pmap->pm_pdir; 1277 1278 xpq_queue_lock(); 1279 1280 /* Copy user pmap L4 PDEs (in user addr. range) to per-cpu L4 */ 1281 for (i = 0; i < PDIR_SLOT_PTE; i++) { 1282 xpq_queue_pte_update(l4_pd_ma + i * sizeof(pd_entry_t), new_pgd[i]); 1283 } 1284 1285 if (__predict_true(pmap != pmap_kernel())) { 1286 xen_set_user_pgd(pmap_pdirpa(pmap, 0)); 1287 ci->ci_xen_current_user_pgd = pmap_pdirpa(pmap, 0); 1288 } 1289 else { 1290 xpq_queue_pt_switch(l4_pd_ma); 1291 ci->ci_xen_current_user_pgd = 0; 1292 } 1293 xpq_queue_unlock(); 1294 1295 tlbflush(); 1296 1297 splx(s); 1298 1299 #endif /* __x86_64__ */ 1300 } 1301 1302 /* 1303 * pmap_cpu_init_late: perform late per-CPU initialization. 1304 * Short note about percpu PDIR pages: 1305 * Both the PAE and __x86_64__ architectures have per-cpu PDIR 1306 * tables. This is to get around Xen's pagetable setup constraints for 1307 * PAE (multiple L3[3]s cannot point to the same L2 - Xen 1308 * will refuse to pin a table setup this way.) and for multiple cpus 1309 * to map in different user pmaps on __x86_64__ (see: cpu_load_pmap()) 1310 * 1311 * What this means for us is that the PDIR of the pmap_kernel() is 1312 * considered to be a canonical "SHADOW" PDIR with the following 1313 * properties: 1314 * - Its recursive mapping points to itself 1315 * - per-cpu recurseive mappings point to themselves 1316 * - per-cpu L4 pages' kernel entries are expected to be in sync with 1317 * the shadow 1318 * - APDP_PDE_SHADOW accesses the shadow pdir 1319 * - APDP_PDE accesses the per-cpu pdir 1320 * - alternate mappings are considered per-cpu - however, x86 pmap 1321 * currently partially consults the shadow - this works because the 1322 * shadow PDE is updated together with the per-cpu entry (see: 1323 * xen_pmap.c: pmap_map_ptes(), and the pmap is locked while the 1324 * alternate ptes are mapped in. 1325 */ 1326 1327 void 1328 pmap_cpu_init_late(struct cpu_info *ci) 1329 { 1330 #if defined(PAE) || defined(__x86_64__) 1331 /* 1332 * The BP has already its own PD page allocated during early 1333 * MD startup. 1334 */ 1335 1336 if (ci == &cpu_info_primary) 1337 return; 1338 1339 KASSERT(ci != NULL); 1340 1341 #if defined(PAE) 1342 ci->ci_pae_l3_pdir = (paddr_t *)uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 1343 UVM_KMF_WIRED | UVM_KMF_ZERO | UVM_KMF_NOWAIT); 1344 1345 if (ci->ci_pae_l3_pdir == NULL) { 1346 panic("%s: failed to allocate L3 per-cpu PD for CPU %d\n", 1347 __func__, cpu_index(ci)); 1348 } 1349 ci->ci_pae_l3_pdirpa = vtophys((vaddr_t) ci->ci_pae_l3_pdir); 1350 KASSERT(ci->ci_pae_l3_pdirpa != 0); 1351 1352 /* Initialise L2 entries 0 - 2: Point them to pmap_kernel() */ 1353 ci->ci_pae_l3_pdir[0] = 1354 xpmap_ptom_masked(pmap_kernel()->pm_pdirpa[0]) | PG_V; 1355 ci->ci_pae_l3_pdir[1] = 1356 xpmap_ptom_masked(pmap_kernel()->pm_pdirpa[1]) | PG_V; 1357 ci->ci_pae_l3_pdir[2] = 1358 xpmap_ptom_masked(pmap_kernel()->pm_pdirpa[2]) | PG_V; 1359 #endif /* PAE */ 1360 1361 ci->ci_kpm_pdir = (pd_entry_t *)uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 1362 UVM_KMF_WIRED | UVM_KMF_ZERO | UVM_KMF_NOWAIT); 1363 1364 if (ci->ci_kpm_pdir == NULL) { 1365 panic("%s: failed to allocate L4 per-cpu PD for CPU %d\n", 1366 __func__, cpu_index(ci)); 1367 } 1368 ci->ci_kpm_pdirpa = vtophys((vaddr_t) ci->ci_kpm_pdir); 1369 KASSERT(ci->ci_kpm_pdirpa != 0); 1370 1371 #if defined(__x86_64__) 1372 /* 1373 * Copy over the pmap_kernel() shadow L4 entries 1374 */ 1375 1376 memcpy(ci->ci_kpm_pdir, pmap_kernel()->pm_pdir, PAGE_SIZE); 1377 1378 /* Recursive kernel mapping */ 1379 ci->ci_kpm_pdir[PDIR_SLOT_PTE] = xpmap_ptom_masked(ci->ci_kpm_pdirpa) | PG_k | PG_V; 1380 #elif defined(PAE) 1381 /* Copy over the pmap_kernel() shadow L2 entries that map the kernel */ 1382 memcpy(ci->ci_kpm_pdir, pmap_kernel()->pm_pdir + PDIR_SLOT_KERN, nkptp[PTP_LEVELS - 1] * sizeof(pd_entry_t)); 1383 #endif /* __x86_64__ else PAE */ 1384 1385 /* Xen wants R/O */ 1386 pmap_kenter_pa((vaddr_t)ci->ci_kpm_pdir, ci->ci_kpm_pdirpa, 1387 VM_PROT_READ, 0); 1388 1389 #if defined(PAE) 1390 /* Initialise L3 entry 3. This mapping is shared across all 1391 * pmaps and is static, ie; loading a new pmap will not update 1392 * this entry. 1393 */ 1394 1395 ci->ci_pae_l3_pdir[3] = xpmap_ptom_masked(ci->ci_kpm_pdirpa) | PG_k | PG_V; 1396 1397 /* Mark L3 R/O (Xen wants this) */ 1398 pmap_kenter_pa((vaddr_t)ci->ci_pae_l3_pdir, ci->ci_pae_l3_pdirpa, 1399 VM_PROT_READ, 0); 1400 1401 xpq_queue_lock(); 1402 xpq_queue_pin_l3_table(xpmap_ptom_masked(ci->ci_pae_l3_pdirpa)); 1403 xpq_queue_unlock(); 1404 1405 #elif defined(__x86_64__) 1406 xpq_queue_lock(); 1407 xpq_queue_pin_l4_table(xpmap_ptom_masked(ci->ci_kpm_pdirpa)); 1408 xpq_queue_unlock(); 1409 #endif /* PAE */ 1410 #endif /* defined(PAE) || defined(__x86_64__) */ 1411 } 1412 1413 1414 1415 /* 1416 * Notify all other cpus to halt. 1417 */ 1418 1419 void 1420 cpu_broadcast_halt(void) 1421 { 1422 xen_broadcast_ipi(XEN_IPI_HALT); 1423 } 1424 1425 /* 1426 * Send a dummy ipi to a cpu. 1427 */ 1428 1429 void 1430 cpu_kick(struct cpu_info *ci) 1431 { 1432 (void)xen_send_ipi(ci, XEN_IPI_KICK); 1433 } 1434
Indexes created Fri Oct 03 02:09:57 GMT 2025