cpu.c revision 1.64
1 /* $NetBSD: cpu.c,v 1.64 2011/08/16 02:59:16 dholland Exp $ */ 2 /* NetBSD: cpu.c,v 1.18 2004/02/20 17:35:01 yamt Exp */ 3 4 /*- 5 * Copyright (c) 2000 The NetBSD Foundation, Inc. 6 * Copyright (c) 2002, 2006, 2007 YAMAMOTO Takashi, 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to The NetBSD Foundation 10 * by RedBack Networks Inc. 11 * 12 * Author: Bill Sommerfeld 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * Copyright (c) 1999 Stefan Grefen 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 56 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.64 2011/08/16 02:59:16 dholland Exp $"); 70 71 #include "opt_ddb.h" 72 #include "opt_multiprocessor.h" 73 #include "opt_mpbios.h" /* for MPDEBUG */ 74 #include "opt_mtrr.h" 75 #include "opt_xen.h" 76 77 #include "lapic.h" 78 #include "ioapic.h" 79 80 #include <sys/param.h> 81 #include <sys/proc.h> 82 #include <sys/systm.h> 83 #include <sys/device.h> 84 #include <sys/kmem.h> 85 #include <sys/cpu.h> 86 #include <sys/atomic.h> 87 #include <sys/reboot.h> 88 #include <sys/idle.h> 89 90 #include <uvm/uvm.h> 91 92 #include <machine/cpufunc.h> 93 #include <machine/cpuvar.h> 94 #include <machine/pmap.h> 95 #include <machine/vmparam.h> 96 #include <machine/mpbiosvar.h> 97 #include <machine/pcb.h> 98 #include <machine/specialreg.h> 99 #include <machine/segments.h> 100 #include <machine/gdt.h> 101 #include <machine/mtrr.h> 102 #include <machine/pio.h> 103 104 #ifdef i386 105 #include <machine/npx.h> 106 #else 107 #include <machine/fpu.h> 108 #endif 109 110 #include <xen/xen.h> 111 #include <xen/xen3-public/vcpu.h> 112 #include <xen/vcpuvar.h> 113 114 #if NLAPIC > 0 115 #include <machine/apicvar.h> 116 #include <machine/i82489reg.h> 117 #include <machine/i82489var.h> 118 #endif 119 120 #include <dev/ic/mc146818reg.h> 121 #include <dev/isa/isareg.h> 122 123 #if MAXCPUS > 32 124 #error cpu_info contains 32bit bitmasks 125 #endif 126 127 static int cpu_match(device_t, cfdata_t, void *); 128 static void cpu_attach(device_t, device_t, void *); 129 static void cpu_defer(device_t); 130 static int cpu_rescan(device_t, const char *, const int *); 131 static void cpu_childdetached(device_t, device_t); 132 static int vcpu_match(device_t, cfdata_t, void *); 133 static void vcpu_attach(device_t, device_t, void *); 134 static void cpu_attach_common(device_t, device_t, void *); 135 void cpu_offline_md(void); 136 137 struct cpu_softc { 138 device_t sc_dev; /* device tree glue */ 139 struct cpu_info *sc_info; /* pointer to CPU info */ 140 bool sc_wasonline; 141 }; 142 143 int mp_cpu_start(struct cpu_info *, vaddr_t); 144 void mp_cpu_start_cleanup(struct cpu_info *); 145 const struct cpu_functions mp_cpu_funcs = { mp_cpu_start, NULL, 146 mp_cpu_start_cleanup }; 147 148 CFATTACH_DECL2_NEW(cpu, sizeof(struct cpu_softc), 149 cpu_match, cpu_attach, NULL, NULL, cpu_rescan, cpu_childdetached); 150 151 CFATTACH_DECL_NEW(vcpu, sizeof(struct cpu_softc), 152 vcpu_match, vcpu_attach, NULL, NULL); 153 154 /* 155 * Statically-allocated CPU info for the primary CPU (or the only 156 * CPU, on uniprocessors). The CPU info list is initialized to 157 * point at it. 158 */ 159 #ifdef TRAPLOG 160 #include <machine/tlog.h> 161 struct tlog tlog_primary; 162 #endif 163 struct cpu_info cpu_info_primary __aligned(CACHE_LINE_SIZE) = { 164 .ci_dev = 0, 165 .ci_self = &cpu_info_primary, 166 .ci_idepth = -1, 167 .ci_curlwp = &lwp0, 168 .ci_curldt = -1, 169 .ci_cpumask = 1, 170 #ifdef TRAPLOG 171 .ci_tlog = &tlog_primary, 172 #endif 173 174 }; 175 struct cpu_info phycpu_info_primary __aligned(CACHE_LINE_SIZE) = { 176 .ci_dev = 0, 177 .ci_self = &phycpu_info_primary, 178 }; 179 180 struct cpu_info *cpu_info_list = &cpu_info_primary; 181 struct cpu_info *phycpu_info_list = &phycpu_info_primary; 182 183 uint32_t cpus_attached = 1; 184 uint32_t cpus_running = 1; 185 186 uint32_t phycpus_attached = 0; 187 uint32_t phycpus_running = 0; 188 189 uint32_t cpu_feature[5]; /* X86 CPUID feature bits 190 * [0] basic features %edx 191 * [1] basic features %ecx 192 * [2] extended features %edx 193 * [3] extended features %ecx 194 * [4] VIA padlock features 195 */ 196 197 bool x86_mp_online; 198 paddr_t mp_trampoline_paddr = MP_TRAMPOLINE; 199 200 #if defined(MULTIPROCESSOR) 201 void cpu_hatch(void *); 202 static void cpu_boot_secondary(struct cpu_info *ci); 203 static void cpu_start_secondary(struct cpu_info *ci); 204 #endif /* MULTIPROCESSOR */ 205 206 static int 207 cpu_match(device_t parent, cfdata_t match, void *aux) 208 { 209 210 return 1; 211 } 212 213 static void 214 cpu_attach(device_t parent, device_t self, void *aux) 215 { 216 struct cpu_softc *sc = device_private(self); 217 struct cpu_attach_args *caa = aux; 218 struct cpu_info *ci; 219 uintptr_t ptr; 220 static int nphycpu = 0; 221 222 sc->sc_dev = self; 223 224 if (phycpus_attached == ~0) { 225 aprint_error(": increase MAXCPUS\n"); 226 return; 227 } 228 229 /* 230 * If we're an Application Processor, allocate a cpu_info 231 * If we're the first attached CPU use the primary cpu_info, 232 * otherwise allocate a new one 233 */ 234 aprint_naive("\n"); 235 aprint_normal("\n"); 236 if (nphycpu > 0) { 237 struct cpu_info *tmp; 238 ptr = (uintptr_t)kmem_zalloc(sizeof(*ci) + CACHE_LINE_SIZE - 1, 239 KM_SLEEP); 240 ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE); 241 ci->ci_curldt = -1; 242 243 tmp = phycpu_info_list; 244 while (tmp->ci_next) 245 tmp = tmp->ci_next; 246 247 tmp->ci_next = ci; 248 } else { 249 ci = &phycpu_info_primary; 250 } 251 252 ci->ci_self = ci; 253 sc->sc_info = ci; 254 255 ci->ci_dev = self; 256 ci->ci_acpiid = caa->cpu_id; 257 ci->ci_cpuid = caa->cpu_number; 258 ci->ci_vcpu = NULL; 259 ci->ci_index = nphycpu++; 260 ci->ci_cpumask = (1 << cpu_index(ci)); 261 262 atomic_or_32(&phycpus_attached, ci->ci_cpumask); 263 264 if (!pmf_device_register(self, NULL, NULL)) 265 aprint_error_dev(self, "couldn't establish power handler\n"); 266 267 (void)config_defer(self, cpu_defer); 268 } 269 270 static void 271 cpu_defer(device_t self) 272 { 273 cpu_rescan(self, NULL, NULL); 274 } 275 276 static int 277 cpu_rescan(device_t self, const char *ifattr, const int *locators) 278 { 279 struct cpu_softc *sc = device_private(self); 280 struct cpufeature_attach_args cfaa; 281 struct cpu_info *ci = sc->sc_info; 282 283 memset(&cfaa, 0, sizeof(cfaa)); 284 cfaa.ci = ci; 285 286 if (ifattr_match(ifattr, "cpufeaturebus")) { 287 288 if (ci->ci_frequency == NULL) { 289 cfaa.name = "frequency"; 290 ci->ci_frequency = config_found_ia(self, 291 "cpufeaturebus", &cfaa, NULL); 292 } 293 } 294 295 return 0; 296 } 297 298 static void 299 cpu_childdetached(device_t self, device_t child) 300 { 301 struct cpu_softc *sc = device_private(self); 302 struct cpu_info *ci = sc->sc_info; 303 304 if (ci->ci_frequency == child) 305 ci->ci_frequency = NULL; 306 } 307 308 static int 309 vcpu_match(device_t parent, cfdata_t match, void *aux) 310 { 311 struct vcpu_attach_args *vcaa = aux; 312 struct vcpu_runstate_info vcr; 313 int error; 314 315 if (strcmp(vcaa->vcaa_name, match->cf_name) == 0) { 316 error = HYPERVISOR_vcpu_op(VCPUOP_get_runstate_info, 317 vcaa->vcaa_caa.cpu_number, 318 &vcr); 319 switch (error) { 320 case 0: 321 return 1; 322 case -ENOENT: 323 return 0; 324 default: 325 panic("Unknown hypervisor error %d returned on vcpu runstate probe\n", error); 326 } 327 } 328 329 return 0; 330 } 331 332 static void 333 vcpu_attach(device_t parent, device_t self, void *aux) 334 { 335 struct vcpu_attach_args *vcaa = aux; 336 337 KASSERT(vcaa->vcaa_caa.cpu_func == NULL); 338 vcaa->vcaa_caa.cpu_func = &mp_cpu_funcs; 339 cpu_attach_common(parent, self, &vcaa->vcaa_caa); 340 } 341 342 static int 343 vcpu_is_up(struct cpu_info *ci) 344 { 345 KASSERT(ci != NULL); 346 return HYPERVISOR_vcpu_op(VCPUOP_is_up, ci->ci_cpuid, NULL); 347 } 348 349 static void 350 cpu_vm_init(struct cpu_info *ci) 351 { 352 int ncolors = 2, i; 353 354 for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) { 355 struct x86_cache_info *cai; 356 int tcolors; 357 358 cai = &ci->ci_cinfo[i]; 359 360 tcolors = atop(cai->cai_totalsize); 361 switch(cai->cai_associativity) { 362 case 0xff: 363 tcolors = 1; /* fully associative */ 364 break; 365 case 0: 366 case 1: 367 break; 368 default: 369 tcolors /= cai->cai_associativity; 370 } 371 ncolors = max(ncolors, tcolors); 372 } 373 374 /* 375 * Knowing the size of the largest cache on this CPU, re-color 376 * our pages. 377 */ 378 if (ncolors <= uvmexp.ncolors) 379 return; 380 aprint_debug_dev(ci->ci_dev, "%d page colors\n", ncolors); 381 uvm_page_recolor(ncolors); 382 } 383 384 static void 385 cpu_attach_common(device_t parent, device_t self, void *aux) 386 { 387 struct cpu_softc *sc = device_private(self); 388 struct cpu_attach_args *caa = aux; 389 struct cpu_info *ci; 390 uintptr_t ptr; 391 int cpunum = caa->cpu_number; 392 static bool again = false; 393 394 sc->sc_dev = self; 395 396 /* 397 * If we're an Application Processor, allocate a cpu_info 398 * structure, otherwise use the primary's. 399 */ 400 if (caa->cpu_role == CPU_ROLE_AP) { 401 aprint_naive(": Application Processor\n"); 402 ptr = (uintptr_t)kmem_alloc(sizeof(*ci) + CACHE_LINE_SIZE - 1, 403 KM_SLEEP); 404 ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE); 405 memset(ci, 0, sizeof(*ci)); 406 #ifdef TRAPLOG 407 ci->ci_tlog_base = kmem_zalloc(sizeof(struct tlog), KM_SLEEP); 408 #endif 409 } else { 410 aprint_naive(": %s Processor\n", 411 caa->cpu_role == CPU_ROLE_SP ? "Single" : "Boot"); 412 ci = &cpu_info_primary; 413 } 414 415 ci->ci_self = ci; 416 sc->sc_info = ci; 417 ci->ci_dev = self; 418 ci->ci_cpuid = cpunum; 419 420 KASSERT(HYPERVISOR_shared_info != NULL); 421 ci->ci_vcpu = &HYPERVISOR_shared_info->vcpu_info[cpunum]; 422 423 KASSERT(ci->ci_func == 0); 424 ci->ci_func = caa->cpu_func; 425 426 /* Must be called before mi_cpu_attach(). */ 427 cpu_vm_init(ci); 428 429 if (caa->cpu_role == CPU_ROLE_AP) { 430 int error; 431 432 error = mi_cpu_attach(ci); 433 434 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 435 if (error != 0) { 436 aprint_normal("\n"); 437 aprint_error_dev(self, 438 "mi_cpu_attach failed with %d\n", error); 439 return; 440 } 441 442 } else { 443 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 444 } 445 446 ci->ci_cpumask = (1 << cpu_index(ci)); 447 pmap_reference(pmap_kernel()); 448 ci->ci_pmap = pmap_kernel(); 449 ci->ci_tlbstate = TLBSTATE_STALE; 450 451 /* 452 * Boot processor may not be attached first, but the below 453 * must be done to allow booting other processors. 454 */ 455 if (!again) { 456 atomic_or_32(&ci->ci_flags, CPUF_PRESENT | CPUF_PRIMARY); 457 /* Basic init. */ 458 cpu_intr_init(ci); 459 cpu_get_tsc_freq(ci); 460 cpu_init(ci); 461 pmap_cpu_init_late(ci); /* XXX: cosmetic */ 462 463 /* Every processor needs to init it's own ipi h/w (similar to lapic) */ 464 xen_ipi_init(); 465 /* XXX: clock_init() */ 466 467 /* Make sure DELAY() is initialized. */ 468 DELAY(1); 469 again = true; 470 } 471 472 /* further PCB init done later. */ 473 474 switch (caa->cpu_role) { 475 case CPU_ROLE_SP: 476 atomic_or_32(&ci->ci_flags, CPUF_SP); 477 cpu_identify(ci); 478 #if 0 479 x86_errata(); 480 #endif 481 x86_cpu_idle_init(); 482 483 break; 484 485 case CPU_ROLE_BP: 486 atomic_or_32(&ci->ci_flags, CPUF_BSP); 487 cpu_identify(ci); 488 cpu_init(ci); 489 #if 0 490 x86_errata(); 491 #endif 492 x86_cpu_idle_init(); 493 494 break; 495 496 case CPU_ROLE_AP: 497 atomic_or_32(&ci->ci_flags, CPUF_AP); 498 499 /* 500 * report on an AP 501 */ 502 503 #if defined(MULTIPROCESSOR) 504 /* interrupt handler stack */ 505 cpu_intr_init(ci); 506 507 /* Setup per-cpu memory for gdt */ 508 gdt_alloc_cpu(ci); 509 510 pmap_cpu_init_late(ci); 511 cpu_start_secondary(ci); 512 513 if (ci->ci_flags & CPUF_PRESENT) { 514 struct cpu_info *tmp; 515 516 cpu_identify(ci); 517 tmp = cpu_info_list; 518 while (tmp->ci_next) 519 tmp = tmp->ci_next; 520 521 tmp->ci_next = ci; 522 } 523 #else 524 aprint_error(": not started\n"); 525 #endif 526 break; 527 528 default: 529 aprint_normal("\n"); 530 panic("unknown processor type??\n"); 531 } 532 533 pat_init(ci); 534 atomic_or_32(&cpus_attached, ci->ci_cpumask); 535 536 #if 0 537 if (!pmf_device_register(self, cpu_suspend, cpu_resume)) 538 aprint_error_dev(self, "couldn't establish power handler\n"); 539 #endif 540 541 #ifdef MPVERBOSE 542 if (mp_verbose) { 543 struct lwp *l = ci->ci_data.cpu_idlelwp; 544 struct pcb *pcb = lwp_getpcb(l); 545 546 aprint_verbose_dev(self, 547 "idle lwp at %p, idle sp at 0x%p\n", 548 l, 549 #ifdef i386 550 (void *)pcb->pcb_esp 551 #else /* i386 */ 552 (void *)pcb->pcb_rsp 553 #endif /* i386 */ 554 ); 555 556 } 557 #endif /* MPVERBOSE */ 558 } 559 560 /* 561 * Initialize the processor appropriately. 562 */ 563 564 void 565 cpu_init(struct cpu_info *ci) 566 { 567 568 /* 569 * On a P6 or above, enable global TLB caching if the 570 * hardware supports it. 571 */ 572 if (cpu_feature[0] & CPUID_PGE) 573 lcr4(rcr4() | CR4_PGE); /* enable global TLB caching */ 574 575 #ifdef XXXMTRR 576 /* 577 * On a P6 or above, initialize MTRR's if the hardware supports them. 578 */ 579 if (cpu_feature[0] & CPUID_MTRR) { 580 if ((ci->ci_flags & CPUF_AP) == 0) 581 i686_mtrr_init_first(); 582 mtrr_init_cpu(ci); 583 } 584 #endif 585 /* 586 * If we have FXSAVE/FXRESTOR, use them. 587 */ 588 if (cpu_feature[0] & CPUID_FXSR) { 589 lcr4(rcr4() | CR4_OSFXSR); 590 591 /* 592 * If we have SSE/SSE2, enable XMM exceptions. 593 */ 594 if (cpu_feature[0] & (CPUID_SSE|CPUID_SSE2)) 595 lcr4(rcr4() | CR4_OSXMMEXCPT); 596 } 597 598 #ifdef __x86_64__ 599 /* No user PGD mapped for this CPU yet */ 600 ci->ci_xen_current_user_pgd = 0; 601 #endif 602 603 atomic_or_32(&cpus_running, ci->ci_cpumask); 604 atomic_or_32(&ci->ci_flags, CPUF_RUNNING); 605 606 /* XXX: register vcpu_register_runstate_memory_area, and figure out how to make sure this VCPU is running ? */ 607 } 608 609 610 #ifdef MULTIPROCESSOR 611 612 void 613 cpu_boot_secondary_processors(void) 614 { 615 struct cpu_info *ci; 616 u_long i; 617 for (i = 0; i < maxcpus; i++) { 618 ci = cpu_lookup(i); 619 if (ci == NULL) 620 continue; 621 if (ci->ci_data.cpu_idlelwp == NULL) 622 continue; 623 if ((ci->ci_flags & CPUF_PRESENT) == 0) 624 continue; 625 if (ci->ci_flags & (CPUF_BSP|CPUF_SP|CPUF_PRIMARY)) 626 continue; 627 cpu_boot_secondary(ci); 628 } 629 630 x86_mp_online = true; 631 } 632 633 static void 634 cpu_init_idle_lwp(struct cpu_info *ci) 635 { 636 struct lwp *l = ci->ci_data.cpu_idlelwp; 637 struct pcb *pcb = lwp_getpcb(l); 638 639 pcb->pcb_cr0 = rcr0(); 640 } 641 642 void 643 cpu_init_idle_lwps(void) 644 { 645 struct cpu_info *ci; 646 u_long i; 647 648 for (i = 0; i < maxcpus; i++) { 649 ci = cpu_lookup(i); 650 if (ci == NULL) 651 continue; 652 if (ci->ci_data.cpu_idlelwp == NULL) 653 continue; 654 if ((ci->ci_flags & CPUF_PRESENT) == 0) 655 continue; 656 cpu_init_idle_lwp(ci); 657 } 658 } 659 660 static void 661 cpu_start_secondary(struct cpu_info *ci) 662 { 663 int i; 664 665 aprint_debug_dev(ci->ci_dev, "starting\n"); 666 667 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 668 669 if (CPU_STARTUP(ci, (vaddr_t) cpu_hatch) != 0) { 670 return; 671 } 672 673 /* 674 * wait for it to become ready 675 */ 676 for (i = 100000; (!(ci->ci_flags & CPUF_PRESENT)) && i > 0; i--) { 677 delay(10); 678 } 679 if ((ci->ci_flags & CPUF_PRESENT) == 0) { 680 aprint_error_dev(ci->ci_dev, "failed to become ready\n"); 681 #if defined(MPDEBUG) && defined(DDB) 682 printf("dropping into debugger; continue from here to resume boot\n"); 683 Debugger(); 684 #endif 685 } 686 687 CPU_START_CLEANUP(ci); 688 } 689 690 void 691 cpu_boot_secondary(struct cpu_info *ci) 692 { 693 int i; 694 atomic_or_32(&ci->ci_flags, CPUF_GO); 695 for (i = 100000; (!(ci->ci_flags & CPUF_RUNNING)) && i > 0; i--) { 696 delay(10); 697 } 698 if ((ci->ci_flags & CPUF_RUNNING) == 0) { 699 aprint_error_dev(ci->ci_dev, "CPU failed to start\n"); 700 #if defined(MPDEBUG) && defined(DDB) 701 printf("dropping into debugger; continue from here to resume boot\n"); 702 Debugger(); 703 #endif 704 } 705 } 706 707 /* 708 * APs end up here immediately after initialisation and VCPUOP_up in 709 * mp_cpu_start(). 710 * At this point, we are running in the idle pcb/idle stack of the new 711 * CPU. This function jumps to the idle loop and starts looking for 712 * work. 713 */ 714 extern void x86_64_tls_switch(struct lwp *); 715 void 716 cpu_hatch(void *v) 717 { 718 struct cpu_info *ci = (struct cpu_info *)v; 719 struct pcb *pcb; 720 int s, i; 721 722 /* Setup TLS and kernel GS/FS */ 723 cpu_init_msrs(ci, true); 724 cpu_init_idt(); 725 gdt_init_cpu(ci); 726 727 cpu_probe(ci); 728 729 atomic_or_32(&ci->ci_flags, CPUF_PRESENT); 730 731 while ((ci->ci_flags & CPUF_GO) == 0) { 732 /* Don't use delay, boot CPU may be patching the text. */ 733 for (i = 10000; i != 0; i--) 734 x86_pause(); 735 } 736 737 /* Because the text may have been patched in x86_patch(). */ 738 x86_flush(); 739 tlbflushg(); 740 741 KASSERT((ci->ci_flags & CPUF_RUNNING) == 0); 742 743 pcb = lwp_getpcb(curlwp); 744 pcb->pcb_cr3 = pmap_pdirpa(pmap_kernel(), 0); /* XXX: consider using pmap_load() ? */ 745 pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp); 746 747 xen_ipi_init(); 748 749 xen_initclocks(); 750 751 /* XXX: lapic_initclocks(); */ 752 753 #ifdef __x86_64__ 754 fpuinit(ci); 755 #endif 756 757 lldt(GSEL(GLDT_SEL, SEL_KPL)); 758 759 cpu_init(ci); 760 cpu_get_tsc_freq(ci); 761 762 s = splhigh(); 763 x86_enable_intr(); 764 splx(s); 765 #if 0 766 x86_errata(); 767 #endif 768 769 aprint_debug_dev(ci->ci_dev, "running\n"); 770 771 cpu_switchto(NULL, ci->ci_data.cpu_idlelwp, true); 772 773 panic("switch to idle_loop context returned!\n"); 774 /* NOTREACHED */ 775 } 776 777 #if defined(DDB) 778 779 #include <ddb/db_output.h> 780 #include <machine/db_machdep.h> 781 782 /* 783 * Dump CPU information from ddb. 784 */ 785 void 786 cpu_debug_dump(void) 787 { 788 struct cpu_info *ci; 789 CPU_INFO_ITERATOR cii; 790 791 db_printf("addr dev id flags ipis curlwp fpcurlwp\n"); 792 for (CPU_INFO_FOREACH(cii, ci)) { 793 db_printf("%p %s %ld %x %x %10p %10p\n", 794 ci, 795 ci->ci_dev == NULL ? "BOOT" : device_xname(ci->ci_dev), 796 (long)ci->ci_cpuid, 797 ci->ci_flags, ci->ci_ipis, 798 ci->ci_curlwp, 799 ci->ci_fpcurlwp); 800 } 801 } 802 #endif /* DDB */ 803 804 #endif /* MULTIPROCESSOR */ 805 806 extern void hypervisor_callback(void); 807 extern void failsafe_callback(void); 808 #ifdef __x86_64__ 809 typedef void (vector)(void); 810 extern vector Xsyscall, Xsyscall32; 811 #endif 812 813 /* 814 * Setup the "trampoline". On Xen, we setup nearly all cpu context 815 * outside a trampoline, so we prototype and call targetip like so: 816 * void targetip(struct cpu_info *); 817 */ 818 819 static void 820 gdt_prepframes(paddr_t *frames, vaddr_t base, uint32_t entries) 821 { 822 int i; 823 for (i = 0; i < roundup(entries, PAGE_SIZE) >> PAGE_SHIFT; i++) { 824 825 frames[i] = ((paddr_t) xpmap_ptetomach( 826 (pt_entry_t *) (base + (i << PAGE_SHIFT)))) 827 >> PAGE_SHIFT; 828 829 /* Mark Read-only */ 830 pmap_pte_clearbits(kvtopte(base + (i << PAGE_SHIFT)), 831 PG_RW); 832 } 833 } 834 835 #ifdef __x86_64__ 836 extern char *ldtstore; /* XXX: Xen MP todo */ 837 838 static void 839 xen_init_amd64_vcpuctxt(struct cpu_info *ci, 840 struct vcpu_guest_context *initctx, 841 void targetrip(struct cpu_info *)) 842 { 843 /* page frames to point at GDT */ 844 extern int gdt_size; 845 paddr_t frames[16]; 846 psize_t gdt_ents; 847 848 struct lwp *l; 849 struct pcb *pcb; 850 851 volatile struct vcpu_info *vci; 852 853 KASSERT(ci != NULL); 854 KASSERT(ci != &cpu_info_primary); 855 KASSERT(initctx != NULL); 856 KASSERT(targetrip != NULL); 857 858 memset(initctx, 0, sizeof *initctx); 859 860 gdt_ents = roundup(gdt_size, PAGE_SIZE) >> PAGE_SHIFT; /* XXX: re-investigate roundup(gdt_size... ) for gdt_ents. */ 861 KASSERT(gdt_ents <= 16); 862 863 gdt_prepframes(frames, (vaddr_t) ci->ci_gdt, gdt_ents); 864 865 /* XXX: The stuff in here is amd64 specific. move to mptramp.[Sc] ? */ 866 867 /* Initialise the vcpu context: We use idle_loop()'s pcb context. */ 868 869 l = ci->ci_data.cpu_idlelwp; 870 871 KASSERT(l != NULL); 872 pcb = lwp_getpcb(l); 873 KASSERT(pcb != NULL); 874 875 /* resume with interrupts off */ 876 vci = ci->ci_vcpu; 877 vci->evtchn_upcall_mask = 1; 878 xen_mb(); 879 880 /* resume in kernel-mode */ 881 initctx->flags = VGCF_in_kernel | VGCF_online; 882 883 /* Stack and entry points: 884 * We arrange for the stack frame for cpu_hatch() to 885 * appear as a callee frame of lwp_trampoline(). Being a 886 * leaf frame prevents trampling on any of the MD stack setup 887 * that x86/vm_machdep.c:cpu_lwp_fork() does for idle_loop() 888 */ 889 890 initctx->user_regs.rdi = (uint64_t) ci; /* targetrip(ci); */ 891 initctx->user_regs.rip = (vaddr_t) targetrip; 892 893 initctx->user_regs.cs = GSEL(GCODE_SEL, SEL_KPL); 894 895 initctx->user_regs.rflags = pcb->pcb_flags; 896 initctx->user_regs.rsp = pcb->pcb_rsp; 897 898 /* Data segments */ 899 initctx->user_regs.ss = GSEL(GDATA_SEL, SEL_KPL); 900 initctx->user_regs.es = GSEL(GDATA_SEL, SEL_KPL); 901 initctx->user_regs.ds = GSEL(GDATA_SEL, SEL_KPL); 902 903 /* GDT */ 904 memcpy(initctx->gdt_frames, frames, sizeof frames); 905 initctx->gdt_ents = gdt_ents; 906 907 /* LDT */ 908 initctx->ldt_base = (unsigned long) ldtstore; 909 initctx->ldt_ents = LDT_SIZE >> 3; 910 911 /* Kernel context state */ 912 initctx->kernel_ss = GSEL(GDATA_SEL, SEL_KPL); 913 initctx->kernel_sp = pcb->pcb_rsp0; 914 initctx->ctrlreg[0] = pcb->pcb_cr0; 915 initctx->ctrlreg[1] = 0; /* "resuming" from kernel - no User cr3. */ 916 initctx->ctrlreg[2] = pcb->pcb_cr2; /* XXX: */ 917 /* 918 * Use pmap_kernel() L4 PD directly, until we setup the 919 * per-cpu L4 PD in pmap_cpu_init_late() 920 */ 921 initctx->ctrlreg[3] = xpmap_ptom(pcb->pcb_cr3); 922 initctx->ctrlreg[4] = CR4_PAE | CR4_OSFXSR | CR4_OSXMMEXCPT; 923 924 925 /* Xen callbacks */ 926 initctx->event_callback_eip = (unsigned long) hypervisor_callback; 927 initctx->failsafe_callback_eip = (unsigned long) failsafe_callback; 928 initctx->syscall_callback_eip = (unsigned long) Xsyscall; 929 930 return; 931 } 932 #else /* i386 */ 933 extern union descriptor *ldt; 934 extern void Xsyscall(void); 935 936 static void 937 xen_init_i386_vcpuctxt(struct cpu_info *ci, 938 struct vcpu_guest_context *initctx, 939 void targeteip(struct cpu_info *)) 940 { 941 /* page frames to point at GDT */ 942 extern int gdt_size; 943 paddr_t frames[16]; 944 psize_t gdt_ents; 945 946 struct lwp *l; 947 struct pcb *pcb; 948 949 volatile struct vcpu_info *vci; 950 951 KASSERT(ci != NULL); 952 KASSERT(ci != &cpu_info_primary); 953 KASSERT(initctx != NULL); 954 KASSERT(targeteip != NULL); 955 956 memset(initctx, 0, sizeof *initctx); 957 958 gdt_ents = roundup(gdt_size, PAGE_SIZE) >> PAGE_SHIFT; /* XXX: re-investigate roundup(gdt_size... ) for gdt_ents. */ 959 KASSERT(gdt_ents <= 16); 960 961 gdt_prepframes(frames, (vaddr_t) ci->ci_gdt, gdt_ents); 962 963 /* 964 * Initialise the vcpu context: 965 * We use this cpu's idle_loop() pcb context. 966 */ 967 968 l = ci->ci_data.cpu_idlelwp; 969 970 KASSERT(l != NULL); 971 pcb = lwp_getpcb(l); 972 KASSERT(pcb != NULL); 973 974 /* resume with interrupts off */ 975 vci = ci->ci_vcpu; 976 vci->evtchn_upcall_mask = 1; 977 xen_mb(); 978 979 /* resume in kernel-mode */ 980 initctx->flags = VGCF_in_kernel | VGCF_online; 981 982 /* Stack frame setup for cpu_hatch(): 983 * We arrange for the stack frame for cpu_hatch() to 984 * appear as a callee frame of lwp_trampoline(). Being a 985 * leaf frame prevents trampling on any of the MD stack setup 986 * that x86/vm_machdep.c:cpu_lwp_fork() does for idle_loop() 987 */ 988 989 initctx->user_regs.esp = pcb->pcb_esp - 4; /* Leave word for 990 arg1 */ 991 { /* targeteip(ci); */ 992 uint32_t *arg = (uint32_t *) initctx->user_regs.esp; 993 arg[1] = (uint32_t) ci; /* arg1 */ 994 995 } 996 997 initctx->user_regs.eip = (vaddr_t) targeteip; 998 initctx->user_regs.cs = GSEL(GCODE_SEL, SEL_KPL); 999 initctx->user_regs.eflags |= pcb->pcb_iopl; 1000 1001 /* Data segments */ 1002 initctx->user_regs.ss = GSEL(GDATA_SEL, SEL_KPL); 1003 initctx->user_regs.es = GSEL(GDATA_SEL, SEL_KPL); 1004 initctx->user_regs.ds = GSEL(GDATA_SEL, SEL_KPL); 1005 initctx->user_regs.fs = GSEL(GDATA_SEL, SEL_KPL); 1006 1007 /* GDT */ 1008 memcpy(initctx->gdt_frames, frames, sizeof frames); 1009 initctx->gdt_ents = gdt_ents; 1010 1011 /* LDT */ 1012 initctx->ldt_base = (unsigned long) ldt; 1013 initctx->ldt_ents = NLDT; 1014 1015 /* Kernel context state */ 1016 initctx->kernel_ss = GSEL(GDATA_SEL, SEL_KPL); 1017 initctx->kernel_sp = pcb->pcb_esp0; 1018 initctx->ctrlreg[0] = pcb->pcb_cr0; 1019 initctx->ctrlreg[1] = 0; /* "resuming" from kernel - no User cr3. */ 1020 initctx->ctrlreg[2] = pcb->pcb_cr2; /* XXX: */ 1021 /* 1022 * Use pmap_kernel() L4 PD directly, until we setup the 1023 * per-cpu L4 PD in pmap_cpu_init_late() 1024 */ 1025 initctx->ctrlreg[3] = xpmap_ptom(pcb->pcb_cr3); 1026 initctx->ctrlreg[4] = /* CR4_PAE | */CR4_OSFXSR | CR4_OSXMMEXCPT; 1027 1028 1029 /* Xen callbacks */ 1030 initctx->event_callback_eip = (unsigned long) hypervisor_callback; 1031 initctx->event_callback_cs = GSEL(GCODE_SEL, SEL_KPL); 1032 initctx->failsafe_callback_eip = (unsigned long) failsafe_callback; 1033 initctx->failsafe_callback_cs = GSEL(GCODE_SEL, SEL_KPL); 1034 1035 return; 1036 } 1037 #endif /* __x86_64__ */ 1038 1039 int 1040 mp_cpu_start(struct cpu_info *ci, vaddr_t target) 1041 { 1042 1043 int hyperror; 1044 struct vcpu_guest_context vcpuctx; 1045 1046 KASSERT(ci != NULL); 1047 KASSERT(ci != &cpu_info_primary); 1048 KASSERT(ci->ci_flags & CPUF_AP); 1049 1050 #ifdef __x86_64__ 1051 xen_init_amd64_vcpuctxt(ci, &vcpuctx, (void (*)(struct cpu_info *))target); 1052 #else /* i386 */ 1053 xen_init_i386_vcpuctxt(ci, &vcpuctx, (void (*)(struct cpu_info *))target); 1054 #endif /* __x86_64__ */ 1055 1056 /* Initialise the given vcpu to execute cpu_hatch(ci); */ 1057 if ((hyperror = HYPERVISOR_vcpu_op(VCPUOP_initialise, ci->ci_cpuid, &vcpuctx))) { 1058 aprint_error(": context initialisation failed. errno = %d\n", hyperror); 1059 return hyperror; 1060 } 1061 1062 /* Start it up */ 1063 1064 /* First bring it down - the Xen documentation conveniently omits this slight detail. */ 1065 if ((hyperror = HYPERVISOR_vcpu_op(VCPUOP_down, ci->ci_cpuid, NULL))) { 1066 aprint_error(": VCPUOP_down hypervisor command failed. errno = %d\n", hyperror); 1067 return hyperror; 1068 } 1069 1070 if ((hyperror = HYPERVISOR_vcpu_op(VCPUOP_up, ci->ci_cpuid, NULL))) { 1071 aprint_error(": VCPUOP_up hypervisor command failed. errno = %d\n", hyperror); 1072 return hyperror; 1073 } 1074 1075 if (!vcpu_is_up(ci)) { 1076 aprint_error(": did not come up\n"); 1077 return -1; 1078 } 1079 1080 return 0; 1081 } 1082 1083 void 1084 mp_cpu_start_cleanup(struct cpu_info *ci) 1085 { 1086 #if 0 1087 /* 1088 * Ensure the NVRAM reset byte contains something vaguely sane. 1089 */ 1090 1091 outb(IO_RTC, NVRAM_RESET); 1092 outb(IO_RTC+1, NVRAM_RESET_RST); 1093 #endif 1094 if (vcpu_is_up(ci)) { 1095 aprint_debug_dev(ci->ci_dev, "is started.\n"); 1096 } 1097 else { 1098 aprint_error_dev(ci->ci_dev, "did not start up.\n"); 1099 } 1100 1101 } 1102 1103 void 1104 cpu_init_msrs(struct cpu_info *ci, bool full) 1105 { 1106 #ifdef __x86_64__ 1107 if (full) { 1108 HYPERVISOR_set_segment_base (SEGBASE_FS, 0); 1109 HYPERVISOR_set_segment_base (SEGBASE_GS_KERNEL, (uint64_t) ci); 1110 HYPERVISOR_set_segment_base (SEGBASE_GS_USER, 0); 1111 } 1112 #endif /* __x86_64__ */ 1113 1114 if (cpu_feature[2] & CPUID_NOX) 1115 wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_NXE); 1116 1117 } 1118 1119 void 1120 cpu_offline_md(void) 1121 { 1122 int s; 1123 1124 s = splhigh(); 1125 #ifdef __i386__ 1126 npxsave_cpu(true); 1127 #else 1128 fpusave_cpu(true); 1129 #endif 1130 splx(s); 1131 } 1132 1133 #if 0 1134 /* XXX joerg restructure and restart CPUs individually */ 1135 static bool 1136 cpu_suspend(device_t dv, const pmf_qual_t *qual) 1137 { 1138 struct cpu_softc *sc = device_private(dv); 1139 struct cpu_info *ci = sc->sc_info; 1140 int err; 1141 1142 if (ci->ci_flags & CPUF_PRIMARY) 1143 return true; 1144 if (ci->ci_data.cpu_idlelwp == NULL) 1145 return true; 1146 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1147 return true; 1148 1149 sc->sc_wasonline = !(ci->ci_schedstate.spc_flags & SPCF_OFFLINE); 1150 1151 if (sc->sc_wasonline) { 1152 mutex_enter(&cpu_lock); 1153 err = cpu_setstate(ci, false); 1154 mutex_exit(&cpu_lock); 1155 1156 if (err) 1157 return false; 1158 } 1159 1160 return true; 1161 } 1162 1163 static bool 1164 cpu_resume(device_t dv, const pmf_qual_t *qual) 1165 { 1166 struct cpu_softc *sc = device_private(dv); 1167 struct cpu_info *ci = sc->sc_info; 1168 int err = 0; 1169 1170 if (ci->ci_flags & CPUF_PRIMARY) 1171 return true; 1172 if (ci->ci_data.cpu_idlelwp == NULL) 1173 return true; 1174 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1175 return true; 1176 1177 if (sc->sc_wasonline) { 1178 mutex_enter(&cpu_lock); 1179 err = cpu_setstate(ci, true); 1180 mutex_exit(&cpu_lock); 1181 } 1182 1183 return err == 0; 1184 } 1185 #endif 1186 1187 void 1188 cpu_get_tsc_freq(struct cpu_info *ci) 1189 { 1190 uint32_t vcpu_tversion; 1191 const volatile vcpu_time_info_t *tinfo = &ci->ci_vcpu->time; 1192 1193 vcpu_tversion = tinfo->version; 1194 while (tinfo->version == vcpu_tversion); /* Wait for a time update. XXX: timeout ? */ 1195 1196 uint64_t freq = 1000000000ULL << 32; 1197 freq = freq / (uint64_t)tinfo->tsc_to_system_mul; 1198 if ( tinfo->tsc_shift < 0 ) 1199 freq = freq << -tinfo->tsc_shift; 1200 else 1201 freq = freq >> tinfo->tsc_shift; 1202 ci->ci_data.cpu_cc_freq = freq; 1203 } 1204 1205 void 1206 x86_cpu_idle_xen(void) 1207 { 1208 struct cpu_info *ci = curcpu(); 1209 1210 KASSERT(ci->ci_ilevel == IPL_NONE); 1211 1212 x86_disable_intr(); 1213 if (!__predict_false(ci->ci_want_resched)) { 1214 idle_block(); 1215 } else { 1216 x86_enable_intr(); 1217 } 1218 } 1219 1220 /* 1221 * Loads pmap for the current CPU. 1222 */ 1223 void 1224 cpu_load_pmap(struct pmap *pmap) 1225 { 1226 #ifdef i386 1227 #ifdef PAE 1228 int i, s; 1229 struct cpu_info *ci; 1230 1231 s = splvm(); /* just to be safe */ 1232 xpq_queue_lock(); 1233 ci = curcpu(); 1234 paddr_t l3_pd = xpmap_ptom_masked(ci->ci_pae_l3_pdirpa); 1235 /* don't update the kernel L3 slot */ 1236 for (i = 0 ; i < PDP_SIZE - 1; i++) { 1237 xpq_queue_pte_update(l3_pd + i * sizeof(pd_entry_t), 1238 xpmap_ptom(pmap->pm_pdirpa[i]) | PG_V); 1239 } 1240 xpq_queue_unlock(); 1241 splx(s); 1242 tlbflush(); 1243 #else /* PAE */ 1244 lcr3(pmap_pdirpa(pmap, 0)); 1245 #endif /* PAE */ 1246 #endif /* i386 */ 1247 1248 #ifdef __x86_64__ 1249 int i, s; 1250 pd_entry_t *old_pgd, *new_pgd; 1251 paddr_t addr; 1252 struct cpu_info *ci; 1253 1254 /* kernel pmap always in cr3 and should never go in user cr3 */ 1255 if (pmap_pdirpa(pmap, 0) != pmap_pdirpa(pmap_kernel(), 0)) { 1256 ci = curcpu(); 1257 /* 1258 * Map user space address in kernel space and load 1259 * user cr3 1260 */ 1261 s = splvm(); 1262 new_pgd = pmap->pm_pdir; 1263 old_pgd = pmap_kernel()->pm_pdir; 1264 addr = xpmap_ptom(pmap_pdirpa(pmap_kernel(), 0)); 1265 for (i = 0; i < PDIR_SLOT_PTE; 1266 i++, addr += sizeof(pd_entry_t)) { 1267 if ((new_pgd[i] & PG_V) || (old_pgd[i] & PG_V)) 1268 xpq_queue_pte_update(addr, new_pgd[i]); 1269 } 1270 xen_set_user_pgd(pmap_pdirpa(pmap, 0)); 1271 ci->ci_xen_current_user_pgd = pmap_pdirpa(pmap, 0); 1272 tlbflush(); 1273 splx(s); 1274 } 1275 #endif /* __x86_64__ */ 1276 } 1277 1278 /* 1279 * Notify all other cpus to halt. 1280 */ 1281 1282 void 1283 cpu_broadcast_halt(void) 1284 { 1285 xen_broadcast_ipi(XEN_IPI_HALT); 1286 } 1287 1288 /* 1289 * Send a dummy ipi to a cpu. 1290 */ 1291 1292 void 1293 cpu_kick(struct cpu_info *ci) 1294 { 1295 (void)xen_send_ipi(ci, XEN_IPI_KICK); 1296 } 1297
Indexes created Mon Sep 22 13:09:51 GMT 2025