cpu.c revision 1.65
1 /* $NetBSD: cpu.c,v 1.65 2011/09/20 00:12:24 jym Exp $ */ 2 /* NetBSD: cpu.c,v 1.18 2004/02/20 17:35:01 yamt Exp */ 3 4 /*- 5 * Copyright (c) 2000 The NetBSD Foundation, Inc. 6 * Copyright (c) 2002, 2006, 2007 YAMAMOTO Takashi, 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to The NetBSD Foundation 10 * by RedBack Networks Inc. 11 * 12 * Author: Bill Sommerfeld 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * Copyright (c) 1999 Stefan Grefen 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 56 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.65 2011/09/20 00:12:24 jym Exp $"); 70 71 #include "opt_ddb.h" 72 #include "opt_multiprocessor.h" 73 #include "opt_mpbios.h" /* for MPDEBUG */ 74 #include "opt_mtrr.h" 75 #include "opt_xen.h" 76 77 #include "lapic.h" 78 #include "ioapic.h" 79 80 #include <sys/param.h> 81 #include <sys/proc.h> 82 #include <sys/systm.h> 83 #include <sys/device.h> 84 #include <sys/kmem.h> 85 #include <sys/cpu.h> 86 #include <sys/atomic.h> 87 #include <sys/reboot.h> 88 #include <sys/idle.h> 89 90 #include <uvm/uvm.h> 91 92 #include <machine/cpufunc.h> 93 #include <machine/cpuvar.h> 94 #include <machine/pmap.h> 95 #include <machine/vmparam.h> 96 #include <machine/mpbiosvar.h> 97 #include <machine/pcb.h> 98 #include <machine/specialreg.h> 99 #include <machine/segments.h> 100 #include <machine/gdt.h> 101 #include <machine/mtrr.h> 102 #include <machine/pio.h> 103 104 #ifdef i386 105 #include <machine/npx.h> 106 #else 107 #include <machine/fpu.h> 108 #endif 109 110 #include <xen/xen.h> 111 #include <xen/xen3-public/vcpu.h> 112 #include <xen/vcpuvar.h> 113 114 #if NLAPIC > 0 115 #include <machine/apicvar.h> 116 #include <machine/i82489reg.h> 117 #include <machine/i82489var.h> 118 #endif 119 120 #include <dev/ic/mc146818reg.h> 121 #include <dev/isa/isareg.h> 122 123 #if MAXCPUS > 32 124 #error cpu_info contains 32bit bitmasks 125 #endif 126 127 static int cpu_match(device_t, cfdata_t, void *); 128 static void cpu_attach(device_t, device_t, void *); 129 static void cpu_defer(device_t); 130 static int cpu_rescan(device_t, const char *, const int *); 131 static void cpu_childdetached(device_t, device_t); 132 static int vcpu_match(device_t, cfdata_t, void *); 133 static void vcpu_attach(device_t, device_t, void *); 134 static void cpu_attach_common(device_t, device_t, void *); 135 void cpu_offline_md(void); 136 137 struct cpu_softc { 138 device_t sc_dev; /* device tree glue */ 139 struct cpu_info *sc_info; /* pointer to CPU info */ 140 bool sc_wasonline; 141 }; 142 143 int mp_cpu_start(struct cpu_info *, vaddr_t); 144 void mp_cpu_start_cleanup(struct cpu_info *); 145 const struct cpu_functions mp_cpu_funcs = { mp_cpu_start, NULL, 146 mp_cpu_start_cleanup }; 147 148 CFATTACH_DECL2_NEW(cpu, sizeof(struct cpu_softc), 149 cpu_match, cpu_attach, NULL, NULL, cpu_rescan, cpu_childdetached); 150 151 CFATTACH_DECL_NEW(vcpu, sizeof(struct cpu_softc), 152 vcpu_match, vcpu_attach, NULL, NULL); 153 154 /* 155 * Statically-allocated CPU info for the primary CPU (or the only 156 * CPU, on uniprocessors). The CPU info list is initialized to 157 * point at it. 158 */ 159 #ifdef TRAPLOG 160 #include <machine/tlog.h> 161 struct tlog tlog_primary; 162 #endif 163 struct cpu_info cpu_info_primary __aligned(CACHE_LINE_SIZE) = { 164 .ci_dev = 0, 165 .ci_self = &cpu_info_primary, 166 .ci_idepth = -1, 167 .ci_curlwp = &lwp0, 168 .ci_curldt = -1, 169 .ci_cpumask = 1, 170 #ifdef TRAPLOG 171 .ci_tlog = &tlog_primary, 172 #endif 173 174 }; 175 struct cpu_info phycpu_info_primary __aligned(CACHE_LINE_SIZE) = { 176 .ci_dev = 0, 177 .ci_self = &phycpu_info_primary, 178 }; 179 180 struct cpu_info *cpu_info_list = &cpu_info_primary; 181 struct cpu_info *phycpu_info_list = &phycpu_info_primary; 182 183 uint32_t cpus_attached = 1; 184 uint32_t cpus_running = 1; 185 186 uint32_t phycpus_attached = 0; 187 uint32_t phycpus_running = 0; 188 189 uint32_t cpu_feature[5]; /* X86 CPUID feature bits 190 * [0] basic features %edx 191 * [1] basic features %ecx 192 * [2] extended features %edx 193 * [3] extended features %ecx 194 * [4] VIA padlock features 195 */ 196 197 bool x86_mp_online; 198 paddr_t mp_trampoline_paddr = MP_TRAMPOLINE; 199 200 #if defined(MULTIPROCESSOR) 201 void cpu_hatch(void *); 202 static void cpu_boot_secondary(struct cpu_info *ci); 203 static void cpu_start_secondary(struct cpu_info *ci); 204 #endif /* MULTIPROCESSOR */ 205 206 static int 207 cpu_match(device_t parent, cfdata_t match, void *aux) 208 { 209 210 return 1; 211 } 212 213 static void 214 cpu_attach(device_t parent, device_t self, void *aux) 215 { 216 struct cpu_softc *sc = device_private(self); 217 struct cpu_attach_args *caa = aux; 218 struct cpu_info *ci; 219 uintptr_t ptr; 220 static int nphycpu = 0; 221 222 sc->sc_dev = self; 223 224 if (phycpus_attached == ~0) { 225 aprint_error(": increase MAXCPUS\n"); 226 return; 227 } 228 229 /* 230 * If we're an Application Processor, allocate a cpu_info 231 * If we're the first attached CPU use the primary cpu_info, 232 * otherwise allocate a new one 233 */ 234 aprint_naive("\n"); 235 aprint_normal("\n"); 236 if (nphycpu > 0) { 237 struct cpu_info *tmp; 238 ptr = (uintptr_t)kmem_zalloc(sizeof(*ci) + CACHE_LINE_SIZE - 1, 239 KM_SLEEP); 240 ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE); 241 ci->ci_curldt = -1; 242 243 tmp = phycpu_info_list; 244 while (tmp->ci_next) 245 tmp = tmp->ci_next; 246 247 tmp->ci_next = ci; 248 } else { 249 ci = &phycpu_info_primary; 250 } 251 252 ci->ci_self = ci; 253 sc->sc_info = ci; 254 255 ci->ci_dev = self; 256 ci->ci_acpiid = caa->cpu_id; 257 ci->ci_cpuid = caa->cpu_number; 258 ci->ci_vcpu = NULL; 259 ci->ci_index = nphycpu++; 260 ci->ci_cpumask = (1 << cpu_index(ci)); 261 262 atomic_or_32(&phycpus_attached, ci->ci_cpumask); 263 264 if (!pmf_device_register(self, NULL, NULL)) 265 aprint_error_dev(self, "couldn't establish power handler\n"); 266 267 (void)config_defer(self, cpu_defer); 268 } 269 270 static void 271 cpu_defer(device_t self) 272 { 273 cpu_rescan(self, NULL, NULL); 274 } 275 276 static int 277 cpu_rescan(device_t self, const char *ifattr, const int *locators) 278 { 279 struct cpu_softc *sc = device_private(self); 280 struct cpufeature_attach_args cfaa; 281 struct cpu_info *ci = sc->sc_info; 282 283 memset(&cfaa, 0, sizeof(cfaa)); 284 cfaa.ci = ci; 285 286 if (ifattr_match(ifattr, "cpufeaturebus")) { 287 288 if (ci->ci_frequency == NULL) { 289 cfaa.name = "frequency"; 290 ci->ci_frequency = config_found_ia(self, 291 "cpufeaturebus", &cfaa, NULL); 292 } 293 } 294 295 return 0; 296 } 297 298 static void 299 cpu_childdetached(device_t self, device_t child) 300 { 301 struct cpu_softc *sc = device_private(self); 302 struct cpu_info *ci = sc->sc_info; 303 304 if (ci->ci_frequency == child) 305 ci->ci_frequency = NULL; 306 } 307 308 static int 309 vcpu_match(device_t parent, cfdata_t match, void *aux) 310 { 311 struct vcpu_attach_args *vcaa = aux; 312 struct vcpu_runstate_info vcr; 313 int error; 314 315 if (strcmp(vcaa->vcaa_name, match->cf_name) == 0) { 316 error = HYPERVISOR_vcpu_op(VCPUOP_get_runstate_info, 317 vcaa->vcaa_caa.cpu_number, 318 &vcr); 319 switch (error) { 320 case 0: 321 return 1; 322 case -ENOENT: 323 return 0; 324 default: 325 panic("Unknown hypervisor error %d returned on vcpu runstate probe\n", error); 326 } 327 } 328 329 return 0; 330 } 331 332 static void 333 vcpu_attach(device_t parent, device_t self, void *aux) 334 { 335 struct vcpu_attach_args *vcaa = aux; 336 337 KASSERT(vcaa->vcaa_caa.cpu_func == NULL); 338 vcaa->vcaa_caa.cpu_func = &mp_cpu_funcs; 339 cpu_attach_common(parent, self, &vcaa->vcaa_caa); 340 341 if (!pmf_device_register(self, NULL, NULL)) 342 aprint_error_dev(self, "couldn't establish power handler\n"); 343 } 344 345 static int 346 vcpu_is_up(struct cpu_info *ci) 347 { 348 KASSERT(ci != NULL); 349 return HYPERVISOR_vcpu_op(VCPUOP_is_up, ci->ci_cpuid, NULL); 350 } 351 352 static void 353 cpu_vm_init(struct cpu_info *ci) 354 { 355 int ncolors = 2, i; 356 357 for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) { 358 struct x86_cache_info *cai; 359 int tcolors; 360 361 cai = &ci->ci_cinfo[i]; 362 363 tcolors = atop(cai->cai_totalsize); 364 switch(cai->cai_associativity) { 365 case 0xff: 366 tcolors = 1; /* fully associative */ 367 break; 368 case 0: 369 case 1: 370 break; 371 default: 372 tcolors /= cai->cai_associativity; 373 } 374 ncolors = max(ncolors, tcolors); 375 } 376 377 /* 378 * Knowing the size of the largest cache on this CPU, re-color 379 * our pages. 380 */ 381 if (ncolors <= uvmexp.ncolors) 382 return; 383 aprint_debug_dev(ci->ci_dev, "%d page colors\n", ncolors); 384 uvm_page_recolor(ncolors); 385 } 386 387 static void 388 cpu_attach_common(device_t parent, device_t self, void *aux) 389 { 390 struct cpu_softc *sc = device_private(self); 391 struct cpu_attach_args *caa = aux; 392 struct cpu_info *ci; 393 uintptr_t ptr; 394 int cpunum = caa->cpu_number; 395 static bool again = false; 396 397 sc->sc_dev = self; 398 399 /* 400 * If we're an Application Processor, allocate a cpu_info 401 * structure, otherwise use the primary's. 402 */ 403 if (caa->cpu_role == CPU_ROLE_AP) { 404 aprint_naive(": Application Processor\n"); 405 ptr = (uintptr_t)kmem_alloc(sizeof(*ci) + CACHE_LINE_SIZE - 1, 406 KM_SLEEP); 407 ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE); 408 memset(ci, 0, sizeof(*ci)); 409 #ifdef TRAPLOG 410 ci->ci_tlog_base = kmem_zalloc(sizeof(struct tlog), KM_SLEEP); 411 #endif 412 } else { 413 aprint_naive(": %s Processor\n", 414 caa->cpu_role == CPU_ROLE_SP ? "Single" : "Boot"); 415 ci = &cpu_info_primary; 416 } 417 418 ci->ci_self = ci; 419 sc->sc_info = ci; 420 ci->ci_dev = self; 421 ci->ci_cpuid = cpunum; 422 423 KASSERT(HYPERVISOR_shared_info != NULL); 424 ci->ci_vcpu = &HYPERVISOR_shared_info->vcpu_info[cpunum]; 425 426 KASSERT(ci->ci_func == 0); 427 ci->ci_func = caa->cpu_func; 428 429 /* Must be called before mi_cpu_attach(). */ 430 cpu_vm_init(ci); 431 432 if (caa->cpu_role == CPU_ROLE_AP) { 433 int error; 434 435 error = mi_cpu_attach(ci); 436 437 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 438 if (error != 0) { 439 aprint_normal("\n"); 440 aprint_error_dev(self, 441 "mi_cpu_attach failed with %d\n", error); 442 return; 443 } 444 445 } else { 446 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 447 } 448 449 ci->ci_cpumask = (1 << cpu_index(ci)); 450 pmap_reference(pmap_kernel()); 451 ci->ci_pmap = pmap_kernel(); 452 ci->ci_tlbstate = TLBSTATE_STALE; 453 454 /* 455 * Boot processor may not be attached first, but the below 456 * must be done to allow booting other processors. 457 */ 458 if (!again) { 459 atomic_or_32(&ci->ci_flags, CPUF_PRESENT | CPUF_PRIMARY); 460 /* Basic init. */ 461 cpu_intr_init(ci); 462 cpu_get_tsc_freq(ci); 463 cpu_init(ci); 464 pmap_cpu_init_late(ci); /* XXX: cosmetic */ 465 466 /* Every processor needs to init it's own ipi h/w (similar to lapic) */ 467 xen_ipi_init(); 468 /* XXX: clock_init() */ 469 470 /* Make sure DELAY() is initialized. */ 471 DELAY(1); 472 again = true; 473 } 474 475 /* further PCB init done later. */ 476 477 switch (caa->cpu_role) { 478 case CPU_ROLE_SP: 479 atomic_or_32(&ci->ci_flags, CPUF_SP); 480 cpu_identify(ci); 481 #if 0 482 x86_errata(); 483 #endif 484 x86_cpu_idle_init(); 485 486 break; 487 488 case CPU_ROLE_BP: 489 atomic_or_32(&ci->ci_flags, CPUF_BSP); 490 cpu_identify(ci); 491 cpu_init(ci); 492 #if 0 493 x86_errata(); 494 #endif 495 x86_cpu_idle_init(); 496 497 break; 498 499 case CPU_ROLE_AP: 500 atomic_or_32(&ci->ci_flags, CPUF_AP); 501 502 /* 503 * report on an AP 504 */ 505 506 #if defined(MULTIPROCESSOR) 507 /* interrupt handler stack */ 508 cpu_intr_init(ci); 509 510 /* Setup per-cpu memory for gdt */ 511 gdt_alloc_cpu(ci); 512 513 pmap_cpu_init_late(ci); 514 cpu_start_secondary(ci); 515 516 if (ci->ci_flags & CPUF_PRESENT) { 517 struct cpu_info *tmp; 518 519 cpu_identify(ci); 520 tmp = cpu_info_list; 521 while (tmp->ci_next) 522 tmp = tmp->ci_next; 523 524 tmp->ci_next = ci; 525 } 526 #else 527 aprint_error(": not started\n"); 528 #endif 529 break; 530 531 default: 532 aprint_normal("\n"); 533 panic("unknown processor type??\n"); 534 } 535 536 pat_init(ci); 537 atomic_or_32(&cpus_attached, ci->ci_cpumask); 538 539 #if 0 540 if (!pmf_device_register(self, cpu_suspend, cpu_resume)) 541 aprint_error_dev(self, "couldn't establish power handler\n"); 542 #endif 543 544 #ifdef MPVERBOSE 545 if (mp_verbose) { 546 struct lwp *l = ci->ci_data.cpu_idlelwp; 547 struct pcb *pcb = lwp_getpcb(l); 548 549 aprint_verbose_dev(self, 550 "idle lwp at %p, idle sp at 0x%p\n", 551 l, 552 #ifdef i386 553 (void *)pcb->pcb_esp 554 #else /* i386 */ 555 (void *)pcb->pcb_rsp 556 #endif /* i386 */ 557 ); 558 559 } 560 #endif /* MPVERBOSE */ 561 } 562 563 /* 564 * Initialize the processor appropriately. 565 */ 566 567 void 568 cpu_init(struct cpu_info *ci) 569 { 570 571 /* 572 * On a P6 or above, enable global TLB caching if the 573 * hardware supports it. 574 */ 575 if (cpu_feature[0] & CPUID_PGE) 576 lcr4(rcr4() | CR4_PGE); /* enable global TLB caching */ 577 578 #ifdef XXXMTRR 579 /* 580 * On a P6 or above, initialize MTRR's if the hardware supports them. 581 */ 582 if (cpu_feature[0] & CPUID_MTRR) { 583 if ((ci->ci_flags & CPUF_AP) == 0) 584 i686_mtrr_init_first(); 585 mtrr_init_cpu(ci); 586 } 587 #endif 588 /* 589 * If we have FXSAVE/FXRESTOR, use them. 590 */ 591 if (cpu_feature[0] & CPUID_FXSR) { 592 lcr4(rcr4() | CR4_OSFXSR); 593 594 /* 595 * If we have SSE/SSE2, enable XMM exceptions. 596 */ 597 if (cpu_feature[0] & (CPUID_SSE|CPUID_SSE2)) 598 lcr4(rcr4() | CR4_OSXMMEXCPT); 599 } 600 601 #ifdef __x86_64__ 602 /* No user PGD mapped for this CPU yet */ 603 ci->ci_xen_current_user_pgd = 0; 604 #endif 605 606 atomic_or_32(&cpus_running, ci->ci_cpumask); 607 atomic_or_32(&ci->ci_flags, CPUF_RUNNING); 608 609 /* XXX: register vcpu_register_runstate_memory_area, and figure out how to make sure this VCPU is running ? */ 610 } 611 612 613 #ifdef MULTIPROCESSOR 614 615 void 616 cpu_boot_secondary_processors(void) 617 { 618 struct cpu_info *ci; 619 u_long i; 620 for (i = 0; i < maxcpus; i++) { 621 ci = cpu_lookup(i); 622 if (ci == NULL) 623 continue; 624 if (ci->ci_data.cpu_idlelwp == NULL) 625 continue; 626 if ((ci->ci_flags & CPUF_PRESENT) == 0) 627 continue; 628 if (ci->ci_flags & (CPUF_BSP|CPUF_SP|CPUF_PRIMARY)) 629 continue; 630 cpu_boot_secondary(ci); 631 } 632 633 x86_mp_online = true; 634 } 635 636 static void 637 cpu_init_idle_lwp(struct cpu_info *ci) 638 { 639 struct lwp *l = ci->ci_data.cpu_idlelwp; 640 struct pcb *pcb = lwp_getpcb(l); 641 642 pcb->pcb_cr0 = rcr0(); 643 } 644 645 void 646 cpu_init_idle_lwps(void) 647 { 648 struct cpu_info *ci; 649 u_long i; 650 651 for (i = 0; i < maxcpus; i++) { 652 ci = cpu_lookup(i); 653 if (ci == NULL) 654 continue; 655 if (ci->ci_data.cpu_idlelwp == NULL) 656 continue; 657 if ((ci->ci_flags & CPUF_PRESENT) == 0) 658 continue; 659 cpu_init_idle_lwp(ci); 660 } 661 } 662 663 static void 664 cpu_start_secondary(struct cpu_info *ci) 665 { 666 int i; 667 668 aprint_debug_dev(ci->ci_dev, "starting\n"); 669 670 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 671 672 if (CPU_STARTUP(ci, (vaddr_t) cpu_hatch) != 0) { 673 return; 674 } 675 676 /* 677 * wait for it to become ready 678 */ 679 for (i = 100000; (!(ci->ci_flags & CPUF_PRESENT)) && i > 0; i--) { 680 delay(10); 681 } 682 if ((ci->ci_flags & CPUF_PRESENT) == 0) { 683 aprint_error_dev(ci->ci_dev, "failed to become ready\n"); 684 #if defined(MPDEBUG) && defined(DDB) 685 printf("dropping into debugger; continue from here to resume boot\n"); 686 Debugger(); 687 #endif 688 } 689 690 CPU_START_CLEANUP(ci); 691 } 692 693 void 694 cpu_boot_secondary(struct cpu_info *ci) 695 { 696 int i; 697 atomic_or_32(&ci->ci_flags, CPUF_GO); 698 for (i = 100000; (!(ci->ci_flags & CPUF_RUNNING)) && i > 0; i--) { 699 delay(10); 700 } 701 if ((ci->ci_flags & CPUF_RUNNING) == 0) { 702 aprint_error_dev(ci->ci_dev, "CPU failed to start\n"); 703 #if defined(MPDEBUG) && defined(DDB) 704 printf("dropping into debugger; continue from here to resume boot\n"); 705 Debugger(); 706 #endif 707 } 708 } 709 710 /* 711 * APs end up here immediately after initialisation and VCPUOP_up in 712 * mp_cpu_start(). 713 * At this point, we are running in the idle pcb/idle stack of the new 714 * CPU. This function jumps to the idle loop and starts looking for 715 * work. 716 */ 717 extern void x86_64_tls_switch(struct lwp *); 718 void 719 cpu_hatch(void *v) 720 { 721 struct cpu_info *ci = (struct cpu_info *)v; 722 struct pcb *pcb; 723 int s, i; 724 725 /* Setup TLS and kernel GS/FS */ 726 cpu_init_msrs(ci, true); 727 cpu_init_idt(); 728 gdt_init_cpu(ci); 729 730 cpu_probe(ci); 731 732 atomic_or_32(&ci->ci_flags, CPUF_PRESENT); 733 734 while ((ci->ci_flags & CPUF_GO) == 0) { 735 /* Don't use delay, boot CPU may be patching the text. */ 736 for (i = 10000; i != 0; i--) 737 x86_pause(); 738 } 739 740 /* Because the text may have been patched in x86_patch(). */ 741 x86_flush(); 742 tlbflushg(); 743 744 KASSERT((ci->ci_flags & CPUF_RUNNING) == 0); 745 746 pcb = lwp_getpcb(curlwp); 747 pcb->pcb_cr3 = pmap_pdirpa(pmap_kernel(), 0); /* XXX: consider using pmap_load() ? */ 748 pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp); 749 750 xen_ipi_init(); 751 752 xen_initclocks(); 753 754 /* XXX: lapic_initclocks(); */ 755 756 #ifdef __x86_64__ 757 fpuinit(ci); 758 #endif 759 760 lldt(GSEL(GLDT_SEL, SEL_KPL)); 761 762 cpu_init(ci); 763 cpu_get_tsc_freq(ci); 764 765 s = splhigh(); 766 x86_enable_intr(); 767 splx(s); 768 #if 0 769 x86_errata(); 770 #endif 771 772 aprint_debug_dev(ci->ci_dev, "running\n"); 773 774 cpu_switchto(NULL, ci->ci_data.cpu_idlelwp, true); 775 776 panic("switch to idle_loop context returned!\n"); 777 /* NOTREACHED */ 778 } 779 780 #if defined(DDB) 781 782 #include <ddb/db_output.h> 783 #include <machine/db_machdep.h> 784 785 /* 786 * Dump CPU information from ddb. 787 */ 788 void 789 cpu_debug_dump(void) 790 { 791 struct cpu_info *ci; 792 CPU_INFO_ITERATOR cii; 793 794 db_printf("addr dev id flags ipis curlwp fpcurlwp\n"); 795 for (CPU_INFO_FOREACH(cii, ci)) { 796 db_printf("%p %s %ld %x %x %10p %10p\n", 797 ci, 798 ci->ci_dev == NULL ? "BOOT" : device_xname(ci->ci_dev), 799 (long)ci->ci_cpuid, 800 ci->ci_flags, ci->ci_ipis, 801 ci->ci_curlwp, 802 ci->ci_fpcurlwp); 803 } 804 } 805 #endif /* DDB */ 806 807 #endif /* MULTIPROCESSOR */ 808 809 extern void hypervisor_callback(void); 810 extern void failsafe_callback(void); 811 #ifdef __x86_64__ 812 typedef void (vector)(void); 813 extern vector Xsyscall, Xsyscall32; 814 #endif 815 816 /* 817 * Setup the "trampoline". On Xen, we setup nearly all cpu context 818 * outside a trampoline, so we prototype and call targetip like so: 819 * void targetip(struct cpu_info *); 820 */ 821 822 static void 823 gdt_prepframes(paddr_t *frames, vaddr_t base, uint32_t entries) 824 { 825 int i; 826 for (i = 0; i < roundup(entries, PAGE_SIZE) >> PAGE_SHIFT; i++) { 827 828 frames[i] = ((paddr_t) xpmap_ptetomach( 829 (pt_entry_t *) (base + (i << PAGE_SHIFT)))) 830 >> PAGE_SHIFT; 831 832 /* Mark Read-only */ 833 pmap_pte_clearbits(kvtopte(base + (i << PAGE_SHIFT)), 834 PG_RW); 835 } 836 } 837 838 #ifdef __x86_64__ 839 extern char *ldtstore; /* XXX: Xen MP todo */ 840 841 static void 842 xen_init_amd64_vcpuctxt(struct cpu_info *ci, 843 struct vcpu_guest_context *initctx, 844 void targetrip(struct cpu_info *)) 845 { 846 /* page frames to point at GDT */ 847 extern int gdt_size; 848 paddr_t frames[16]; 849 psize_t gdt_ents; 850 851 struct lwp *l; 852 struct pcb *pcb; 853 854 volatile struct vcpu_info *vci; 855 856 KASSERT(ci != NULL); 857 KASSERT(ci != &cpu_info_primary); 858 KASSERT(initctx != NULL); 859 KASSERT(targetrip != NULL); 860 861 memset(initctx, 0, sizeof *initctx); 862 863 gdt_ents = roundup(gdt_size, PAGE_SIZE) >> PAGE_SHIFT; /* XXX: re-investigate roundup(gdt_size... ) for gdt_ents. */ 864 KASSERT(gdt_ents <= 16); 865 866 gdt_prepframes(frames, (vaddr_t) ci->ci_gdt, gdt_ents); 867 868 /* XXX: The stuff in here is amd64 specific. move to mptramp.[Sc] ? */ 869 870 /* Initialise the vcpu context: We use idle_loop()'s pcb context. */ 871 872 l = ci->ci_data.cpu_idlelwp; 873 874 KASSERT(l != NULL); 875 pcb = lwp_getpcb(l); 876 KASSERT(pcb != NULL); 877 878 /* resume with interrupts off */ 879 vci = ci->ci_vcpu; 880 vci->evtchn_upcall_mask = 1; 881 xen_mb(); 882 883 /* resume in kernel-mode */ 884 initctx->flags = VGCF_in_kernel | VGCF_online; 885 886 /* Stack and entry points: 887 * We arrange for the stack frame for cpu_hatch() to 888 * appear as a callee frame of lwp_trampoline(). Being a 889 * leaf frame prevents trampling on any of the MD stack setup 890 * that x86/vm_machdep.c:cpu_lwp_fork() does for idle_loop() 891 */ 892 893 initctx->user_regs.rdi = (uint64_t) ci; /* targetrip(ci); */ 894 initctx->user_regs.rip = (vaddr_t) targetrip; 895 896 initctx->user_regs.cs = GSEL(GCODE_SEL, SEL_KPL); 897 898 initctx->user_regs.rflags = pcb->pcb_flags; 899 initctx->user_regs.rsp = pcb->pcb_rsp; 900 901 /* Data segments */ 902 initctx->user_regs.ss = GSEL(GDATA_SEL, SEL_KPL); 903 initctx->user_regs.es = GSEL(GDATA_SEL, SEL_KPL); 904 initctx->user_regs.ds = GSEL(GDATA_SEL, SEL_KPL); 905 906 /* GDT */ 907 memcpy(initctx->gdt_frames, frames, sizeof frames); 908 initctx->gdt_ents = gdt_ents; 909 910 /* LDT */ 911 initctx->ldt_base = (unsigned long) ldtstore; 912 initctx->ldt_ents = LDT_SIZE >> 3; 913 914 /* Kernel context state */ 915 initctx->kernel_ss = GSEL(GDATA_SEL, SEL_KPL); 916 initctx->kernel_sp = pcb->pcb_rsp0; 917 initctx->ctrlreg[0] = pcb->pcb_cr0; 918 initctx->ctrlreg[1] = 0; /* "resuming" from kernel - no User cr3. */ 919 initctx->ctrlreg[2] = pcb->pcb_cr2; /* XXX: */ 920 /* 921 * Use pmap_kernel() L4 PD directly, until we setup the 922 * per-cpu L4 PD in pmap_cpu_init_late() 923 */ 924 initctx->ctrlreg[3] = xpmap_ptom(pcb->pcb_cr3); 925 initctx->ctrlreg[4] = CR4_PAE | CR4_OSFXSR | CR4_OSXMMEXCPT; 926 927 928 /* Xen callbacks */ 929 initctx->event_callback_eip = (unsigned long) hypervisor_callback; 930 initctx->failsafe_callback_eip = (unsigned long) failsafe_callback; 931 initctx->syscall_callback_eip = (unsigned long) Xsyscall; 932 933 return; 934 } 935 #else /* i386 */ 936 extern union descriptor *ldt; 937 extern void Xsyscall(void); 938 939 static void 940 xen_init_i386_vcpuctxt(struct cpu_info *ci, 941 struct vcpu_guest_context *initctx, 942 void targeteip(struct cpu_info *)) 943 { 944 /* page frames to point at GDT */ 945 extern int gdt_size; 946 paddr_t frames[16]; 947 psize_t gdt_ents; 948 949 struct lwp *l; 950 struct pcb *pcb; 951 952 volatile struct vcpu_info *vci; 953 954 KASSERT(ci != NULL); 955 KASSERT(ci != &cpu_info_primary); 956 KASSERT(initctx != NULL); 957 KASSERT(targeteip != NULL); 958 959 memset(initctx, 0, sizeof *initctx); 960 961 gdt_ents = roundup(gdt_size, PAGE_SIZE) >> PAGE_SHIFT; /* XXX: re-investigate roundup(gdt_size... ) for gdt_ents. */ 962 KASSERT(gdt_ents <= 16); 963 964 gdt_prepframes(frames, (vaddr_t) ci->ci_gdt, gdt_ents); 965 966 /* 967 * Initialise the vcpu context: 968 * We use this cpu's idle_loop() pcb context. 969 */ 970 971 l = ci->ci_data.cpu_idlelwp; 972 973 KASSERT(l != NULL); 974 pcb = lwp_getpcb(l); 975 KASSERT(pcb != NULL); 976 977 /* resume with interrupts off */ 978 vci = ci->ci_vcpu; 979 vci->evtchn_upcall_mask = 1; 980 xen_mb(); 981 982 /* resume in kernel-mode */ 983 initctx->flags = VGCF_in_kernel | VGCF_online; 984 985 /* Stack frame setup for cpu_hatch(): 986 * We arrange for the stack frame for cpu_hatch() to 987 * appear as a callee frame of lwp_trampoline(). Being a 988 * leaf frame prevents trampling on any of the MD stack setup 989 * that x86/vm_machdep.c:cpu_lwp_fork() does for idle_loop() 990 */ 991 992 initctx->user_regs.esp = pcb->pcb_esp - 4; /* Leave word for 993 arg1 */ 994 { /* targeteip(ci); */ 995 uint32_t *arg = (uint32_t *) initctx->user_regs.esp; 996 arg[1] = (uint32_t) ci; /* arg1 */ 997 998 } 999 1000 initctx->user_regs.eip = (vaddr_t) targeteip; 1001 initctx->user_regs.cs = GSEL(GCODE_SEL, SEL_KPL); 1002 initctx->user_regs.eflags |= pcb->pcb_iopl; 1003 1004 /* Data segments */ 1005 initctx->user_regs.ss = GSEL(GDATA_SEL, SEL_KPL); 1006 initctx->user_regs.es = GSEL(GDATA_SEL, SEL_KPL); 1007 initctx->user_regs.ds = GSEL(GDATA_SEL, SEL_KPL); 1008 initctx->user_regs.fs = GSEL(GDATA_SEL, SEL_KPL); 1009 1010 /* GDT */ 1011 memcpy(initctx->gdt_frames, frames, sizeof frames); 1012 initctx->gdt_ents = gdt_ents; 1013 1014 /* LDT */ 1015 initctx->ldt_base = (unsigned long) ldt; 1016 initctx->ldt_ents = NLDT; 1017 1018 /* Kernel context state */ 1019 initctx->kernel_ss = GSEL(GDATA_SEL, SEL_KPL); 1020 initctx->kernel_sp = pcb->pcb_esp0; 1021 initctx->ctrlreg[0] = pcb->pcb_cr0; 1022 initctx->ctrlreg[1] = 0; /* "resuming" from kernel - no User cr3. */ 1023 initctx->ctrlreg[2] = pcb->pcb_cr2; /* XXX: */ 1024 /* 1025 * Use pmap_kernel() L4 PD directly, until we setup the 1026 * per-cpu L4 PD in pmap_cpu_init_late() 1027 */ 1028 initctx->ctrlreg[3] = xpmap_ptom(pcb->pcb_cr3); 1029 initctx->ctrlreg[4] = /* CR4_PAE | */CR4_OSFXSR | CR4_OSXMMEXCPT; 1030 1031 1032 /* Xen callbacks */ 1033 initctx->event_callback_eip = (unsigned long) hypervisor_callback; 1034 initctx->event_callback_cs = GSEL(GCODE_SEL, SEL_KPL); 1035 initctx->failsafe_callback_eip = (unsigned long) failsafe_callback; 1036 initctx->failsafe_callback_cs = GSEL(GCODE_SEL, SEL_KPL); 1037 1038 return; 1039 } 1040 #endif /* __x86_64__ */ 1041 1042 int 1043 mp_cpu_start(struct cpu_info *ci, vaddr_t target) 1044 { 1045 1046 int hyperror; 1047 struct vcpu_guest_context vcpuctx; 1048 1049 KASSERT(ci != NULL); 1050 KASSERT(ci != &cpu_info_primary); 1051 KASSERT(ci->ci_flags & CPUF_AP); 1052 1053 #ifdef __x86_64__ 1054 xen_init_amd64_vcpuctxt(ci, &vcpuctx, (void (*)(struct cpu_info *))target); 1055 #else /* i386 */ 1056 xen_init_i386_vcpuctxt(ci, &vcpuctx, (void (*)(struct cpu_info *))target); 1057 #endif /* __x86_64__ */ 1058 1059 /* Initialise the given vcpu to execute cpu_hatch(ci); */ 1060 if ((hyperror = HYPERVISOR_vcpu_op(VCPUOP_initialise, ci->ci_cpuid, &vcpuctx))) { 1061 aprint_error(": context initialisation failed. errno = %d\n", hyperror); 1062 return hyperror; 1063 } 1064 1065 /* Start it up */ 1066 1067 /* First bring it down - the Xen documentation conveniently omits this slight detail. */ 1068 if ((hyperror = HYPERVISOR_vcpu_op(VCPUOP_down, ci->ci_cpuid, NULL))) { 1069 aprint_error(": VCPUOP_down hypervisor command failed. errno = %d\n", hyperror); 1070 return hyperror; 1071 } 1072 1073 if ((hyperror = HYPERVISOR_vcpu_op(VCPUOP_up, ci->ci_cpuid, NULL))) { 1074 aprint_error(": VCPUOP_up hypervisor command failed. errno = %d\n", hyperror); 1075 return hyperror; 1076 } 1077 1078 if (!vcpu_is_up(ci)) { 1079 aprint_error(": did not come up\n"); 1080 return -1; 1081 } 1082 1083 return 0; 1084 } 1085 1086 void 1087 mp_cpu_start_cleanup(struct cpu_info *ci) 1088 { 1089 #if 0 1090 /* 1091 * Ensure the NVRAM reset byte contains something vaguely sane. 1092 */ 1093 1094 outb(IO_RTC, NVRAM_RESET); 1095 outb(IO_RTC+1, NVRAM_RESET_RST); 1096 #endif 1097 if (vcpu_is_up(ci)) { 1098 aprint_debug_dev(ci->ci_dev, "is started.\n"); 1099 } 1100 else { 1101 aprint_error_dev(ci->ci_dev, "did not start up.\n"); 1102 } 1103 1104 } 1105 1106 void 1107 cpu_init_msrs(struct cpu_info *ci, bool full) 1108 { 1109 #ifdef __x86_64__ 1110 if (full) { 1111 HYPERVISOR_set_segment_base (SEGBASE_FS, 0); 1112 HYPERVISOR_set_segment_base (SEGBASE_GS_KERNEL, (uint64_t) ci); 1113 HYPERVISOR_set_segment_base (SEGBASE_GS_USER, 0); 1114 } 1115 #endif /* __x86_64__ */ 1116 1117 if (cpu_feature[2] & CPUID_NOX) 1118 wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_NXE); 1119 1120 } 1121 1122 void 1123 cpu_offline_md(void) 1124 { 1125 int s; 1126 1127 s = splhigh(); 1128 #ifdef __i386__ 1129 npxsave_cpu(true); 1130 #else 1131 fpusave_cpu(true); 1132 #endif 1133 splx(s); 1134 } 1135 1136 #if 0 1137 /* XXX joerg restructure and restart CPUs individually */ 1138 static bool 1139 cpu_suspend(device_t dv, const pmf_qual_t *qual) 1140 { 1141 struct cpu_softc *sc = device_private(dv); 1142 struct cpu_info *ci = sc->sc_info; 1143 int err; 1144 1145 if (ci->ci_flags & CPUF_PRIMARY) 1146 return true; 1147 if (ci->ci_data.cpu_idlelwp == NULL) 1148 return true; 1149 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1150 return true; 1151 1152 sc->sc_wasonline = !(ci->ci_schedstate.spc_flags & SPCF_OFFLINE); 1153 1154 if (sc->sc_wasonline) { 1155 mutex_enter(&cpu_lock); 1156 err = cpu_setstate(ci, false); 1157 mutex_exit(&cpu_lock); 1158 1159 if (err) 1160 return false; 1161 } 1162 1163 return true; 1164 } 1165 1166 static bool 1167 cpu_resume(device_t dv, const pmf_qual_t *qual) 1168 { 1169 struct cpu_softc *sc = device_private(dv); 1170 struct cpu_info *ci = sc->sc_info; 1171 int err = 0; 1172 1173 if (ci->ci_flags & CPUF_PRIMARY) 1174 return true; 1175 if (ci->ci_data.cpu_idlelwp == NULL) 1176 return true; 1177 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1178 return true; 1179 1180 if (sc->sc_wasonline) { 1181 mutex_enter(&cpu_lock); 1182 err = cpu_setstate(ci, true); 1183 mutex_exit(&cpu_lock); 1184 } 1185 1186 return err == 0; 1187 } 1188 #endif 1189 1190 void 1191 cpu_get_tsc_freq(struct cpu_info *ci) 1192 { 1193 uint32_t vcpu_tversion; 1194 const volatile vcpu_time_info_t *tinfo = &ci->ci_vcpu->time; 1195 1196 vcpu_tversion = tinfo->version; 1197 while (tinfo->version == vcpu_tversion); /* Wait for a time update. XXX: timeout ? */ 1198 1199 uint64_t freq = 1000000000ULL << 32; 1200 freq = freq / (uint64_t)tinfo->tsc_to_system_mul; 1201 if ( tinfo->tsc_shift < 0 ) 1202 freq = freq << -tinfo->tsc_shift; 1203 else 1204 freq = freq >> tinfo->tsc_shift; 1205 ci->ci_data.cpu_cc_freq = freq; 1206 } 1207 1208 void 1209 x86_cpu_idle_xen(void) 1210 { 1211 struct cpu_info *ci = curcpu(); 1212 1213 KASSERT(ci->ci_ilevel == IPL_NONE); 1214 1215 x86_disable_intr(); 1216 if (!__predict_false(ci->ci_want_resched)) { 1217 idle_block(); 1218 } else { 1219 x86_enable_intr(); 1220 } 1221 } 1222 1223 /* 1224 * Loads pmap for the current CPU. 1225 */ 1226 void 1227 cpu_load_pmap(struct pmap *pmap) 1228 { 1229 #ifdef i386 1230 #ifdef PAE 1231 int i, s; 1232 struct cpu_info *ci; 1233 1234 s = splvm(); /* just to be safe */ 1235 xpq_queue_lock(); 1236 ci = curcpu(); 1237 paddr_t l3_pd = xpmap_ptom_masked(ci->ci_pae_l3_pdirpa); 1238 /* don't update the kernel L3 slot */ 1239 for (i = 0 ; i < PDP_SIZE - 1; i++) { 1240 xpq_queue_pte_update(l3_pd + i * sizeof(pd_entry_t), 1241 xpmap_ptom(pmap->pm_pdirpa[i]) | PG_V); 1242 } 1243 xpq_queue_unlock(); 1244 splx(s); 1245 tlbflush(); 1246 #else /* PAE */ 1247 lcr3(pmap_pdirpa(pmap, 0)); 1248 #endif /* PAE */ 1249 #endif /* i386 */ 1250 1251 #ifdef __x86_64__ 1252 int i, s; 1253 pd_entry_t *old_pgd, *new_pgd; 1254 paddr_t addr; 1255 struct cpu_info *ci; 1256 1257 /* kernel pmap always in cr3 and should never go in user cr3 */ 1258 if (pmap_pdirpa(pmap, 0) != pmap_pdirpa(pmap_kernel(), 0)) { 1259 ci = curcpu(); 1260 /* 1261 * Map user space address in kernel space and load 1262 * user cr3 1263 */ 1264 s = splvm(); 1265 new_pgd = pmap->pm_pdir; 1266 old_pgd = pmap_kernel()->pm_pdir; 1267 addr = xpmap_ptom(pmap_pdirpa(pmap_kernel(), 0)); 1268 for (i = 0; i < PDIR_SLOT_PTE; 1269 i++, addr += sizeof(pd_entry_t)) { 1270 if ((new_pgd[i] & PG_V) || (old_pgd[i] & PG_V)) 1271 xpq_queue_pte_update(addr, new_pgd[i]); 1272 } 1273 xen_set_user_pgd(pmap_pdirpa(pmap, 0)); 1274 ci->ci_xen_current_user_pgd = pmap_pdirpa(pmap, 0); 1275 tlbflush(); 1276 splx(s); 1277 } 1278 #endif /* __x86_64__ */ 1279 } 1280 1281 /* 1282 * Notify all other cpus to halt. 1283 */ 1284 1285 void 1286 cpu_broadcast_halt(void) 1287 { 1288 xen_broadcast_ipi(XEN_IPI_HALT); 1289 } 1290 1291 /* 1292 * Send a dummy ipi to a cpu. 1293 */ 1294 1295 void 1296 cpu_kick(struct cpu_info *ci) 1297 { 1298 (void)xen_send_ipi(ci, XEN_IPI_KICK); 1299 } 1300
Indexes created Tue Sep 23 14:10:03 GMT 2025