cpu.c revision 1.66
1 /* $NetBSD: cpu.c,v 1.66 2011/09/28 15:38:22 jruoho Exp $ */ 2 /* NetBSD: cpu.c,v 1.18 2004/02/20 17:35:01 yamt Exp */ 3 4 /*- 5 * Copyright (c) 2000 The NetBSD Foundation, Inc. 6 * Copyright (c) 2002, 2006, 2007 YAMAMOTO Takashi, 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to The NetBSD Foundation 10 * by RedBack Networks Inc. 11 * 12 * Author: Bill Sommerfeld 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * Copyright (c) 1999 Stefan Grefen 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 56 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.66 2011/09/28 15:38:22 jruoho Exp $"); 70 71 #include "opt_ddb.h" 72 #include "opt_multiprocessor.h" 73 #include "opt_mpbios.h" /* for MPDEBUG */ 74 #include "opt_mtrr.h" 75 #include "opt_xen.h" 76 77 #include "lapic.h" 78 #include "ioapic.h" 79 80 #include <sys/param.h> 81 #include <sys/proc.h> 82 #include <sys/systm.h> 83 #include <sys/device.h> 84 #include <sys/kmem.h> 85 #include <sys/cpu.h> 86 #include <sys/cpufreq.h> 87 #include <sys/atomic.h> 88 #include <sys/reboot.h> 89 #include <sys/idle.h> 90 91 #include <uvm/uvm.h> 92 93 #include <machine/cpufunc.h> 94 #include <machine/cpuvar.h> 95 #include <machine/pmap.h> 96 #include <machine/vmparam.h> 97 #include <machine/mpbiosvar.h> 98 #include <machine/pcb.h> 99 #include <machine/specialreg.h> 100 #include <machine/segments.h> 101 #include <machine/gdt.h> 102 #include <machine/mtrr.h> 103 #include <machine/pio.h> 104 105 #ifdef i386 106 #include <machine/npx.h> 107 #else 108 #include <machine/fpu.h> 109 #endif 110 111 #include <xen/xen.h> 112 #include <xen/xen3-public/vcpu.h> 113 #include <xen/vcpuvar.h> 114 115 #if NLAPIC > 0 116 #include <machine/apicvar.h> 117 #include <machine/i82489reg.h> 118 #include <machine/i82489var.h> 119 #endif 120 121 #include <dev/ic/mc146818reg.h> 122 #include <dev/isa/isareg.h> 123 124 #if MAXCPUS > 32 125 #error cpu_info contains 32bit bitmasks 126 #endif 127 128 static int cpu_match(device_t, cfdata_t, void *); 129 static void cpu_attach(device_t, device_t, void *); 130 static void cpu_defer(device_t); 131 static int cpu_rescan(device_t, const char *, const int *); 132 static void cpu_childdetached(device_t, device_t); 133 static int vcpu_match(device_t, cfdata_t, void *); 134 static void vcpu_attach(device_t, device_t, void *); 135 static void cpu_attach_common(device_t, device_t, void *); 136 void cpu_offline_md(void); 137 138 struct cpu_softc { 139 device_t sc_dev; /* device tree glue */ 140 struct cpu_info *sc_info; /* pointer to CPU info */ 141 bool sc_wasonline; 142 }; 143 144 int mp_cpu_start(struct cpu_info *, vaddr_t); 145 void mp_cpu_start_cleanup(struct cpu_info *); 146 const struct cpu_functions mp_cpu_funcs = { mp_cpu_start, NULL, 147 mp_cpu_start_cleanup }; 148 149 CFATTACH_DECL2_NEW(cpu, sizeof(struct cpu_softc), 150 cpu_match, cpu_attach, NULL, NULL, cpu_rescan, cpu_childdetached); 151 152 CFATTACH_DECL_NEW(vcpu, sizeof(struct cpu_softc), 153 vcpu_match, vcpu_attach, NULL, NULL); 154 155 /* 156 * Statically-allocated CPU info for the primary CPU (or the only 157 * CPU, on uniprocessors). The CPU info list is initialized to 158 * point at it. 159 */ 160 #ifdef TRAPLOG 161 #include <machine/tlog.h> 162 struct tlog tlog_primary; 163 #endif 164 struct cpu_info cpu_info_primary __aligned(CACHE_LINE_SIZE) = { 165 .ci_dev = 0, 166 .ci_self = &cpu_info_primary, 167 .ci_idepth = -1, 168 .ci_curlwp = &lwp0, 169 .ci_curldt = -1, 170 .ci_cpumask = 1, 171 #ifdef TRAPLOG 172 .ci_tlog = &tlog_primary, 173 #endif 174 175 }; 176 struct cpu_info phycpu_info_primary __aligned(CACHE_LINE_SIZE) = { 177 .ci_dev = 0, 178 .ci_self = &phycpu_info_primary, 179 }; 180 181 struct cpu_info *cpu_info_list = &cpu_info_primary; 182 struct cpu_info *phycpu_info_list = &phycpu_info_primary; 183 184 uint32_t cpus_attached = 1; 185 uint32_t cpus_running = 1; 186 187 uint32_t phycpus_attached = 0; 188 uint32_t phycpus_running = 0; 189 190 uint32_t cpu_feature[5]; /* X86 CPUID feature bits 191 * [0] basic features %edx 192 * [1] basic features %ecx 193 * [2] extended features %edx 194 * [3] extended features %ecx 195 * [4] VIA padlock features 196 */ 197 198 bool x86_mp_online; 199 paddr_t mp_trampoline_paddr = MP_TRAMPOLINE; 200 201 #if defined(MULTIPROCESSOR) 202 void cpu_hatch(void *); 203 static void cpu_boot_secondary(struct cpu_info *ci); 204 static void cpu_start_secondary(struct cpu_info *ci); 205 #endif /* MULTIPROCESSOR */ 206 207 static int 208 cpu_match(device_t parent, cfdata_t match, void *aux) 209 { 210 211 return 1; 212 } 213 214 static void 215 cpu_attach(device_t parent, device_t self, void *aux) 216 { 217 struct cpu_softc *sc = device_private(self); 218 struct cpu_attach_args *caa = aux; 219 struct cpu_info *ci; 220 uintptr_t ptr; 221 static int nphycpu = 0; 222 223 sc->sc_dev = self; 224 225 if (phycpus_attached == ~0) { 226 aprint_error(": increase MAXCPUS\n"); 227 return; 228 } 229 230 /* 231 * If we're an Application Processor, allocate a cpu_info 232 * If we're the first attached CPU use the primary cpu_info, 233 * otherwise allocate a new one 234 */ 235 aprint_naive("\n"); 236 aprint_normal("\n"); 237 if (nphycpu > 0) { 238 struct cpu_info *tmp; 239 ptr = (uintptr_t)kmem_zalloc(sizeof(*ci) + CACHE_LINE_SIZE - 1, 240 KM_SLEEP); 241 ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE); 242 ci->ci_curldt = -1; 243 244 tmp = phycpu_info_list; 245 while (tmp->ci_next) 246 tmp = tmp->ci_next; 247 248 tmp->ci_next = ci; 249 } else { 250 ci = &phycpu_info_primary; 251 } 252 253 ci->ci_self = ci; 254 sc->sc_info = ci; 255 256 ci->ci_dev = self; 257 ci->ci_acpiid = caa->cpu_id; 258 ci->ci_cpuid = caa->cpu_number; 259 ci->ci_vcpu = NULL; 260 ci->ci_index = nphycpu++; 261 ci->ci_cpumask = (1 << cpu_index(ci)); 262 263 atomic_or_32(&phycpus_attached, ci->ci_cpumask); 264 265 if (!pmf_device_register(self, NULL, NULL)) 266 aprint_error_dev(self, "couldn't establish power handler\n"); 267 268 (void)config_defer(self, cpu_defer); 269 } 270 271 static void 272 cpu_defer(device_t self) 273 { 274 cpu_rescan(self, NULL, NULL); 275 } 276 277 static int 278 cpu_rescan(device_t self, const char *ifattr, const int *locators) 279 { 280 struct cpu_softc *sc = device_private(self); 281 struct cpufeature_attach_args cfaa; 282 struct cpu_info *ci = sc->sc_info; 283 284 memset(&cfaa, 0, sizeof(cfaa)); 285 cfaa.ci = ci; 286 287 if (ifattr_match(ifattr, "cpufeaturebus")) { 288 289 if (ci->ci_frequency == NULL) { 290 cfaa.name = "frequency"; 291 ci->ci_frequency = config_found_ia(self, 292 "cpufeaturebus", &cfaa, NULL); 293 } 294 } 295 296 return 0; 297 } 298 299 static void 300 cpu_childdetached(device_t self, device_t child) 301 { 302 struct cpu_softc *sc = device_private(self); 303 struct cpu_info *ci = sc->sc_info; 304 305 if (ci->ci_frequency == child) 306 ci->ci_frequency = NULL; 307 } 308 309 static int 310 vcpu_match(device_t parent, cfdata_t match, void *aux) 311 { 312 struct vcpu_attach_args *vcaa = aux; 313 struct vcpu_runstate_info vcr; 314 int error; 315 316 if (strcmp(vcaa->vcaa_name, match->cf_name) == 0) { 317 error = HYPERVISOR_vcpu_op(VCPUOP_get_runstate_info, 318 vcaa->vcaa_caa.cpu_number, 319 &vcr); 320 switch (error) { 321 case 0: 322 return 1; 323 case -ENOENT: 324 return 0; 325 default: 326 panic("Unknown hypervisor error %d returned on vcpu runstate probe\n", error); 327 } 328 } 329 330 return 0; 331 } 332 333 static void 334 vcpu_attach(device_t parent, device_t self, void *aux) 335 { 336 struct vcpu_attach_args *vcaa = aux; 337 338 KASSERT(vcaa->vcaa_caa.cpu_func == NULL); 339 vcaa->vcaa_caa.cpu_func = &mp_cpu_funcs; 340 cpu_attach_common(parent, self, &vcaa->vcaa_caa); 341 342 if (!pmf_device_register(self, NULL, NULL)) 343 aprint_error_dev(self, "couldn't establish power handler\n"); 344 } 345 346 static int 347 vcpu_is_up(struct cpu_info *ci) 348 { 349 KASSERT(ci != NULL); 350 return HYPERVISOR_vcpu_op(VCPUOP_is_up, ci->ci_cpuid, NULL); 351 } 352 353 static void 354 cpu_vm_init(struct cpu_info *ci) 355 { 356 int ncolors = 2, i; 357 358 for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) { 359 struct x86_cache_info *cai; 360 int tcolors; 361 362 cai = &ci->ci_cinfo[i]; 363 364 tcolors = atop(cai->cai_totalsize); 365 switch(cai->cai_associativity) { 366 case 0xff: 367 tcolors = 1; /* fully associative */ 368 break; 369 case 0: 370 case 1: 371 break; 372 default: 373 tcolors /= cai->cai_associativity; 374 } 375 ncolors = max(ncolors, tcolors); 376 } 377 378 /* 379 * Knowing the size of the largest cache on this CPU, re-color 380 * our pages. 381 */ 382 if (ncolors <= uvmexp.ncolors) 383 return; 384 aprint_debug_dev(ci->ci_dev, "%d page colors\n", ncolors); 385 uvm_page_recolor(ncolors); 386 } 387 388 static void 389 cpu_attach_common(device_t parent, device_t self, void *aux) 390 { 391 struct cpu_softc *sc = device_private(self); 392 struct cpu_attach_args *caa = aux; 393 struct cpu_info *ci; 394 uintptr_t ptr; 395 int cpunum = caa->cpu_number; 396 static bool again = false; 397 398 sc->sc_dev = self; 399 400 /* 401 * If we're an Application Processor, allocate a cpu_info 402 * structure, otherwise use the primary's. 403 */ 404 if (caa->cpu_role == CPU_ROLE_AP) { 405 aprint_naive(": Application Processor\n"); 406 ptr = (uintptr_t)kmem_alloc(sizeof(*ci) + CACHE_LINE_SIZE - 1, 407 KM_SLEEP); 408 ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE); 409 memset(ci, 0, sizeof(*ci)); 410 #ifdef TRAPLOG 411 ci->ci_tlog_base = kmem_zalloc(sizeof(struct tlog), KM_SLEEP); 412 #endif 413 } else { 414 aprint_naive(": %s Processor\n", 415 caa->cpu_role == CPU_ROLE_SP ? "Single" : "Boot"); 416 ci = &cpu_info_primary; 417 } 418 419 ci->ci_self = ci; 420 sc->sc_info = ci; 421 ci->ci_dev = self; 422 ci->ci_cpuid = cpunum; 423 424 KASSERT(HYPERVISOR_shared_info != NULL); 425 ci->ci_vcpu = &HYPERVISOR_shared_info->vcpu_info[cpunum]; 426 427 KASSERT(ci->ci_func == 0); 428 ci->ci_func = caa->cpu_func; 429 430 /* Must be called before mi_cpu_attach(). */ 431 cpu_vm_init(ci); 432 433 if (caa->cpu_role == CPU_ROLE_AP) { 434 int error; 435 436 error = mi_cpu_attach(ci); 437 438 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 439 if (error != 0) { 440 aprint_normal("\n"); 441 aprint_error_dev(self, 442 "mi_cpu_attach failed with %d\n", error); 443 return; 444 } 445 446 } else { 447 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 448 } 449 450 ci->ci_cpumask = (1 << cpu_index(ci)); 451 pmap_reference(pmap_kernel()); 452 ci->ci_pmap = pmap_kernel(); 453 ci->ci_tlbstate = TLBSTATE_STALE; 454 455 /* 456 * Boot processor may not be attached first, but the below 457 * must be done to allow booting other processors. 458 */ 459 if (!again) { 460 atomic_or_32(&ci->ci_flags, CPUF_PRESENT | CPUF_PRIMARY); 461 /* Basic init. */ 462 cpu_intr_init(ci); 463 cpu_get_tsc_freq(ci); 464 cpu_init(ci); 465 pmap_cpu_init_late(ci); /* XXX: cosmetic */ 466 467 /* Every processor needs to init it's own ipi h/w (similar to lapic) */ 468 xen_ipi_init(); 469 /* XXX: clock_init() */ 470 471 /* Make sure DELAY() is initialized. */ 472 DELAY(1); 473 again = true; 474 } 475 476 /* further PCB init done later. */ 477 478 switch (caa->cpu_role) { 479 case CPU_ROLE_SP: 480 atomic_or_32(&ci->ci_flags, CPUF_SP); 481 cpu_identify(ci); 482 #if 0 483 x86_errata(); 484 #endif 485 x86_cpu_idle_init(); 486 487 break; 488 489 case CPU_ROLE_BP: 490 atomic_or_32(&ci->ci_flags, CPUF_BSP); 491 cpu_identify(ci); 492 cpu_init(ci); 493 #if 0 494 x86_errata(); 495 #endif 496 x86_cpu_idle_init(); 497 498 break; 499 500 case CPU_ROLE_AP: 501 atomic_or_32(&ci->ci_flags, CPUF_AP); 502 503 /* 504 * report on an AP 505 */ 506 507 #if defined(MULTIPROCESSOR) 508 /* interrupt handler stack */ 509 cpu_intr_init(ci); 510 511 /* Setup per-cpu memory for gdt */ 512 gdt_alloc_cpu(ci); 513 514 pmap_cpu_init_late(ci); 515 cpu_start_secondary(ci); 516 517 if (ci->ci_flags & CPUF_PRESENT) { 518 struct cpu_info *tmp; 519 520 cpu_identify(ci); 521 tmp = cpu_info_list; 522 while (tmp->ci_next) 523 tmp = tmp->ci_next; 524 525 tmp->ci_next = ci; 526 } 527 #else 528 aprint_error(": not started\n"); 529 #endif 530 break; 531 532 default: 533 aprint_normal("\n"); 534 panic("unknown processor type??\n"); 535 } 536 537 pat_init(ci); 538 atomic_or_32(&cpus_attached, ci->ci_cpumask); 539 540 #if 0 541 if (!pmf_device_register(self, cpu_suspend, cpu_resume)) 542 aprint_error_dev(self, "couldn't establish power handler\n"); 543 #endif 544 545 #ifdef MPVERBOSE 546 if (mp_verbose) { 547 struct lwp *l = ci->ci_data.cpu_idlelwp; 548 struct pcb *pcb = lwp_getpcb(l); 549 550 aprint_verbose_dev(self, 551 "idle lwp at %p, idle sp at 0x%p\n", 552 l, 553 #ifdef i386 554 (void *)pcb->pcb_esp 555 #else /* i386 */ 556 (void *)pcb->pcb_rsp 557 #endif /* i386 */ 558 ); 559 560 } 561 #endif /* MPVERBOSE */ 562 } 563 564 /* 565 * Initialize the processor appropriately. 566 */ 567 568 void 569 cpu_init(struct cpu_info *ci) 570 { 571 572 /* 573 * On a P6 or above, enable global TLB caching if the 574 * hardware supports it. 575 */ 576 if (cpu_feature[0] & CPUID_PGE) 577 lcr4(rcr4() | CR4_PGE); /* enable global TLB caching */ 578 579 #ifdef XXXMTRR 580 /* 581 * On a P6 or above, initialize MTRR's if the hardware supports them. 582 */ 583 if (cpu_feature[0] & CPUID_MTRR) { 584 if ((ci->ci_flags & CPUF_AP) == 0) 585 i686_mtrr_init_first(); 586 mtrr_init_cpu(ci); 587 } 588 #endif 589 /* 590 * If we have FXSAVE/FXRESTOR, use them. 591 */ 592 if (cpu_feature[0] & CPUID_FXSR) { 593 lcr4(rcr4() | CR4_OSFXSR); 594 595 /* 596 * If we have SSE/SSE2, enable XMM exceptions. 597 */ 598 if (cpu_feature[0] & (CPUID_SSE|CPUID_SSE2)) 599 lcr4(rcr4() | CR4_OSXMMEXCPT); 600 } 601 602 #ifdef __x86_64__ 603 /* No user PGD mapped for this CPU yet */ 604 ci->ci_xen_current_user_pgd = 0; 605 #endif 606 607 atomic_or_32(&cpus_running, ci->ci_cpumask); 608 atomic_or_32(&ci->ci_flags, CPUF_RUNNING); 609 610 /* XXX: register vcpu_register_runstate_memory_area, and figure out how to make sure this VCPU is running ? */ 611 } 612 613 614 #ifdef MULTIPROCESSOR 615 616 void 617 cpu_boot_secondary_processors(void) 618 { 619 struct cpu_info *ci; 620 u_long i; 621 for (i = 0; i < maxcpus; i++) { 622 ci = cpu_lookup(i); 623 if (ci == NULL) 624 continue; 625 if (ci->ci_data.cpu_idlelwp == NULL) 626 continue; 627 if ((ci->ci_flags & CPUF_PRESENT) == 0) 628 continue; 629 if (ci->ci_flags & (CPUF_BSP|CPUF_SP|CPUF_PRIMARY)) 630 continue; 631 cpu_boot_secondary(ci); 632 } 633 634 x86_mp_online = true; 635 } 636 637 static void 638 cpu_init_idle_lwp(struct cpu_info *ci) 639 { 640 struct lwp *l = ci->ci_data.cpu_idlelwp; 641 struct pcb *pcb = lwp_getpcb(l); 642 643 pcb->pcb_cr0 = rcr0(); 644 } 645 646 void 647 cpu_init_idle_lwps(void) 648 { 649 struct cpu_info *ci; 650 u_long i; 651 652 for (i = 0; i < maxcpus; i++) { 653 ci = cpu_lookup(i); 654 if (ci == NULL) 655 continue; 656 if (ci->ci_data.cpu_idlelwp == NULL) 657 continue; 658 if ((ci->ci_flags & CPUF_PRESENT) == 0) 659 continue; 660 cpu_init_idle_lwp(ci); 661 } 662 } 663 664 static void 665 cpu_start_secondary(struct cpu_info *ci) 666 { 667 int i; 668 669 aprint_debug_dev(ci->ci_dev, "starting\n"); 670 671 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 672 673 if (CPU_STARTUP(ci, (vaddr_t) cpu_hatch) != 0) { 674 return; 675 } 676 677 /* 678 * wait for it to become ready 679 */ 680 for (i = 100000; (!(ci->ci_flags & CPUF_PRESENT)) && i > 0; i--) { 681 delay(10); 682 } 683 if ((ci->ci_flags & CPUF_PRESENT) == 0) { 684 aprint_error_dev(ci->ci_dev, "failed to become ready\n"); 685 #if defined(MPDEBUG) && defined(DDB) 686 printf("dropping into debugger; continue from here to resume boot\n"); 687 Debugger(); 688 #endif 689 } 690 691 CPU_START_CLEANUP(ci); 692 } 693 694 void 695 cpu_boot_secondary(struct cpu_info *ci) 696 { 697 int i; 698 atomic_or_32(&ci->ci_flags, CPUF_GO); 699 for (i = 100000; (!(ci->ci_flags & CPUF_RUNNING)) && i > 0; i--) { 700 delay(10); 701 } 702 if ((ci->ci_flags & CPUF_RUNNING) == 0) { 703 aprint_error_dev(ci->ci_dev, "CPU failed to start\n"); 704 #if defined(MPDEBUG) && defined(DDB) 705 printf("dropping into debugger; continue from here to resume boot\n"); 706 Debugger(); 707 #endif 708 } 709 } 710 711 /* 712 * APs end up here immediately after initialisation and VCPUOP_up in 713 * mp_cpu_start(). 714 * At this point, we are running in the idle pcb/idle stack of the new 715 * CPU. This function jumps to the idle loop and starts looking for 716 * work. 717 */ 718 extern void x86_64_tls_switch(struct lwp *); 719 void 720 cpu_hatch(void *v) 721 { 722 struct cpu_info *ci = (struct cpu_info *)v; 723 struct pcb *pcb; 724 int s, i; 725 726 /* Setup TLS and kernel GS/FS */ 727 cpu_init_msrs(ci, true); 728 cpu_init_idt(); 729 gdt_init_cpu(ci); 730 731 cpu_probe(ci); 732 733 atomic_or_32(&ci->ci_flags, CPUF_PRESENT); 734 735 while ((ci->ci_flags & CPUF_GO) == 0) { 736 /* Don't use delay, boot CPU may be patching the text. */ 737 for (i = 10000; i != 0; i--) 738 x86_pause(); 739 } 740 741 /* Because the text may have been patched in x86_patch(). */ 742 x86_flush(); 743 tlbflushg(); 744 745 KASSERT((ci->ci_flags & CPUF_RUNNING) == 0); 746 747 pcb = lwp_getpcb(curlwp); 748 pcb->pcb_cr3 = pmap_pdirpa(pmap_kernel(), 0); /* XXX: consider using pmap_load() ? */ 749 pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp); 750 751 xen_ipi_init(); 752 753 xen_initclocks(); 754 755 /* XXX: lapic_initclocks(); */ 756 757 #ifdef __x86_64__ 758 fpuinit(ci); 759 #endif 760 761 lldt(GSEL(GLDT_SEL, SEL_KPL)); 762 763 cpu_init(ci); 764 cpu_get_tsc_freq(ci); 765 766 s = splhigh(); 767 x86_enable_intr(); 768 splx(s); 769 #if 0 770 x86_errata(); 771 #endif 772 773 aprint_debug_dev(ci->ci_dev, "running\n"); 774 775 cpu_switchto(NULL, ci->ci_data.cpu_idlelwp, true); 776 777 panic("switch to idle_loop context returned!\n"); 778 /* NOTREACHED */ 779 } 780 781 #if defined(DDB) 782 783 #include <ddb/db_output.h> 784 #include <machine/db_machdep.h> 785 786 /* 787 * Dump CPU information from ddb. 788 */ 789 void 790 cpu_debug_dump(void) 791 { 792 struct cpu_info *ci; 793 CPU_INFO_ITERATOR cii; 794 795 db_printf("addr dev id flags ipis curlwp fpcurlwp\n"); 796 for (CPU_INFO_FOREACH(cii, ci)) { 797 db_printf("%p %s %ld %x %x %10p %10p\n", 798 ci, 799 ci->ci_dev == NULL ? "BOOT" : device_xname(ci->ci_dev), 800 (long)ci->ci_cpuid, 801 ci->ci_flags, ci->ci_ipis, 802 ci->ci_curlwp, 803 ci->ci_fpcurlwp); 804 } 805 } 806 #endif /* DDB */ 807 808 #endif /* MULTIPROCESSOR */ 809 810 extern void hypervisor_callback(void); 811 extern void failsafe_callback(void); 812 #ifdef __x86_64__ 813 typedef void (vector)(void); 814 extern vector Xsyscall, Xsyscall32; 815 #endif 816 817 /* 818 * Setup the "trampoline". On Xen, we setup nearly all cpu context 819 * outside a trampoline, so we prototype and call targetip like so: 820 * void targetip(struct cpu_info *); 821 */ 822 823 static void 824 gdt_prepframes(paddr_t *frames, vaddr_t base, uint32_t entries) 825 { 826 int i; 827 for (i = 0; i < roundup(entries, PAGE_SIZE) >> PAGE_SHIFT; i++) { 828 829 frames[i] = ((paddr_t) xpmap_ptetomach( 830 (pt_entry_t *) (base + (i << PAGE_SHIFT)))) 831 >> PAGE_SHIFT; 832 833 /* Mark Read-only */ 834 pmap_pte_clearbits(kvtopte(base + (i << PAGE_SHIFT)), 835 PG_RW); 836 } 837 } 838 839 #ifdef __x86_64__ 840 extern char *ldtstore; /* XXX: Xen MP todo */ 841 842 static void 843 xen_init_amd64_vcpuctxt(struct cpu_info *ci, 844 struct vcpu_guest_context *initctx, 845 void targetrip(struct cpu_info *)) 846 { 847 /* page frames to point at GDT */ 848 extern int gdt_size; 849 paddr_t frames[16]; 850 psize_t gdt_ents; 851 852 struct lwp *l; 853 struct pcb *pcb; 854 855 volatile struct vcpu_info *vci; 856 857 KASSERT(ci != NULL); 858 KASSERT(ci != &cpu_info_primary); 859 KASSERT(initctx != NULL); 860 KASSERT(targetrip != NULL); 861 862 memset(initctx, 0, sizeof *initctx); 863 864 gdt_ents = roundup(gdt_size, PAGE_SIZE) >> PAGE_SHIFT; /* XXX: re-investigate roundup(gdt_size... ) for gdt_ents. */ 865 KASSERT(gdt_ents <= 16); 866 867 gdt_prepframes(frames, (vaddr_t) ci->ci_gdt, gdt_ents); 868 869 /* XXX: The stuff in here is amd64 specific. move to mptramp.[Sc] ? */ 870 871 /* Initialise the vcpu context: We use idle_loop()'s pcb context. */ 872 873 l = ci->ci_data.cpu_idlelwp; 874 875 KASSERT(l != NULL); 876 pcb = lwp_getpcb(l); 877 KASSERT(pcb != NULL); 878 879 /* resume with interrupts off */ 880 vci = ci->ci_vcpu; 881 vci->evtchn_upcall_mask = 1; 882 xen_mb(); 883 884 /* resume in kernel-mode */ 885 initctx->flags = VGCF_in_kernel | VGCF_online; 886 887 /* Stack and entry points: 888 * We arrange for the stack frame for cpu_hatch() to 889 * appear as a callee frame of lwp_trampoline(). Being a 890 * leaf frame prevents trampling on any of the MD stack setup 891 * that x86/vm_machdep.c:cpu_lwp_fork() does for idle_loop() 892 */ 893 894 initctx->user_regs.rdi = (uint64_t) ci; /* targetrip(ci); */ 895 initctx->user_regs.rip = (vaddr_t) targetrip; 896 897 initctx->user_regs.cs = GSEL(GCODE_SEL, SEL_KPL); 898 899 initctx->user_regs.rflags = pcb->pcb_flags; 900 initctx->user_regs.rsp = pcb->pcb_rsp; 901 902 /* Data segments */ 903 initctx->user_regs.ss = GSEL(GDATA_SEL, SEL_KPL); 904 initctx->user_regs.es = GSEL(GDATA_SEL, SEL_KPL); 905 initctx->user_regs.ds = GSEL(GDATA_SEL, SEL_KPL); 906 907 /* GDT */ 908 memcpy(initctx->gdt_frames, frames, sizeof frames); 909 initctx->gdt_ents = gdt_ents; 910 911 /* LDT */ 912 initctx->ldt_base = (unsigned long) ldtstore; 913 initctx->ldt_ents = LDT_SIZE >> 3; 914 915 /* Kernel context state */ 916 initctx->kernel_ss = GSEL(GDATA_SEL, SEL_KPL); 917 initctx->kernel_sp = pcb->pcb_rsp0; 918 initctx->ctrlreg[0] = pcb->pcb_cr0; 919 initctx->ctrlreg[1] = 0; /* "resuming" from kernel - no User cr3. */ 920 initctx->ctrlreg[2] = pcb->pcb_cr2; /* XXX: */ 921 /* 922 * Use pmap_kernel() L4 PD directly, until we setup the 923 * per-cpu L4 PD in pmap_cpu_init_late() 924 */ 925 initctx->ctrlreg[3] = xpmap_ptom(pcb->pcb_cr3); 926 initctx->ctrlreg[4] = CR4_PAE | CR4_OSFXSR | CR4_OSXMMEXCPT; 927 928 929 /* Xen callbacks */ 930 initctx->event_callback_eip = (unsigned long) hypervisor_callback; 931 initctx->failsafe_callback_eip = (unsigned long) failsafe_callback; 932 initctx->syscall_callback_eip = (unsigned long) Xsyscall; 933 934 return; 935 } 936 #else /* i386 */ 937 extern union descriptor *ldt; 938 extern void Xsyscall(void); 939 940 static void 941 xen_init_i386_vcpuctxt(struct cpu_info *ci, 942 struct vcpu_guest_context *initctx, 943 void targeteip(struct cpu_info *)) 944 { 945 /* page frames to point at GDT */ 946 extern int gdt_size; 947 paddr_t frames[16]; 948 psize_t gdt_ents; 949 950 struct lwp *l; 951 struct pcb *pcb; 952 953 volatile struct vcpu_info *vci; 954 955 KASSERT(ci != NULL); 956 KASSERT(ci != &cpu_info_primary); 957 KASSERT(initctx != NULL); 958 KASSERT(targeteip != NULL); 959 960 memset(initctx, 0, sizeof *initctx); 961 962 gdt_ents = roundup(gdt_size, PAGE_SIZE) >> PAGE_SHIFT; /* XXX: re-investigate roundup(gdt_size... ) for gdt_ents. */ 963 KASSERT(gdt_ents <= 16); 964 965 gdt_prepframes(frames, (vaddr_t) ci->ci_gdt, gdt_ents); 966 967 /* 968 * Initialise the vcpu context: 969 * We use this cpu's idle_loop() pcb context. 970 */ 971 972 l = ci->ci_data.cpu_idlelwp; 973 974 KASSERT(l != NULL); 975 pcb = lwp_getpcb(l); 976 KASSERT(pcb != NULL); 977 978 /* resume with interrupts off */ 979 vci = ci->ci_vcpu; 980 vci->evtchn_upcall_mask = 1; 981 xen_mb(); 982 983 /* resume in kernel-mode */ 984 initctx->flags = VGCF_in_kernel | VGCF_online; 985 986 /* Stack frame setup for cpu_hatch(): 987 * We arrange for the stack frame for cpu_hatch() to 988 * appear as a callee frame of lwp_trampoline(). Being a 989 * leaf frame prevents trampling on any of the MD stack setup 990 * that x86/vm_machdep.c:cpu_lwp_fork() does for idle_loop() 991 */ 992 993 initctx->user_regs.esp = pcb->pcb_esp - 4; /* Leave word for 994 arg1 */ 995 { /* targeteip(ci); */ 996 uint32_t *arg = (uint32_t *) initctx->user_regs.esp; 997 arg[1] = (uint32_t) ci; /* arg1 */ 998 999 } 1000 1001 initctx->user_regs.eip = (vaddr_t) targeteip; 1002 initctx->user_regs.cs = GSEL(GCODE_SEL, SEL_KPL); 1003 initctx->user_regs.eflags |= pcb->pcb_iopl; 1004 1005 /* Data segments */ 1006 initctx->user_regs.ss = GSEL(GDATA_SEL, SEL_KPL); 1007 initctx->user_regs.es = GSEL(GDATA_SEL, SEL_KPL); 1008 initctx->user_regs.ds = GSEL(GDATA_SEL, SEL_KPL); 1009 initctx->user_regs.fs = GSEL(GDATA_SEL, SEL_KPL); 1010 1011 /* GDT */ 1012 memcpy(initctx->gdt_frames, frames, sizeof frames); 1013 initctx->gdt_ents = gdt_ents; 1014 1015 /* LDT */ 1016 initctx->ldt_base = (unsigned long) ldt; 1017 initctx->ldt_ents = NLDT; 1018 1019 /* Kernel context state */ 1020 initctx->kernel_ss = GSEL(GDATA_SEL, SEL_KPL); 1021 initctx->kernel_sp = pcb->pcb_esp0; 1022 initctx->ctrlreg[0] = pcb->pcb_cr0; 1023 initctx->ctrlreg[1] = 0; /* "resuming" from kernel - no User cr3. */ 1024 initctx->ctrlreg[2] = pcb->pcb_cr2; /* XXX: */ 1025 /* 1026 * Use pmap_kernel() L4 PD directly, until we setup the 1027 * per-cpu L4 PD in pmap_cpu_init_late() 1028 */ 1029 initctx->ctrlreg[3] = xpmap_ptom(pcb->pcb_cr3); 1030 initctx->ctrlreg[4] = /* CR4_PAE | */CR4_OSFXSR | CR4_OSXMMEXCPT; 1031 1032 1033 /* Xen callbacks */ 1034 initctx->event_callback_eip = (unsigned long) hypervisor_callback; 1035 initctx->event_callback_cs = GSEL(GCODE_SEL, SEL_KPL); 1036 initctx->failsafe_callback_eip = (unsigned long) failsafe_callback; 1037 initctx->failsafe_callback_cs = GSEL(GCODE_SEL, SEL_KPL); 1038 1039 return; 1040 } 1041 #endif /* __x86_64__ */ 1042 1043 int 1044 mp_cpu_start(struct cpu_info *ci, vaddr_t target) 1045 { 1046 1047 int hyperror; 1048 struct vcpu_guest_context vcpuctx; 1049 1050 KASSERT(ci != NULL); 1051 KASSERT(ci != &cpu_info_primary); 1052 KASSERT(ci->ci_flags & CPUF_AP); 1053 1054 #ifdef __x86_64__ 1055 xen_init_amd64_vcpuctxt(ci, &vcpuctx, (void (*)(struct cpu_info *))target); 1056 #else /* i386 */ 1057 xen_init_i386_vcpuctxt(ci, &vcpuctx, (void (*)(struct cpu_info *))target); 1058 #endif /* __x86_64__ */ 1059 1060 /* Initialise the given vcpu to execute cpu_hatch(ci); */ 1061 if ((hyperror = HYPERVISOR_vcpu_op(VCPUOP_initialise, ci->ci_cpuid, &vcpuctx))) { 1062 aprint_error(": context initialisation failed. errno = %d\n", hyperror); 1063 return hyperror; 1064 } 1065 1066 /* Start it up */ 1067 1068 /* First bring it down - the Xen documentation conveniently omits this slight detail. */ 1069 if ((hyperror = HYPERVISOR_vcpu_op(VCPUOP_down, ci->ci_cpuid, NULL))) { 1070 aprint_error(": VCPUOP_down hypervisor command failed. errno = %d\n", hyperror); 1071 return hyperror; 1072 } 1073 1074 if ((hyperror = HYPERVISOR_vcpu_op(VCPUOP_up, ci->ci_cpuid, NULL))) { 1075 aprint_error(": VCPUOP_up hypervisor command failed. errno = %d\n", hyperror); 1076 return hyperror; 1077 } 1078 1079 if (!vcpu_is_up(ci)) { 1080 aprint_error(": did not come up\n"); 1081 return -1; 1082 } 1083 1084 return 0; 1085 } 1086 1087 void 1088 mp_cpu_start_cleanup(struct cpu_info *ci) 1089 { 1090 #if 0 1091 /* 1092 * Ensure the NVRAM reset byte contains something vaguely sane. 1093 */ 1094 1095 outb(IO_RTC, NVRAM_RESET); 1096 outb(IO_RTC+1, NVRAM_RESET_RST); 1097 #endif 1098 if (vcpu_is_up(ci)) { 1099 aprint_debug_dev(ci->ci_dev, "is started.\n"); 1100 } 1101 else { 1102 aprint_error_dev(ci->ci_dev, "did not start up.\n"); 1103 } 1104 1105 } 1106 1107 void 1108 cpu_init_msrs(struct cpu_info *ci, bool full) 1109 { 1110 #ifdef __x86_64__ 1111 if (full) { 1112 HYPERVISOR_set_segment_base (SEGBASE_FS, 0); 1113 HYPERVISOR_set_segment_base (SEGBASE_GS_KERNEL, (uint64_t) ci); 1114 HYPERVISOR_set_segment_base (SEGBASE_GS_USER, 0); 1115 } 1116 #endif /* __x86_64__ */ 1117 1118 if (cpu_feature[2] & CPUID_NOX) 1119 wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_NXE); 1120 1121 } 1122 1123 void 1124 cpu_offline_md(void) 1125 { 1126 int s; 1127 1128 s = splhigh(); 1129 #ifdef __i386__ 1130 npxsave_cpu(true); 1131 #else 1132 fpusave_cpu(true); 1133 #endif 1134 splx(s); 1135 } 1136 1137 #if 0 1138 /* XXX joerg restructure and restart CPUs individually */ 1139 static bool 1140 cpu_suspend(device_t dv, const pmf_qual_t *qual) 1141 { 1142 struct cpu_softc *sc = device_private(dv); 1143 struct cpu_info *ci = sc->sc_info; 1144 int err; 1145 1146 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1147 return true; 1148 1149 cpufreq_suspend(ci); 1150 1151 if ((ci->ci_flags & CPUF_PRIMARY) != 0) 1152 return true; 1153 1154 if (ci->ci_data.cpu_idlelwp == NULL) 1155 return true; 1156 1157 sc->sc_wasonline = !(ci->ci_schedstate.spc_flags & SPCF_OFFLINE); 1158 1159 if (sc->sc_wasonline) { 1160 mutex_enter(&cpu_lock); 1161 err = cpu_setstate(ci, false); 1162 mutex_exit(&cpu_lock); 1163 1164 if (err != 0) 1165 return false; 1166 } 1167 1168 return true; 1169 } 1170 1171 static bool 1172 cpu_resume(device_t dv, const pmf_qual_t *qual) 1173 { 1174 struct cpu_softc *sc = device_private(dv); 1175 struct cpu_info *ci = sc->sc_info; 1176 int err = 0; 1177 1178 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1179 return true; 1180 1181 if ((ci->ci_flags & CPUF_PRIMARY) != 0) 1182 goto out; 1183 1184 if (ci->ci_data.cpu_idlelwp == NULL) 1185 goto out; 1186 1187 if (sc->sc_wasonline) { 1188 mutex_enter(&cpu_lock); 1189 err = cpu_setstate(ci, true); 1190 mutex_exit(&cpu_lock); 1191 } 1192 1193 out: 1194 if (err != 0) 1195 return false; 1196 1197 cpufreq_resume(ci); 1198 1199 return true; 1200 } 1201 #endif 1202 1203 void 1204 cpu_get_tsc_freq(struct cpu_info *ci) 1205 { 1206 uint32_t vcpu_tversion; 1207 const volatile vcpu_time_info_t *tinfo = &ci->ci_vcpu->time; 1208 1209 vcpu_tversion = tinfo->version; 1210 while (tinfo->version == vcpu_tversion); /* Wait for a time update. XXX: timeout ? */ 1211 1212 uint64_t freq = 1000000000ULL << 32; 1213 freq = freq / (uint64_t)tinfo->tsc_to_system_mul; 1214 if ( tinfo->tsc_shift < 0 ) 1215 freq = freq << -tinfo->tsc_shift; 1216 else 1217 freq = freq >> tinfo->tsc_shift; 1218 ci->ci_data.cpu_cc_freq = freq; 1219 } 1220 1221 void 1222 x86_cpu_idle_xen(void) 1223 { 1224 struct cpu_info *ci = curcpu(); 1225 1226 KASSERT(ci->ci_ilevel == IPL_NONE); 1227 1228 x86_disable_intr(); 1229 if (!__predict_false(ci->ci_want_resched)) { 1230 idle_block(); 1231 } else { 1232 x86_enable_intr(); 1233 } 1234 } 1235 1236 /* 1237 * Loads pmap for the current CPU. 1238 */ 1239 void 1240 cpu_load_pmap(struct pmap *pmap) 1241 { 1242 #ifdef i386 1243 #ifdef PAE 1244 int i, s; 1245 struct cpu_info *ci; 1246 1247 s = splvm(); /* just to be safe */ 1248 xpq_queue_lock(); 1249 ci = curcpu(); 1250 paddr_t l3_pd = xpmap_ptom_masked(ci->ci_pae_l3_pdirpa); 1251 /* don't update the kernel L3 slot */ 1252 for (i = 0 ; i < PDP_SIZE - 1; i++) { 1253 xpq_queue_pte_update(l3_pd + i * sizeof(pd_entry_t), 1254 xpmap_ptom(pmap->pm_pdirpa[i]) | PG_V); 1255 } 1256 xpq_queue_unlock(); 1257 splx(s); 1258 tlbflush(); 1259 #else /* PAE */ 1260 lcr3(pmap_pdirpa(pmap, 0)); 1261 #endif /* PAE */ 1262 #endif /* i386 */ 1263 1264 #ifdef __x86_64__ 1265 int i, s; 1266 pd_entry_t *old_pgd, *new_pgd; 1267 paddr_t addr; 1268 struct cpu_info *ci; 1269 1270 /* kernel pmap always in cr3 and should never go in user cr3 */ 1271 if (pmap_pdirpa(pmap, 0) != pmap_pdirpa(pmap_kernel(), 0)) { 1272 ci = curcpu(); 1273 /* 1274 * Map user space address in kernel space and load 1275 * user cr3 1276 */ 1277 s = splvm(); 1278 new_pgd = pmap->pm_pdir; 1279 old_pgd = pmap_kernel()->pm_pdir; 1280 addr = xpmap_ptom(pmap_pdirpa(pmap_kernel(), 0)); 1281 for (i = 0; i < PDIR_SLOT_PTE; 1282 i++, addr += sizeof(pd_entry_t)) { 1283 if ((new_pgd[i] & PG_V) || (old_pgd[i] & PG_V)) 1284 xpq_queue_pte_update(addr, new_pgd[i]); 1285 } 1286 xen_set_user_pgd(pmap_pdirpa(pmap, 0)); 1287 ci->ci_xen_current_user_pgd = pmap_pdirpa(pmap, 0); 1288 tlbflush(); 1289 splx(s); 1290 } 1291 #endif /* __x86_64__ */ 1292 } 1293 1294 /* 1295 * Notify all other cpus to halt. 1296 */ 1297 1298 void 1299 cpu_broadcast_halt(void) 1300 { 1301 xen_broadcast_ipi(XEN_IPI_HALT); 1302 } 1303 1304 /* 1305 * Send a dummy ipi to a cpu. 1306 */ 1307 1308 void 1309 cpu_kick(struct cpu_info *ci) 1310 { 1311 (void)xen_send_ipi(ci, XEN_IPI_KICK); 1312 } 1313
Indexes created Wed Sep 24 05:09:52 GMT 2025