cpu.c revision 1.67
1 /* $NetBSD: cpu.c,v 1.67 2011/10/06 06:56:30 mrg Exp $ */ 2 /* NetBSD: cpu.c,v 1.18 2004/02/20 17:35:01 yamt Exp */ 3 4 /*- 5 * Copyright (c) 2000 The NetBSD Foundation, Inc. 6 * Copyright (c) 2002, 2006, 2007 YAMAMOTO Takashi, 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to The NetBSD Foundation 10 * by RedBack Networks Inc. 11 * 12 * Author: Bill Sommerfeld 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * Copyright (c) 1999 Stefan Grefen 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 56 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.67 2011/10/06 06:56:30 mrg Exp $"); 70 71 #include "opt_ddb.h" 72 #include "opt_multiprocessor.h" 73 #include "opt_mpbios.h" /* for MPDEBUG */ 74 #include "opt_mtrr.h" 75 #include "opt_xen.h" 76 77 #include "lapic.h" 78 #include "ioapic.h" 79 80 #include <sys/param.h> 81 #include <sys/proc.h> 82 #include <sys/systm.h> 83 #include <sys/device.h> 84 #include <sys/kmem.h> 85 #include <sys/cpu.h> 86 #include <sys/cpufreq.h> 87 #include <sys/atomic.h> 88 #include <sys/reboot.h> 89 #include <sys/idle.h> 90 91 #include <uvm/uvm.h> 92 93 #include <machine/cpufunc.h> 94 #include <machine/cpuvar.h> 95 #include <machine/pmap.h> 96 #include <machine/vmparam.h> 97 #include <machine/mpbiosvar.h> 98 #include <machine/pcb.h> 99 #include <machine/specialreg.h> 100 #include <machine/segments.h> 101 #include <machine/gdt.h> 102 #include <machine/mtrr.h> 103 #include <machine/pio.h> 104 105 #ifdef i386 106 #include <machine/npx.h> 107 #else 108 #include <machine/fpu.h> 109 #endif 110 111 #include <xen/xen.h> 112 #include <xen/xen3-public/vcpu.h> 113 #include <xen/vcpuvar.h> 114 115 #if NLAPIC > 0 116 #include <machine/apicvar.h> 117 #include <machine/i82489reg.h> 118 #include <machine/i82489var.h> 119 #endif 120 121 #include <dev/ic/mc146818reg.h> 122 #include <dev/isa/isareg.h> 123 124 #if MAXCPUS > 32 125 #error cpu_info contains 32bit bitmasks 126 #endif 127 128 static int cpu_match(device_t, cfdata_t, void *); 129 static void cpu_attach(device_t, device_t, void *); 130 static void cpu_defer(device_t); 131 static int cpu_rescan(device_t, const char *, const int *); 132 static void cpu_childdetached(device_t, device_t); 133 static int vcpu_match(device_t, cfdata_t, void *); 134 static void vcpu_attach(device_t, device_t, void *); 135 static void cpu_attach_common(device_t, device_t, void *); 136 void cpu_offline_md(void); 137 138 struct cpu_softc { 139 device_t sc_dev; /* device tree glue */ 140 struct cpu_info *sc_info; /* pointer to CPU info */ 141 bool sc_wasonline; 142 }; 143 144 int mp_cpu_start(struct cpu_info *, vaddr_t); 145 void mp_cpu_start_cleanup(struct cpu_info *); 146 const struct cpu_functions mp_cpu_funcs = { mp_cpu_start, NULL, 147 mp_cpu_start_cleanup }; 148 149 CFATTACH_DECL2_NEW(cpu, sizeof(struct cpu_softc), 150 cpu_match, cpu_attach, NULL, NULL, cpu_rescan, cpu_childdetached); 151 152 CFATTACH_DECL_NEW(vcpu, sizeof(struct cpu_softc), 153 vcpu_match, vcpu_attach, NULL, NULL); 154 155 /* 156 * Statically-allocated CPU info for the primary CPU (or the only 157 * CPU, on uniprocessors). The CPU info list is initialized to 158 * point at it. 159 */ 160 #ifdef TRAPLOG 161 #include <machine/tlog.h> 162 struct tlog tlog_primary; 163 #endif 164 struct cpu_info cpu_info_primary __aligned(CACHE_LINE_SIZE) = { 165 .ci_dev = 0, 166 .ci_self = &cpu_info_primary, 167 .ci_idepth = -1, 168 .ci_curlwp = &lwp0, 169 .ci_curldt = -1, 170 .ci_cpumask = 1, 171 #ifdef TRAPLOG 172 .ci_tlog = &tlog_primary, 173 #endif 174 175 }; 176 struct cpu_info phycpu_info_primary __aligned(CACHE_LINE_SIZE) = { 177 .ci_dev = 0, 178 .ci_self = &phycpu_info_primary, 179 }; 180 181 struct cpu_info *cpu_info_list = &cpu_info_primary; 182 struct cpu_info *phycpu_info_list = &phycpu_info_primary; 183 184 uint32_t cpus_attached = 1; 185 uint32_t cpus_running = 1; 186 187 uint32_t phycpus_attached = 0; 188 uint32_t phycpus_running = 0; 189 190 uint32_t cpu_feature[5]; /* X86 CPUID feature bits 191 * [0] basic features %edx 192 * [1] basic features %ecx 193 * [2] extended features %edx 194 * [3] extended features %ecx 195 * [4] VIA padlock features 196 */ 197 198 bool x86_mp_online; 199 paddr_t mp_trampoline_paddr = MP_TRAMPOLINE; 200 201 #if defined(MULTIPROCESSOR) 202 void cpu_hatch(void *); 203 static void cpu_boot_secondary(struct cpu_info *ci); 204 static void cpu_start_secondary(struct cpu_info *ci); 205 #endif /* MULTIPROCESSOR */ 206 207 static int 208 cpu_match(device_t parent, cfdata_t match, void *aux) 209 { 210 211 return 1; 212 } 213 214 static void 215 cpu_attach(device_t parent, device_t self, void *aux) 216 { 217 struct cpu_softc *sc = device_private(self); 218 struct cpu_attach_args *caa = aux; 219 struct cpu_info *ci; 220 uintptr_t ptr; 221 static int nphycpu = 0; 222 223 sc->sc_dev = self; 224 225 if (phycpus_attached == ~0) { 226 aprint_error(": increase MAXCPUS\n"); 227 return; 228 } 229 230 /* 231 * If we're an Application Processor, allocate a cpu_info 232 * If we're the first attached CPU use the primary cpu_info, 233 * otherwise allocate a new one 234 */ 235 aprint_naive("\n"); 236 aprint_normal("\n"); 237 if (nphycpu > 0) { 238 struct cpu_info *tmp; 239 ptr = (uintptr_t)kmem_zalloc(sizeof(*ci) + CACHE_LINE_SIZE - 1, 240 KM_SLEEP); 241 ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE); 242 ci->ci_curldt = -1; 243 244 tmp = phycpu_info_list; 245 while (tmp->ci_next) 246 tmp = tmp->ci_next; 247 248 tmp->ci_next = ci; 249 } else { 250 ci = &phycpu_info_primary; 251 } 252 253 ci->ci_self = ci; 254 sc->sc_info = ci; 255 256 ci->ci_dev = self; 257 ci->ci_acpiid = caa->cpu_id; 258 ci->ci_cpuid = caa->cpu_number; 259 ci->ci_vcpu = NULL; 260 ci->ci_index = nphycpu++; 261 ci->ci_cpumask = (1 << cpu_index(ci)); 262 263 atomic_or_32(&phycpus_attached, ci->ci_cpumask); 264 265 if (!pmf_device_register(self, NULL, NULL)) 266 aprint_error_dev(self, "couldn't establish power handler\n"); 267 268 (void)config_defer(self, cpu_defer); 269 } 270 271 static void 272 cpu_defer(device_t self) 273 { 274 cpu_rescan(self, NULL, NULL); 275 } 276 277 static int 278 cpu_rescan(device_t self, const char *ifattr, const int *locators) 279 { 280 struct cpu_softc *sc = device_private(self); 281 struct cpufeature_attach_args cfaa; 282 struct cpu_info *ci = sc->sc_info; 283 284 memset(&cfaa, 0, sizeof(cfaa)); 285 cfaa.ci = ci; 286 287 if (ifattr_match(ifattr, "cpufeaturebus")) { 288 289 if (ci->ci_frequency == NULL) { 290 cfaa.name = "frequency"; 291 ci->ci_frequency = config_found_ia(self, 292 "cpufeaturebus", &cfaa, NULL); 293 } 294 } 295 296 return 0; 297 } 298 299 static void 300 cpu_childdetached(device_t self, device_t child) 301 { 302 struct cpu_softc *sc = device_private(self); 303 struct cpu_info *ci = sc->sc_info; 304 305 if (ci->ci_frequency == child) 306 ci->ci_frequency = NULL; 307 } 308 309 static int 310 vcpu_match(device_t parent, cfdata_t match, void *aux) 311 { 312 struct vcpu_attach_args *vcaa = aux; 313 struct vcpu_runstate_info vcr; 314 int error; 315 316 if (strcmp(vcaa->vcaa_name, match->cf_name) == 0) { 317 error = HYPERVISOR_vcpu_op(VCPUOP_get_runstate_info, 318 vcaa->vcaa_caa.cpu_number, 319 &vcr); 320 switch (error) { 321 case 0: 322 return 1; 323 case -ENOENT: 324 return 0; 325 default: 326 panic("Unknown hypervisor error %d returned on vcpu runstate probe\n", error); 327 } 328 } 329 330 return 0; 331 } 332 333 static void 334 vcpu_attach(device_t parent, device_t self, void *aux) 335 { 336 struct vcpu_attach_args *vcaa = aux; 337 338 KASSERT(vcaa->vcaa_caa.cpu_func == NULL); 339 vcaa->vcaa_caa.cpu_func = &mp_cpu_funcs; 340 cpu_attach_common(parent, self, &vcaa->vcaa_caa); 341 342 if (!pmf_device_register(self, NULL, NULL)) 343 aprint_error_dev(self, "couldn't establish power handler\n"); 344 } 345 346 static int 347 vcpu_is_up(struct cpu_info *ci) 348 { 349 KASSERT(ci != NULL); 350 return HYPERVISOR_vcpu_op(VCPUOP_is_up, ci->ci_cpuid, NULL); 351 } 352 353 static void 354 cpu_vm_init(struct cpu_info *ci) 355 { 356 int ncolors = 2, i; 357 358 for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) { 359 struct x86_cache_info *cai; 360 int tcolors; 361 362 cai = &ci->ci_cinfo[i]; 363 364 tcolors = atop(cai->cai_totalsize); 365 switch(cai->cai_associativity) { 366 case 0xff: 367 tcolors = 1; /* fully associative */ 368 break; 369 case 0: 370 case 1: 371 break; 372 default: 373 tcolors /= cai->cai_associativity; 374 } 375 ncolors = max(ncolors, tcolors); 376 } 377 378 /* 379 * Knowing the size of the largest cache on this CPU, potentially 380 * re-color our pages. 381 */ 382 aprint_debug_dev(ci->ci_dev, "%d page colors\n", ncolors); 383 uvm_page_recolor(ncolors); 384 } 385 386 static void 387 cpu_attach_common(device_t parent, device_t self, void *aux) 388 { 389 struct cpu_softc *sc = device_private(self); 390 struct cpu_attach_args *caa = aux; 391 struct cpu_info *ci; 392 uintptr_t ptr; 393 int cpunum = caa->cpu_number; 394 static bool again = false; 395 396 sc->sc_dev = self; 397 398 /* 399 * If we're an Application Processor, allocate a cpu_info 400 * structure, otherwise use the primary's. 401 */ 402 if (caa->cpu_role == CPU_ROLE_AP) { 403 aprint_naive(": Application Processor\n"); 404 ptr = (uintptr_t)kmem_alloc(sizeof(*ci) + CACHE_LINE_SIZE - 1, 405 KM_SLEEP); 406 ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE); 407 memset(ci, 0, sizeof(*ci)); 408 #ifdef TRAPLOG 409 ci->ci_tlog_base = kmem_zalloc(sizeof(struct tlog), KM_SLEEP); 410 #endif 411 } else { 412 aprint_naive(": %s Processor\n", 413 caa->cpu_role == CPU_ROLE_SP ? "Single" : "Boot"); 414 ci = &cpu_info_primary; 415 } 416 417 ci->ci_self = ci; 418 sc->sc_info = ci; 419 ci->ci_dev = self; 420 ci->ci_cpuid = cpunum; 421 422 KASSERT(HYPERVISOR_shared_info != NULL); 423 ci->ci_vcpu = &HYPERVISOR_shared_info->vcpu_info[cpunum]; 424 425 KASSERT(ci->ci_func == 0); 426 ci->ci_func = caa->cpu_func; 427 428 /* Must be called before mi_cpu_attach(). */ 429 cpu_vm_init(ci); 430 431 if (caa->cpu_role == CPU_ROLE_AP) { 432 int error; 433 434 error = mi_cpu_attach(ci); 435 436 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 437 if (error != 0) { 438 aprint_normal("\n"); 439 aprint_error_dev(self, 440 "mi_cpu_attach failed with %d\n", error); 441 return; 442 } 443 444 } else { 445 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 446 } 447 448 ci->ci_cpumask = (1 << cpu_index(ci)); 449 pmap_reference(pmap_kernel()); 450 ci->ci_pmap = pmap_kernel(); 451 ci->ci_tlbstate = TLBSTATE_STALE; 452 453 /* 454 * Boot processor may not be attached first, but the below 455 * must be done to allow booting other processors. 456 */ 457 if (!again) { 458 atomic_or_32(&ci->ci_flags, CPUF_PRESENT | CPUF_PRIMARY); 459 /* Basic init. */ 460 cpu_intr_init(ci); 461 cpu_get_tsc_freq(ci); 462 cpu_init(ci); 463 pmap_cpu_init_late(ci); /* XXX: cosmetic */ 464 465 /* Every processor needs to init it's own ipi h/w (similar to lapic) */ 466 xen_ipi_init(); 467 /* XXX: clock_init() */ 468 469 /* Make sure DELAY() is initialized. */ 470 DELAY(1); 471 again = true; 472 } 473 474 /* further PCB init done later. */ 475 476 switch (caa->cpu_role) { 477 case CPU_ROLE_SP: 478 atomic_or_32(&ci->ci_flags, CPUF_SP); 479 cpu_identify(ci); 480 #if 0 481 x86_errata(); 482 #endif 483 x86_cpu_idle_init(); 484 485 break; 486 487 case CPU_ROLE_BP: 488 atomic_or_32(&ci->ci_flags, CPUF_BSP); 489 cpu_identify(ci); 490 cpu_init(ci); 491 #if 0 492 x86_errata(); 493 #endif 494 x86_cpu_idle_init(); 495 496 break; 497 498 case CPU_ROLE_AP: 499 atomic_or_32(&ci->ci_flags, CPUF_AP); 500 501 /* 502 * report on an AP 503 */ 504 505 #if defined(MULTIPROCESSOR) 506 /* interrupt handler stack */ 507 cpu_intr_init(ci); 508 509 /* Setup per-cpu memory for gdt */ 510 gdt_alloc_cpu(ci); 511 512 pmap_cpu_init_late(ci); 513 cpu_start_secondary(ci); 514 515 if (ci->ci_flags & CPUF_PRESENT) { 516 struct cpu_info *tmp; 517 518 cpu_identify(ci); 519 tmp = cpu_info_list; 520 while (tmp->ci_next) 521 tmp = tmp->ci_next; 522 523 tmp->ci_next = ci; 524 } 525 #else 526 aprint_error(": not started\n"); 527 #endif 528 break; 529 530 default: 531 aprint_normal("\n"); 532 panic("unknown processor type??\n"); 533 } 534 535 pat_init(ci); 536 atomic_or_32(&cpus_attached, ci->ci_cpumask); 537 538 #if 0 539 if (!pmf_device_register(self, cpu_suspend, cpu_resume)) 540 aprint_error_dev(self, "couldn't establish power handler\n"); 541 #endif 542 543 #ifdef MPVERBOSE 544 if (mp_verbose) { 545 struct lwp *l = ci->ci_data.cpu_idlelwp; 546 struct pcb *pcb = lwp_getpcb(l); 547 548 aprint_verbose_dev(self, 549 "idle lwp at %p, idle sp at 0x%p\n", 550 l, 551 #ifdef i386 552 (void *)pcb->pcb_esp 553 #else /* i386 */ 554 (void *)pcb->pcb_rsp 555 #endif /* i386 */ 556 ); 557 558 } 559 #endif /* MPVERBOSE */ 560 } 561 562 /* 563 * Initialize the processor appropriately. 564 */ 565 566 void 567 cpu_init(struct cpu_info *ci) 568 { 569 570 /* 571 * On a P6 or above, enable global TLB caching if the 572 * hardware supports it. 573 */ 574 if (cpu_feature[0] & CPUID_PGE) 575 lcr4(rcr4() | CR4_PGE); /* enable global TLB caching */ 576 577 #ifdef XXXMTRR 578 /* 579 * On a P6 or above, initialize MTRR's if the hardware supports them. 580 */ 581 if (cpu_feature[0] & CPUID_MTRR) { 582 if ((ci->ci_flags & CPUF_AP) == 0) 583 i686_mtrr_init_first(); 584 mtrr_init_cpu(ci); 585 } 586 #endif 587 /* 588 * If we have FXSAVE/FXRESTOR, use them. 589 */ 590 if (cpu_feature[0] & CPUID_FXSR) { 591 lcr4(rcr4() | CR4_OSFXSR); 592 593 /* 594 * If we have SSE/SSE2, enable XMM exceptions. 595 */ 596 if (cpu_feature[0] & (CPUID_SSE|CPUID_SSE2)) 597 lcr4(rcr4() | CR4_OSXMMEXCPT); 598 } 599 600 #ifdef __x86_64__ 601 /* No user PGD mapped for this CPU yet */ 602 ci->ci_xen_current_user_pgd = 0; 603 #endif 604 605 atomic_or_32(&cpus_running, ci->ci_cpumask); 606 atomic_or_32(&ci->ci_flags, CPUF_RUNNING); 607 608 /* XXX: register vcpu_register_runstate_memory_area, and figure out how to make sure this VCPU is running ? */ 609 } 610 611 612 #ifdef MULTIPROCESSOR 613 614 void 615 cpu_boot_secondary_processors(void) 616 { 617 struct cpu_info *ci; 618 u_long i; 619 for (i = 0; i < maxcpus; i++) { 620 ci = cpu_lookup(i); 621 if (ci == NULL) 622 continue; 623 if (ci->ci_data.cpu_idlelwp == NULL) 624 continue; 625 if ((ci->ci_flags & CPUF_PRESENT) == 0) 626 continue; 627 if (ci->ci_flags & (CPUF_BSP|CPUF_SP|CPUF_PRIMARY)) 628 continue; 629 cpu_boot_secondary(ci); 630 } 631 632 x86_mp_online = true; 633 } 634 635 static void 636 cpu_init_idle_lwp(struct cpu_info *ci) 637 { 638 struct lwp *l = ci->ci_data.cpu_idlelwp; 639 struct pcb *pcb = lwp_getpcb(l); 640 641 pcb->pcb_cr0 = rcr0(); 642 } 643 644 void 645 cpu_init_idle_lwps(void) 646 { 647 struct cpu_info *ci; 648 u_long i; 649 650 for (i = 0; i < maxcpus; i++) { 651 ci = cpu_lookup(i); 652 if (ci == NULL) 653 continue; 654 if (ci->ci_data.cpu_idlelwp == NULL) 655 continue; 656 if ((ci->ci_flags & CPUF_PRESENT) == 0) 657 continue; 658 cpu_init_idle_lwp(ci); 659 } 660 } 661 662 static void 663 cpu_start_secondary(struct cpu_info *ci) 664 { 665 int i; 666 667 aprint_debug_dev(ci->ci_dev, "starting\n"); 668 669 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 670 671 if (CPU_STARTUP(ci, (vaddr_t) cpu_hatch) != 0) { 672 return; 673 } 674 675 /* 676 * wait for it to become ready 677 */ 678 for (i = 100000; (!(ci->ci_flags & CPUF_PRESENT)) && i > 0; i--) { 679 delay(10); 680 } 681 if ((ci->ci_flags & CPUF_PRESENT) == 0) { 682 aprint_error_dev(ci->ci_dev, "failed to become ready\n"); 683 #if defined(MPDEBUG) && defined(DDB) 684 printf("dropping into debugger; continue from here to resume boot\n"); 685 Debugger(); 686 #endif 687 } 688 689 CPU_START_CLEANUP(ci); 690 } 691 692 void 693 cpu_boot_secondary(struct cpu_info *ci) 694 { 695 int i; 696 atomic_or_32(&ci->ci_flags, CPUF_GO); 697 for (i = 100000; (!(ci->ci_flags & CPUF_RUNNING)) && i > 0; i--) { 698 delay(10); 699 } 700 if ((ci->ci_flags & CPUF_RUNNING) == 0) { 701 aprint_error_dev(ci->ci_dev, "CPU failed to start\n"); 702 #if defined(MPDEBUG) && defined(DDB) 703 printf("dropping into debugger; continue from here to resume boot\n"); 704 Debugger(); 705 #endif 706 } 707 } 708 709 /* 710 * APs end up here immediately after initialisation and VCPUOP_up in 711 * mp_cpu_start(). 712 * At this point, we are running in the idle pcb/idle stack of the new 713 * CPU. This function jumps to the idle loop and starts looking for 714 * work. 715 */ 716 extern void x86_64_tls_switch(struct lwp *); 717 void 718 cpu_hatch(void *v) 719 { 720 struct cpu_info *ci = (struct cpu_info *)v; 721 struct pcb *pcb; 722 int s, i; 723 724 /* Setup TLS and kernel GS/FS */ 725 cpu_init_msrs(ci, true); 726 cpu_init_idt(); 727 gdt_init_cpu(ci); 728 729 cpu_probe(ci); 730 731 atomic_or_32(&ci->ci_flags, CPUF_PRESENT); 732 733 while ((ci->ci_flags & CPUF_GO) == 0) { 734 /* Don't use delay, boot CPU may be patching the text. */ 735 for (i = 10000; i != 0; i--) 736 x86_pause(); 737 } 738 739 /* Because the text may have been patched in x86_patch(). */ 740 x86_flush(); 741 tlbflushg(); 742 743 KASSERT((ci->ci_flags & CPUF_RUNNING) == 0); 744 745 pcb = lwp_getpcb(curlwp); 746 pcb->pcb_cr3 = pmap_pdirpa(pmap_kernel(), 0); /* XXX: consider using pmap_load() ? */ 747 pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp); 748 749 xen_ipi_init(); 750 751 xen_initclocks(); 752 753 /* XXX: lapic_initclocks(); */ 754 755 #ifdef __x86_64__ 756 fpuinit(ci); 757 #endif 758 759 lldt(GSEL(GLDT_SEL, SEL_KPL)); 760 761 cpu_init(ci); 762 cpu_get_tsc_freq(ci); 763 764 s = splhigh(); 765 x86_enable_intr(); 766 splx(s); 767 #if 0 768 x86_errata(); 769 #endif 770 771 aprint_debug_dev(ci->ci_dev, "running\n"); 772 773 cpu_switchto(NULL, ci->ci_data.cpu_idlelwp, true); 774 775 panic("switch to idle_loop context returned!\n"); 776 /* NOTREACHED */ 777 } 778 779 #if defined(DDB) 780 781 #include <ddb/db_output.h> 782 #include <machine/db_machdep.h> 783 784 /* 785 * Dump CPU information from ddb. 786 */ 787 void 788 cpu_debug_dump(void) 789 { 790 struct cpu_info *ci; 791 CPU_INFO_ITERATOR cii; 792 793 db_printf("addr dev id flags ipis curlwp fpcurlwp\n"); 794 for (CPU_INFO_FOREACH(cii, ci)) { 795 db_printf("%p %s %ld %x %x %10p %10p\n", 796 ci, 797 ci->ci_dev == NULL ? "BOOT" : device_xname(ci->ci_dev), 798 (long)ci->ci_cpuid, 799 ci->ci_flags, ci->ci_ipis, 800 ci->ci_curlwp, 801 ci->ci_fpcurlwp); 802 } 803 } 804 #endif /* DDB */ 805 806 #endif /* MULTIPROCESSOR */ 807 808 extern void hypervisor_callback(void); 809 extern void failsafe_callback(void); 810 #ifdef __x86_64__ 811 typedef void (vector)(void); 812 extern vector Xsyscall, Xsyscall32; 813 #endif 814 815 /* 816 * Setup the "trampoline". On Xen, we setup nearly all cpu context 817 * outside a trampoline, so we prototype and call targetip like so: 818 * void targetip(struct cpu_info *); 819 */ 820 821 static void 822 gdt_prepframes(paddr_t *frames, vaddr_t base, uint32_t entries) 823 { 824 int i; 825 for (i = 0; i < roundup(entries, PAGE_SIZE) >> PAGE_SHIFT; i++) { 826 827 frames[i] = ((paddr_t) xpmap_ptetomach( 828 (pt_entry_t *) (base + (i << PAGE_SHIFT)))) 829 >> PAGE_SHIFT; 830 831 /* Mark Read-only */ 832 pmap_pte_clearbits(kvtopte(base + (i << PAGE_SHIFT)), 833 PG_RW); 834 } 835 } 836 837 #ifdef __x86_64__ 838 extern char *ldtstore; /* XXX: Xen MP todo */ 839 840 static void 841 xen_init_amd64_vcpuctxt(struct cpu_info *ci, 842 struct vcpu_guest_context *initctx, 843 void targetrip(struct cpu_info *)) 844 { 845 /* page frames to point at GDT */ 846 extern int gdt_size; 847 paddr_t frames[16]; 848 psize_t gdt_ents; 849 850 struct lwp *l; 851 struct pcb *pcb; 852 853 volatile struct vcpu_info *vci; 854 855 KASSERT(ci != NULL); 856 KASSERT(ci != &cpu_info_primary); 857 KASSERT(initctx != NULL); 858 KASSERT(targetrip != NULL); 859 860 memset(initctx, 0, sizeof *initctx); 861 862 gdt_ents = roundup(gdt_size, PAGE_SIZE) >> PAGE_SHIFT; /* XXX: re-investigate roundup(gdt_size... ) for gdt_ents. */ 863 KASSERT(gdt_ents <= 16); 864 865 gdt_prepframes(frames, (vaddr_t) ci->ci_gdt, gdt_ents); 866 867 /* XXX: The stuff in here is amd64 specific. move to mptramp.[Sc] ? */ 868 869 /* Initialise the vcpu context: We use idle_loop()'s pcb context. */ 870 871 l = ci->ci_data.cpu_idlelwp; 872 873 KASSERT(l != NULL); 874 pcb = lwp_getpcb(l); 875 KASSERT(pcb != NULL); 876 877 /* resume with interrupts off */ 878 vci = ci->ci_vcpu; 879 vci->evtchn_upcall_mask = 1; 880 xen_mb(); 881 882 /* resume in kernel-mode */ 883 initctx->flags = VGCF_in_kernel | VGCF_online; 884 885 /* Stack and entry points: 886 * We arrange for the stack frame for cpu_hatch() to 887 * appear as a callee frame of lwp_trampoline(). Being a 888 * leaf frame prevents trampling on any of the MD stack setup 889 * that x86/vm_machdep.c:cpu_lwp_fork() does for idle_loop() 890 */ 891 892 initctx->user_regs.rdi = (uint64_t) ci; /* targetrip(ci); */ 893 initctx->user_regs.rip = (vaddr_t) targetrip; 894 895 initctx->user_regs.cs = GSEL(GCODE_SEL, SEL_KPL); 896 897 initctx->user_regs.rflags = pcb->pcb_flags; 898 initctx->user_regs.rsp = pcb->pcb_rsp; 899 900 /* Data segments */ 901 initctx->user_regs.ss = GSEL(GDATA_SEL, SEL_KPL); 902 initctx->user_regs.es = GSEL(GDATA_SEL, SEL_KPL); 903 initctx->user_regs.ds = GSEL(GDATA_SEL, SEL_KPL); 904 905 /* GDT */ 906 memcpy(initctx->gdt_frames, frames, sizeof frames); 907 initctx->gdt_ents = gdt_ents; 908 909 /* LDT */ 910 initctx->ldt_base = (unsigned long) ldtstore; 911 initctx->ldt_ents = LDT_SIZE >> 3; 912 913 /* Kernel context state */ 914 initctx->kernel_ss = GSEL(GDATA_SEL, SEL_KPL); 915 initctx->kernel_sp = pcb->pcb_rsp0; 916 initctx->ctrlreg[0] = pcb->pcb_cr0; 917 initctx->ctrlreg[1] = 0; /* "resuming" from kernel - no User cr3. */ 918 initctx->ctrlreg[2] = pcb->pcb_cr2; /* XXX: */ 919 /* 920 * Use pmap_kernel() L4 PD directly, until we setup the 921 * per-cpu L4 PD in pmap_cpu_init_late() 922 */ 923 initctx->ctrlreg[3] = xpmap_ptom(pcb->pcb_cr3); 924 initctx->ctrlreg[4] = CR4_PAE | CR4_OSFXSR | CR4_OSXMMEXCPT; 925 926 927 /* Xen callbacks */ 928 initctx->event_callback_eip = (unsigned long) hypervisor_callback; 929 initctx->failsafe_callback_eip = (unsigned long) failsafe_callback; 930 initctx->syscall_callback_eip = (unsigned long) Xsyscall; 931 932 return; 933 } 934 #else /* i386 */ 935 extern union descriptor *ldt; 936 extern void Xsyscall(void); 937 938 static void 939 xen_init_i386_vcpuctxt(struct cpu_info *ci, 940 struct vcpu_guest_context *initctx, 941 void targeteip(struct cpu_info *)) 942 { 943 /* page frames to point at GDT */ 944 extern int gdt_size; 945 paddr_t frames[16]; 946 psize_t gdt_ents; 947 948 struct lwp *l; 949 struct pcb *pcb; 950 951 volatile struct vcpu_info *vci; 952 953 KASSERT(ci != NULL); 954 KASSERT(ci != &cpu_info_primary); 955 KASSERT(initctx != NULL); 956 KASSERT(targeteip != NULL); 957 958 memset(initctx, 0, sizeof *initctx); 959 960 gdt_ents = roundup(gdt_size, PAGE_SIZE) >> PAGE_SHIFT; /* XXX: re-investigate roundup(gdt_size... ) for gdt_ents. */ 961 KASSERT(gdt_ents <= 16); 962 963 gdt_prepframes(frames, (vaddr_t) ci->ci_gdt, gdt_ents); 964 965 /* 966 * Initialise the vcpu context: 967 * We use this cpu's idle_loop() pcb context. 968 */ 969 970 l = ci->ci_data.cpu_idlelwp; 971 972 KASSERT(l != NULL); 973 pcb = lwp_getpcb(l); 974 KASSERT(pcb != NULL); 975 976 /* resume with interrupts off */ 977 vci = ci->ci_vcpu; 978 vci->evtchn_upcall_mask = 1; 979 xen_mb(); 980 981 /* resume in kernel-mode */ 982 initctx->flags = VGCF_in_kernel | VGCF_online; 983 984 /* Stack frame setup for cpu_hatch(): 985 * We arrange for the stack frame for cpu_hatch() to 986 * appear as a callee frame of lwp_trampoline(). Being a 987 * leaf frame prevents trampling on any of the MD stack setup 988 * that x86/vm_machdep.c:cpu_lwp_fork() does for idle_loop() 989 */ 990 991 initctx->user_regs.esp = pcb->pcb_esp - 4; /* Leave word for 992 arg1 */ 993 { /* targeteip(ci); */ 994 uint32_t *arg = (uint32_t *) initctx->user_regs.esp; 995 arg[1] = (uint32_t) ci; /* arg1 */ 996 997 } 998 999 initctx->user_regs.eip = (vaddr_t) targeteip; 1000 initctx->user_regs.cs = GSEL(GCODE_SEL, SEL_KPL); 1001 initctx->user_regs.eflags |= pcb->pcb_iopl; 1002 1003 /* Data segments */ 1004 initctx->user_regs.ss = GSEL(GDATA_SEL, SEL_KPL); 1005 initctx->user_regs.es = GSEL(GDATA_SEL, SEL_KPL); 1006 initctx->user_regs.ds = GSEL(GDATA_SEL, SEL_KPL); 1007 initctx->user_regs.fs = GSEL(GDATA_SEL, SEL_KPL); 1008 1009 /* GDT */ 1010 memcpy(initctx->gdt_frames, frames, sizeof frames); 1011 initctx->gdt_ents = gdt_ents; 1012 1013 /* LDT */ 1014 initctx->ldt_base = (unsigned long) ldt; 1015 initctx->ldt_ents = NLDT; 1016 1017 /* Kernel context state */ 1018 initctx->kernel_ss = GSEL(GDATA_SEL, SEL_KPL); 1019 initctx->kernel_sp = pcb->pcb_esp0; 1020 initctx->ctrlreg[0] = pcb->pcb_cr0; 1021 initctx->ctrlreg[1] = 0; /* "resuming" from kernel - no User cr3. */ 1022 initctx->ctrlreg[2] = pcb->pcb_cr2; /* XXX: */ 1023 /* 1024 * Use pmap_kernel() L4 PD directly, until we setup the 1025 * per-cpu L4 PD in pmap_cpu_init_late() 1026 */ 1027 initctx->ctrlreg[3] = xpmap_ptom(pcb->pcb_cr3); 1028 initctx->ctrlreg[4] = /* CR4_PAE | */CR4_OSFXSR | CR4_OSXMMEXCPT; 1029 1030 1031 /* Xen callbacks */ 1032 initctx->event_callback_eip = (unsigned long) hypervisor_callback; 1033 initctx->event_callback_cs = GSEL(GCODE_SEL, SEL_KPL); 1034 initctx->failsafe_callback_eip = (unsigned long) failsafe_callback; 1035 initctx->failsafe_callback_cs = GSEL(GCODE_SEL, SEL_KPL); 1036 1037 return; 1038 } 1039 #endif /* __x86_64__ */ 1040 1041 int 1042 mp_cpu_start(struct cpu_info *ci, vaddr_t target) 1043 { 1044 1045 int hyperror; 1046 struct vcpu_guest_context vcpuctx; 1047 1048 KASSERT(ci != NULL); 1049 KASSERT(ci != &cpu_info_primary); 1050 KASSERT(ci->ci_flags & CPUF_AP); 1051 1052 #ifdef __x86_64__ 1053 xen_init_amd64_vcpuctxt(ci, &vcpuctx, (void (*)(struct cpu_info *))target); 1054 #else /* i386 */ 1055 xen_init_i386_vcpuctxt(ci, &vcpuctx, (void (*)(struct cpu_info *))target); 1056 #endif /* __x86_64__ */ 1057 1058 /* Initialise the given vcpu to execute cpu_hatch(ci); */ 1059 if ((hyperror = HYPERVISOR_vcpu_op(VCPUOP_initialise, ci->ci_cpuid, &vcpuctx))) { 1060 aprint_error(": context initialisation failed. errno = %d\n", hyperror); 1061 return hyperror; 1062 } 1063 1064 /* Start it up */ 1065 1066 /* First bring it down - the Xen documentation conveniently omits this slight detail. */ 1067 if ((hyperror = HYPERVISOR_vcpu_op(VCPUOP_down, ci->ci_cpuid, NULL))) { 1068 aprint_error(": VCPUOP_down hypervisor command failed. errno = %d\n", hyperror); 1069 return hyperror; 1070 } 1071 1072 if ((hyperror = HYPERVISOR_vcpu_op(VCPUOP_up, ci->ci_cpuid, NULL))) { 1073 aprint_error(": VCPUOP_up hypervisor command failed. errno = %d\n", hyperror); 1074 return hyperror; 1075 } 1076 1077 if (!vcpu_is_up(ci)) { 1078 aprint_error(": did not come up\n"); 1079 return -1; 1080 } 1081 1082 return 0; 1083 } 1084 1085 void 1086 mp_cpu_start_cleanup(struct cpu_info *ci) 1087 { 1088 #if 0 1089 /* 1090 * Ensure the NVRAM reset byte contains something vaguely sane. 1091 */ 1092 1093 outb(IO_RTC, NVRAM_RESET); 1094 outb(IO_RTC+1, NVRAM_RESET_RST); 1095 #endif 1096 if (vcpu_is_up(ci)) { 1097 aprint_debug_dev(ci->ci_dev, "is started.\n"); 1098 } 1099 else { 1100 aprint_error_dev(ci->ci_dev, "did not start up.\n"); 1101 } 1102 1103 } 1104 1105 void 1106 cpu_init_msrs(struct cpu_info *ci, bool full) 1107 { 1108 #ifdef __x86_64__ 1109 if (full) { 1110 HYPERVISOR_set_segment_base (SEGBASE_FS, 0); 1111 HYPERVISOR_set_segment_base (SEGBASE_GS_KERNEL, (uint64_t) ci); 1112 HYPERVISOR_set_segment_base (SEGBASE_GS_USER, 0); 1113 } 1114 #endif /* __x86_64__ */ 1115 1116 if (cpu_feature[2] & CPUID_NOX) 1117 wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_NXE); 1118 1119 } 1120 1121 void 1122 cpu_offline_md(void) 1123 { 1124 int s; 1125 1126 s = splhigh(); 1127 #ifdef __i386__ 1128 npxsave_cpu(true); 1129 #else 1130 fpusave_cpu(true); 1131 #endif 1132 splx(s); 1133 } 1134 1135 #if 0 1136 /* XXX joerg restructure and restart CPUs individually */ 1137 static bool 1138 cpu_suspend(device_t dv, const pmf_qual_t *qual) 1139 { 1140 struct cpu_softc *sc = device_private(dv); 1141 struct cpu_info *ci = sc->sc_info; 1142 int err; 1143 1144 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1145 return true; 1146 1147 cpufreq_suspend(ci); 1148 1149 if ((ci->ci_flags & CPUF_PRIMARY) != 0) 1150 return true; 1151 1152 if (ci->ci_data.cpu_idlelwp == NULL) 1153 return true; 1154 1155 sc->sc_wasonline = !(ci->ci_schedstate.spc_flags & SPCF_OFFLINE); 1156 1157 if (sc->sc_wasonline) { 1158 mutex_enter(&cpu_lock); 1159 err = cpu_setstate(ci, false); 1160 mutex_exit(&cpu_lock); 1161 1162 if (err != 0) 1163 return false; 1164 } 1165 1166 return true; 1167 } 1168 1169 static bool 1170 cpu_resume(device_t dv, const pmf_qual_t *qual) 1171 { 1172 struct cpu_softc *sc = device_private(dv); 1173 struct cpu_info *ci = sc->sc_info; 1174 int err = 0; 1175 1176 if ((ci->ci_flags & CPUF_PRESENT) == 0) 1177 return true; 1178 1179 if ((ci->ci_flags & CPUF_PRIMARY) != 0) 1180 goto out; 1181 1182 if (ci->ci_data.cpu_idlelwp == NULL) 1183 goto out; 1184 1185 if (sc->sc_wasonline) { 1186 mutex_enter(&cpu_lock); 1187 err = cpu_setstate(ci, true); 1188 mutex_exit(&cpu_lock); 1189 } 1190 1191 out: 1192 if (err != 0) 1193 return false; 1194 1195 cpufreq_resume(ci); 1196 1197 return true; 1198 } 1199 #endif 1200 1201 void 1202 cpu_get_tsc_freq(struct cpu_info *ci) 1203 { 1204 uint32_t vcpu_tversion; 1205 const volatile vcpu_time_info_t *tinfo = &ci->ci_vcpu->time; 1206 1207 vcpu_tversion = tinfo->version; 1208 while (tinfo->version == vcpu_tversion); /* Wait for a time update. XXX: timeout ? */ 1209 1210 uint64_t freq = 1000000000ULL << 32; 1211 freq = freq / (uint64_t)tinfo->tsc_to_system_mul; 1212 if ( tinfo->tsc_shift < 0 ) 1213 freq = freq << -tinfo->tsc_shift; 1214 else 1215 freq = freq >> tinfo->tsc_shift; 1216 ci->ci_data.cpu_cc_freq = freq; 1217 } 1218 1219 void 1220 x86_cpu_idle_xen(void) 1221 { 1222 struct cpu_info *ci = curcpu(); 1223 1224 KASSERT(ci->ci_ilevel == IPL_NONE); 1225 1226 x86_disable_intr(); 1227 if (!__predict_false(ci->ci_want_resched)) { 1228 idle_block(); 1229 } else { 1230 x86_enable_intr(); 1231 } 1232 } 1233 1234 /* 1235 * Loads pmap for the current CPU. 1236 */ 1237 void 1238 cpu_load_pmap(struct pmap *pmap) 1239 { 1240 #ifdef i386 1241 #ifdef PAE 1242 int i, s; 1243 struct cpu_info *ci; 1244 1245 s = splvm(); /* just to be safe */ 1246 xpq_queue_lock(); 1247 ci = curcpu(); 1248 paddr_t l3_pd = xpmap_ptom_masked(ci->ci_pae_l3_pdirpa); 1249 /* don't update the kernel L3 slot */ 1250 for (i = 0 ; i < PDP_SIZE - 1; i++) { 1251 xpq_queue_pte_update(l3_pd + i * sizeof(pd_entry_t), 1252 xpmap_ptom(pmap->pm_pdirpa[i]) | PG_V); 1253 } 1254 xpq_queue_unlock(); 1255 splx(s); 1256 tlbflush(); 1257 #else /* PAE */ 1258 lcr3(pmap_pdirpa(pmap, 0)); 1259 #endif /* PAE */ 1260 #endif /* i386 */ 1261 1262 #ifdef __x86_64__ 1263 int i, s; 1264 pd_entry_t *old_pgd, *new_pgd; 1265 paddr_t addr; 1266 struct cpu_info *ci; 1267 1268 /* kernel pmap always in cr3 and should never go in user cr3 */ 1269 if (pmap_pdirpa(pmap, 0) != pmap_pdirpa(pmap_kernel(), 0)) { 1270 ci = curcpu(); 1271 /* 1272 * Map user space address in kernel space and load 1273 * user cr3 1274 */ 1275 s = splvm(); 1276 new_pgd = pmap->pm_pdir; 1277 old_pgd = pmap_kernel()->pm_pdir; 1278 addr = xpmap_ptom(pmap_pdirpa(pmap_kernel(), 0)); 1279 for (i = 0; i < PDIR_SLOT_PTE; 1280 i++, addr += sizeof(pd_entry_t)) { 1281 if ((new_pgd[i] & PG_V) || (old_pgd[i] & PG_V)) 1282 xpq_queue_pte_update(addr, new_pgd[i]); 1283 } 1284 xen_set_user_pgd(pmap_pdirpa(pmap, 0)); 1285 ci->ci_xen_current_user_pgd = pmap_pdirpa(pmap, 0); 1286 tlbflush(); 1287 splx(s); 1288 } 1289 #endif /* __x86_64__ */ 1290 } 1291 1292 /* 1293 * Notify all other cpus to halt. 1294 */ 1295 1296 void 1297 cpu_broadcast_halt(void) 1298 { 1299 xen_broadcast_ipi(XEN_IPI_HALT); 1300 } 1301 1302 /* 1303 * Send a dummy ipi to a cpu. 1304 */ 1305 1306 void 1307 cpu_kick(struct cpu_info *ci) 1308 { 1309 (void)xen_send_ipi(ci, XEN_IPI_KICK); 1310 } 1311
Indexes created Tue Sep 23 14:10:03 GMT 2025