cpu.c revision 1.90
1 /* $NetBSD: cpu.c,v 1.90 2012/03/11 16:16:44 jym Exp $ */ 2 /* NetBSD: cpu.c,v 1.18 2004/02/20 17:35:01 yamt Exp */ 3 4 /*- 5 * Copyright (c) 2000 The NetBSD Foundation, Inc. 6 * Copyright (c) 2002, 2006, 2007 YAMAMOTO Takashi, 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to The NetBSD Foundation 10 * by RedBack Networks Inc. 11 * 12 * Author: Bill Sommerfeld 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * Copyright (c) 1999 Stefan Grefen 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 56 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.90 2012/03/11 16:16:44 jym Exp $"); 70 71 #include "opt_ddb.h" 72 #include "opt_multiprocessor.h" 73 #include "opt_mpbios.h" /* for MPDEBUG */ 74 #include "opt_mtrr.h" 75 #include "opt_xen.h" 76 77 #include "lapic.h" 78 #include "ioapic.h" 79 80 #include <sys/param.h> 81 #include <sys/proc.h> 82 #include <sys/systm.h> 83 #include <sys/device.h> 84 #include <sys/kmem.h> 85 #include <sys/cpu.h> 86 #include <sys/cpufreq.h> 87 #include <sys/atomic.h> 88 #include <sys/reboot.h> 89 #include <sys/idle.h> 90 91 #include <uvm/uvm.h> 92 93 #include <machine/cpufunc.h> 94 #include <machine/cpuvar.h> 95 #include <machine/pmap.h> 96 #include <machine/vmparam.h> 97 #include <machine/mpbiosvar.h> 98 #include <machine/pcb.h> 99 #include <machine/specialreg.h> 100 #include <machine/segments.h> 101 #include <machine/gdt.h> 102 #include <machine/mtrr.h> 103 #include <machine/pio.h> 104 105 #ifdef i386 106 #include <machine/npx.h> 107 #else 108 #include <machine/fpu.h> 109 #endif 110 111 #include <xen/xen.h> 112 #include <xen/xen-public/vcpu.h> 113 #include <xen/vcpuvar.h> 114 115 #if NLAPIC > 0 116 #include <machine/apicvar.h> 117 #include <machine/i82489reg.h> 118 #include <machine/i82489var.h> 119 #endif 120 121 #include <dev/ic/mc146818reg.h> 122 #include <dev/isa/isareg.h> 123 124 #if MAXCPUS > 32 125 #error cpu_info contains 32bit bitmasks 126 #endif 127 128 static int cpu_match(device_t, cfdata_t, void *); 129 static void cpu_attach(device_t, device_t, void *); 130 static void cpu_defer(device_t); 131 static int cpu_rescan(device_t, const char *, const int *); 132 static void cpu_childdetached(device_t, device_t); 133 static int vcpu_match(device_t, cfdata_t, void *); 134 static void vcpu_attach(device_t, device_t, void *); 135 static void cpu_attach_common(device_t, device_t, void *); 136 void cpu_offline_md(void); 137 138 struct cpu_softc { 139 device_t sc_dev; /* device tree glue */ 140 struct cpu_info *sc_info; /* pointer to CPU info */ 141 bool sc_wasonline; 142 }; 143 144 int mp_cpu_start(struct cpu_info *, vaddr_t); 145 void mp_cpu_start_cleanup(struct cpu_info *); 146 const struct cpu_functions mp_cpu_funcs = { mp_cpu_start, NULL, 147 mp_cpu_start_cleanup }; 148 149 CFATTACH_DECL2_NEW(cpu, sizeof(struct cpu_softc), 150 cpu_match, cpu_attach, NULL, NULL, cpu_rescan, cpu_childdetached); 151 152 CFATTACH_DECL_NEW(vcpu, sizeof(struct cpu_softc), 153 vcpu_match, vcpu_attach, NULL, NULL); 154 155 /* 156 * Statically-allocated CPU info for the primary CPU (or the only 157 * CPU, on uniprocessors). The CPU info list is initialized to 158 * point at it. 159 */ 160 #ifdef TRAPLOG 161 #include <machine/tlog.h> 162 struct tlog tlog_primary; 163 #endif 164 struct cpu_info cpu_info_primary __aligned(CACHE_LINE_SIZE) = { 165 .ci_dev = 0, 166 .ci_self = &cpu_info_primary, 167 .ci_idepth = -1, 168 .ci_curlwp = &lwp0, 169 .ci_curldt = -1, 170 .ci_cpumask = 1, 171 #ifdef TRAPLOG 172 .ci_tlog = &tlog_primary, 173 #endif 174 175 }; 176 struct cpu_info phycpu_info_primary __aligned(CACHE_LINE_SIZE) = { 177 .ci_dev = 0, 178 .ci_self = &phycpu_info_primary, 179 }; 180 181 struct cpu_info *cpu_info_list = &cpu_info_primary; 182 struct cpu_info *phycpu_info_list = &phycpu_info_primary; 183 184 uint32_t cpus_attached = 1; 185 uint32_t cpus_running = 1; 186 187 uint32_t cpu_feature[5]; /* X86 CPUID feature bits 188 * [0] basic features %edx 189 * [1] basic features %ecx 190 * [2] extended features %edx 191 * [3] extended features %ecx 192 * [4] VIA padlock features 193 */ 194 195 bool x86_mp_online; 196 paddr_t mp_trampoline_paddr = MP_TRAMPOLINE; 197 198 #if defined(MULTIPROCESSOR) 199 void cpu_hatch(void *); 200 static void cpu_boot_secondary(struct cpu_info *ci); 201 static void cpu_start_secondary(struct cpu_info *ci); 202 #endif /* MULTIPROCESSOR */ 203 204 static int 205 cpu_match(device_t parent, cfdata_t match, void *aux) 206 { 207 208 return 1; 209 } 210 211 static void 212 cpu_attach(device_t parent, device_t self, void *aux) 213 { 214 struct cpu_softc *sc = device_private(self); 215 struct cpu_attach_args *caa = aux; 216 struct cpu_info *ci; 217 uintptr_t ptr; 218 static int nphycpu = 0; 219 220 sc->sc_dev = self; 221 222 /* 223 * If we're an Application Processor, allocate a cpu_info 224 * If we're the first attached CPU use the primary cpu_info, 225 * otherwise allocate a new one 226 */ 227 aprint_naive("\n"); 228 aprint_normal("\n"); 229 if (nphycpu > 0) { 230 struct cpu_info *tmp; 231 ptr = (uintptr_t)kmem_zalloc(sizeof(*ci) + CACHE_LINE_SIZE - 1, 232 KM_SLEEP); 233 ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE); 234 ci->ci_curldt = -1; 235 236 tmp = phycpu_info_list; 237 while (tmp->ci_next) 238 tmp = tmp->ci_next; 239 240 tmp->ci_next = ci; 241 } else { 242 ci = &phycpu_info_primary; 243 } 244 245 ci->ci_self = ci; 246 sc->sc_info = ci; 247 248 ci->ci_dev = self; 249 ci->ci_acpiid = caa->cpu_id; 250 ci->ci_cpuid = caa->cpu_number; 251 ci->ci_vcpu = NULL; 252 ci->ci_index = nphycpu++; 253 254 if (!pmf_device_register(self, NULL, NULL)) 255 aprint_error_dev(self, "couldn't establish power handler\n"); 256 257 (void)config_defer(self, cpu_defer); 258 } 259 260 static void 261 cpu_defer(device_t self) 262 { 263 cpu_rescan(self, NULL, NULL); 264 } 265 266 static int 267 cpu_rescan(device_t self, const char *ifattr, const int *locators) 268 { 269 struct cpu_softc *sc = device_private(self); 270 struct cpufeature_attach_args cfaa; 271 struct cpu_info *ci = sc->sc_info; 272 273 memset(&cfaa, 0, sizeof(cfaa)); 274 cfaa.ci = ci; 275 276 if (ifattr_match(ifattr, "cpufeaturebus")) { 277 278 if (ci->ci_frequency == NULL) { 279 cfaa.name = "frequency"; 280 ci->ci_frequency = config_found_ia(self, 281 "cpufeaturebus", &cfaa, NULL); 282 } 283 } 284 285 return 0; 286 } 287 288 static void 289 cpu_childdetached(device_t self, device_t child) 290 { 291 struct cpu_softc *sc = device_private(self); 292 struct cpu_info *ci = sc->sc_info; 293 294 if (ci->ci_frequency == child) 295 ci->ci_frequency = NULL; 296 } 297 298 static int 299 vcpu_match(device_t parent, cfdata_t match, void *aux) 300 { 301 struct vcpu_attach_args *vcaa = aux; 302 struct vcpu_runstate_info vcr; 303 int error; 304 305 if (strcmp(vcaa->vcaa_name, match->cf_name) == 0) { 306 error = HYPERVISOR_vcpu_op(VCPUOP_get_runstate_info, 307 vcaa->vcaa_caa.cpu_number, 308 &vcr); 309 switch (error) { 310 case 0: 311 return 1; 312 case -ENOENT: 313 return 0; 314 default: 315 panic("Unknown hypervisor error %d returned on vcpu runstate probe\n", error); 316 } 317 } 318 319 return 0; 320 } 321 322 static void 323 vcpu_attach(device_t parent, device_t self, void *aux) 324 { 325 struct vcpu_attach_args *vcaa = aux; 326 327 KASSERT(vcaa->vcaa_caa.cpu_func == NULL); 328 vcaa->vcaa_caa.cpu_func = &mp_cpu_funcs; 329 cpu_attach_common(parent, self, &vcaa->vcaa_caa); 330 331 if (!pmf_device_register(self, NULL, NULL)) 332 aprint_error_dev(self, "couldn't establish power handler\n"); 333 } 334 335 static int 336 vcpu_is_up(struct cpu_info *ci) 337 { 338 KASSERT(ci != NULL); 339 return HYPERVISOR_vcpu_op(VCPUOP_is_up, ci->ci_cpuid, NULL); 340 } 341 342 static void 343 cpu_vm_init(struct cpu_info *ci) 344 { 345 int ncolors = 2, i; 346 347 for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) { 348 struct x86_cache_info *cai; 349 int tcolors; 350 351 cai = &ci->ci_cinfo[i]; 352 353 tcolors = atop(cai->cai_totalsize); 354 switch(cai->cai_associativity) { 355 case 0xff: 356 tcolors = 1; /* fully associative */ 357 break; 358 case 0: 359 case 1: 360 break; 361 default: 362 tcolors /= cai->cai_associativity; 363 } 364 ncolors = max(ncolors, tcolors); 365 } 366 367 /* 368 * Knowing the size of the largest cache on this CPU, potentially 369 * re-color our pages. 370 */ 371 aprint_debug_dev(ci->ci_dev, "%d page colors\n", ncolors); 372 uvm_page_recolor(ncolors); 373 } 374 375 static void 376 cpu_attach_common(device_t parent, device_t self, void *aux) 377 { 378 struct cpu_softc *sc = device_private(self); 379 struct cpu_attach_args *caa = aux; 380 struct cpu_info *ci; 381 uintptr_t ptr; 382 int cpunum = caa->cpu_number; 383 static bool again = false; 384 385 sc->sc_dev = self; 386 387 /* 388 * If we're an Application Processor, allocate a cpu_info 389 * structure, otherwise use the primary's. 390 */ 391 if (caa->cpu_role == CPU_ROLE_AP) { 392 aprint_naive(": Application Processor\n"); 393 ptr = (uintptr_t)kmem_alloc(sizeof(*ci) + CACHE_LINE_SIZE - 1, 394 KM_SLEEP); 395 ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE); 396 memset(ci, 0, sizeof(*ci)); 397 #ifdef TRAPLOG 398 ci->ci_tlog_base = kmem_zalloc(sizeof(struct tlog), KM_SLEEP); 399 #endif 400 } else { 401 aprint_naive(": %s Processor\n", 402 caa->cpu_role == CPU_ROLE_SP ? "Single" : "Boot"); 403 ci = &cpu_info_primary; 404 } 405 406 ci->ci_self = ci; 407 sc->sc_info = ci; 408 ci->ci_dev = self; 409 ci->ci_cpuid = cpunum; 410 411 KASSERT(HYPERVISOR_shared_info != NULL); 412 KASSERT(cpunum < XEN_LEGACY_MAX_VCPUS); 413 ci->ci_vcpu = &HYPERVISOR_shared_info->vcpu_info[cpunum]; 414 415 KASSERT(ci->ci_func == 0); 416 ci->ci_func = caa->cpu_func; 417 418 /* Must be called before mi_cpu_attach(). */ 419 cpu_vm_init(ci); 420 421 if (caa->cpu_role == CPU_ROLE_AP) { 422 int error; 423 424 error = mi_cpu_attach(ci); 425 426 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 427 if (error != 0) { 428 aprint_normal("\n"); 429 aprint_error_dev(self, 430 "mi_cpu_attach failed with %d\n", error); 431 return; 432 } 433 434 } else { 435 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 436 } 437 438 KASSERT(ci->ci_cpuid == ci->ci_index); 439 ci->ci_cpumask = (1 << cpu_index(ci)); 440 pmap_reference(pmap_kernel()); 441 ci->ci_pmap = pmap_kernel(); 442 ci->ci_tlbstate = TLBSTATE_STALE; 443 444 /* 445 * Boot processor may not be attached first, but the below 446 * must be done to allow booting other processors. 447 */ 448 if (!again) { 449 atomic_or_32(&ci->ci_flags, CPUF_PRESENT | CPUF_PRIMARY); 450 /* Basic init. */ 451 cpu_intr_init(ci); 452 cpu_get_tsc_freq(ci); 453 cpu_init(ci); 454 pmap_cpu_init_late(ci); 455 456 /* Every processor needs to init it's own ipi h/w (similar to lapic) */ 457 xen_ipi_init(); 458 459 /* Make sure DELAY() is initialized. */ 460 DELAY(1); 461 again = true; 462 } 463 464 /* further PCB init done later. */ 465 466 switch (caa->cpu_role) { 467 case CPU_ROLE_SP: 468 atomic_or_32(&ci->ci_flags, CPUF_SP); 469 cpu_identify(ci); 470 x86_cpu_idle_init(); 471 472 break; 473 474 case CPU_ROLE_BP: 475 atomic_or_32(&ci->ci_flags, CPUF_BSP); 476 cpu_identify(ci); 477 x86_cpu_idle_init(); 478 479 break; 480 481 case CPU_ROLE_AP: 482 atomic_or_32(&ci->ci_flags, CPUF_AP); 483 484 /* 485 * report on an AP 486 */ 487 488 #if defined(MULTIPROCESSOR) 489 /* interrupt handler stack */ 490 cpu_intr_init(ci); 491 492 /* Setup per-cpu memory for gdt */ 493 gdt_alloc_cpu(ci); 494 495 pmap_cpu_init_late(ci); 496 cpu_start_secondary(ci); 497 498 if (ci->ci_flags & CPUF_PRESENT) { 499 struct cpu_info *tmp; 500 501 cpu_identify(ci); 502 tmp = cpu_info_list; 503 while (tmp->ci_next) 504 tmp = tmp->ci_next; 505 506 tmp->ci_next = ci; 507 } 508 #else 509 aprint_error(": not started\n"); 510 #endif 511 break; 512 513 default: 514 aprint_normal("\n"); 515 panic("unknown processor type??\n"); 516 } 517 518 atomic_or_32(&cpus_attached, ci->ci_cpumask); 519 520 #ifdef MPVERBOSE 521 if (mp_verbose) { 522 struct lwp *l = ci->ci_data.cpu_idlelwp; 523 struct pcb *pcb = lwp_getpcb(l); 524 525 aprint_verbose_dev(self, 526 "idle lwp at %p, idle sp at 0x%p\n", 527 l, 528 #ifdef i386 529 (void *)pcb->pcb_esp 530 #else /* i386 */ 531 (void *)pcb->pcb_rsp 532 #endif /* i386 */ 533 ); 534 535 } 536 #endif /* MPVERBOSE */ 537 } 538 539 /* 540 * Initialize the processor appropriately. 541 */ 542 543 void 544 cpu_init(struct cpu_info *ci) 545 { 546 547 /* 548 * If we have FXSAVE/FXRESTOR, use them. 549 */ 550 if (cpu_feature[0] & CPUID_FXSR) { 551 lcr4(rcr4() | CR4_OSFXSR); 552 553 /* 554 * If we have SSE/SSE2, enable XMM exceptions. 555 */ 556 if (cpu_feature[0] & (CPUID_SSE|CPUID_SSE2)) 557 lcr4(rcr4() | CR4_OSXMMEXCPT); 558 } 559 560 #ifdef __x86_64__ 561 /* No user PGD mapped for this CPU yet */ 562 ci->ci_xen_current_user_pgd = 0; 563 #endif 564 #if defined(__x86_64__) || defined(PAE) 565 mutex_init(&ci->ci_kpm_mtx, MUTEX_DEFAULT, IPL_VM); 566 #endif 567 568 atomic_or_32(&cpus_running, ci->ci_cpumask); 569 atomic_or_32(&ci->ci_flags, CPUF_RUNNING); 570 } 571 572 573 #ifdef MULTIPROCESSOR 574 575 void 576 cpu_boot_secondary_processors(void) 577 { 578 struct cpu_info *ci; 579 u_long i; 580 for (i = 0; i < maxcpus; i++) { 581 ci = cpu_lookup(i); 582 if (ci == NULL) 583 continue; 584 if (ci->ci_data.cpu_idlelwp == NULL) 585 continue; 586 if ((ci->ci_flags & CPUF_PRESENT) == 0) 587 continue; 588 if (ci->ci_flags & (CPUF_BSP|CPUF_SP|CPUF_PRIMARY)) 589 continue; 590 cpu_boot_secondary(ci); 591 } 592 593 x86_mp_online = true; 594 } 595 596 static void 597 cpu_init_idle_lwp(struct cpu_info *ci) 598 { 599 struct lwp *l = ci->ci_data.cpu_idlelwp; 600 struct pcb *pcb = lwp_getpcb(l); 601 602 pcb->pcb_cr0 = rcr0(); 603 } 604 605 void 606 cpu_init_idle_lwps(void) 607 { 608 struct cpu_info *ci; 609 u_long i; 610 611 for (i = 0; i < maxcpus; i++) { 612 ci = cpu_lookup(i); 613 if (ci == NULL) 614 continue; 615 if (ci->ci_data.cpu_idlelwp == NULL) 616 continue; 617 if ((ci->ci_flags & CPUF_PRESENT) == 0) 618 continue; 619 cpu_init_idle_lwp(ci); 620 } 621 } 622 623 static void 624 cpu_start_secondary(struct cpu_info *ci) 625 { 626 int i; 627 628 aprint_debug_dev(ci->ci_dev, "starting\n"); 629 630 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 631 632 if (CPU_STARTUP(ci, (vaddr_t) cpu_hatch) != 0) { 633 return; 634 } 635 636 /* 637 * wait for it to become ready 638 */ 639 for (i = 100000; (!(ci->ci_flags & CPUF_PRESENT)) && i > 0; i--) { 640 delay(10); 641 } 642 if ((ci->ci_flags & CPUF_PRESENT) == 0) { 643 aprint_error_dev(ci->ci_dev, "failed to become ready\n"); 644 #if defined(MPDEBUG) && defined(DDB) 645 printf("dropping into debugger; continue from here to resume boot\n"); 646 Debugger(); 647 #endif 648 } 649 650 CPU_START_CLEANUP(ci); 651 } 652 653 void 654 cpu_boot_secondary(struct cpu_info *ci) 655 { 656 int i; 657 atomic_or_32(&ci->ci_flags, CPUF_GO); 658 for (i = 100000; (!(ci->ci_flags & CPUF_RUNNING)) && i > 0; i--) { 659 delay(10); 660 } 661 if ((ci->ci_flags & CPUF_RUNNING) == 0) { 662 aprint_error_dev(ci->ci_dev, "CPU failed to start\n"); 663 #if defined(MPDEBUG) && defined(DDB) 664 printf("dropping into debugger; continue from here to resume boot\n"); 665 Debugger(); 666 #endif 667 } 668 } 669 670 /* 671 * APs end up here immediately after initialisation and VCPUOP_up in 672 * mp_cpu_start(). 673 * At this point, we are running in the idle pcb/idle stack of the new 674 * CPU. This function jumps to the idle loop and starts looking for 675 * work. 676 */ 677 extern void x86_64_tls_switch(struct lwp *); 678 void 679 cpu_hatch(void *v) 680 { 681 struct cpu_info *ci = (struct cpu_info *)v; 682 struct pcb *pcb; 683 int s, i; 684 685 /* Setup TLS and kernel GS/FS */ 686 cpu_init_msrs(ci, true); 687 cpu_init_idt(); 688 gdt_init_cpu(ci); 689 690 cpu_probe(ci); 691 692 atomic_or_32(&ci->ci_flags, CPUF_PRESENT); 693 694 while ((ci->ci_flags & CPUF_GO) == 0) { 695 /* Don't use delay, boot CPU may be patching the text. */ 696 for (i = 10000; i != 0; i--) 697 x86_pause(); 698 } 699 700 /* Because the text may have been patched in x86_patch(). */ 701 x86_flush(); 702 tlbflushg(); 703 704 KASSERT((ci->ci_flags & CPUF_RUNNING) == 0); 705 706 pcb = lwp_getpcb(curlwp); 707 pcb->pcb_cr3 = pmap_pdirpa(pmap_kernel(), 0); 708 pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp); 709 710 xen_ipi_init(); 711 712 xen_initclocks(); 713 714 #ifdef __x86_64__ 715 fpuinit(ci); 716 #endif 717 718 lldt(GSEL(GLDT_SEL, SEL_KPL)); 719 720 cpu_init(ci); 721 cpu_get_tsc_freq(ci); 722 723 s = splhigh(); 724 x86_enable_intr(); 725 splx(s); 726 727 aprint_debug_dev(ci->ci_dev, "running\n"); 728 729 cpu_switchto(NULL, ci->ci_data.cpu_idlelwp, true); 730 731 panic("switch to idle_loop context returned!\n"); 732 /* NOTREACHED */ 733 } 734 735 #if defined(DDB) 736 737 #include <ddb/db_output.h> 738 #include <machine/db_machdep.h> 739 740 /* 741 * Dump CPU information from ddb. 742 */ 743 void 744 cpu_debug_dump(void) 745 { 746 struct cpu_info *ci; 747 CPU_INFO_ITERATOR cii; 748 749 db_printf("addr dev id flags ipis curlwp fpcurlwp\n"); 750 for (CPU_INFO_FOREACH(cii, ci)) { 751 db_printf("%p %s %ld %x %x %10p %10p\n", 752 ci, 753 ci->ci_dev == NULL ? "BOOT" : device_xname(ci->ci_dev), 754 (long)ci->ci_cpuid, 755 ci->ci_flags, ci->ci_ipis, 756 ci->ci_curlwp, 757 ci->ci_fpcurlwp); 758 } 759 } 760 #endif /* DDB */ 761 762 #endif /* MULTIPROCESSOR */ 763 764 extern void hypervisor_callback(void); 765 extern void failsafe_callback(void); 766 #ifdef __x86_64__ 767 typedef void (vector)(void); 768 extern vector Xsyscall, Xsyscall32; 769 #endif 770 771 /* 772 * Setup the "trampoline". On Xen, we setup nearly all cpu context 773 * outside a trampoline, so we prototype and call targetip like so: 774 * void targetip(struct cpu_info *); 775 */ 776 777 static void 778 gdt_prepframes(paddr_t *frames, vaddr_t base, uint32_t entries) 779 { 780 int i; 781 for (i = 0; i < roundup(entries, PAGE_SIZE) >> PAGE_SHIFT; i++) { 782 783 frames[i] = ((paddr_t) xpmap_ptetomach( 784 (pt_entry_t *) (base + (i << PAGE_SHIFT)))) 785 >> PAGE_SHIFT; 786 787 /* Mark Read-only */ 788 pmap_pte_clearbits(kvtopte(base + (i << PAGE_SHIFT)), 789 PG_RW); 790 } 791 } 792 793 #ifdef __x86_64__ 794 extern char *ldtstore; 795 796 static void 797 xen_init_amd64_vcpuctxt(struct cpu_info *ci, 798 struct vcpu_guest_context *initctx, 799 void targetrip(struct cpu_info *)) 800 { 801 /* page frames to point at GDT */ 802 extern int gdt_size; 803 paddr_t frames[16]; 804 psize_t gdt_ents; 805 806 struct lwp *l; 807 struct pcb *pcb; 808 809 volatile struct vcpu_info *vci; 810 811 KASSERT(ci != NULL); 812 KASSERT(ci != &cpu_info_primary); 813 KASSERT(initctx != NULL); 814 KASSERT(targetrip != NULL); 815 816 memset(initctx, 0, sizeof *initctx); 817 818 gdt_ents = roundup(gdt_size, PAGE_SIZE) >> PAGE_SHIFT; 819 KASSERT(gdt_ents <= 16); 820 821 gdt_prepframes(frames, (vaddr_t) ci->ci_gdt, gdt_ents); 822 823 /* Initialise the vcpu context: We use idle_loop()'s pcb context. */ 824 825 l = ci->ci_data.cpu_idlelwp; 826 827 KASSERT(l != NULL); 828 pcb = lwp_getpcb(l); 829 KASSERT(pcb != NULL); 830 831 /* resume with interrupts off */ 832 vci = ci->ci_vcpu; 833 vci->evtchn_upcall_mask = 1; 834 xen_mb(); 835 836 /* resume in kernel-mode */ 837 initctx->flags = VGCF_in_kernel | VGCF_online; 838 839 /* Stack and entry points: 840 * We arrange for the stack frame for cpu_hatch() to 841 * appear as a callee frame of lwp_trampoline(). Being a 842 * leaf frame prevents trampling on any of the MD stack setup 843 * that x86/vm_machdep.c:cpu_lwp_fork() does for idle_loop() 844 */ 845 846 initctx->user_regs.rdi = (uint64_t) ci; /* targetrip(ci); */ 847 initctx->user_regs.rip = (vaddr_t) targetrip; 848 849 initctx->user_regs.cs = GSEL(GCODE_SEL, SEL_KPL); 850 851 initctx->user_regs.rflags = pcb->pcb_flags; 852 initctx->user_regs.rsp = pcb->pcb_rsp; 853 854 /* Data segments */ 855 initctx->user_regs.ss = GSEL(GDATA_SEL, SEL_KPL); 856 initctx->user_regs.es = GSEL(GDATA_SEL, SEL_KPL); 857 initctx->user_regs.ds = GSEL(GDATA_SEL, SEL_KPL); 858 859 /* GDT */ 860 memcpy(initctx->gdt_frames, frames, sizeof frames); 861 initctx->gdt_ents = gdt_ents; 862 863 /* LDT */ 864 initctx->ldt_base = (unsigned long) ldtstore; 865 initctx->ldt_ents = LDT_SIZE >> 3; 866 867 /* Kernel context state */ 868 initctx->kernel_ss = GSEL(GDATA_SEL, SEL_KPL); 869 initctx->kernel_sp = pcb->pcb_rsp0; 870 initctx->ctrlreg[0] = pcb->pcb_cr0; 871 initctx->ctrlreg[1] = 0; /* "resuming" from kernel - no User cr3. */ 872 initctx->ctrlreg[2] = (vaddr_t) targetrip; 873 /* 874 * Use pmap_kernel() L4 PD directly, until we setup the 875 * per-cpu L4 PD in pmap_cpu_init_late() 876 */ 877 initctx->ctrlreg[3] = xen_pfn_to_cr3(x86_btop(xpmap_ptom(ci->ci_kpm_pdirpa))); 878 initctx->ctrlreg[4] = CR4_PAE | CR4_OSFXSR | CR4_OSXMMEXCPT; 879 880 881 /* Xen callbacks */ 882 initctx->event_callback_eip = (unsigned long) hypervisor_callback; 883 initctx->failsafe_callback_eip = (unsigned long) failsafe_callback; 884 initctx->syscall_callback_eip = (unsigned long) Xsyscall; 885 886 return; 887 } 888 #else /* i386 */ 889 extern union descriptor *ldt; 890 extern void Xsyscall(void); 891 892 static void 893 xen_init_i386_vcpuctxt(struct cpu_info *ci, 894 struct vcpu_guest_context *initctx, 895 void targeteip(struct cpu_info *)) 896 { 897 /* page frames to point at GDT */ 898 extern int gdt_size; 899 paddr_t frames[16]; 900 psize_t gdt_ents; 901 902 struct lwp *l; 903 struct pcb *pcb; 904 905 volatile struct vcpu_info *vci; 906 907 KASSERT(ci != NULL); 908 KASSERT(ci != &cpu_info_primary); 909 KASSERT(initctx != NULL); 910 KASSERT(targeteip != NULL); 911 912 memset(initctx, 0, sizeof *initctx); 913 914 gdt_ents = roundup(gdt_size, PAGE_SIZE) >> PAGE_SHIFT; 915 KASSERT(gdt_ents <= 16); 916 917 gdt_prepframes(frames, (vaddr_t) ci->ci_gdt, gdt_ents); 918 919 /* 920 * Initialise the vcpu context: 921 * We use this cpu's idle_loop() pcb context. 922 */ 923 924 l = ci->ci_data.cpu_idlelwp; 925 926 KASSERT(l != NULL); 927 pcb = lwp_getpcb(l); 928 KASSERT(pcb != NULL); 929 930 /* resume with interrupts off */ 931 vci = ci->ci_vcpu; 932 vci->evtchn_upcall_mask = 1; 933 xen_mb(); 934 935 /* resume in kernel-mode */ 936 initctx->flags = VGCF_in_kernel | VGCF_online; 937 938 /* Stack frame setup for cpu_hatch(): 939 * We arrange for the stack frame for cpu_hatch() to 940 * appear as a callee frame of lwp_trampoline(). Being a 941 * leaf frame prevents trampling on any of the MD stack setup 942 * that x86/vm_machdep.c:cpu_lwp_fork() does for idle_loop() 943 */ 944 945 initctx->user_regs.esp = pcb->pcb_esp - 4; /* Leave word for 946 arg1 */ 947 { /* targeteip(ci); */ 948 uint32_t *arg = (uint32_t *) initctx->user_regs.esp; 949 arg[1] = (uint32_t) ci; /* arg1 */ 950 951 } 952 953 initctx->user_regs.eip = (vaddr_t) targeteip; 954 initctx->user_regs.cs = GSEL(GCODE_SEL, SEL_KPL); 955 initctx->user_regs.eflags |= pcb->pcb_iopl; 956 957 /* Data segments */ 958 initctx->user_regs.ss = GSEL(GDATA_SEL, SEL_KPL); 959 initctx->user_regs.es = GSEL(GDATA_SEL, SEL_KPL); 960 initctx->user_regs.ds = GSEL(GDATA_SEL, SEL_KPL); 961 initctx->user_regs.fs = GSEL(GDATA_SEL, SEL_KPL); 962 963 /* GDT */ 964 memcpy(initctx->gdt_frames, frames, sizeof frames); 965 initctx->gdt_ents = gdt_ents; 966 967 /* LDT */ 968 initctx->ldt_base = (unsigned long) ldt; 969 initctx->ldt_ents = NLDT; 970 971 /* Kernel context state */ 972 initctx->kernel_ss = GSEL(GDATA_SEL, SEL_KPL); 973 initctx->kernel_sp = pcb->pcb_esp0; 974 initctx->ctrlreg[0] = pcb->pcb_cr0; 975 initctx->ctrlreg[1] = 0; /* "resuming" from kernel - no User cr3. */ 976 initctx->ctrlreg[2] = (vaddr_t) targeteip; 977 #ifdef PAE 978 initctx->ctrlreg[3] = xen_pfn_to_cr3(x86_btop(xpmap_ptom(ci->ci_pae_l3_pdirpa))); 979 #else /* PAE */ 980 initctx->ctrlreg[3] = xen_pfn_to_cr3(x86_btop(xpmap_ptom(pcb->pcb_cr3))); 981 #endif /* PAE */ 982 initctx->ctrlreg[4] = /* CR4_PAE | */CR4_OSFXSR | CR4_OSXMMEXCPT; 983 984 985 /* Xen callbacks */ 986 initctx->event_callback_eip = (unsigned long) hypervisor_callback; 987 initctx->event_callback_cs = GSEL(GCODE_SEL, SEL_KPL); 988 initctx->failsafe_callback_eip = (unsigned long) failsafe_callback; 989 initctx->failsafe_callback_cs = GSEL(GCODE_SEL, SEL_KPL); 990 991 return; 992 } 993 #endif /* __x86_64__ */ 994 995 int 996 mp_cpu_start(struct cpu_info *ci, vaddr_t target) 997 { 998 999 int hyperror; 1000 struct vcpu_guest_context vcpuctx; 1001 1002 KASSERT(ci != NULL); 1003 KASSERT(ci != &cpu_info_primary); 1004 KASSERT(ci->ci_flags & CPUF_AP); 1005 1006 #ifdef __x86_64__ 1007 xen_init_amd64_vcpuctxt(ci, &vcpuctx, (void (*)(struct cpu_info *))target); 1008 #else /* i386 */ 1009 xen_init_i386_vcpuctxt(ci, &vcpuctx, (void (*)(struct cpu_info *))target); 1010 #endif /* __x86_64__ */ 1011 1012 /* Initialise the given vcpu to execute cpu_hatch(ci); */ 1013 if ((hyperror = HYPERVISOR_vcpu_op(VCPUOP_initialise, ci->ci_cpuid, &vcpuctx))) { 1014 aprint_error(": context initialisation failed. errno = %d\n", hyperror); 1015 return hyperror; 1016 } 1017 1018 /* Start it up */ 1019 1020 /* First bring it down */ 1021 if ((hyperror = HYPERVISOR_vcpu_op(VCPUOP_down, ci->ci_cpuid, NULL))) { 1022 aprint_error(": VCPUOP_down hypervisor command failed. errno = %d\n", hyperror); 1023 return hyperror; 1024 } 1025 1026 if ((hyperror = HYPERVISOR_vcpu_op(VCPUOP_up, ci->ci_cpuid, NULL))) { 1027 aprint_error(": VCPUOP_up hypervisor command failed. errno = %d\n", hyperror); 1028 return hyperror; 1029 } 1030 1031 if (!vcpu_is_up(ci)) { 1032 aprint_error(": did not come up\n"); 1033 return -1; 1034 } 1035 1036 return 0; 1037 } 1038 1039 void 1040 mp_cpu_start_cleanup(struct cpu_info *ci) 1041 { 1042 if (vcpu_is_up(ci)) { 1043 aprint_debug_dev(ci->ci_dev, "is started.\n"); 1044 } 1045 else { 1046 aprint_error_dev(ci->ci_dev, "did not start up.\n"); 1047 } 1048 1049 } 1050 1051 void 1052 cpu_init_msrs(struct cpu_info *ci, bool full) 1053 { 1054 #ifdef __x86_64__ 1055 if (full) { 1056 HYPERVISOR_set_segment_base (SEGBASE_FS, 0); 1057 HYPERVISOR_set_segment_base (SEGBASE_GS_KERNEL, (uint64_t) ci); 1058 HYPERVISOR_set_segment_base (SEGBASE_GS_USER, 0); 1059 } 1060 #endif /* __x86_64__ */ 1061 1062 if (cpu_feature[2] & CPUID_NOX) 1063 wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_NXE); 1064 1065 } 1066 1067 void 1068 cpu_offline_md(void) 1069 { 1070 int s; 1071 1072 s = splhigh(); 1073 #ifdef __i386__ 1074 npxsave_cpu(true); 1075 #else 1076 fpusave_cpu(true); 1077 #endif 1078 splx(s); 1079 } 1080 1081 void 1082 cpu_get_tsc_freq(struct cpu_info *ci) 1083 { 1084 uint32_t vcpu_tversion; 1085 const volatile vcpu_time_info_t *tinfo = &ci->ci_vcpu->time; 1086 1087 vcpu_tversion = tinfo->version; 1088 while (tinfo->version == vcpu_tversion); /* Wait for a time update. XXX: timeout ? */ 1089 1090 uint64_t freq = 1000000000ULL << 32; 1091 freq = freq / (uint64_t)tinfo->tsc_to_system_mul; 1092 if ( tinfo->tsc_shift < 0 ) 1093 freq = freq << -tinfo->tsc_shift; 1094 else 1095 freq = freq >> tinfo->tsc_shift; 1096 ci->ci_data.cpu_cc_freq = freq; 1097 } 1098 1099 void 1100 x86_cpu_idle_xen(void) 1101 { 1102 struct cpu_info *ci = curcpu(); 1103 1104 KASSERT(ci->ci_ilevel == IPL_NONE); 1105 1106 x86_disable_intr(); 1107 if (!__predict_false(ci->ci_want_resched)) { 1108 idle_block(); 1109 } else { 1110 x86_enable_intr(); 1111 } 1112 } 1113 1114 /* 1115 * Loads pmap for the current CPU. 1116 */ 1117 void 1118 cpu_load_pmap(struct pmap *pmap, struct pmap *oldpmap) 1119 { 1120 KASSERT(pmap != pmap_kernel()); 1121 1122 #if defined(__x86_64__) || defined(PAE) 1123 struct cpu_info *ci = curcpu(); 1124 uint32_t cpumask = ci->ci_cpumask; 1125 1126 mutex_enter(&ci->ci_kpm_mtx); 1127 /* make new pmap visible to pmap_kpm_sync_xcall() */ 1128 atomic_or_32(&pmap->pm_xen_ptp_cpus, cpumask); 1129 #endif 1130 #ifdef i386 1131 #ifdef PAE 1132 { 1133 int i; 1134 paddr_t l3_pd = xpmap_ptom_masked(ci->ci_pae_l3_pdirpa); 1135 /* don't update the kernel L3 slot */ 1136 for (i = 0 ; i < PDP_SIZE - 1; i++) { 1137 xpq_queue_pte_update(l3_pd + i * sizeof(pd_entry_t), 1138 xpmap_ptom(pmap->pm_pdirpa[i]) | PG_V); 1139 } 1140 tlbflush(); 1141 } 1142 #else /* PAE */ 1143 lcr3(pmap_pdirpa(pmap, 0)); 1144 #endif /* PAE */ 1145 #endif /* i386 */ 1146 1147 #ifdef __x86_64__ 1148 { 1149 int i; 1150 pd_entry_t *new_pgd; 1151 paddr_t l4_pd_ma; 1152 1153 l4_pd_ma = xpmap_ptom_masked(ci->ci_kpm_pdirpa); 1154 1155 /* 1156 * Map user space address in kernel space and load 1157 * user cr3 1158 */ 1159 new_pgd = pmap->pm_pdir; 1160 KASSERT(pmap == ci->ci_pmap); 1161 1162 /* Copy user pmap L4 PDEs (in user addr. range) to per-cpu L4 */ 1163 for (i = 0; i < PDIR_SLOT_PTE; i++) { 1164 KASSERT(pmap != pmap_kernel() || new_pgd[i] == 0); 1165 if (ci->ci_kpm_pdir[i] != new_pgd[i]) { 1166 xpq_queue_pte_update( 1167 l4_pd_ma + i * sizeof(pd_entry_t), 1168 new_pgd[i]); 1169 } 1170 } 1171 1172 xen_set_user_pgd(pmap_pdirpa(pmap, 0)); 1173 ci->ci_xen_current_user_pgd = pmap_pdirpa(pmap, 0); 1174 1175 tlbflush(); 1176 } 1177 1178 #endif /* __x86_64__ */ 1179 #if defined(__x86_64__) || defined(PAE) 1180 /* old pmap no longer visible to pmap_kpm_sync_xcall() */ 1181 atomic_and_32(&oldpmap->pm_xen_ptp_cpus, ~cpumask); 1182 mutex_exit(&ci->ci_kpm_mtx); 1183 #endif 1184 } 1185 1186 /* 1187 * pmap_cpu_init_late: perform late per-CPU initialization. 1188 * Short note about percpu PDIR pages: 1189 * Both the PAE and __x86_64__ architectures have per-cpu PDIR 1190 * tables. This is to get around Xen's pagetable setup constraints for 1191 * PAE (multiple L3[3]s cannot point to the same L2 - Xen 1192 * will refuse to pin a table setup this way.) and for multiple cpus 1193 * to map in different user pmaps on __x86_64__ (see: cpu_load_pmap()) 1194 * 1195 * What this means for us is that the PDIR of the pmap_kernel() is 1196 * considered to be a canonical "SHADOW" PDIR with the following 1197 * properties: 1198 * - Its recursive mapping points to itself 1199 * - per-cpu recursive mappings point to themselves on __x86_64__ 1200 * - per-cpu L4 pages' kernel entries are expected to be in sync with 1201 * the shadow 1202 */ 1203 1204 void 1205 pmap_cpu_init_late(struct cpu_info *ci) 1206 { 1207 #if defined(PAE) || defined(__x86_64__) 1208 /* 1209 * The BP has already its own PD page allocated during early 1210 * MD startup. 1211 */ 1212 1213 #if defined(__x86_64__) 1214 /* Setup per-cpu normal_pdes */ 1215 int i; 1216 extern pd_entry_t * const normal_pdes[]; 1217 for (i = 0;i < PTP_LEVELS - 1;i++) { 1218 ci->ci_normal_pdes[i] = normal_pdes[i]; 1219 } 1220 #endif /* __x86_64__ */ 1221 1222 if (ci == &cpu_info_primary) 1223 return; 1224 1225 KASSERT(ci != NULL); 1226 1227 #if defined(PAE) 1228 cpu_alloc_l3_page(ci); 1229 KASSERT(ci->ci_pae_l3_pdirpa != 0); 1230 1231 /* Initialise L2 entries 0 - 2: Point them to pmap_kernel() */ 1232 int i; 1233 for (i = 0 ; i < PDP_SIZE - 1; i++) { 1234 ci->ci_pae_l3_pdir[i] = 1235 xpmap_ptom_masked(pmap_kernel()->pm_pdirpa[i]) | PG_V; 1236 } 1237 #endif /* PAE */ 1238 1239 ci->ci_kpm_pdir = (pd_entry_t *)uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 1240 UVM_KMF_WIRED | UVM_KMF_ZERO | UVM_KMF_NOWAIT); 1241 1242 if (ci->ci_kpm_pdir == NULL) { 1243 panic("%s: failed to allocate L4 per-cpu PD for CPU %d\n", 1244 __func__, cpu_index(ci)); 1245 } 1246 ci->ci_kpm_pdirpa = vtophys((vaddr_t) ci->ci_kpm_pdir); 1247 KASSERT(ci->ci_kpm_pdirpa != 0); 1248 1249 #if defined(__x86_64__) 1250 /* 1251 * Copy over the pmap_kernel() shadow L4 entries 1252 */ 1253 1254 memcpy(ci->ci_kpm_pdir, pmap_kernel()->pm_pdir, PAGE_SIZE); 1255 1256 /* Recursive kernel mapping */ 1257 ci->ci_kpm_pdir[PDIR_SLOT_PTE] = xpmap_ptom_masked(ci->ci_kpm_pdirpa) | PG_k | PG_V; 1258 #elif defined(PAE) 1259 /* Copy over the pmap_kernel() shadow L2 entries that map the kernel */ 1260 memcpy(ci->ci_kpm_pdir, pmap_kernel()->pm_pdir + PDIR_SLOT_KERN, nkptp[PTP_LEVELS - 1] * sizeof(pd_entry_t)); 1261 #endif /* __x86_64__ else PAE */ 1262 1263 /* Xen wants R/O */ 1264 pmap_protect(pmap_kernel(), (vaddr_t)ci->ci_kpm_pdir, 1265 (vaddr_t)ci->ci_kpm_pdir + PAGE_SIZE, VM_PROT_READ); 1266 pmap_update(pmap_kernel()); 1267 #if defined(PAE) 1268 /* Initialise L3 entry 3. This mapping is shared across all 1269 * pmaps and is static, ie; loading a new pmap will not update 1270 * this entry. 1271 */ 1272 1273 ci->ci_pae_l3_pdir[3] = xpmap_ptom_masked(ci->ci_kpm_pdirpa) | PG_k | PG_V; 1274 1275 /* Mark L3 R/O (Xen wants this) */ 1276 pmap_protect(pmap_kernel(), (vaddr_t)ci->ci_pae_l3_pdir, 1277 (vaddr_t)ci->ci_pae_l3_pdir + PAGE_SIZE, VM_PROT_READ); 1278 pmap_update(pmap_kernel()); 1279 1280 xpq_queue_pin_l3_table(xpmap_ptom_masked(ci->ci_pae_l3_pdirpa)); 1281 1282 #elif defined(__x86_64__) 1283 xpq_queue_pin_l4_table(xpmap_ptom_masked(ci->ci_kpm_pdirpa)); 1284 #endif /* PAE , __x86_64__ */ 1285 #endif /* defined(PAE) || defined(__x86_64__) */ 1286 } 1287 1288 /* 1289 * Notify all other cpus to halt. 1290 */ 1291 1292 void 1293 cpu_broadcast_halt(void) 1294 { 1295 xen_broadcast_ipi(XEN_IPI_HALT); 1296 } 1297 1298 /* 1299 * Send a dummy ipi to a cpu. 1300 */ 1301 1302 void 1303 cpu_kick(struct cpu_info *ci) 1304 { 1305 (void)xen_send_ipi(ci, XEN_IPI_KICK); 1306 } 1307
Indexes created Wed Sep 24 05:09:52 GMT 2025