qcomgpio.c revision 1.4 1 1.4 jmcneill /* $NetBSD: qcomgpio.c,v 1.4 2024/12/12 12:47:57 jmcneill Exp $ */
2 1.1 jmcneill
3 1.1 jmcneill /*-
4 1.1 jmcneill * Copyright (c) 2024 The NetBSD Foundation, Inc.
5 1.1 jmcneill * All rights reserved.
6 1.1 jmcneill *
7 1.1 jmcneill * This code is derived from software contributed to The NetBSD Foundation
8 1.1 jmcneill * by Jared McNeill <jmcneill (at) invisible.ca>.
9 1.1 jmcneill *
10 1.1 jmcneill * Redistribution and use in source and binary forms, with or without
11 1.1 jmcneill * modification, are permitted provided that the following conditions
12 1.1 jmcneill * are met:
13 1.1 jmcneill * 1. Redistributions of source code must retain the above copyright
14 1.1 jmcneill * notice, this list of conditions and the following disclaimer.
15 1.1 jmcneill * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 jmcneill * notice, this list of conditions and the following disclaimer in the
17 1.1 jmcneill * documentation and/or other materials provided with the distribution.
18 1.1 jmcneill *
19 1.1 jmcneill * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 1.1 jmcneill * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.1 jmcneill * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.1 jmcneill * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 1.1 jmcneill * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.1 jmcneill * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.1 jmcneill * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.1 jmcneill * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.1 jmcneill * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.1 jmcneill * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.1 jmcneill * POSSIBILITY OF SUCH DAMAGE.
30 1.1 jmcneill */
31 1.1 jmcneill
32 1.1 jmcneill #include <sys/cdefs.h>
33 1.4 jmcneill __KERNEL_RCSID(0, "$NetBSD: qcomgpio.c,v 1.4 2024/12/12 12:47:57 jmcneill Exp $");
34 1.1 jmcneill
35 1.1 jmcneill #include <sys/param.h>
36 1.1 jmcneill #include <sys/bus.h>
37 1.1 jmcneill #include <sys/cpu.h>
38 1.1 jmcneill #include <sys/device.h>
39 1.1 jmcneill #include <sys/gpio.h>
40 1.1 jmcneill #include <sys/queue.h>
41 1.1 jmcneill #include <sys/kmem.h>
42 1.1 jmcneill #include <sys/mutex.h>
43 1.1 jmcneill
44 1.1 jmcneill #include <dev/acpi/acpireg.h>
45 1.1 jmcneill #include <dev/acpi/acpivar.h>
46 1.1 jmcneill #include <dev/acpi/acpi_intr.h>
47 1.1 jmcneill #include <dev/acpi/acpi_event.h>
48 1.1 jmcneill #include <dev/acpi/acpi_gpio.h>
49 1.1 jmcneill #include <dev/acpi/qcomgpioreg.h>
50 1.1 jmcneill
51 1.1 jmcneill #include <dev/gpio/gpiovar.h>
52 1.1 jmcneill
53 1.1 jmcneill typedef enum {
54 1.1 jmcneill QCOMGPIO_X1E,
55 1.1 jmcneill } qcomgpio_type;
56 1.1 jmcneill
57 1.3 jmcneill struct qcomgpio_reserved {
58 1.3 jmcneill int start;
59 1.3 jmcneill int count;
60 1.3 jmcneill };
61 1.3 jmcneill
62 1.1 jmcneill struct qcomgpio_config {
63 1.3 jmcneill struct qcomgpio_reserved *reserved;
64 1.3 jmcneill u_int num_reserved;
65 1.1 jmcneill };
66 1.1 jmcneill
67 1.1 jmcneill struct qcomgpio_intr_handler {
68 1.1 jmcneill int (*ih_func)(void *);
69 1.1 jmcneill void *ih_arg;
70 1.1 jmcneill int ih_pin;
71 1.2 jmcneill int ih_type;
72 1.1 jmcneill LIST_ENTRY(qcomgpio_intr_handler) ih_list;
73 1.1 jmcneill };
74 1.1 jmcneill
75 1.4 jmcneill struct qcomgpio_pdcmap {
76 1.4 jmcneill int pm_pin;
77 1.4 jmcneill u_int pm_irq;
78 1.4 jmcneill };
79 1.4 jmcneill
80 1.1 jmcneill struct qcomgpio_softc {
81 1.1 jmcneill device_t sc_dev;
82 1.1 jmcneill device_t sc_gpiodev;
83 1.1 jmcneill bus_space_handle_t sc_bsh;
84 1.1 jmcneill bus_space_tag_t sc_bst;
85 1.1 jmcneill const struct qcomgpio_config *sc_config;
86 1.1 jmcneill struct gpio_chipset_tag sc_gc;
87 1.1 jmcneill gpio_pin_t *sc_pins;
88 1.4 jmcneill u_int sc_npins;
89 1.1 jmcneill LIST_HEAD(, qcomgpio_intr_handler) sc_intrs;
90 1.1 jmcneill kmutex_t sc_lock;
91 1.4 jmcneill
92 1.4 jmcneill struct qcomgpio_pdcmap *sc_pdcmap;
93 1.4 jmcneill u_int sc_npdcmap;
94 1.1 jmcneill };
95 1.1 jmcneill
96 1.1 jmcneill #define RD4(sc, reg) \
97 1.1 jmcneill bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
98 1.1 jmcneill #define WR4(sc, reg, val) \
99 1.1 jmcneill bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
100 1.1 jmcneill
101 1.1 jmcneill static int qcomgpio_match(device_t, cfdata_t, void *);
102 1.1 jmcneill static void qcomgpio_attach(device_t, device_t, void *);
103 1.1 jmcneill
104 1.3 jmcneill static bool qcomgpio_pin_reserved(struct qcomgpio_softc *, int);
105 1.1 jmcneill static int qcomgpio_pin_read(void *, int);
106 1.1 jmcneill static void qcomgpio_pin_write(void *, int, int);
107 1.1 jmcneill static void qcomgpio_pin_ctl(void *, int, int);
108 1.1 jmcneill static void * qcomgpio_intr_establish(void *, int, int, int,
109 1.1 jmcneill int (*)(void *), void *);
110 1.1 jmcneill static void qcomgpio_intr_disestablish(void *, void *);
111 1.1 jmcneill static bool qcomgpio_intr_str(void *, int, int, char *, size_t);
112 1.1 jmcneill static void qcomgpio_intr_mask(void *, void *);
113 1.1 jmcneill static void qcomgpio_intr_unmask(void *, void *);
114 1.1 jmcneill
115 1.4 jmcneill static u_int qcomgpio_acpi_num_pins(device_t, ACPI_HANDLE);
116 1.4 jmcneill static void qcomgpio_acpi_fill_pdcmap(struct qcomgpio_softc *,
117 1.4 jmcneill ACPI_HANDLE);
118 1.2 jmcneill static int qcomgpio_acpi_translate(void *, ACPI_RESOURCE_GPIO *, void **);
119 1.1 jmcneill static void qcomgpio_register_event(void *, struct acpi_event *,
120 1.1 jmcneill ACPI_RESOURCE_GPIO *);
121 1.1 jmcneill static int qcomgpio_intr(void *);
122 1.1 jmcneill
123 1.1 jmcneill CFATTACH_DECL_NEW(qcomgpio, sizeof(struct qcomgpio_softc),
124 1.1 jmcneill qcomgpio_match, qcomgpio_attach, NULL, NULL);
125 1.1 jmcneill
126 1.4 jmcneill static UINT8 qcomgpio_gpio_dsm_uuid[ACPI_UUID_LENGTH] = {
127 1.4 jmcneill 0xa4, 0xb2, 0xb9, 0x98, 0x63, 0x16, 0x5f, 0x4a,
128 1.4 jmcneill 0x82, 0xf2, 0xc6, 0xc9, 0x9a, 0x39, 0x47, 0x26
129 1.4 jmcneill };
130 1.4 jmcneill #define QCOMGPIO_GPIO_DSM_REV 0
131 1.4 jmcneill #define QCOMGPIO_GPIO_DSM_FUNC_NUM_PINS 2
132 1.4 jmcneill
133 1.4 jmcneill static UINT8 qcomgpio_pdc_dsm_uuid[ACPI_UUID_LENGTH] = {
134 1.4 jmcneill 0xd4, 0x0f, 0x1b, 0x92, 0x7c, 0x56, 0xa0, 0x43,
135 1.4 jmcneill 0xbb, 0x14, 0x26, 0x48, 0xf7, 0xb2, 0xa1, 0x8c
136 1.4 jmcneill };
137 1.4 jmcneill #define QCOMGPIO_PDC_DSM_REV 0
138 1.4 jmcneill #define QCOMGPIO_PDC_DSM_FUNC_CIPR 2
139 1.2 jmcneill
140 1.3 jmcneill static struct qcomgpio_reserved qcomgpio_x1e_reserved[] = {
141 1.3 jmcneill { .start = 34, .count = 2 },
142 1.3 jmcneill { .start = 44, .count = 4 },
143 1.3 jmcneill { .start = 72, .count = 2 },
144 1.3 jmcneill { .start = 238, .count = 1 },
145 1.3 jmcneill };
146 1.3 jmcneill
147 1.1 jmcneill static struct qcomgpio_config qcomgpio_x1e_config = {
148 1.3 jmcneill .reserved = qcomgpio_x1e_reserved,
149 1.3 jmcneill .num_reserved = __arraycount(qcomgpio_x1e_reserved),
150 1.1 jmcneill };
151 1.1 jmcneill
152 1.1 jmcneill static const struct device_compatible_entry compat_data[] = {
153 1.1 jmcneill { .compat = "QCOM0C0C", .data = &qcomgpio_x1e_config },
154 1.1 jmcneill DEVICE_COMPAT_EOL
155 1.1 jmcneill };
156 1.1 jmcneill
157 1.1 jmcneill static int
158 1.1 jmcneill qcomgpio_match(device_t parent, cfdata_t cf, void *aux)
159 1.1 jmcneill {
160 1.1 jmcneill struct acpi_attach_args *aa = aux;
161 1.1 jmcneill
162 1.1 jmcneill return acpi_compatible_match(aa, compat_data);
163 1.1 jmcneill }
164 1.1 jmcneill
165 1.1 jmcneill static void
166 1.1 jmcneill qcomgpio_attach(device_t parent, device_t self, void *aux)
167 1.1 jmcneill {
168 1.1 jmcneill struct qcomgpio_softc * const sc = device_private(self);
169 1.1 jmcneill struct acpi_attach_args *aa = aux;
170 1.1 jmcneill struct gpiobus_attach_args gba;
171 1.1 jmcneill ACPI_HANDLE hdl = aa->aa_node->ad_handle;
172 1.1 jmcneill struct acpi_resources res;
173 1.1 jmcneill struct acpi_mem *mem;
174 1.1 jmcneill struct acpi_irq *irq;
175 1.1 jmcneill ACPI_STATUS rv;
176 1.4 jmcneill int error, pin, n;
177 1.1 jmcneill void *ih;
178 1.1 jmcneill
179 1.1 jmcneill sc->sc_dev = self;
180 1.1 jmcneill sc->sc_config = acpi_compatible_lookup(aa, compat_data)->data;
181 1.1 jmcneill sc->sc_bst = aa->aa_memt;
182 1.1 jmcneill KASSERT(sc->sc_config != NULL);
183 1.1 jmcneill LIST_INIT(&sc->sc_intrs);
184 1.1 jmcneill mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM);
185 1.1 jmcneill
186 1.1 jmcneill rv = acpi_resource_parse(sc->sc_dev, hdl, "_CRS",
187 1.1 jmcneill &res, &acpi_resource_parse_ops_default);
188 1.1 jmcneill if (ACPI_FAILURE(rv)) {
189 1.1 jmcneill return;
190 1.1 jmcneill }
191 1.1 jmcneill
192 1.1 jmcneill mem = acpi_res_mem(&res, 0);
193 1.1 jmcneill if (mem == NULL) {
194 1.1 jmcneill aprint_error_dev(self, "couldn't find mem resource\n");
195 1.1 jmcneill goto done;
196 1.1 jmcneill }
197 1.1 jmcneill
198 1.1 jmcneill irq = acpi_res_irq(&res, 0);
199 1.1 jmcneill if (irq == NULL) {
200 1.1 jmcneill aprint_error_dev(self, "couldn't find irq resource\n");
201 1.1 jmcneill goto done;
202 1.1 jmcneill }
203 1.1 jmcneill
204 1.1 jmcneill error = bus_space_map(sc->sc_bst, mem->ar_base, mem->ar_length, 0,
205 1.1 jmcneill &sc->sc_bsh);
206 1.1 jmcneill if (error) {
207 1.1 jmcneill aprint_error_dev(self, "couldn't map registers\n");
208 1.1 jmcneill goto done;
209 1.1 jmcneill }
210 1.1 jmcneill
211 1.4 jmcneill sc->sc_npdcmap = res.ar_nirq;
212 1.4 jmcneill sc->sc_pdcmap = kmem_zalloc(sizeof(*sc->sc_pdcmap) * sc->sc_npdcmap,
213 1.4 jmcneill KM_SLEEP);
214 1.4 jmcneill for (n = 0; n < sc->sc_npdcmap; n++) {
215 1.4 jmcneill sc->sc_pdcmap[n].pm_irq = acpi_res_irq(&res, n)->ar_irq;
216 1.4 jmcneill sc->sc_pdcmap[n].pm_pin = -1;
217 1.4 jmcneill aprint_debug_dev(self, "IRQ resource %u -> %#x\n",
218 1.4 jmcneill n, sc->sc_pdcmap[n].pm_irq);
219 1.4 jmcneill }
220 1.4 jmcneill qcomgpio_acpi_fill_pdcmap(sc, hdl);
221 1.4 jmcneill
222 1.4 jmcneill sc->sc_npins = qcomgpio_acpi_num_pins(self, hdl);
223 1.4 jmcneill if (sc->sc_npins == 0) {
224 1.4 jmcneill aprint_error_dev(self, "couldn't determine pin count!\n");
225 1.4 jmcneill goto done;
226 1.4 jmcneill }
227 1.4 jmcneill sc->sc_pins = kmem_zalloc(sizeof(*sc->sc_pins) * sc->sc_npins,
228 1.4 jmcneill KM_SLEEP);
229 1.4 jmcneill for (pin = 0; pin < sc->sc_npins; pin++) {
230 1.3 jmcneill sc->sc_pins[pin].pin_caps = qcomgpio_pin_reserved(sc, pin) ?
231 1.3 jmcneill 0 : (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT);
232 1.1 jmcneill sc->sc_pins[pin].pin_num = pin;
233 1.1 jmcneill sc->sc_pins[pin].pin_intrcaps =
234 1.1 jmcneill GPIO_INTR_POS_EDGE | GPIO_INTR_NEG_EDGE |
235 1.1 jmcneill GPIO_INTR_DOUBLE_EDGE | GPIO_INTR_HIGH_LEVEL |
236 1.1 jmcneill GPIO_INTR_LOW_LEVEL | GPIO_INTR_MPSAFE;
237 1.1 jmcneill }
238 1.1 jmcneill
239 1.1 jmcneill sc->sc_gc.gp_cookie = sc;
240 1.1 jmcneill sc->sc_gc.gp_pin_read = qcomgpio_pin_read;
241 1.1 jmcneill sc->sc_gc.gp_pin_write = qcomgpio_pin_write;
242 1.1 jmcneill sc->sc_gc.gp_pin_ctl = qcomgpio_pin_ctl;
243 1.1 jmcneill sc->sc_gc.gp_intr_establish = qcomgpio_intr_establish;
244 1.1 jmcneill sc->sc_gc.gp_intr_disestablish = qcomgpio_intr_disestablish;
245 1.1 jmcneill sc->sc_gc.gp_intr_str = qcomgpio_intr_str;
246 1.1 jmcneill sc->sc_gc.gp_intr_mask = qcomgpio_intr_mask;
247 1.1 jmcneill sc->sc_gc.gp_intr_unmask = qcomgpio_intr_unmask;
248 1.1 jmcneill
249 1.1 jmcneill rv = acpi_event_create_gpio(self, hdl, qcomgpio_register_event, sc);
250 1.1 jmcneill if (ACPI_FAILURE(rv)) {
251 1.1 jmcneill if (rv != AE_NOT_FOUND) {
252 1.1 jmcneill aprint_error_dev(self, "failed to create events: %s\n",
253 1.1 jmcneill AcpiFormatException(rv));
254 1.1 jmcneill }
255 1.1 jmcneill goto done;
256 1.1 jmcneill }
257 1.1 jmcneill
258 1.1 jmcneill ih = acpi_intr_establish(self, (uint64_t)(uintptr_t)hdl,
259 1.1 jmcneill IPL_VM, false, qcomgpio_intr, sc, device_xname(self));
260 1.1 jmcneill if (ih == NULL) {
261 1.1 jmcneill aprint_error_dev(self, "couldn't establish interrupt\n");
262 1.1 jmcneill goto done;
263 1.1 jmcneill }
264 1.1 jmcneill
265 1.1 jmcneill memset(&gba, 0, sizeof(gba));
266 1.1 jmcneill gba.gba_gc = &sc->sc_gc;
267 1.1 jmcneill gba.gba_pins = sc->sc_pins;
268 1.4 jmcneill gba.gba_npins = sc->sc_npins;
269 1.1 jmcneill sc->sc_gpiodev = config_found(self, &gba, gpiobus_print,
270 1.1 jmcneill CFARGS(.iattr = "gpiobus"));
271 1.1 jmcneill if (sc->sc_gpiodev != NULL) {
272 1.1 jmcneill acpi_gpio_register(aa->aa_node, self,
273 1.1 jmcneill qcomgpio_acpi_translate, sc);
274 1.1 jmcneill }
275 1.1 jmcneill
276 1.1 jmcneill done:
277 1.1 jmcneill acpi_resource_cleanup(&res);
278 1.1 jmcneill }
279 1.1 jmcneill
280 1.4 jmcneill static u_int
281 1.4 jmcneill qcomgpio_acpi_num_pins(device_t dev, ACPI_HANDLE hdl)
282 1.4 jmcneill {
283 1.4 jmcneill ACPI_STATUS rv;
284 1.4 jmcneill ACPI_INTEGER npins;
285 1.4 jmcneill
286 1.4 jmcneill rv = acpi_dsm_integer(hdl, qcomgpio_gpio_dsm_uuid,
287 1.4 jmcneill QCOMGPIO_GPIO_DSM_REV, QCOMGPIO_GPIO_DSM_FUNC_NUM_PINS,
288 1.4 jmcneill NULL, &npins);
289 1.4 jmcneill if (ACPI_FAILURE(rv)) {
290 1.4 jmcneill aprint_error_dev(dev, "GPIO _DSM failed: %s\n",
291 1.4 jmcneill AcpiFormatException(rv));
292 1.4 jmcneill return 0;
293 1.4 jmcneill }
294 1.4 jmcneill
295 1.4 jmcneill aprint_debug_dev(dev, "GPIO pin count: %u\n", (u_int)npins);
296 1.4 jmcneill
297 1.4 jmcneill return (u_int)npins;
298 1.4 jmcneill }
299 1.4 jmcneill
300 1.4 jmcneill static void
301 1.4 jmcneill qcomgpio_acpi_fill_pdcmap(struct qcomgpio_softc *sc,
302 1.4 jmcneill ACPI_HANDLE hdl)
303 1.4 jmcneill {
304 1.4 jmcneill ACPI_STATUS rv;
305 1.4 jmcneill ACPI_OBJECT *obj;
306 1.4 jmcneill u_int n;
307 1.4 jmcneill
308 1.4 jmcneill rv = acpi_dsm_typed(hdl, qcomgpio_pdc_dsm_uuid,
309 1.4 jmcneill QCOMGPIO_PDC_DSM_REV, QCOMGPIO_PDC_DSM_FUNC_CIPR,
310 1.4 jmcneill NULL, ACPI_TYPE_PACKAGE, &obj);
311 1.4 jmcneill if (ACPI_FAILURE(rv)) {
312 1.4 jmcneill aprint_error_dev(sc->sc_dev, "PDC _DSM failed: %s\n",
313 1.4 jmcneill AcpiFormatException(rv));
314 1.4 jmcneill return;
315 1.4 jmcneill }
316 1.4 jmcneill
317 1.4 jmcneill for (n = 0; n < obj->Package.Count; n++) {
318 1.4 jmcneill ACPI_OBJECT *map = &obj->Package.Elements[n];
319 1.4 jmcneill u_int irq, pdc;
320 1.4 jmcneill int pin;
321 1.4 jmcneill
322 1.4 jmcneill if (map->Type != ACPI_TYPE_PACKAGE ||
323 1.4 jmcneill map->Package.Count < 3 ||
324 1.4 jmcneill map->Package.Elements[0].Type != ACPI_TYPE_INTEGER ||
325 1.4 jmcneill map->Package.Elements[1].Type != ACPI_TYPE_INTEGER ||
326 1.4 jmcneill map->Package.Elements[2].Type != ACPI_TYPE_INTEGER) {
327 1.4 jmcneill continue;
328 1.4 jmcneill }
329 1.4 jmcneill
330 1.4 jmcneill irq = (u_int)map->Package.Elements[2].Integer.Value;
331 1.4 jmcneill pin = (int)map->Package.Elements[1].Integer.Value;
332 1.4 jmcneill for (pdc = 0; pdc < sc->sc_npdcmap; pdc++) {
333 1.4 jmcneill if (sc->sc_pdcmap[pdc].pm_irq == irq) {
334 1.4 jmcneill sc->sc_pdcmap[pdc].pm_pin = pin;
335 1.4 jmcneill break;
336 1.4 jmcneill }
337 1.4 jmcneill }
338 1.4 jmcneill aprint_debug_dev(sc->sc_dev,
339 1.4 jmcneill "PDC irq %#x -> pin %d%s\n", irq, pin,
340 1.4 jmcneill pdc == sc->sc_npdcmap ? " (unused)" : "");
341 1.4 jmcneill }
342 1.4 jmcneill
343 1.4 jmcneill ACPI_FREE(obj);
344 1.4 jmcneill }
345 1.4 jmcneill
346 1.1 jmcneill static int
347 1.2 jmcneill qcomgpio_acpi_translate(void *priv, ACPI_RESOURCE_GPIO *gpio, void **gpiop)
348 1.1 jmcneill {
349 1.1 jmcneill struct qcomgpio_softc * const sc = priv;
350 1.4 jmcneill const ACPI_INTEGER vpin = gpio->PinTable[0];
351 1.4 jmcneill int pin = -1;
352 1.1 jmcneill
353 1.4 jmcneill if (vpin < sc->sc_npins) {
354 1.4 jmcneill /* Virtual pin number is 1:1 mapping with hardware. */
355 1.4 jmcneill pin = vpin;
356 1.4 jmcneill } else if (vpin / 64 < sc->sc_npdcmap) {
357 1.4 jmcneill /* Translate the virtual pin number to a hardware pin. */
358 1.4 jmcneill pin = sc->sc_pdcmap[vpin / 64].pm_pin;
359 1.4 jmcneill }
360 1.1 jmcneill
361 1.4 jmcneill aprint_debug_dev(sc->sc_dev, "translate %#lx -> %u\n", vpin, pin);
362 1.1 jmcneill
363 1.1 jmcneill if (gpiop != NULL) {
364 1.1 jmcneill if (sc->sc_gpiodev != NULL) {
365 1.1 jmcneill *gpiop = device_private(sc->sc_gpiodev);
366 1.1 jmcneill } else {
367 1.1 jmcneill device_printf(sc->sc_dev,
368 1.4 jmcneill "no gpiodev for pin %#lx -> %u\n", vpin, pin);
369 1.4 jmcneill pin = -1;
370 1.1 jmcneill }
371 1.1 jmcneill }
372 1.1 jmcneill
373 1.4 jmcneill return pin;
374 1.1 jmcneill }
375 1.1 jmcneill
376 1.1 jmcneill static int
377 1.1 jmcneill qcomgpio_acpi_event(void *priv)
378 1.1 jmcneill {
379 1.1 jmcneill struct acpi_event * const ev = priv;
380 1.1 jmcneill
381 1.1 jmcneill acpi_event_notify(ev);
382 1.1 jmcneill
383 1.1 jmcneill return 1;
384 1.1 jmcneill }
385 1.1 jmcneill
386 1.1 jmcneill static void
387 1.1 jmcneill qcomgpio_register_event(void *priv, struct acpi_event *ev,
388 1.1 jmcneill ACPI_RESOURCE_GPIO *gpio)
389 1.1 jmcneill {
390 1.1 jmcneill struct qcomgpio_softc * const sc = priv;
391 1.1 jmcneill int irqmode;
392 1.1 jmcneill void *ih;
393 1.1 jmcneill
394 1.2 jmcneill const int pin = qcomgpio_acpi_translate(sc, gpio, NULL);
395 1.1 jmcneill
396 1.1 jmcneill if (pin < 0) {
397 1.1 jmcneill aprint_error_dev(sc->sc_dev,
398 1.1 jmcneill "ignoring event for pin %#x (out of range)\n",
399 1.1 jmcneill gpio->PinTable[0]);
400 1.1 jmcneill return;
401 1.1 jmcneill }
402 1.1 jmcneill
403 1.1 jmcneill if (gpio->Triggering == ACPI_LEVEL_SENSITIVE) {
404 1.1 jmcneill irqmode = gpio->Polarity == ACPI_ACTIVE_HIGH ?
405 1.1 jmcneill GPIO_INTR_HIGH_LEVEL : GPIO_INTR_LOW_LEVEL;
406 1.1 jmcneill } else {
407 1.1 jmcneill KASSERT(gpio->Triggering == ACPI_EDGE_SENSITIVE);
408 1.1 jmcneill if (gpio->Polarity == ACPI_ACTIVE_LOW) {
409 1.1 jmcneill irqmode = GPIO_INTR_NEG_EDGE;
410 1.1 jmcneill } else if (gpio->Polarity == ACPI_ACTIVE_HIGH) {
411 1.1 jmcneill irqmode = GPIO_INTR_POS_EDGE;
412 1.1 jmcneill } else {
413 1.1 jmcneill KASSERT(gpio->Polarity == ACPI_ACTIVE_BOTH);
414 1.1 jmcneill irqmode = GPIO_INTR_DOUBLE_EDGE;
415 1.1 jmcneill }
416 1.1 jmcneill }
417 1.1 jmcneill
418 1.1 jmcneill ih = qcomgpio_intr_establish(sc, pin, IPL_VM, irqmode,
419 1.1 jmcneill qcomgpio_acpi_event, ev);
420 1.1 jmcneill if (ih == NULL) {
421 1.1 jmcneill aprint_error_dev(sc->sc_dev,
422 1.1 jmcneill "couldn't register event for pin %#x\n",
423 1.1 jmcneill gpio->PinTable[0]);
424 1.2 jmcneill return;
425 1.2 jmcneill }
426 1.2 jmcneill if (gpio->Triggering == ACPI_LEVEL_SENSITIVE) {
427 1.2 jmcneill acpi_event_set_intrcookie(ev, ih);
428 1.1 jmcneill }
429 1.1 jmcneill }
430 1.1 jmcneill
431 1.3 jmcneill static bool
432 1.3 jmcneill qcomgpio_pin_reserved(struct qcomgpio_softc *sc, int pin)
433 1.3 jmcneill {
434 1.3 jmcneill u_int n;
435 1.3 jmcneill
436 1.3 jmcneill for (n = 0; n < sc->sc_config->num_reserved; n++) {
437 1.3 jmcneill if (pin >= sc->sc_config->reserved[n].start &&
438 1.3 jmcneill pin < sc->sc_config->reserved[n].start +
439 1.3 jmcneill sc->sc_config->reserved[n].count) {
440 1.3 jmcneill return true;
441 1.3 jmcneill }
442 1.3 jmcneill }
443 1.3 jmcneill
444 1.3 jmcneill return false;
445 1.3 jmcneill }
446 1.3 jmcneill
447 1.1 jmcneill static int
448 1.1 jmcneill qcomgpio_pin_read(void *priv, int pin)
449 1.1 jmcneill {
450 1.1 jmcneill struct qcomgpio_softc * const sc = priv;
451 1.1 jmcneill uint32_t val;
452 1.1 jmcneill
453 1.4 jmcneill if (pin < 0 || pin >= sc->sc_npins) {
454 1.1 jmcneill return 0;
455 1.1 jmcneill }
456 1.2 jmcneill if ((sc->sc_pins[pin].pin_caps & GPIO_PIN_INPUT) == 0) {
457 1.2 jmcneill return 0;
458 1.2 jmcneill }
459 1.1 jmcneill
460 1.1 jmcneill val = RD4(sc, TLMM_GPIO_IN_OUT(pin));
461 1.1 jmcneill return (val & TLMM_GPIO_IN_OUT_GPIO_IN) != 0;
462 1.1 jmcneill }
463 1.1 jmcneill
464 1.1 jmcneill static void
465 1.1 jmcneill qcomgpio_pin_write(void *priv, int pin, int pinval)
466 1.1 jmcneill {
467 1.1 jmcneill struct qcomgpio_softc * const sc = priv;
468 1.1 jmcneill uint32_t val;
469 1.1 jmcneill
470 1.4 jmcneill if (pin < 0 || pin >= sc->sc_npins) {
471 1.1 jmcneill return;
472 1.1 jmcneill }
473 1.2 jmcneill if ((sc->sc_pins[pin].pin_caps & GPIO_PIN_OUTPUT) == 0) {
474 1.2 jmcneill return;
475 1.2 jmcneill }
476 1.1 jmcneill
477 1.1 jmcneill val = RD4(sc, TLMM_GPIO_IN_OUT(pin));
478 1.1 jmcneill if (pinval) {
479 1.1 jmcneill val |= TLMM_GPIO_IN_OUT_GPIO_OUT;
480 1.1 jmcneill } else {
481 1.1 jmcneill val &= ~TLMM_GPIO_IN_OUT_GPIO_OUT;
482 1.1 jmcneill }
483 1.1 jmcneill WR4(sc, TLMM_GPIO_IN_OUT(pin), val);
484 1.1 jmcneill }
485 1.1 jmcneill
486 1.1 jmcneill static void
487 1.1 jmcneill qcomgpio_pin_ctl(void *priv, int pin, int flags)
488 1.1 jmcneill {
489 1.1 jmcneill /* Nothing to do here, as firmware has already configured pins. */
490 1.1 jmcneill }
491 1.1 jmcneill
492 1.1 jmcneill static void *
493 1.1 jmcneill qcomgpio_intr_establish(void *priv, int pin, int ipl, int irqmode,
494 1.1 jmcneill int (*func)(void *), void *arg)
495 1.1 jmcneill {
496 1.1 jmcneill struct qcomgpio_softc * const sc = priv;
497 1.1 jmcneill struct qcomgpio_intr_handler *qih, *qihp;
498 1.1 jmcneill uint32_t dect, pol;
499 1.1 jmcneill uint32_t val;
500 1.1 jmcneill
501 1.4 jmcneill if (pin < 0 || pin >= sc->sc_npins) {
502 1.1 jmcneill return NULL;
503 1.1 jmcneill }
504 1.1 jmcneill if (ipl != IPL_VM) {
505 1.1 jmcneill device_printf(sc->sc_dev, "%s: only IPL_VM supported\n",
506 1.1 jmcneill __func__);
507 1.1 jmcneill return NULL;
508 1.1 jmcneill }
509 1.1 jmcneill
510 1.1 jmcneill qih = kmem_alloc(sizeof(*qih), KM_SLEEP);
511 1.1 jmcneill qih->ih_func = func;
512 1.1 jmcneill qih->ih_arg = arg;
513 1.1 jmcneill qih->ih_pin = pin;
514 1.2 jmcneill qih->ih_type = (irqmode & GPIO_INTR_LEVEL_MASK) != 0 ?
515 1.2 jmcneill IST_LEVEL : IST_EDGE;
516 1.1 jmcneill
517 1.1 jmcneill mutex_enter(&sc->sc_lock);
518 1.1 jmcneill
519 1.1 jmcneill LIST_FOREACH(qihp, &sc->sc_intrs, ih_list) {
520 1.1 jmcneill if (qihp->ih_pin == qih->ih_pin) {
521 1.1 jmcneill mutex_exit(&sc->sc_lock);
522 1.1 jmcneill kmem_free(qih, sizeof(*qih));
523 1.1 jmcneill device_printf(sc->sc_dev,
524 1.1 jmcneill "%s: pin %d already establish\n", __func__, pin);
525 1.1 jmcneill return NULL;
526 1.1 jmcneill }
527 1.1 jmcneill }
528 1.1 jmcneill
529 1.1 jmcneill LIST_INSERT_HEAD(&sc->sc_intrs, qih, ih_list);
530 1.1 jmcneill
531 1.1 jmcneill if ((irqmode & GPIO_INTR_LEVEL_MASK) != 0) {
532 1.1 jmcneill dect = TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_LEVEL;
533 1.1 jmcneill pol = (irqmode & GPIO_INTR_HIGH_LEVEL) != 0 ?
534 1.1 jmcneill TLMM_GPIO_INTR_CFG_INTR_POL_CTL : 0;
535 1.1 jmcneill } else {
536 1.1 jmcneill KASSERT((irqmode & GPIO_INTR_EDGE_MASK) != 0);
537 1.1 jmcneill if ((irqmode & GPIO_INTR_NEG_EDGE) != 0) {
538 1.1 jmcneill dect = TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_EDGE_NEG;
539 1.1 jmcneill pol = TLMM_GPIO_INTR_CFG_INTR_POL_CTL;
540 1.1 jmcneill } else if ((irqmode & GPIO_INTR_POS_EDGE) != 0) {
541 1.1 jmcneill dect = TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_EDGE_POS;
542 1.1 jmcneill pol = TLMM_GPIO_INTR_CFG_INTR_POL_CTL;
543 1.1 jmcneill } else {
544 1.1 jmcneill KASSERT((irqmode & GPIO_INTR_DOUBLE_EDGE) != 0);
545 1.1 jmcneill dect = TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_EDGE_BOTH;
546 1.1 jmcneill pol = 0;
547 1.1 jmcneill }
548 1.1 jmcneill }
549 1.1 jmcneill
550 1.1 jmcneill val = RD4(sc, TLMM_GPIO_INTR_CFG(pin));
551 1.1 jmcneill val &= ~TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_MASK;
552 1.1 jmcneill val |= __SHIFTIN(dect, TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_MASK);
553 1.1 jmcneill val &= ~TLMM_GPIO_INTR_CFG_INTR_POL_CTL;
554 1.1 jmcneill val |= pol;
555 1.1 jmcneill val &= ~TLMM_GPIO_INTR_CFG_TARGET_PROC_MASK;
556 1.1 jmcneill val |= __SHIFTIN(TLMM_GPIO_INTR_CFG_TARGET_PROC_RPM,
557 1.1 jmcneill TLMM_GPIO_INTR_CFG_TARGET_PROC_MASK);
558 1.1 jmcneill val |= TLMM_GPIO_INTR_CFG_INTR_RAW_STATUS_EN;
559 1.1 jmcneill val |= TLMM_GPIO_INTR_CFG_INTR_ENABLE;
560 1.1 jmcneill WR4(sc, TLMM_GPIO_INTR_CFG(pin), val);
561 1.1 jmcneill
562 1.1 jmcneill mutex_exit(&sc->sc_lock);
563 1.1 jmcneill
564 1.1 jmcneill return qih;
565 1.1 jmcneill }
566 1.1 jmcneill
567 1.1 jmcneill static void
568 1.1 jmcneill qcomgpio_intr_disestablish(void *priv, void *ih)
569 1.1 jmcneill {
570 1.1 jmcneill struct qcomgpio_softc * const sc = priv;
571 1.1 jmcneill struct qcomgpio_intr_handler *qih = ih;
572 1.1 jmcneill uint32_t val;
573 1.1 jmcneill
574 1.1 jmcneill mutex_enter(&sc->sc_lock);
575 1.1 jmcneill
576 1.1 jmcneill LIST_REMOVE(qih, ih_list);
577 1.1 jmcneill
578 1.1 jmcneill val = RD4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin));
579 1.1 jmcneill val &= ~TLMM_GPIO_INTR_CFG_INTR_ENABLE;
580 1.1 jmcneill WR4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin), val);
581 1.1 jmcneill
582 1.1 jmcneill mutex_exit(&sc->sc_lock);
583 1.1 jmcneill
584 1.1 jmcneill kmem_free(qih, sizeof(*qih));
585 1.1 jmcneill }
586 1.1 jmcneill
587 1.1 jmcneill static bool
588 1.1 jmcneill qcomgpio_intr_str(void *priv, int pin, int irqmode, char *buf, size_t buflen)
589 1.1 jmcneill {
590 1.1 jmcneill struct qcomgpio_softc * const sc = priv;
591 1.1 jmcneill int rv;
592 1.1 jmcneill
593 1.1 jmcneill rv = snprintf(buf, buflen, "%s pin %d", device_xname(sc->sc_dev), pin);
594 1.1 jmcneill
595 1.1 jmcneill return rv < buflen;
596 1.1 jmcneill }
597 1.1 jmcneill
598 1.1 jmcneill static void
599 1.1 jmcneill qcomgpio_intr_mask(void *priv, void *ih)
600 1.1 jmcneill {
601 1.1 jmcneill struct qcomgpio_softc * const sc = priv;
602 1.1 jmcneill struct qcomgpio_intr_handler *qih = ih;
603 1.1 jmcneill uint32_t val;
604 1.1 jmcneill
605 1.1 jmcneill val = RD4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin));
606 1.2 jmcneill if (qih->ih_type == IST_LEVEL) {
607 1.2 jmcneill val &= ~TLMM_GPIO_INTR_CFG_INTR_RAW_STATUS_EN;
608 1.2 jmcneill }
609 1.1 jmcneill val &= ~TLMM_GPIO_INTR_CFG_INTR_ENABLE;
610 1.1 jmcneill WR4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin), val);
611 1.1 jmcneill }
612 1.1 jmcneill
613 1.1 jmcneill static void
614 1.1 jmcneill qcomgpio_intr_unmask(void *priv, void *ih)
615 1.1 jmcneill {
616 1.1 jmcneill struct qcomgpio_softc * const sc = priv;
617 1.1 jmcneill struct qcomgpio_intr_handler *qih = ih;
618 1.1 jmcneill uint32_t val;
619 1.1 jmcneill
620 1.1 jmcneill val = RD4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin));
621 1.2 jmcneill if (qih->ih_type == IST_LEVEL) {
622 1.2 jmcneill val |= TLMM_GPIO_INTR_CFG_INTR_RAW_STATUS_EN;
623 1.2 jmcneill }
624 1.1 jmcneill val |= TLMM_GPIO_INTR_CFG_INTR_ENABLE;
625 1.1 jmcneill WR4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin), val);
626 1.1 jmcneill }
627 1.1 jmcneill
628 1.1 jmcneill static int
629 1.1 jmcneill qcomgpio_intr(void *priv)
630 1.1 jmcneill {
631 1.1 jmcneill struct qcomgpio_softc * const sc = priv;
632 1.1 jmcneill struct qcomgpio_intr_handler *qih;
633 1.1 jmcneill int rv = 0;
634 1.1 jmcneill
635 1.1 jmcneill mutex_enter(&sc->sc_lock);
636 1.1 jmcneill
637 1.1 jmcneill LIST_FOREACH(qih, &sc->sc_intrs, ih_list) {
638 1.1 jmcneill const int pin = qih->ih_pin;
639 1.1 jmcneill uint32_t val;
640 1.1 jmcneill
641 1.1 jmcneill val = RD4(sc, TLMM_GPIO_INTR_STATUS(pin));
642 1.1 jmcneill if ((val & TLMM_GPIO_INTR_STATUS_INTR_STATUS) != 0) {
643 1.1 jmcneill rv |= qih->ih_func(qih->ih_arg);
644 1.1 jmcneill
645 1.1 jmcneill val &= ~TLMM_GPIO_INTR_STATUS_INTR_STATUS;
646 1.1 jmcneill WR4(sc, TLMM_GPIO_INTR_STATUS(pin), val);
647 1.1 jmcneill }
648 1.1 jmcneill }
649 1.1 jmcneill
650 1.1 jmcneill mutex_exit(&sc->sc_lock);
651 1.1 jmcneill
652 1.1 jmcneill return rv;
653 1.1 jmcneill }
654