qcomgpio.c revision 1.7 1 1.7 riastrad /* $NetBSD: qcomgpio.c,v 1.7 2024/12/17 22:04:57 riastradh Exp $ */
2 1.1 jmcneill
3 1.1 jmcneill /*-
4 1.1 jmcneill * Copyright (c) 2024 The NetBSD Foundation, Inc.
5 1.1 jmcneill * All rights reserved.
6 1.1 jmcneill *
7 1.1 jmcneill * This code is derived from software contributed to The NetBSD Foundation
8 1.1 jmcneill * by Jared McNeill <jmcneill (at) invisible.ca>.
9 1.1 jmcneill *
10 1.1 jmcneill * Redistribution and use in source and binary forms, with or without
11 1.1 jmcneill * modification, are permitted provided that the following conditions
12 1.1 jmcneill * are met:
13 1.1 jmcneill * 1. Redistributions of source code must retain the above copyright
14 1.1 jmcneill * notice, this list of conditions and the following disclaimer.
15 1.1 jmcneill * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 jmcneill * notice, this list of conditions and the following disclaimer in the
17 1.1 jmcneill * documentation and/or other materials provided with the distribution.
18 1.1 jmcneill *
19 1.1 jmcneill * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 1.1 jmcneill * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.1 jmcneill * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.1 jmcneill * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 1.1 jmcneill * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.1 jmcneill * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.1 jmcneill * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.1 jmcneill * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.1 jmcneill * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.1 jmcneill * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.1 jmcneill * POSSIBILITY OF SUCH DAMAGE.
30 1.1 jmcneill */
31 1.1 jmcneill
32 1.1 jmcneill #include <sys/cdefs.h>
33 1.7 riastrad __KERNEL_RCSID(0, "$NetBSD: qcomgpio.c,v 1.7 2024/12/17 22:04:57 riastradh Exp $");
34 1.1 jmcneill
35 1.1 jmcneill #include <sys/param.h>
36 1.7 riastrad #include <sys/types.h>
37 1.7 riastrad
38 1.1 jmcneill #include <sys/bus.h>
39 1.1 jmcneill #include <sys/cpu.h>
40 1.1 jmcneill #include <sys/device.h>
41 1.7 riastrad #include <sys/evcnt.h>
42 1.1 jmcneill #include <sys/gpio.h>
43 1.1 jmcneill #include <sys/kmem.h>
44 1.1 jmcneill #include <sys/mutex.h>
45 1.7 riastrad #include <sys/queue.h>
46 1.1 jmcneill
47 1.7 riastrad #include <dev/acpi/acpi_event.h>
48 1.7 riastrad #include <dev/acpi/acpi_gpio.h>
49 1.7 riastrad #include <dev/acpi/acpi_intr.h>
50 1.1 jmcneill #include <dev/acpi/acpireg.h>
51 1.1 jmcneill #include <dev/acpi/acpivar.h>
52 1.1 jmcneill #include <dev/acpi/qcomgpioreg.h>
53 1.1 jmcneill
54 1.1 jmcneill #include <dev/gpio/gpiovar.h>
55 1.1 jmcneill
56 1.1 jmcneill typedef enum {
57 1.1 jmcneill QCOMGPIO_X1E,
58 1.1 jmcneill } qcomgpio_type;
59 1.1 jmcneill
60 1.3 jmcneill struct qcomgpio_reserved {
61 1.3 jmcneill int start;
62 1.3 jmcneill int count;
63 1.3 jmcneill };
64 1.3 jmcneill
65 1.1 jmcneill struct qcomgpio_config {
66 1.3 jmcneill struct qcomgpio_reserved *reserved;
67 1.3 jmcneill u_int num_reserved;
68 1.5 jmcneill u_int *pdc_filter;
69 1.5 jmcneill u_int num_pdc_filter;
70 1.1 jmcneill };
71 1.1 jmcneill
72 1.1 jmcneill struct qcomgpio_intr_handler {
73 1.1 jmcneill int (*ih_func)(void *);
74 1.1 jmcneill void *ih_arg;
75 1.1 jmcneill int ih_pin;
76 1.2 jmcneill int ih_type;
77 1.6 jmcneill struct evcnt ih_evcnt;
78 1.6 jmcneill char ih_name[16];
79 1.1 jmcneill LIST_ENTRY(qcomgpio_intr_handler) ih_list;
80 1.1 jmcneill };
81 1.1 jmcneill
82 1.4 jmcneill struct qcomgpio_pdcmap {
83 1.4 jmcneill int pm_pin;
84 1.4 jmcneill u_int pm_irq;
85 1.4 jmcneill };
86 1.4 jmcneill
87 1.1 jmcneill struct qcomgpio_softc {
88 1.1 jmcneill device_t sc_dev;
89 1.1 jmcneill device_t sc_gpiodev;
90 1.1 jmcneill bus_space_handle_t sc_bsh;
91 1.1 jmcneill bus_space_tag_t sc_bst;
92 1.1 jmcneill const struct qcomgpio_config *sc_config;
93 1.1 jmcneill struct gpio_chipset_tag sc_gc;
94 1.1 jmcneill gpio_pin_t *sc_pins;
95 1.4 jmcneill u_int sc_npins;
96 1.1 jmcneill LIST_HEAD(, qcomgpio_intr_handler) sc_intrs;
97 1.1 jmcneill kmutex_t sc_lock;
98 1.4 jmcneill
99 1.4 jmcneill struct qcomgpio_pdcmap *sc_pdcmap;
100 1.4 jmcneill u_int sc_npdcmap;
101 1.1 jmcneill };
102 1.1 jmcneill
103 1.1 jmcneill #define RD4(sc, reg) \
104 1.1 jmcneill bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
105 1.1 jmcneill #define WR4(sc, reg, val) \
106 1.1 jmcneill bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
107 1.1 jmcneill
108 1.1 jmcneill static int qcomgpio_match(device_t, cfdata_t, void *);
109 1.1 jmcneill static void qcomgpio_attach(device_t, device_t, void *);
110 1.1 jmcneill
111 1.3 jmcneill static bool qcomgpio_pin_reserved(struct qcomgpio_softc *, int);
112 1.1 jmcneill static int qcomgpio_pin_read(void *, int);
113 1.1 jmcneill static void qcomgpio_pin_write(void *, int, int);
114 1.1 jmcneill static void qcomgpio_pin_ctl(void *, int, int);
115 1.1 jmcneill static void * qcomgpio_intr_establish(void *, int, int, int,
116 1.1 jmcneill int (*)(void *), void *);
117 1.1 jmcneill static void qcomgpio_intr_disestablish(void *, void *);
118 1.1 jmcneill static bool qcomgpio_intr_str(void *, int, int, char *, size_t);
119 1.1 jmcneill static void qcomgpio_intr_mask(void *, void *);
120 1.1 jmcneill static void qcomgpio_intr_unmask(void *, void *);
121 1.1 jmcneill
122 1.4 jmcneill static u_int qcomgpio_acpi_num_pins(device_t, ACPI_HANDLE);
123 1.4 jmcneill static void qcomgpio_acpi_fill_pdcmap(struct qcomgpio_softc *,
124 1.4 jmcneill ACPI_HANDLE);
125 1.2 jmcneill static int qcomgpio_acpi_translate(void *, ACPI_RESOURCE_GPIO *, void **);
126 1.1 jmcneill static void qcomgpio_register_event(void *, struct acpi_event *,
127 1.1 jmcneill ACPI_RESOURCE_GPIO *);
128 1.1 jmcneill static int qcomgpio_intr(void *);
129 1.1 jmcneill
130 1.1 jmcneill CFATTACH_DECL_NEW(qcomgpio, sizeof(struct qcomgpio_softc),
131 1.1 jmcneill qcomgpio_match, qcomgpio_attach, NULL, NULL);
132 1.1 jmcneill
133 1.4 jmcneill static UINT8 qcomgpio_gpio_dsm_uuid[ACPI_UUID_LENGTH] = {
134 1.4 jmcneill 0xa4, 0xb2, 0xb9, 0x98, 0x63, 0x16, 0x5f, 0x4a,
135 1.4 jmcneill 0x82, 0xf2, 0xc6, 0xc9, 0x9a, 0x39, 0x47, 0x26
136 1.4 jmcneill };
137 1.4 jmcneill #define QCOMGPIO_GPIO_DSM_REV 0
138 1.4 jmcneill #define QCOMGPIO_GPIO_DSM_FUNC_NUM_PINS 2
139 1.4 jmcneill
140 1.4 jmcneill static UINT8 qcomgpio_pdc_dsm_uuid[ACPI_UUID_LENGTH] = {
141 1.4 jmcneill 0xd4, 0x0f, 0x1b, 0x92, 0x7c, 0x56, 0xa0, 0x43,
142 1.4 jmcneill 0xbb, 0x14, 0x26, 0x48, 0xf7, 0xb2, 0xa1, 0x8c
143 1.4 jmcneill };
144 1.4 jmcneill #define QCOMGPIO_PDC_DSM_REV 0
145 1.4 jmcneill #define QCOMGPIO_PDC_DSM_FUNC_CIPR 2
146 1.2 jmcneill
147 1.3 jmcneill static struct qcomgpio_reserved qcomgpio_x1e_reserved[] = {
148 1.3 jmcneill { .start = 34, .count = 2 },
149 1.3 jmcneill { .start = 44, .count = 4 },
150 1.3 jmcneill { .start = 72, .count = 2 },
151 1.3 jmcneill { .start = 238, .count = 1 },
152 1.3 jmcneill };
153 1.3 jmcneill
154 1.5 jmcneill static int qcomgpio_x1e_pdc_filter[] = {
155 1.5 jmcneill 0x140, /* Interrupt storm due to missing SMI support. */
156 1.5 jmcneill };
157 1.5 jmcneill
158 1.1 jmcneill static struct qcomgpio_config qcomgpio_x1e_config = {
159 1.3 jmcneill .reserved = qcomgpio_x1e_reserved,
160 1.3 jmcneill .num_reserved = __arraycount(qcomgpio_x1e_reserved),
161 1.5 jmcneill .pdc_filter = qcomgpio_x1e_pdc_filter,
162 1.5 jmcneill .num_pdc_filter = __arraycount(qcomgpio_x1e_pdc_filter),
163 1.1 jmcneill };
164 1.1 jmcneill
165 1.1 jmcneill static const struct device_compatible_entry compat_data[] = {
166 1.1 jmcneill { .compat = "QCOM0C0C", .data = &qcomgpio_x1e_config },
167 1.1 jmcneill DEVICE_COMPAT_EOL
168 1.1 jmcneill };
169 1.1 jmcneill
170 1.1 jmcneill static int
171 1.1 jmcneill qcomgpio_match(device_t parent, cfdata_t cf, void *aux)
172 1.1 jmcneill {
173 1.1 jmcneill struct acpi_attach_args *aa = aux;
174 1.1 jmcneill
175 1.1 jmcneill return acpi_compatible_match(aa, compat_data);
176 1.1 jmcneill }
177 1.1 jmcneill
178 1.1 jmcneill static void
179 1.1 jmcneill qcomgpio_attach(device_t parent, device_t self, void *aux)
180 1.1 jmcneill {
181 1.1 jmcneill struct qcomgpio_softc * const sc = device_private(self);
182 1.1 jmcneill struct acpi_attach_args *aa = aux;
183 1.1 jmcneill struct gpiobus_attach_args gba;
184 1.1 jmcneill ACPI_HANDLE hdl = aa->aa_node->ad_handle;
185 1.1 jmcneill struct acpi_resources res;
186 1.1 jmcneill struct acpi_mem *mem;
187 1.1 jmcneill struct acpi_irq *irq;
188 1.1 jmcneill ACPI_STATUS rv;
189 1.4 jmcneill int error, pin, n;
190 1.1 jmcneill void *ih;
191 1.1 jmcneill
192 1.1 jmcneill sc->sc_dev = self;
193 1.1 jmcneill sc->sc_config = acpi_compatible_lookup(aa, compat_data)->data;
194 1.1 jmcneill sc->sc_bst = aa->aa_memt;
195 1.1 jmcneill KASSERT(sc->sc_config != NULL);
196 1.1 jmcneill LIST_INIT(&sc->sc_intrs);
197 1.1 jmcneill mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM);
198 1.1 jmcneill
199 1.1 jmcneill rv = acpi_resource_parse(sc->sc_dev, hdl, "_CRS",
200 1.1 jmcneill &res, &acpi_resource_parse_ops_default);
201 1.1 jmcneill if (ACPI_FAILURE(rv)) {
202 1.1 jmcneill return;
203 1.1 jmcneill }
204 1.1 jmcneill
205 1.1 jmcneill mem = acpi_res_mem(&res, 0);
206 1.1 jmcneill if (mem == NULL) {
207 1.1 jmcneill aprint_error_dev(self, "couldn't find mem resource\n");
208 1.1 jmcneill goto done;
209 1.1 jmcneill }
210 1.1 jmcneill
211 1.1 jmcneill irq = acpi_res_irq(&res, 0);
212 1.1 jmcneill if (irq == NULL) {
213 1.1 jmcneill aprint_error_dev(self, "couldn't find irq resource\n");
214 1.1 jmcneill goto done;
215 1.1 jmcneill }
216 1.1 jmcneill
217 1.1 jmcneill error = bus_space_map(sc->sc_bst, mem->ar_base, mem->ar_length, 0,
218 1.1 jmcneill &sc->sc_bsh);
219 1.1 jmcneill if (error) {
220 1.1 jmcneill aprint_error_dev(self, "couldn't map registers\n");
221 1.1 jmcneill goto done;
222 1.1 jmcneill }
223 1.1 jmcneill
224 1.4 jmcneill sc->sc_npdcmap = res.ar_nirq;
225 1.4 jmcneill sc->sc_pdcmap = kmem_zalloc(sizeof(*sc->sc_pdcmap) * sc->sc_npdcmap,
226 1.4 jmcneill KM_SLEEP);
227 1.4 jmcneill for (n = 0; n < sc->sc_npdcmap; n++) {
228 1.4 jmcneill sc->sc_pdcmap[n].pm_irq = acpi_res_irq(&res, n)->ar_irq;
229 1.4 jmcneill sc->sc_pdcmap[n].pm_pin = -1;
230 1.4 jmcneill aprint_debug_dev(self, "IRQ resource %u -> %#x\n",
231 1.4 jmcneill n, sc->sc_pdcmap[n].pm_irq);
232 1.4 jmcneill }
233 1.4 jmcneill qcomgpio_acpi_fill_pdcmap(sc, hdl);
234 1.4 jmcneill
235 1.4 jmcneill sc->sc_npins = qcomgpio_acpi_num_pins(self, hdl);
236 1.4 jmcneill if (sc->sc_npins == 0) {
237 1.4 jmcneill aprint_error_dev(self, "couldn't determine pin count!\n");
238 1.4 jmcneill goto done;
239 1.4 jmcneill }
240 1.4 jmcneill sc->sc_pins = kmem_zalloc(sizeof(*sc->sc_pins) * sc->sc_npins,
241 1.4 jmcneill KM_SLEEP);
242 1.4 jmcneill for (pin = 0; pin < sc->sc_npins; pin++) {
243 1.3 jmcneill sc->sc_pins[pin].pin_caps = qcomgpio_pin_reserved(sc, pin) ?
244 1.3 jmcneill 0 : (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT);
245 1.1 jmcneill sc->sc_pins[pin].pin_num = pin;
246 1.1 jmcneill sc->sc_pins[pin].pin_intrcaps =
247 1.1 jmcneill GPIO_INTR_POS_EDGE | GPIO_INTR_NEG_EDGE |
248 1.1 jmcneill GPIO_INTR_DOUBLE_EDGE | GPIO_INTR_HIGH_LEVEL |
249 1.1 jmcneill GPIO_INTR_LOW_LEVEL | GPIO_INTR_MPSAFE;
250 1.1 jmcneill }
251 1.1 jmcneill
252 1.1 jmcneill sc->sc_gc.gp_cookie = sc;
253 1.1 jmcneill sc->sc_gc.gp_pin_read = qcomgpio_pin_read;
254 1.1 jmcneill sc->sc_gc.gp_pin_write = qcomgpio_pin_write;
255 1.1 jmcneill sc->sc_gc.gp_pin_ctl = qcomgpio_pin_ctl;
256 1.1 jmcneill sc->sc_gc.gp_intr_establish = qcomgpio_intr_establish;
257 1.1 jmcneill sc->sc_gc.gp_intr_disestablish = qcomgpio_intr_disestablish;
258 1.1 jmcneill sc->sc_gc.gp_intr_str = qcomgpio_intr_str;
259 1.1 jmcneill sc->sc_gc.gp_intr_mask = qcomgpio_intr_mask;
260 1.1 jmcneill sc->sc_gc.gp_intr_unmask = qcomgpio_intr_unmask;
261 1.1 jmcneill
262 1.1 jmcneill rv = acpi_event_create_gpio(self, hdl, qcomgpio_register_event, sc);
263 1.1 jmcneill if (ACPI_FAILURE(rv)) {
264 1.1 jmcneill if (rv != AE_NOT_FOUND) {
265 1.1 jmcneill aprint_error_dev(self, "failed to create events: %s\n",
266 1.1 jmcneill AcpiFormatException(rv));
267 1.1 jmcneill }
268 1.1 jmcneill goto done;
269 1.1 jmcneill }
270 1.1 jmcneill
271 1.1 jmcneill ih = acpi_intr_establish(self, (uint64_t)(uintptr_t)hdl,
272 1.1 jmcneill IPL_VM, false, qcomgpio_intr, sc, device_xname(self));
273 1.1 jmcneill if (ih == NULL) {
274 1.1 jmcneill aprint_error_dev(self, "couldn't establish interrupt\n");
275 1.1 jmcneill goto done;
276 1.1 jmcneill }
277 1.1 jmcneill
278 1.1 jmcneill memset(&gba, 0, sizeof(gba));
279 1.1 jmcneill gba.gba_gc = &sc->sc_gc;
280 1.1 jmcneill gba.gba_pins = sc->sc_pins;
281 1.4 jmcneill gba.gba_npins = sc->sc_npins;
282 1.1 jmcneill sc->sc_gpiodev = config_found(self, &gba, gpiobus_print,
283 1.1 jmcneill CFARGS(.iattr = "gpiobus"));
284 1.1 jmcneill if (sc->sc_gpiodev != NULL) {
285 1.1 jmcneill acpi_gpio_register(aa->aa_node, self,
286 1.1 jmcneill qcomgpio_acpi_translate, sc);
287 1.1 jmcneill }
288 1.1 jmcneill
289 1.1 jmcneill done:
290 1.1 jmcneill acpi_resource_cleanup(&res);
291 1.1 jmcneill }
292 1.1 jmcneill
293 1.4 jmcneill static u_int
294 1.4 jmcneill qcomgpio_acpi_num_pins(device_t dev, ACPI_HANDLE hdl)
295 1.4 jmcneill {
296 1.4 jmcneill ACPI_STATUS rv;
297 1.4 jmcneill ACPI_INTEGER npins;
298 1.4 jmcneill
299 1.4 jmcneill rv = acpi_dsm_integer(hdl, qcomgpio_gpio_dsm_uuid,
300 1.4 jmcneill QCOMGPIO_GPIO_DSM_REV, QCOMGPIO_GPIO_DSM_FUNC_NUM_PINS,
301 1.4 jmcneill NULL, &npins);
302 1.4 jmcneill if (ACPI_FAILURE(rv)) {
303 1.4 jmcneill aprint_error_dev(dev, "GPIO _DSM failed: %s\n",
304 1.4 jmcneill AcpiFormatException(rv));
305 1.4 jmcneill return 0;
306 1.4 jmcneill }
307 1.4 jmcneill
308 1.4 jmcneill aprint_debug_dev(dev, "GPIO pin count: %u\n", (u_int)npins);
309 1.4 jmcneill
310 1.4 jmcneill return (u_int)npins;
311 1.4 jmcneill }
312 1.4 jmcneill
313 1.4 jmcneill static void
314 1.4 jmcneill qcomgpio_acpi_fill_pdcmap(struct qcomgpio_softc *sc,
315 1.4 jmcneill ACPI_HANDLE hdl)
316 1.4 jmcneill {
317 1.4 jmcneill ACPI_STATUS rv;
318 1.4 jmcneill ACPI_OBJECT *obj;
319 1.5 jmcneill u_int n, filt;
320 1.4 jmcneill
321 1.4 jmcneill rv = acpi_dsm_typed(hdl, qcomgpio_pdc_dsm_uuid,
322 1.4 jmcneill QCOMGPIO_PDC_DSM_REV, QCOMGPIO_PDC_DSM_FUNC_CIPR,
323 1.4 jmcneill NULL, ACPI_TYPE_PACKAGE, &obj);
324 1.4 jmcneill if (ACPI_FAILURE(rv)) {
325 1.4 jmcneill aprint_error_dev(sc->sc_dev, "PDC _DSM failed: %s\n",
326 1.4 jmcneill AcpiFormatException(rv));
327 1.4 jmcneill return;
328 1.4 jmcneill }
329 1.4 jmcneill
330 1.4 jmcneill for (n = 0; n < obj->Package.Count; n++) {
331 1.4 jmcneill ACPI_OBJECT *map = &obj->Package.Elements[n];
332 1.5 jmcneill bool filter = false;
333 1.4 jmcneill u_int irq, pdc;
334 1.4 jmcneill int pin;
335 1.4 jmcneill
336 1.4 jmcneill if (map->Type != ACPI_TYPE_PACKAGE ||
337 1.4 jmcneill map->Package.Count < 3 ||
338 1.4 jmcneill map->Package.Elements[0].Type != ACPI_TYPE_INTEGER ||
339 1.4 jmcneill map->Package.Elements[1].Type != ACPI_TYPE_INTEGER ||
340 1.4 jmcneill map->Package.Elements[2].Type != ACPI_TYPE_INTEGER) {
341 1.4 jmcneill continue;
342 1.4 jmcneill }
343 1.4 jmcneill
344 1.4 jmcneill irq = (u_int)map->Package.Elements[2].Integer.Value;
345 1.4 jmcneill pin = (int)map->Package.Elements[1].Integer.Value;
346 1.4 jmcneill for (pdc = 0; pdc < sc->sc_npdcmap; pdc++) {
347 1.4 jmcneill if (sc->sc_pdcmap[pdc].pm_irq == irq) {
348 1.5 jmcneill for (filt = 0;
349 1.5 jmcneill filt < sc->sc_config->num_pdc_filter;
350 1.5 jmcneill filt++) {
351 1.5 jmcneill if (sc->sc_config->pdc_filter[filt] ==
352 1.5 jmcneill pdc * 64) {
353 1.5 jmcneill filter = true;
354 1.5 jmcneill break;
355 1.5 jmcneill }
356 1.5 jmcneill }
357 1.5 jmcneill
358 1.5 jmcneill if (!filter) {
359 1.5 jmcneill sc->sc_pdcmap[pdc].pm_pin = pin;
360 1.5 jmcneill }
361 1.4 jmcneill break;
362 1.4 jmcneill }
363 1.4 jmcneill }
364 1.5 jmcneill
365 1.4 jmcneill aprint_debug_dev(sc->sc_dev,
366 1.5 jmcneill "PDC irq %#x -> pin %d%s%s\n", irq, pin,
367 1.5 jmcneill filter ? " (filtered)" : "",
368 1.4 jmcneill pdc == sc->sc_npdcmap ? " (unused)" : "");
369 1.4 jmcneill }
370 1.4 jmcneill
371 1.4 jmcneill ACPI_FREE(obj);
372 1.4 jmcneill }
373 1.4 jmcneill
374 1.1 jmcneill static int
375 1.2 jmcneill qcomgpio_acpi_translate(void *priv, ACPI_RESOURCE_GPIO *gpio, void **gpiop)
376 1.1 jmcneill {
377 1.1 jmcneill struct qcomgpio_softc * const sc = priv;
378 1.4 jmcneill const ACPI_INTEGER vpin = gpio->PinTable[0];
379 1.4 jmcneill int pin = -1;
380 1.1 jmcneill
381 1.4 jmcneill if (vpin < sc->sc_npins) {
382 1.4 jmcneill /* Virtual pin number is 1:1 mapping with hardware. */
383 1.4 jmcneill pin = vpin;
384 1.4 jmcneill } else if (vpin / 64 < sc->sc_npdcmap) {
385 1.4 jmcneill /* Translate the virtual pin number to a hardware pin. */
386 1.4 jmcneill pin = sc->sc_pdcmap[vpin / 64].pm_pin;
387 1.4 jmcneill }
388 1.1 jmcneill
389 1.4 jmcneill aprint_debug_dev(sc->sc_dev, "translate %#lx -> %u\n", vpin, pin);
390 1.1 jmcneill
391 1.1 jmcneill if (gpiop != NULL) {
392 1.1 jmcneill if (sc->sc_gpiodev != NULL) {
393 1.1 jmcneill *gpiop = device_private(sc->sc_gpiodev);
394 1.1 jmcneill } else {
395 1.1 jmcneill device_printf(sc->sc_dev,
396 1.4 jmcneill "no gpiodev for pin %#lx -> %u\n", vpin, pin);
397 1.4 jmcneill pin = -1;
398 1.1 jmcneill }
399 1.1 jmcneill }
400 1.1 jmcneill
401 1.4 jmcneill return pin;
402 1.1 jmcneill }
403 1.1 jmcneill
404 1.1 jmcneill static int
405 1.1 jmcneill qcomgpio_acpi_event(void *priv)
406 1.1 jmcneill {
407 1.1 jmcneill struct acpi_event * const ev = priv;
408 1.1 jmcneill
409 1.1 jmcneill acpi_event_notify(ev);
410 1.1 jmcneill
411 1.1 jmcneill return 1;
412 1.1 jmcneill }
413 1.1 jmcneill
414 1.1 jmcneill static void
415 1.1 jmcneill qcomgpio_register_event(void *priv, struct acpi_event *ev,
416 1.1 jmcneill ACPI_RESOURCE_GPIO *gpio)
417 1.1 jmcneill {
418 1.1 jmcneill struct qcomgpio_softc * const sc = priv;
419 1.1 jmcneill int irqmode;
420 1.1 jmcneill void *ih;
421 1.1 jmcneill
422 1.2 jmcneill const int pin = qcomgpio_acpi_translate(sc, gpio, NULL);
423 1.1 jmcneill
424 1.1 jmcneill if (pin < 0) {
425 1.1 jmcneill aprint_error_dev(sc->sc_dev,
426 1.1 jmcneill "ignoring event for pin %#x (out of range)\n",
427 1.1 jmcneill gpio->PinTable[0]);
428 1.1 jmcneill return;
429 1.1 jmcneill }
430 1.1 jmcneill
431 1.1 jmcneill if (gpio->Triggering == ACPI_LEVEL_SENSITIVE) {
432 1.1 jmcneill irqmode = gpio->Polarity == ACPI_ACTIVE_HIGH ?
433 1.1 jmcneill GPIO_INTR_HIGH_LEVEL : GPIO_INTR_LOW_LEVEL;
434 1.1 jmcneill } else {
435 1.1 jmcneill KASSERT(gpio->Triggering == ACPI_EDGE_SENSITIVE);
436 1.1 jmcneill if (gpio->Polarity == ACPI_ACTIVE_LOW) {
437 1.1 jmcneill irqmode = GPIO_INTR_NEG_EDGE;
438 1.1 jmcneill } else if (gpio->Polarity == ACPI_ACTIVE_HIGH) {
439 1.1 jmcneill irqmode = GPIO_INTR_POS_EDGE;
440 1.1 jmcneill } else {
441 1.1 jmcneill KASSERT(gpio->Polarity == ACPI_ACTIVE_BOTH);
442 1.1 jmcneill irqmode = GPIO_INTR_DOUBLE_EDGE;
443 1.1 jmcneill }
444 1.1 jmcneill }
445 1.1 jmcneill
446 1.1 jmcneill ih = qcomgpio_intr_establish(sc, pin, IPL_VM, irqmode,
447 1.1 jmcneill qcomgpio_acpi_event, ev);
448 1.1 jmcneill if (ih == NULL) {
449 1.1 jmcneill aprint_error_dev(sc->sc_dev,
450 1.1 jmcneill "couldn't register event for pin %#x\n",
451 1.1 jmcneill gpio->PinTable[0]);
452 1.2 jmcneill return;
453 1.2 jmcneill }
454 1.2 jmcneill if (gpio->Triggering == ACPI_LEVEL_SENSITIVE) {
455 1.2 jmcneill acpi_event_set_intrcookie(ev, ih);
456 1.1 jmcneill }
457 1.1 jmcneill }
458 1.1 jmcneill
459 1.3 jmcneill static bool
460 1.3 jmcneill qcomgpio_pin_reserved(struct qcomgpio_softc *sc, int pin)
461 1.3 jmcneill {
462 1.3 jmcneill u_int n;
463 1.3 jmcneill
464 1.3 jmcneill for (n = 0; n < sc->sc_config->num_reserved; n++) {
465 1.3 jmcneill if (pin >= sc->sc_config->reserved[n].start &&
466 1.3 jmcneill pin < sc->sc_config->reserved[n].start +
467 1.3 jmcneill sc->sc_config->reserved[n].count) {
468 1.3 jmcneill return true;
469 1.3 jmcneill }
470 1.3 jmcneill }
471 1.3 jmcneill
472 1.3 jmcneill return false;
473 1.3 jmcneill }
474 1.3 jmcneill
475 1.1 jmcneill static int
476 1.1 jmcneill qcomgpio_pin_read(void *priv, int pin)
477 1.1 jmcneill {
478 1.1 jmcneill struct qcomgpio_softc * const sc = priv;
479 1.1 jmcneill uint32_t val;
480 1.1 jmcneill
481 1.4 jmcneill if (pin < 0 || pin >= sc->sc_npins) {
482 1.1 jmcneill return 0;
483 1.1 jmcneill }
484 1.2 jmcneill if ((sc->sc_pins[pin].pin_caps & GPIO_PIN_INPUT) == 0) {
485 1.2 jmcneill return 0;
486 1.2 jmcneill }
487 1.1 jmcneill
488 1.1 jmcneill val = RD4(sc, TLMM_GPIO_IN_OUT(pin));
489 1.1 jmcneill return (val & TLMM_GPIO_IN_OUT_GPIO_IN) != 0;
490 1.1 jmcneill }
491 1.1 jmcneill
492 1.1 jmcneill static void
493 1.1 jmcneill qcomgpio_pin_write(void *priv, int pin, int pinval)
494 1.1 jmcneill {
495 1.1 jmcneill struct qcomgpio_softc * const sc = priv;
496 1.1 jmcneill uint32_t val;
497 1.1 jmcneill
498 1.4 jmcneill if (pin < 0 || pin >= sc->sc_npins) {
499 1.1 jmcneill return;
500 1.1 jmcneill }
501 1.2 jmcneill if ((sc->sc_pins[pin].pin_caps & GPIO_PIN_OUTPUT) == 0) {
502 1.2 jmcneill return;
503 1.2 jmcneill }
504 1.1 jmcneill
505 1.1 jmcneill val = RD4(sc, TLMM_GPIO_IN_OUT(pin));
506 1.1 jmcneill if (pinval) {
507 1.1 jmcneill val |= TLMM_GPIO_IN_OUT_GPIO_OUT;
508 1.1 jmcneill } else {
509 1.1 jmcneill val &= ~TLMM_GPIO_IN_OUT_GPIO_OUT;
510 1.1 jmcneill }
511 1.1 jmcneill WR4(sc, TLMM_GPIO_IN_OUT(pin), val);
512 1.1 jmcneill }
513 1.1 jmcneill
514 1.1 jmcneill static void
515 1.1 jmcneill qcomgpio_pin_ctl(void *priv, int pin, int flags)
516 1.1 jmcneill {
517 1.1 jmcneill /* Nothing to do here, as firmware has already configured pins. */
518 1.1 jmcneill }
519 1.1 jmcneill
520 1.1 jmcneill static void *
521 1.1 jmcneill qcomgpio_intr_establish(void *priv, int pin, int ipl, int irqmode,
522 1.1 jmcneill int (*func)(void *), void *arg)
523 1.1 jmcneill {
524 1.1 jmcneill struct qcomgpio_softc * const sc = priv;
525 1.1 jmcneill struct qcomgpio_intr_handler *qih, *qihp;
526 1.1 jmcneill uint32_t dect, pol;
527 1.1 jmcneill uint32_t val;
528 1.1 jmcneill
529 1.4 jmcneill if (pin < 0 || pin >= sc->sc_npins) {
530 1.1 jmcneill return NULL;
531 1.1 jmcneill }
532 1.1 jmcneill if (ipl != IPL_VM) {
533 1.1 jmcneill device_printf(sc->sc_dev, "%s: only IPL_VM supported\n",
534 1.1 jmcneill __func__);
535 1.1 jmcneill return NULL;
536 1.1 jmcneill }
537 1.1 jmcneill
538 1.1 jmcneill qih = kmem_alloc(sizeof(*qih), KM_SLEEP);
539 1.1 jmcneill qih->ih_func = func;
540 1.1 jmcneill qih->ih_arg = arg;
541 1.1 jmcneill qih->ih_pin = pin;
542 1.2 jmcneill qih->ih_type = (irqmode & GPIO_INTR_LEVEL_MASK) != 0 ?
543 1.2 jmcneill IST_LEVEL : IST_EDGE;
544 1.6 jmcneill snprintf(qih->ih_name, sizeof(qih->ih_name), "pin %d", pin);
545 1.1 jmcneill
546 1.1 jmcneill mutex_enter(&sc->sc_lock);
547 1.1 jmcneill
548 1.1 jmcneill LIST_FOREACH(qihp, &sc->sc_intrs, ih_list) {
549 1.1 jmcneill if (qihp->ih_pin == qih->ih_pin) {
550 1.1 jmcneill mutex_exit(&sc->sc_lock);
551 1.1 jmcneill kmem_free(qih, sizeof(*qih));
552 1.1 jmcneill device_printf(sc->sc_dev,
553 1.1 jmcneill "%s: pin %d already establish\n", __func__, pin);
554 1.1 jmcneill return NULL;
555 1.1 jmcneill }
556 1.1 jmcneill }
557 1.1 jmcneill
558 1.1 jmcneill LIST_INSERT_HEAD(&sc->sc_intrs, qih, ih_list);
559 1.1 jmcneill
560 1.1 jmcneill if ((irqmode & GPIO_INTR_LEVEL_MASK) != 0) {
561 1.1 jmcneill dect = TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_LEVEL;
562 1.1 jmcneill pol = (irqmode & GPIO_INTR_HIGH_LEVEL) != 0 ?
563 1.1 jmcneill TLMM_GPIO_INTR_CFG_INTR_POL_CTL : 0;
564 1.1 jmcneill } else {
565 1.1 jmcneill KASSERT((irqmode & GPIO_INTR_EDGE_MASK) != 0);
566 1.1 jmcneill if ((irqmode & GPIO_INTR_NEG_EDGE) != 0) {
567 1.1 jmcneill dect = TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_EDGE_NEG;
568 1.1 jmcneill pol = TLMM_GPIO_INTR_CFG_INTR_POL_CTL;
569 1.1 jmcneill } else if ((irqmode & GPIO_INTR_POS_EDGE) != 0) {
570 1.1 jmcneill dect = TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_EDGE_POS;
571 1.1 jmcneill pol = TLMM_GPIO_INTR_CFG_INTR_POL_CTL;
572 1.1 jmcneill } else {
573 1.1 jmcneill KASSERT((irqmode & GPIO_INTR_DOUBLE_EDGE) != 0);
574 1.1 jmcneill dect = TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_EDGE_BOTH;
575 1.1 jmcneill pol = 0;
576 1.1 jmcneill }
577 1.1 jmcneill }
578 1.1 jmcneill
579 1.1 jmcneill val = RD4(sc, TLMM_GPIO_INTR_CFG(pin));
580 1.1 jmcneill val &= ~TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_MASK;
581 1.1 jmcneill val |= __SHIFTIN(dect, TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_MASK);
582 1.1 jmcneill val &= ~TLMM_GPIO_INTR_CFG_INTR_POL_CTL;
583 1.1 jmcneill val |= pol;
584 1.1 jmcneill val &= ~TLMM_GPIO_INTR_CFG_TARGET_PROC_MASK;
585 1.1 jmcneill val |= __SHIFTIN(TLMM_GPIO_INTR_CFG_TARGET_PROC_RPM,
586 1.1 jmcneill TLMM_GPIO_INTR_CFG_TARGET_PROC_MASK);
587 1.1 jmcneill val |= TLMM_GPIO_INTR_CFG_INTR_RAW_STATUS_EN;
588 1.1 jmcneill val |= TLMM_GPIO_INTR_CFG_INTR_ENABLE;
589 1.1 jmcneill WR4(sc, TLMM_GPIO_INTR_CFG(pin), val);
590 1.1 jmcneill
591 1.1 jmcneill mutex_exit(&sc->sc_lock);
592 1.1 jmcneill
593 1.6 jmcneill evcnt_attach_dynamic(&qih->ih_evcnt, EVCNT_TYPE_INTR,
594 1.6 jmcneill NULL, device_xname(sc->sc_dev), qih->ih_name);
595 1.6 jmcneill
596 1.1 jmcneill return qih;
597 1.1 jmcneill }
598 1.1 jmcneill
599 1.1 jmcneill static void
600 1.1 jmcneill qcomgpio_intr_disestablish(void *priv, void *ih)
601 1.1 jmcneill {
602 1.1 jmcneill struct qcomgpio_softc * const sc = priv;
603 1.1 jmcneill struct qcomgpio_intr_handler *qih = ih;
604 1.1 jmcneill uint32_t val;
605 1.1 jmcneill
606 1.6 jmcneill evcnt_detach(&qih->ih_evcnt);
607 1.6 jmcneill
608 1.1 jmcneill mutex_enter(&sc->sc_lock);
609 1.1 jmcneill
610 1.1 jmcneill LIST_REMOVE(qih, ih_list);
611 1.1 jmcneill
612 1.1 jmcneill val = RD4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin));
613 1.1 jmcneill val &= ~TLMM_GPIO_INTR_CFG_INTR_ENABLE;
614 1.1 jmcneill WR4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin), val);
615 1.1 jmcneill
616 1.1 jmcneill mutex_exit(&sc->sc_lock);
617 1.1 jmcneill
618 1.1 jmcneill kmem_free(qih, sizeof(*qih));
619 1.1 jmcneill }
620 1.1 jmcneill
621 1.1 jmcneill static bool
622 1.1 jmcneill qcomgpio_intr_str(void *priv, int pin, int irqmode, char *buf, size_t buflen)
623 1.1 jmcneill {
624 1.1 jmcneill struct qcomgpio_softc * const sc = priv;
625 1.1 jmcneill int rv;
626 1.1 jmcneill
627 1.1 jmcneill rv = snprintf(buf, buflen, "%s pin %d", device_xname(sc->sc_dev), pin);
628 1.1 jmcneill
629 1.1 jmcneill return rv < buflen;
630 1.1 jmcneill }
631 1.1 jmcneill
632 1.1 jmcneill static void
633 1.1 jmcneill qcomgpio_intr_mask(void *priv, void *ih)
634 1.1 jmcneill {
635 1.1 jmcneill struct qcomgpio_softc * const sc = priv;
636 1.1 jmcneill struct qcomgpio_intr_handler *qih = ih;
637 1.1 jmcneill uint32_t val;
638 1.1 jmcneill
639 1.1 jmcneill val = RD4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin));
640 1.2 jmcneill if (qih->ih_type == IST_LEVEL) {
641 1.2 jmcneill val &= ~TLMM_GPIO_INTR_CFG_INTR_RAW_STATUS_EN;
642 1.2 jmcneill }
643 1.1 jmcneill val &= ~TLMM_GPIO_INTR_CFG_INTR_ENABLE;
644 1.1 jmcneill WR4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin), val);
645 1.1 jmcneill }
646 1.1 jmcneill
647 1.1 jmcneill static void
648 1.1 jmcneill qcomgpio_intr_unmask(void *priv, void *ih)
649 1.1 jmcneill {
650 1.1 jmcneill struct qcomgpio_softc * const sc = priv;
651 1.1 jmcneill struct qcomgpio_intr_handler *qih = ih;
652 1.1 jmcneill uint32_t val;
653 1.1 jmcneill
654 1.1 jmcneill val = RD4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin));
655 1.2 jmcneill if (qih->ih_type == IST_LEVEL) {
656 1.2 jmcneill val |= TLMM_GPIO_INTR_CFG_INTR_RAW_STATUS_EN;
657 1.2 jmcneill }
658 1.1 jmcneill val |= TLMM_GPIO_INTR_CFG_INTR_ENABLE;
659 1.1 jmcneill WR4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin), val);
660 1.1 jmcneill }
661 1.1 jmcneill
662 1.1 jmcneill static int
663 1.1 jmcneill qcomgpio_intr(void *priv)
664 1.1 jmcneill {
665 1.1 jmcneill struct qcomgpio_softc * const sc = priv;
666 1.1 jmcneill struct qcomgpio_intr_handler *qih;
667 1.1 jmcneill int rv = 0;
668 1.1 jmcneill
669 1.1 jmcneill mutex_enter(&sc->sc_lock);
670 1.1 jmcneill
671 1.1 jmcneill LIST_FOREACH(qih, &sc->sc_intrs, ih_list) {
672 1.1 jmcneill const int pin = qih->ih_pin;
673 1.1 jmcneill uint32_t val;
674 1.1 jmcneill
675 1.1 jmcneill val = RD4(sc, TLMM_GPIO_INTR_STATUS(pin));
676 1.1 jmcneill if ((val & TLMM_GPIO_INTR_STATUS_INTR_STATUS) != 0) {
677 1.6 jmcneill qih->ih_evcnt.ev_count++;
678 1.6 jmcneill
679 1.1 jmcneill rv |= qih->ih_func(qih->ih_arg);
680 1.1 jmcneill
681 1.1 jmcneill val &= ~TLMM_GPIO_INTR_STATUS_INTR_STATUS;
682 1.1 jmcneill WR4(sc, TLMM_GPIO_INTR_STATUS(pin), val);
683 1.1 jmcneill }
684 1.1 jmcneill }
685 1.1 jmcneill
686 1.1 jmcneill mutex_exit(&sc->sc_lock);
687 1.1 jmcneill
688 1.1 jmcneill return rv;
689 1.1 jmcneill }
690