qcomgpio.c revision 1.2
1 /* $NetBSD: qcomgpio.c,v 1.2 2024/12/09 22:10:25 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2024 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jared McNeill <jmcneill (at) invisible.ca>. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: qcomgpio.c,v 1.2 2024/12/09 22:10:25 jmcneill Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/cpu.h> 38 #include <sys/device.h> 39 #include <sys/gpio.h> 40 #include <sys/queue.h> 41 #include <sys/kmem.h> 42 #include <sys/mutex.h> 43 44 #include <dev/acpi/acpireg.h> 45 #include <dev/acpi/acpivar.h> 46 #include <dev/acpi/acpi_intr.h> 47 #include <dev/acpi/acpi_event.h> 48 #include <dev/acpi/acpi_gpio.h> 49 #include <dev/acpi/qcomgpioreg.h> 50 51 #include <dev/gpio/gpiovar.h> 52 53 typedef enum { 54 QCOMGPIO_X1E, 55 } qcomgpio_type; 56 57 struct qcomgpio_config { 58 u_int num_pins; 59 int (*translate)(ACPI_RESOURCE_GPIO *); 60 }; 61 62 struct qcomgpio_intr_handler { 63 int (*ih_func)(void *); 64 void *ih_arg; 65 int ih_pin; 66 int ih_type; 67 LIST_ENTRY(qcomgpio_intr_handler) ih_list; 68 }; 69 70 struct qcomgpio_softc { 71 device_t sc_dev; 72 device_t sc_gpiodev; 73 bus_space_handle_t sc_bsh; 74 bus_space_tag_t sc_bst; 75 const struct qcomgpio_config *sc_config; 76 struct gpio_chipset_tag sc_gc; 77 gpio_pin_t *sc_pins; 78 LIST_HEAD(, qcomgpio_intr_handler) sc_intrs; 79 kmutex_t sc_lock; 80 }; 81 82 #define RD4(sc, reg) \ 83 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 84 #define WR4(sc, reg, val) \ 85 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 86 87 static int qcomgpio_match(device_t, cfdata_t, void *); 88 static void qcomgpio_attach(device_t, device_t, void *); 89 90 static int qcomgpio_pin_read(void *, int); 91 static void qcomgpio_pin_write(void *, int, int); 92 static void qcomgpio_pin_ctl(void *, int, int); 93 static void * qcomgpio_intr_establish(void *, int, int, int, 94 int (*)(void *), void *); 95 static void qcomgpio_intr_disestablish(void *, void *); 96 static bool qcomgpio_intr_str(void *, int, int, char *, size_t); 97 static void qcomgpio_intr_mask(void *, void *); 98 static void qcomgpio_intr_unmask(void *, void *); 99 100 static int qcomgpio_acpi_translate(void *, ACPI_RESOURCE_GPIO *, void **); 101 static void qcomgpio_register_event(void *, struct acpi_event *, 102 ACPI_RESOURCE_GPIO *); 103 static int qcomgpio_intr(void *); 104 105 CFATTACH_DECL_NEW(qcomgpio, sizeof(struct qcomgpio_softc), 106 qcomgpio_match, qcomgpio_attach, NULL, NULL); 107 108 #define X1E_NUM_PINS 239 109 110 static int 111 qcomgpio_x1e_translate(ACPI_RESOURCE_GPIO *gpio) 112 { 113 const ACPI_INTEGER pin = gpio->PinTable[0]; 114 115 if (pin < X1E_NUM_PINS) { 116 return gpio->PinTable[0]; 117 } 118 119 switch (pin) { 120 case 0x180: 121 return 67; 122 case 0x380: 123 return 3; 124 default: 125 return -1; 126 } 127 } 128 129 static struct qcomgpio_config qcomgpio_x1e_config = { 130 .num_pins = X1E_NUM_PINS, 131 .translate = qcomgpio_x1e_translate, 132 }; 133 134 static const struct device_compatible_entry compat_data[] = { 135 { .compat = "QCOM0C0C", .data = &qcomgpio_x1e_config }, 136 DEVICE_COMPAT_EOL 137 }; 138 139 static int 140 qcomgpio_match(device_t parent, cfdata_t cf, void *aux) 141 { 142 struct acpi_attach_args *aa = aux; 143 144 return acpi_compatible_match(aa, compat_data); 145 } 146 147 static void 148 qcomgpio_attach(device_t parent, device_t self, void *aux) 149 { 150 struct qcomgpio_softc * const sc = device_private(self); 151 struct acpi_attach_args *aa = aux; 152 struct gpiobus_attach_args gba; 153 ACPI_HANDLE hdl = aa->aa_node->ad_handle; 154 struct acpi_resources res; 155 struct acpi_mem *mem; 156 struct acpi_irq *irq; 157 ACPI_STATUS rv; 158 int error, pin; 159 void *ih; 160 161 sc->sc_dev = self; 162 sc->sc_config = acpi_compatible_lookup(aa, compat_data)->data; 163 sc->sc_bst = aa->aa_memt; 164 KASSERT(sc->sc_config != NULL); 165 LIST_INIT(&sc->sc_intrs); 166 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 167 168 rv = acpi_resource_parse(sc->sc_dev, hdl, "_CRS", 169 &res, &acpi_resource_parse_ops_default); 170 if (ACPI_FAILURE(rv)) { 171 return; 172 } 173 174 mem = acpi_res_mem(&res, 0); 175 if (mem == NULL) { 176 aprint_error_dev(self, "couldn't find mem resource\n"); 177 goto done; 178 } 179 180 irq = acpi_res_irq(&res, 0); 181 if (irq == NULL) { 182 aprint_error_dev(self, "couldn't find irq resource\n"); 183 goto done; 184 } 185 186 error = bus_space_map(sc->sc_bst, mem->ar_base, mem->ar_length, 0, 187 &sc->sc_bsh); 188 if (error) { 189 aprint_error_dev(self, "couldn't map registers\n"); 190 goto done; 191 } 192 193 sc->sc_pins = kmem_zalloc(sizeof(*sc->sc_pins) * 194 sc->sc_config->num_pins, KM_SLEEP); 195 for (pin = 0; pin < sc->sc_config->num_pins; pin++) { 196 #if notyet 197 uint32_t ctl, func; 198 199 aprint_debuf_dev(self, "pin %u: ", pin); 200 ctl = RD4(sc, TLMM_GPIO_CTL(pin)); 201 func = __SHIFTOUT(ctl, TLMM_GPIO_CTL_MUX); 202 203 sc->sc_pins[pin].pin_caps = 0; 204 if (func == TLMM_GPIO_CTL_MUX_GPIO) { 205 if ((ctl & TLMM_GPIO_CTL_OE) != 0) { 206 sc->sc_pins[pin].pin_caps |= GPIO_PIN_OUTPUT; 207 aprint_debug("gpio output\n"); 208 } else { 209 sc->sc_pins[pin].pin_caps |= GPIO_PIN_INPUT; 210 aprint_debug("gpio input\n"); 211 } 212 } else { 213 aprint_debug("func %#x\n", func); 214 } 215 #else 216 sc->sc_pins[pin].pin_caps = 217 GPIO_PIN_INPUT | GPIO_PIN_OUTPUT; 218 #endif 219 sc->sc_pins[pin].pin_num = pin; 220 sc->sc_pins[pin].pin_intrcaps = 221 GPIO_INTR_POS_EDGE | GPIO_INTR_NEG_EDGE | 222 GPIO_INTR_DOUBLE_EDGE | GPIO_INTR_HIGH_LEVEL | 223 GPIO_INTR_LOW_LEVEL | GPIO_INTR_MPSAFE; 224 225 /* It's not safe to read all pins, so leave pin state unknown */ 226 sc->sc_pins[pin].pin_state = 0; 227 } 228 229 sc->sc_gc.gp_cookie = sc; 230 sc->sc_gc.gp_pin_read = qcomgpio_pin_read; 231 sc->sc_gc.gp_pin_write = qcomgpio_pin_write; 232 sc->sc_gc.gp_pin_ctl = qcomgpio_pin_ctl; 233 sc->sc_gc.gp_intr_establish = qcomgpio_intr_establish; 234 sc->sc_gc.gp_intr_disestablish = qcomgpio_intr_disestablish; 235 sc->sc_gc.gp_intr_str = qcomgpio_intr_str; 236 sc->sc_gc.gp_intr_mask = qcomgpio_intr_mask; 237 sc->sc_gc.gp_intr_unmask = qcomgpio_intr_unmask; 238 239 rv = acpi_event_create_gpio(self, hdl, qcomgpio_register_event, sc); 240 if (ACPI_FAILURE(rv)) { 241 if (rv != AE_NOT_FOUND) { 242 aprint_error_dev(self, "failed to create events: %s\n", 243 AcpiFormatException(rv)); 244 } 245 goto done; 246 } 247 248 ih = acpi_intr_establish(self, (uint64_t)(uintptr_t)hdl, 249 IPL_VM, false, qcomgpio_intr, sc, device_xname(self)); 250 if (ih == NULL) { 251 aprint_error_dev(self, "couldn't establish interrupt\n"); 252 goto done; 253 } 254 255 memset(&gba, 0, sizeof(gba)); 256 gba.gba_gc = &sc->sc_gc; 257 gba.gba_pins = sc->sc_pins; 258 gba.gba_npins = sc->sc_config->num_pins; 259 sc->sc_gpiodev = config_found(self, &gba, gpiobus_print, 260 CFARGS(.iattr = "gpiobus")); 261 if (sc->sc_gpiodev != NULL) { 262 acpi_gpio_register(aa->aa_node, self, 263 qcomgpio_acpi_translate, sc); 264 } 265 266 done: 267 acpi_resource_cleanup(&res); 268 } 269 270 static int 271 qcomgpio_acpi_translate(void *priv, ACPI_RESOURCE_GPIO *gpio, void **gpiop) 272 { 273 struct qcomgpio_softc * const sc = priv; 274 const ACPI_INTEGER pin = gpio->PinTable[0]; 275 int xpin; 276 277 xpin = sc->sc_config->translate(gpio); 278 279 aprint_debug_dev(sc->sc_dev, "translate %#lx -> %u\n", pin, xpin); 280 281 if (gpiop != NULL) { 282 if (sc->sc_gpiodev != NULL) { 283 *gpiop = device_private(sc->sc_gpiodev); 284 } else { 285 device_printf(sc->sc_dev, 286 "no gpiodev for pin %#lx -> %u\n", pin, xpin); 287 xpin = -1; 288 } 289 } 290 291 return xpin; 292 } 293 294 static int 295 qcomgpio_acpi_event(void *priv) 296 { 297 struct acpi_event * const ev = priv; 298 299 acpi_event_notify(ev); 300 301 return 1; 302 } 303 304 static void 305 qcomgpio_register_event(void *priv, struct acpi_event *ev, 306 ACPI_RESOURCE_GPIO *gpio) 307 { 308 struct qcomgpio_softc * const sc = priv; 309 int irqmode; 310 void *ih; 311 312 const int pin = qcomgpio_acpi_translate(sc, gpio, NULL); 313 314 if (pin < 0) { 315 aprint_error_dev(sc->sc_dev, 316 "ignoring event for pin %#x (out of range)\n", 317 gpio->PinTable[0]); 318 return; 319 } 320 321 if (gpio->Triggering == ACPI_LEVEL_SENSITIVE) { 322 irqmode = gpio->Polarity == ACPI_ACTIVE_HIGH ? 323 GPIO_INTR_HIGH_LEVEL : GPIO_INTR_LOW_LEVEL; 324 } else { 325 KASSERT(gpio->Triggering == ACPI_EDGE_SENSITIVE); 326 if (gpio->Polarity == ACPI_ACTIVE_LOW) { 327 irqmode = GPIO_INTR_NEG_EDGE; 328 } else if (gpio->Polarity == ACPI_ACTIVE_HIGH) { 329 irqmode = GPIO_INTR_POS_EDGE; 330 } else { 331 KASSERT(gpio->Polarity == ACPI_ACTIVE_BOTH); 332 irqmode = GPIO_INTR_DOUBLE_EDGE; 333 } 334 } 335 336 ih = qcomgpio_intr_establish(sc, pin, IPL_VM, irqmode, 337 qcomgpio_acpi_event, ev); 338 if (ih == NULL) { 339 aprint_error_dev(sc->sc_dev, 340 "couldn't register event for pin %#x\n", 341 gpio->PinTable[0]); 342 return; 343 } 344 if (gpio->Triggering == ACPI_LEVEL_SENSITIVE) { 345 acpi_event_set_intrcookie(ev, ih); 346 } 347 } 348 349 static int 350 qcomgpio_pin_read(void *priv, int pin) 351 { 352 struct qcomgpio_softc * const sc = priv; 353 uint32_t val; 354 355 if (pin < 0 || pin >= sc->sc_config->num_pins) { 356 return 0; 357 } 358 if ((sc->sc_pins[pin].pin_caps & GPIO_PIN_INPUT) == 0) { 359 return 0; 360 } 361 362 val = RD4(sc, TLMM_GPIO_IN_OUT(pin)); 363 return (val & TLMM_GPIO_IN_OUT_GPIO_IN) != 0; 364 } 365 366 static void 367 qcomgpio_pin_write(void *priv, int pin, int pinval) 368 { 369 struct qcomgpio_softc * const sc = priv; 370 uint32_t val; 371 372 if (pin < 0 || pin >= sc->sc_config->num_pins) { 373 return; 374 } 375 if ((sc->sc_pins[pin].pin_caps & GPIO_PIN_OUTPUT) == 0) { 376 return; 377 } 378 379 val = RD4(sc, TLMM_GPIO_IN_OUT(pin)); 380 if (pinval) { 381 val |= TLMM_GPIO_IN_OUT_GPIO_OUT; 382 } else { 383 val &= ~TLMM_GPIO_IN_OUT_GPIO_OUT; 384 } 385 WR4(sc, TLMM_GPIO_IN_OUT(pin), val); 386 } 387 388 static void 389 qcomgpio_pin_ctl(void *priv, int pin, int flags) 390 { 391 /* Nothing to do here, as firmware has already configured pins. */ 392 } 393 394 static void * 395 qcomgpio_intr_establish(void *priv, int pin, int ipl, int irqmode, 396 int (*func)(void *), void *arg) 397 { 398 struct qcomgpio_softc * const sc = priv; 399 struct qcomgpio_intr_handler *qih, *qihp; 400 uint32_t dect, pol; 401 uint32_t val; 402 403 if (pin < 0 || pin >= sc->sc_config->num_pins) { 404 return NULL; 405 } 406 if (ipl != IPL_VM) { 407 device_printf(sc->sc_dev, "%s: only IPL_VM supported\n", 408 __func__); 409 return NULL; 410 } 411 412 qih = kmem_alloc(sizeof(*qih), KM_SLEEP); 413 qih->ih_func = func; 414 qih->ih_arg = arg; 415 qih->ih_pin = pin; 416 qih->ih_type = (irqmode & GPIO_INTR_LEVEL_MASK) != 0 ? 417 IST_LEVEL : IST_EDGE; 418 419 mutex_enter(&sc->sc_lock); 420 421 LIST_FOREACH(qihp, &sc->sc_intrs, ih_list) { 422 if (qihp->ih_pin == qih->ih_pin) { 423 mutex_exit(&sc->sc_lock); 424 kmem_free(qih, sizeof(*qih)); 425 device_printf(sc->sc_dev, 426 "%s: pin %d already establish\n", __func__, pin); 427 return NULL; 428 } 429 } 430 431 LIST_INSERT_HEAD(&sc->sc_intrs, qih, ih_list); 432 433 if ((irqmode & GPIO_INTR_LEVEL_MASK) != 0) { 434 dect = TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_LEVEL; 435 pol = (irqmode & GPIO_INTR_HIGH_LEVEL) != 0 ? 436 TLMM_GPIO_INTR_CFG_INTR_POL_CTL : 0; 437 } else { 438 KASSERT((irqmode & GPIO_INTR_EDGE_MASK) != 0); 439 if ((irqmode & GPIO_INTR_NEG_EDGE) != 0) { 440 dect = TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_EDGE_NEG; 441 pol = TLMM_GPIO_INTR_CFG_INTR_POL_CTL; 442 } else if ((irqmode & GPIO_INTR_POS_EDGE) != 0) { 443 dect = TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_EDGE_POS; 444 pol = TLMM_GPIO_INTR_CFG_INTR_POL_CTL; 445 } else { 446 KASSERT((irqmode & GPIO_INTR_DOUBLE_EDGE) != 0); 447 dect = TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_EDGE_BOTH; 448 pol = 0; 449 } 450 } 451 452 val = RD4(sc, TLMM_GPIO_INTR_CFG(pin)); 453 val &= ~TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_MASK; 454 val |= __SHIFTIN(dect, TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_MASK); 455 val &= ~TLMM_GPIO_INTR_CFG_INTR_POL_CTL; 456 val |= pol; 457 val &= ~TLMM_GPIO_INTR_CFG_TARGET_PROC_MASK; 458 val |= __SHIFTIN(TLMM_GPIO_INTR_CFG_TARGET_PROC_RPM, 459 TLMM_GPIO_INTR_CFG_TARGET_PROC_MASK); 460 val |= TLMM_GPIO_INTR_CFG_INTR_RAW_STATUS_EN; 461 val |= TLMM_GPIO_INTR_CFG_INTR_ENABLE; 462 WR4(sc, TLMM_GPIO_INTR_CFG(pin), val); 463 464 mutex_exit(&sc->sc_lock); 465 466 return qih; 467 } 468 469 static void 470 qcomgpio_intr_disestablish(void *priv, void *ih) 471 { 472 struct qcomgpio_softc * const sc = priv; 473 struct qcomgpio_intr_handler *qih = ih; 474 uint32_t val; 475 476 mutex_enter(&sc->sc_lock); 477 478 LIST_REMOVE(qih, ih_list); 479 480 val = RD4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin)); 481 val &= ~TLMM_GPIO_INTR_CFG_INTR_ENABLE; 482 WR4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin), val); 483 484 mutex_exit(&sc->sc_lock); 485 486 kmem_free(qih, sizeof(*qih)); 487 } 488 489 static bool 490 qcomgpio_intr_str(void *priv, int pin, int irqmode, char *buf, size_t buflen) 491 { 492 struct qcomgpio_softc * const sc = priv; 493 int rv; 494 495 rv = snprintf(buf, buflen, "%s pin %d", device_xname(sc->sc_dev), pin); 496 497 return rv < buflen; 498 } 499 500 static void 501 qcomgpio_intr_mask(void *priv, void *ih) 502 { 503 struct qcomgpio_softc * const sc = priv; 504 struct qcomgpio_intr_handler *qih = ih; 505 uint32_t val; 506 507 val = RD4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin)); 508 if (qih->ih_type == IST_LEVEL) { 509 val &= ~TLMM_GPIO_INTR_CFG_INTR_RAW_STATUS_EN; 510 } 511 val &= ~TLMM_GPIO_INTR_CFG_INTR_ENABLE; 512 WR4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin), val); 513 } 514 515 static void 516 qcomgpio_intr_unmask(void *priv, void *ih) 517 { 518 struct qcomgpio_softc * const sc = priv; 519 struct qcomgpio_intr_handler *qih = ih; 520 uint32_t val; 521 522 val = RD4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin)); 523 if (qih->ih_type == IST_LEVEL) { 524 val |= TLMM_GPIO_INTR_CFG_INTR_RAW_STATUS_EN; 525 } 526 val |= TLMM_GPIO_INTR_CFG_INTR_ENABLE; 527 WR4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin), val); 528 } 529 530 static int 531 qcomgpio_intr(void *priv) 532 { 533 struct qcomgpio_softc * const sc = priv; 534 struct qcomgpio_intr_handler *qih; 535 int rv = 0; 536 537 mutex_enter(&sc->sc_lock); 538 539 LIST_FOREACH(qih, &sc->sc_intrs, ih_list) { 540 const int pin = qih->ih_pin; 541 uint32_t val; 542 543 val = RD4(sc, TLMM_GPIO_INTR_STATUS(pin)); 544 if ((val & TLMM_GPIO_INTR_STATUS_INTR_STATUS) != 0) { 545 rv |= qih->ih_func(qih->ih_arg); 546 547 val &= ~TLMM_GPIO_INTR_STATUS_INTR_STATUS; 548 WR4(sc, TLMM_GPIO_INTR_STATUS(pin), val); 549 } 550 } 551 552 mutex_exit(&sc->sc_lock); 553 554 return rv; 555 } 556
Indexes created Tue Sep 23 14:10:03 GMT 2025