qcomgpio.c revision 1.3
1 /* $NetBSD: qcomgpio.c,v 1.3 2024/12/11 00:59:16 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2024 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jared McNeill <jmcneill (at) invisible.ca>. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: qcomgpio.c,v 1.3 2024/12/11 00:59:16 jmcneill Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/cpu.h> 38 #include <sys/device.h> 39 #include <sys/gpio.h> 40 #include <sys/queue.h> 41 #include <sys/kmem.h> 42 #include <sys/mutex.h> 43 44 #include <dev/acpi/acpireg.h> 45 #include <dev/acpi/acpivar.h> 46 #include <dev/acpi/acpi_intr.h> 47 #include <dev/acpi/acpi_event.h> 48 #include <dev/acpi/acpi_gpio.h> 49 #include <dev/acpi/qcomgpioreg.h> 50 51 #include <dev/gpio/gpiovar.h> 52 53 typedef enum { 54 QCOMGPIO_X1E, 55 } qcomgpio_type; 56 57 struct qcomgpio_reserved { 58 int start; 59 int count; 60 }; 61 62 struct qcomgpio_config { 63 u_int num_pins; 64 int (*translate)(ACPI_RESOURCE_GPIO *); 65 struct qcomgpio_reserved *reserved; 66 u_int num_reserved; 67 }; 68 69 struct qcomgpio_intr_handler { 70 int (*ih_func)(void *); 71 void *ih_arg; 72 int ih_pin; 73 int ih_type; 74 LIST_ENTRY(qcomgpio_intr_handler) ih_list; 75 }; 76 77 struct qcomgpio_softc { 78 device_t sc_dev; 79 device_t sc_gpiodev; 80 bus_space_handle_t sc_bsh; 81 bus_space_tag_t sc_bst; 82 const struct qcomgpio_config *sc_config; 83 struct gpio_chipset_tag sc_gc; 84 gpio_pin_t *sc_pins; 85 LIST_HEAD(, qcomgpio_intr_handler) sc_intrs; 86 kmutex_t sc_lock; 87 }; 88 89 #define RD4(sc, reg) \ 90 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 91 #define WR4(sc, reg, val) \ 92 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 93 94 static int qcomgpio_match(device_t, cfdata_t, void *); 95 static void qcomgpio_attach(device_t, device_t, void *); 96 97 static bool qcomgpio_pin_reserved(struct qcomgpio_softc *, int); 98 static int qcomgpio_pin_read(void *, int); 99 static void qcomgpio_pin_write(void *, int, int); 100 static void qcomgpio_pin_ctl(void *, int, int); 101 static void * qcomgpio_intr_establish(void *, int, int, int, 102 int (*)(void *), void *); 103 static void qcomgpio_intr_disestablish(void *, void *); 104 static bool qcomgpio_intr_str(void *, int, int, char *, size_t); 105 static void qcomgpio_intr_mask(void *, void *); 106 static void qcomgpio_intr_unmask(void *, void *); 107 108 static int qcomgpio_acpi_translate(void *, ACPI_RESOURCE_GPIO *, void **); 109 static void qcomgpio_register_event(void *, struct acpi_event *, 110 ACPI_RESOURCE_GPIO *); 111 static int qcomgpio_intr(void *); 112 113 CFATTACH_DECL_NEW(qcomgpio, sizeof(struct qcomgpio_softc), 114 qcomgpio_match, qcomgpio_attach, NULL, NULL); 115 116 #define X1E_NUM_PINS 239 117 118 static struct qcomgpio_reserved qcomgpio_x1e_reserved[] = { 119 { .start = 34, .count = 2 }, 120 { .start = 44, .count = 4 }, 121 { .start = 72, .count = 2 }, 122 { .start = 238, .count = 1 }, 123 }; 124 125 static int 126 qcomgpio_x1e_translate(ACPI_RESOURCE_GPIO *gpio) 127 { 128 const ACPI_INTEGER pin = gpio->PinTable[0]; 129 130 if (pin < X1E_NUM_PINS) { 131 return gpio->PinTable[0]; 132 } 133 134 switch (pin) { 135 case 0x180: 136 return 67; 137 case 0x340: 138 return 92; 139 case 0x380: 140 return 3; 141 default: 142 return -1; 143 } 144 } 145 146 static struct qcomgpio_config qcomgpio_x1e_config = { 147 .num_pins = X1E_NUM_PINS, 148 .translate = qcomgpio_x1e_translate, 149 .reserved = qcomgpio_x1e_reserved, 150 .num_reserved = __arraycount(qcomgpio_x1e_reserved), 151 }; 152 153 static const struct device_compatible_entry compat_data[] = { 154 { .compat = "QCOM0C0C", .data = &qcomgpio_x1e_config }, 155 DEVICE_COMPAT_EOL 156 }; 157 158 static int 159 qcomgpio_match(device_t parent, cfdata_t cf, void *aux) 160 { 161 struct acpi_attach_args *aa = aux; 162 163 return acpi_compatible_match(aa, compat_data); 164 } 165 166 static void 167 qcomgpio_attach(device_t parent, device_t self, void *aux) 168 { 169 struct qcomgpio_softc * const sc = device_private(self); 170 struct acpi_attach_args *aa = aux; 171 struct gpiobus_attach_args gba; 172 ACPI_HANDLE hdl = aa->aa_node->ad_handle; 173 struct acpi_resources res; 174 struct acpi_mem *mem; 175 struct acpi_irq *irq; 176 ACPI_STATUS rv; 177 int error, pin; 178 void *ih; 179 180 sc->sc_dev = self; 181 sc->sc_config = acpi_compatible_lookup(aa, compat_data)->data; 182 sc->sc_bst = aa->aa_memt; 183 KASSERT(sc->sc_config != NULL); 184 LIST_INIT(&sc->sc_intrs); 185 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 186 187 rv = acpi_resource_parse(sc->sc_dev, hdl, "_CRS", 188 &res, &acpi_resource_parse_ops_default); 189 if (ACPI_FAILURE(rv)) { 190 return; 191 } 192 193 mem = acpi_res_mem(&res, 0); 194 if (mem == NULL) { 195 aprint_error_dev(self, "couldn't find mem resource\n"); 196 goto done; 197 } 198 199 irq = acpi_res_irq(&res, 0); 200 if (irq == NULL) { 201 aprint_error_dev(self, "couldn't find irq resource\n"); 202 goto done; 203 } 204 205 error = bus_space_map(sc->sc_bst, mem->ar_base, mem->ar_length, 0, 206 &sc->sc_bsh); 207 if (error) { 208 aprint_error_dev(self, "couldn't map registers\n"); 209 goto done; 210 } 211 212 sc->sc_pins = kmem_zalloc(sizeof(*sc->sc_pins) * 213 sc->sc_config->num_pins, KM_SLEEP); 214 for (pin = 0; pin < sc->sc_config->num_pins; pin++) { 215 sc->sc_pins[pin].pin_caps = qcomgpio_pin_reserved(sc, pin) ? 216 0 : (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT); 217 sc->sc_pins[pin].pin_num = pin; 218 sc->sc_pins[pin].pin_intrcaps = 219 GPIO_INTR_POS_EDGE | GPIO_INTR_NEG_EDGE | 220 GPIO_INTR_DOUBLE_EDGE | GPIO_INTR_HIGH_LEVEL | 221 GPIO_INTR_LOW_LEVEL | GPIO_INTR_MPSAFE; 222 } 223 224 sc->sc_gc.gp_cookie = sc; 225 sc->sc_gc.gp_pin_read = qcomgpio_pin_read; 226 sc->sc_gc.gp_pin_write = qcomgpio_pin_write; 227 sc->sc_gc.gp_pin_ctl = qcomgpio_pin_ctl; 228 sc->sc_gc.gp_intr_establish = qcomgpio_intr_establish; 229 sc->sc_gc.gp_intr_disestablish = qcomgpio_intr_disestablish; 230 sc->sc_gc.gp_intr_str = qcomgpio_intr_str; 231 sc->sc_gc.gp_intr_mask = qcomgpio_intr_mask; 232 sc->sc_gc.gp_intr_unmask = qcomgpio_intr_unmask; 233 234 rv = acpi_event_create_gpio(self, hdl, qcomgpio_register_event, sc); 235 if (ACPI_FAILURE(rv)) { 236 if (rv != AE_NOT_FOUND) { 237 aprint_error_dev(self, "failed to create events: %s\n", 238 AcpiFormatException(rv)); 239 } 240 goto done; 241 } 242 243 ih = acpi_intr_establish(self, (uint64_t)(uintptr_t)hdl, 244 IPL_VM, false, qcomgpio_intr, sc, device_xname(self)); 245 if (ih == NULL) { 246 aprint_error_dev(self, "couldn't establish interrupt\n"); 247 goto done; 248 } 249 250 memset(&gba, 0, sizeof(gba)); 251 gba.gba_gc = &sc->sc_gc; 252 gba.gba_pins = sc->sc_pins; 253 gba.gba_npins = sc->sc_config->num_pins; 254 sc->sc_gpiodev = config_found(self, &gba, gpiobus_print, 255 CFARGS(.iattr = "gpiobus")); 256 if (sc->sc_gpiodev != NULL) { 257 acpi_gpio_register(aa->aa_node, self, 258 qcomgpio_acpi_translate, sc); 259 } 260 261 done: 262 acpi_resource_cleanup(&res); 263 } 264 265 static int 266 qcomgpio_acpi_translate(void *priv, ACPI_RESOURCE_GPIO *gpio, void **gpiop) 267 { 268 struct qcomgpio_softc * const sc = priv; 269 const ACPI_INTEGER pin = gpio->PinTable[0]; 270 int xpin; 271 272 xpin = sc->sc_config->translate(gpio); 273 274 aprint_debug_dev(sc->sc_dev, "translate %#lx -> %u\n", pin, xpin); 275 276 if (gpiop != NULL) { 277 if (sc->sc_gpiodev != NULL) { 278 *gpiop = device_private(sc->sc_gpiodev); 279 } else { 280 device_printf(sc->sc_dev, 281 "no gpiodev for pin %#lx -> %u\n", pin, xpin); 282 xpin = -1; 283 } 284 } 285 286 return xpin; 287 } 288 289 static int 290 qcomgpio_acpi_event(void *priv) 291 { 292 struct acpi_event * const ev = priv; 293 294 acpi_event_notify(ev); 295 296 return 1; 297 } 298 299 static void 300 qcomgpio_register_event(void *priv, struct acpi_event *ev, 301 ACPI_RESOURCE_GPIO *gpio) 302 { 303 struct qcomgpio_softc * const sc = priv; 304 int irqmode; 305 void *ih; 306 307 const int pin = qcomgpio_acpi_translate(sc, gpio, NULL); 308 309 if (pin < 0) { 310 aprint_error_dev(sc->sc_dev, 311 "ignoring event for pin %#x (out of range)\n", 312 gpio->PinTable[0]); 313 return; 314 } 315 316 if (gpio->Triggering == ACPI_LEVEL_SENSITIVE) { 317 irqmode = gpio->Polarity == ACPI_ACTIVE_HIGH ? 318 GPIO_INTR_HIGH_LEVEL : GPIO_INTR_LOW_LEVEL; 319 } else { 320 KASSERT(gpio->Triggering == ACPI_EDGE_SENSITIVE); 321 if (gpio->Polarity == ACPI_ACTIVE_LOW) { 322 irqmode = GPIO_INTR_NEG_EDGE; 323 } else if (gpio->Polarity == ACPI_ACTIVE_HIGH) { 324 irqmode = GPIO_INTR_POS_EDGE; 325 } else { 326 KASSERT(gpio->Polarity == ACPI_ACTIVE_BOTH); 327 irqmode = GPIO_INTR_DOUBLE_EDGE; 328 } 329 } 330 331 ih = qcomgpio_intr_establish(sc, pin, IPL_VM, irqmode, 332 qcomgpio_acpi_event, ev); 333 if (ih == NULL) { 334 aprint_error_dev(sc->sc_dev, 335 "couldn't register event for pin %#x\n", 336 gpio->PinTable[0]); 337 return; 338 } 339 if (gpio->Triggering == ACPI_LEVEL_SENSITIVE) { 340 acpi_event_set_intrcookie(ev, ih); 341 } 342 } 343 344 static bool 345 qcomgpio_pin_reserved(struct qcomgpio_softc *sc, int pin) 346 { 347 u_int n; 348 349 for (n = 0; n < sc->sc_config->num_reserved; n++) { 350 if (pin >= sc->sc_config->reserved[n].start && 351 pin < sc->sc_config->reserved[n].start + 352 sc->sc_config->reserved[n].count) { 353 return true; 354 } 355 } 356 357 return false; 358 } 359 360 static int 361 qcomgpio_pin_read(void *priv, int pin) 362 { 363 struct qcomgpio_softc * const sc = priv; 364 uint32_t val; 365 366 if (pin < 0 || pin >= sc->sc_config->num_pins) { 367 return 0; 368 } 369 if ((sc->sc_pins[pin].pin_caps & GPIO_PIN_INPUT) == 0) { 370 return 0; 371 } 372 373 val = RD4(sc, TLMM_GPIO_IN_OUT(pin)); 374 return (val & TLMM_GPIO_IN_OUT_GPIO_IN) != 0; 375 } 376 377 static void 378 qcomgpio_pin_write(void *priv, int pin, int pinval) 379 { 380 struct qcomgpio_softc * const sc = priv; 381 uint32_t val; 382 383 if (pin < 0 || pin >= sc->sc_config->num_pins) { 384 return; 385 } 386 if ((sc->sc_pins[pin].pin_caps & GPIO_PIN_OUTPUT) == 0) { 387 return; 388 } 389 390 val = RD4(sc, TLMM_GPIO_IN_OUT(pin)); 391 if (pinval) { 392 val |= TLMM_GPIO_IN_OUT_GPIO_OUT; 393 } else { 394 val &= ~TLMM_GPIO_IN_OUT_GPIO_OUT; 395 } 396 WR4(sc, TLMM_GPIO_IN_OUT(pin), val); 397 } 398 399 static void 400 qcomgpio_pin_ctl(void *priv, int pin, int flags) 401 { 402 /* Nothing to do here, as firmware has already configured pins. */ 403 } 404 405 static void * 406 qcomgpio_intr_establish(void *priv, int pin, int ipl, int irqmode, 407 int (*func)(void *), void *arg) 408 { 409 struct qcomgpio_softc * const sc = priv; 410 struct qcomgpio_intr_handler *qih, *qihp; 411 uint32_t dect, pol; 412 uint32_t val; 413 414 if (pin < 0 || pin >= sc->sc_config->num_pins) { 415 return NULL; 416 } 417 if (ipl != IPL_VM) { 418 device_printf(sc->sc_dev, "%s: only IPL_VM supported\n", 419 __func__); 420 return NULL; 421 } 422 423 qih = kmem_alloc(sizeof(*qih), KM_SLEEP); 424 qih->ih_func = func; 425 qih->ih_arg = arg; 426 qih->ih_pin = pin; 427 qih->ih_type = (irqmode & GPIO_INTR_LEVEL_MASK) != 0 ? 428 IST_LEVEL : IST_EDGE; 429 430 mutex_enter(&sc->sc_lock); 431 432 LIST_FOREACH(qihp, &sc->sc_intrs, ih_list) { 433 if (qihp->ih_pin == qih->ih_pin) { 434 mutex_exit(&sc->sc_lock); 435 kmem_free(qih, sizeof(*qih)); 436 device_printf(sc->sc_dev, 437 "%s: pin %d already establish\n", __func__, pin); 438 return NULL; 439 } 440 } 441 442 LIST_INSERT_HEAD(&sc->sc_intrs, qih, ih_list); 443 444 if ((irqmode & GPIO_INTR_LEVEL_MASK) != 0) { 445 dect = TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_LEVEL; 446 pol = (irqmode & GPIO_INTR_HIGH_LEVEL) != 0 ? 447 TLMM_GPIO_INTR_CFG_INTR_POL_CTL : 0; 448 } else { 449 KASSERT((irqmode & GPIO_INTR_EDGE_MASK) != 0); 450 if ((irqmode & GPIO_INTR_NEG_EDGE) != 0) { 451 dect = TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_EDGE_NEG; 452 pol = TLMM_GPIO_INTR_CFG_INTR_POL_CTL; 453 } else if ((irqmode & GPIO_INTR_POS_EDGE) != 0) { 454 dect = TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_EDGE_POS; 455 pol = TLMM_GPIO_INTR_CFG_INTR_POL_CTL; 456 } else { 457 KASSERT((irqmode & GPIO_INTR_DOUBLE_EDGE) != 0); 458 dect = TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_EDGE_BOTH; 459 pol = 0; 460 } 461 } 462 463 val = RD4(sc, TLMM_GPIO_INTR_CFG(pin)); 464 val &= ~TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_MASK; 465 val |= __SHIFTIN(dect, TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_MASK); 466 val &= ~TLMM_GPIO_INTR_CFG_INTR_POL_CTL; 467 val |= pol; 468 val &= ~TLMM_GPIO_INTR_CFG_TARGET_PROC_MASK; 469 val |= __SHIFTIN(TLMM_GPIO_INTR_CFG_TARGET_PROC_RPM, 470 TLMM_GPIO_INTR_CFG_TARGET_PROC_MASK); 471 val |= TLMM_GPIO_INTR_CFG_INTR_RAW_STATUS_EN; 472 val |= TLMM_GPIO_INTR_CFG_INTR_ENABLE; 473 WR4(sc, TLMM_GPIO_INTR_CFG(pin), val); 474 475 mutex_exit(&sc->sc_lock); 476 477 return qih; 478 } 479 480 static void 481 qcomgpio_intr_disestablish(void *priv, void *ih) 482 { 483 struct qcomgpio_softc * const sc = priv; 484 struct qcomgpio_intr_handler *qih = ih; 485 uint32_t val; 486 487 mutex_enter(&sc->sc_lock); 488 489 LIST_REMOVE(qih, ih_list); 490 491 val = RD4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin)); 492 val &= ~TLMM_GPIO_INTR_CFG_INTR_ENABLE; 493 WR4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin), val); 494 495 mutex_exit(&sc->sc_lock); 496 497 kmem_free(qih, sizeof(*qih)); 498 } 499 500 static bool 501 qcomgpio_intr_str(void *priv, int pin, int irqmode, char *buf, size_t buflen) 502 { 503 struct qcomgpio_softc * const sc = priv; 504 int rv; 505 506 rv = snprintf(buf, buflen, "%s pin %d", device_xname(sc->sc_dev), pin); 507 508 return rv < buflen; 509 } 510 511 static void 512 qcomgpio_intr_mask(void *priv, void *ih) 513 { 514 struct qcomgpio_softc * const sc = priv; 515 struct qcomgpio_intr_handler *qih = ih; 516 uint32_t val; 517 518 val = RD4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin)); 519 if (qih->ih_type == IST_LEVEL) { 520 val &= ~TLMM_GPIO_INTR_CFG_INTR_RAW_STATUS_EN; 521 } 522 val &= ~TLMM_GPIO_INTR_CFG_INTR_ENABLE; 523 WR4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin), val); 524 } 525 526 static void 527 qcomgpio_intr_unmask(void *priv, void *ih) 528 { 529 struct qcomgpio_softc * const sc = priv; 530 struct qcomgpio_intr_handler *qih = ih; 531 uint32_t val; 532 533 val = RD4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin)); 534 if (qih->ih_type == IST_LEVEL) { 535 val |= TLMM_GPIO_INTR_CFG_INTR_RAW_STATUS_EN; 536 } 537 val |= TLMM_GPIO_INTR_CFG_INTR_ENABLE; 538 WR4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin), val); 539 } 540 541 static int 542 qcomgpio_intr(void *priv) 543 { 544 struct qcomgpio_softc * const sc = priv; 545 struct qcomgpio_intr_handler *qih; 546 int rv = 0; 547 548 mutex_enter(&sc->sc_lock); 549 550 LIST_FOREACH(qih, &sc->sc_intrs, ih_list) { 551 const int pin = qih->ih_pin; 552 uint32_t val; 553 554 val = RD4(sc, TLMM_GPIO_INTR_STATUS(pin)); 555 if ((val & TLMM_GPIO_INTR_STATUS_INTR_STATUS) != 0) { 556 rv |= qih->ih_func(qih->ih_arg); 557 558 val &= ~TLMM_GPIO_INTR_STATUS_INTR_STATUS; 559 WR4(sc, TLMM_GPIO_INTR_STATUS(pin), val); 560 } 561 } 562 563 mutex_exit(&sc->sc_lock); 564 565 return rv; 566 } 567
Indexes created Fri Sep 26 08:10:20 GMT 2025