qcomgpio.c revision 1.4
1 /* $NetBSD: qcomgpio.c,v 1.4 2024/12/12 12:47:57 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2024 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jared McNeill <jmcneill (at) invisible.ca>. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: qcomgpio.c,v 1.4 2024/12/12 12:47:57 jmcneill Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/cpu.h> 38 #include <sys/device.h> 39 #include <sys/gpio.h> 40 #include <sys/queue.h> 41 #include <sys/kmem.h> 42 #include <sys/mutex.h> 43 44 #include <dev/acpi/acpireg.h> 45 #include <dev/acpi/acpivar.h> 46 #include <dev/acpi/acpi_intr.h> 47 #include <dev/acpi/acpi_event.h> 48 #include <dev/acpi/acpi_gpio.h> 49 #include <dev/acpi/qcomgpioreg.h> 50 51 #include <dev/gpio/gpiovar.h> 52 53 typedef enum { 54 QCOMGPIO_X1E, 55 } qcomgpio_type; 56 57 struct qcomgpio_reserved { 58 int start; 59 int count; 60 }; 61 62 struct qcomgpio_config { 63 struct qcomgpio_reserved *reserved; 64 u_int num_reserved; 65 }; 66 67 struct qcomgpio_intr_handler { 68 int (*ih_func)(void *); 69 void *ih_arg; 70 int ih_pin; 71 int ih_type; 72 LIST_ENTRY(qcomgpio_intr_handler) ih_list; 73 }; 74 75 struct qcomgpio_pdcmap { 76 int pm_pin; 77 u_int pm_irq; 78 }; 79 80 struct qcomgpio_softc { 81 device_t sc_dev; 82 device_t sc_gpiodev; 83 bus_space_handle_t sc_bsh; 84 bus_space_tag_t sc_bst; 85 const struct qcomgpio_config *sc_config; 86 struct gpio_chipset_tag sc_gc; 87 gpio_pin_t *sc_pins; 88 u_int sc_npins; 89 LIST_HEAD(, qcomgpio_intr_handler) sc_intrs; 90 kmutex_t sc_lock; 91 92 struct qcomgpio_pdcmap *sc_pdcmap; 93 u_int sc_npdcmap; 94 }; 95 96 #define RD4(sc, reg) \ 97 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 98 #define WR4(sc, reg, val) \ 99 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 100 101 static int qcomgpio_match(device_t, cfdata_t, void *); 102 static void qcomgpio_attach(device_t, device_t, void *); 103 104 static bool qcomgpio_pin_reserved(struct qcomgpio_softc *, int); 105 static int qcomgpio_pin_read(void *, int); 106 static void qcomgpio_pin_write(void *, int, int); 107 static void qcomgpio_pin_ctl(void *, int, int); 108 static void * qcomgpio_intr_establish(void *, int, int, int, 109 int (*)(void *), void *); 110 static void qcomgpio_intr_disestablish(void *, void *); 111 static bool qcomgpio_intr_str(void *, int, int, char *, size_t); 112 static void qcomgpio_intr_mask(void *, void *); 113 static void qcomgpio_intr_unmask(void *, void *); 114 115 static u_int qcomgpio_acpi_num_pins(device_t, ACPI_HANDLE); 116 static void qcomgpio_acpi_fill_pdcmap(struct qcomgpio_softc *, 117 ACPI_HANDLE); 118 static int qcomgpio_acpi_translate(void *, ACPI_RESOURCE_GPIO *, void **); 119 static void qcomgpio_register_event(void *, struct acpi_event *, 120 ACPI_RESOURCE_GPIO *); 121 static int qcomgpio_intr(void *); 122 123 CFATTACH_DECL_NEW(qcomgpio, sizeof(struct qcomgpio_softc), 124 qcomgpio_match, qcomgpio_attach, NULL, NULL); 125 126 static UINT8 qcomgpio_gpio_dsm_uuid[ACPI_UUID_LENGTH] = { 127 0xa4, 0xb2, 0xb9, 0x98, 0x63, 0x16, 0x5f, 0x4a, 128 0x82, 0xf2, 0xc6, 0xc9, 0x9a, 0x39, 0x47, 0x26 129 }; 130 #define QCOMGPIO_GPIO_DSM_REV 0 131 #define QCOMGPIO_GPIO_DSM_FUNC_NUM_PINS 2 132 133 static UINT8 qcomgpio_pdc_dsm_uuid[ACPI_UUID_LENGTH] = { 134 0xd4, 0x0f, 0x1b, 0x92, 0x7c, 0x56, 0xa0, 0x43, 135 0xbb, 0x14, 0x26, 0x48, 0xf7, 0xb2, 0xa1, 0x8c 136 }; 137 #define QCOMGPIO_PDC_DSM_REV 0 138 #define QCOMGPIO_PDC_DSM_FUNC_CIPR 2 139 140 static struct qcomgpio_reserved qcomgpio_x1e_reserved[] = { 141 { .start = 34, .count = 2 }, 142 { .start = 44, .count = 4 }, 143 { .start = 72, .count = 2 }, 144 { .start = 238, .count = 1 }, 145 }; 146 147 static struct qcomgpio_config qcomgpio_x1e_config = { 148 .reserved = qcomgpio_x1e_reserved, 149 .num_reserved = __arraycount(qcomgpio_x1e_reserved), 150 }; 151 152 static const struct device_compatible_entry compat_data[] = { 153 { .compat = "QCOM0C0C", .data = &qcomgpio_x1e_config }, 154 DEVICE_COMPAT_EOL 155 }; 156 157 static int 158 qcomgpio_match(device_t parent, cfdata_t cf, void *aux) 159 { 160 struct acpi_attach_args *aa = aux; 161 162 return acpi_compatible_match(aa, compat_data); 163 } 164 165 static void 166 qcomgpio_attach(device_t parent, device_t self, void *aux) 167 { 168 struct qcomgpio_softc * const sc = device_private(self); 169 struct acpi_attach_args *aa = aux; 170 struct gpiobus_attach_args gba; 171 ACPI_HANDLE hdl = aa->aa_node->ad_handle; 172 struct acpi_resources res; 173 struct acpi_mem *mem; 174 struct acpi_irq *irq; 175 ACPI_STATUS rv; 176 int error, pin, n; 177 void *ih; 178 179 sc->sc_dev = self; 180 sc->sc_config = acpi_compatible_lookup(aa, compat_data)->data; 181 sc->sc_bst = aa->aa_memt; 182 KASSERT(sc->sc_config != NULL); 183 LIST_INIT(&sc->sc_intrs); 184 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 185 186 rv = acpi_resource_parse(sc->sc_dev, hdl, "_CRS", 187 &res, &acpi_resource_parse_ops_default); 188 if (ACPI_FAILURE(rv)) { 189 return; 190 } 191 192 mem = acpi_res_mem(&res, 0); 193 if (mem == NULL) { 194 aprint_error_dev(self, "couldn't find mem resource\n"); 195 goto done; 196 } 197 198 irq = acpi_res_irq(&res, 0); 199 if (irq == NULL) { 200 aprint_error_dev(self, "couldn't find irq resource\n"); 201 goto done; 202 } 203 204 error = bus_space_map(sc->sc_bst, mem->ar_base, mem->ar_length, 0, 205 &sc->sc_bsh); 206 if (error) { 207 aprint_error_dev(self, "couldn't map registers\n"); 208 goto done; 209 } 210 211 sc->sc_npdcmap = res.ar_nirq; 212 sc->sc_pdcmap = kmem_zalloc(sizeof(*sc->sc_pdcmap) * sc->sc_npdcmap, 213 KM_SLEEP); 214 for (n = 0; n < sc->sc_npdcmap; n++) { 215 sc->sc_pdcmap[n].pm_irq = acpi_res_irq(&res, n)->ar_irq; 216 sc->sc_pdcmap[n].pm_pin = -1; 217 aprint_debug_dev(self, "IRQ resource %u -> %#x\n", 218 n, sc->sc_pdcmap[n].pm_irq); 219 } 220 qcomgpio_acpi_fill_pdcmap(sc, hdl); 221 222 sc->sc_npins = qcomgpio_acpi_num_pins(self, hdl); 223 if (sc->sc_npins == 0) { 224 aprint_error_dev(self, "couldn't determine pin count!\n"); 225 goto done; 226 } 227 sc->sc_pins = kmem_zalloc(sizeof(*sc->sc_pins) * sc->sc_npins, 228 KM_SLEEP); 229 for (pin = 0; pin < sc->sc_npins; pin++) { 230 sc->sc_pins[pin].pin_caps = qcomgpio_pin_reserved(sc, pin) ? 231 0 : (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT); 232 sc->sc_pins[pin].pin_num = pin; 233 sc->sc_pins[pin].pin_intrcaps = 234 GPIO_INTR_POS_EDGE | GPIO_INTR_NEG_EDGE | 235 GPIO_INTR_DOUBLE_EDGE | GPIO_INTR_HIGH_LEVEL | 236 GPIO_INTR_LOW_LEVEL | GPIO_INTR_MPSAFE; 237 } 238 239 sc->sc_gc.gp_cookie = sc; 240 sc->sc_gc.gp_pin_read = qcomgpio_pin_read; 241 sc->sc_gc.gp_pin_write = qcomgpio_pin_write; 242 sc->sc_gc.gp_pin_ctl = qcomgpio_pin_ctl; 243 sc->sc_gc.gp_intr_establish = qcomgpio_intr_establish; 244 sc->sc_gc.gp_intr_disestablish = qcomgpio_intr_disestablish; 245 sc->sc_gc.gp_intr_str = qcomgpio_intr_str; 246 sc->sc_gc.gp_intr_mask = qcomgpio_intr_mask; 247 sc->sc_gc.gp_intr_unmask = qcomgpio_intr_unmask; 248 249 rv = acpi_event_create_gpio(self, hdl, qcomgpio_register_event, sc); 250 if (ACPI_FAILURE(rv)) { 251 if (rv != AE_NOT_FOUND) { 252 aprint_error_dev(self, "failed to create events: %s\n", 253 AcpiFormatException(rv)); 254 } 255 goto done; 256 } 257 258 ih = acpi_intr_establish(self, (uint64_t)(uintptr_t)hdl, 259 IPL_VM, false, qcomgpio_intr, sc, device_xname(self)); 260 if (ih == NULL) { 261 aprint_error_dev(self, "couldn't establish interrupt\n"); 262 goto done; 263 } 264 265 memset(&gba, 0, sizeof(gba)); 266 gba.gba_gc = &sc->sc_gc; 267 gba.gba_pins = sc->sc_pins; 268 gba.gba_npins = sc->sc_npins; 269 sc->sc_gpiodev = config_found(self, &gba, gpiobus_print, 270 CFARGS(.iattr = "gpiobus")); 271 if (sc->sc_gpiodev != NULL) { 272 acpi_gpio_register(aa->aa_node, self, 273 qcomgpio_acpi_translate, sc); 274 } 275 276 done: 277 acpi_resource_cleanup(&res); 278 } 279 280 static u_int 281 qcomgpio_acpi_num_pins(device_t dev, ACPI_HANDLE hdl) 282 { 283 ACPI_STATUS rv; 284 ACPI_INTEGER npins; 285 286 rv = acpi_dsm_integer(hdl, qcomgpio_gpio_dsm_uuid, 287 QCOMGPIO_GPIO_DSM_REV, QCOMGPIO_GPIO_DSM_FUNC_NUM_PINS, 288 NULL, &npins); 289 if (ACPI_FAILURE(rv)) { 290 aprint_error_dev(dev, "GPIO _DSM failed: %s\n", 291 AcpiFormatException(rv)); 292 return 0; 293 } 294 295 aprint_debug_dev(dev, "GPIO pin count: %u\n", (u_int)npins); 296 297 return (u_int)npins; 298 } 299 300 static void 301 qcomgpio_acpi_fill_pdcmap(struct qcomgpio_softc *sc, 302 ACPI_HANDLE hdl) 303 { 304 ACPI_STATUS rv; 305 ACPI_OBJECT *obj; 306 u_int n; 307 308 rv = acpi_dsm_typed(hdl, qcomgpio_pdc_dsm_uuid, 309 QCOMGPIO_PDC_DSM_REV, QCOMGPIO_PDC_DSM_FUNC_CIPR, 310 NULL, ACPI_TYPE_PACKAGE, &obj); 311 if (ACPI_FAILURE(rv)) { 312 aprint_error_dev(sc->sc_dev, "PDC _DSM failed: %s\n", 313 AcpiFormatException(rv)); 314 return; 315 } 316 317 for (n = 0; n < obj->Package.Count; n++) { 318 ACPI_OBJECT *map = &obj->Package.Elements[n]; 319 u_int irq, pdc; 320 int pin; 321 322 if (map->Type != ACPI_TYPE_PACKAGE || 323 map->Package.Count < 3 || 324 map->Package.Elements[0].Type != ACPI_TYPE_INTEGER || 325 map->Package.Elements[1].Type != ACPI_TYPE_INTEGER || 326 map->Package.Elements[2].Type != ACPI_TYPE_INTEGER) { 327 continue; 328 } 329 330 irq = (u_int)map->Package.Elements[2].Integer.Value; 331 pin = (int)map->Package.Elements[1].Integer.Value; 332 for (pdc = 0; pdc < sc->sc_npdcmap; pdc++) { 333 if (sc->sc_pdcmap[pdc].pm_irq == irq) { 334 sc->sc_pdcmap[pdc].pm_pin = pin; 335 break; 336 } 337 } 338 aprint_debug_dev(sc->sc_dev, 339 "PDC irq %#x -> pin %d%s\n", irq, pin, 340 pdc == sc->sc_npdcmap ? " (unused)" : ""); 341 } 342 343 ACPI_FREE(obj); 344 } 345 346 static int 347 qcomgpio_acpi_translate(void *priv, ACPI_RESOURCE_GPIO *gpio, void **gpiop) 348 { 349 struct qcomgpio_softc * const sc = priv; 350 const ACPI_INTEGER vpin = gpio->PinTable[0]; 351 int pin = -1; 352 353 if (vpin < sc->sc_npins) { 354 /* Virtual pin number is 1:1 mapping with hardware. */ 355 pin = vpin; 356 } else if (vpin / 64 < sc->sc_npdcmap) { 357 /* Translate the virtual pin number to a hardware pin. */ 358 pin = sc->sc_pdcmap[vpin / 64].pm_pin; 359 } 360 361 aprint_debug_dev(sc->sc_dev, "translate %#lx -> %u\n", vpin, pin); 362 363 if (gpiop != NULL) { 364 if (sc->sc_gpiodev != NULL) { 365 *gpiop = device_private(sc->sc_gpiodev); 366 } else { 367 device_printf(sc->sc_dev, 368 "no gpiodev for pin %#lx -> %u\n", vpin, pin); 369 pin = -1; 370 } 371 } 372 373 return pin; 374 } 375 376 static int 377 qcomgpio_acpi_event(void *priv) 378 { 379 struct acpi_event * const ev = priv; 380 381 acpi_event_notify(ev); 382 383 return 1; 384 } 385 386 static void 387 qcomgpio_register_event(void *priv, struct acpi_event *ev, 388 ACPI_RESOURCE_GPIO *gpio) 389 { 390 struct qcomgpio_softc * const sc = priv; 391 int irqmode; 392 void *ih; 393 394 const int pin = qcomgpio_acpi_translate(sc, gpio, NULL); 395 396 if (pin < 0) { 397 aprint_error_dev(sc->sc_dev, 398 "ignoring event for pin %#x (out of range)\n", 399 gpio->PinTable[0]); 400 return; 401 } 402 403 if (gpio->Triggering == ACPI_LEVEL_SENSITIVE) { 404 irqmode = gpio->Polarity == ACPI_ACTIVE_HIGH ? 405 GPIO_INTR_HIGH_LEVEL : GPIO_INTR_LOW_LEVEL; 406 } else { 407 KASSERT(gpio->Triggering == ACPI_EDGE_SENSITIVE); 408 if (gpio->Polarity == ACPI_ACTIVE_LOW) { 409 irqmode = GPIO_INTR_NEG_EDGE; 410 } else if (gpio->Polarity == ACPI_ACTIVE_HIGH) { 411 irqmode = GPIO_INTR_POS_EDGE; 412 } else { 413 KASSERT(gpio->Polarity == ACPI_ACTIVE_BOTH); 414 irqmode = GPIO_INTR_DOUBLE_EDGE; 415 } 416 } 417 418 ih = qcomgpio_intr_establish(sc, pin, IPL_VM, irqmode, 419 qcomgpio_acpi_event, ev); 420 if (ih == NULL) { 421 aprint_error_dev(sc->sc_dev, 422 "couldn't register event for pin %#x\n", 423 gpio->PinTable[0]); 424 return; 425 } 426 if (gpio->Triggering == ACPI_LEVEL_SENSITIVE) { 427 acpi_event_set_intrcookie(ev, ih); 428 } 429 } 430 431 static bool 432 qcomgpio_pin_reserved(struct qcomgpio_softc *sc, int pin) 433 { 434 u_int n; 435 436 for (n = 0; n < sc->sc_config->num_reserved; n++) { 437 if (pin >= sc->sc_config->reserved[n].start && 438 pin < sc->sc_config->reserved[n].start + 439 sc->sc_config->reserved[n].count) { 440 return true; 441 } 442 } 443 444 return false; 445 } 446 447 static int 448 qcomgpio_pin_read(void *priv, int pin) 449 { 450 struct qcomgpio_softc * const sc = priv; 451 uint32_t val; 452 453 if (pin < 0 || pin >= sc->sc_npins) { 454 return 0; 455 } 456 if ((sc->sc_pins[pin].pin_caps & GPIO_PIN_INPUT) == 0) { 457 return 0; 458 } 459 460 val = RD4(sc, TLMM_GPIO_IN_OUT(pin)); 461 return (val & TLMM_GPIO_IN_OUT_GPIO_IN) != 0; 462 } 463 464 static void 465 qcomgpio_pin_write(void *priv, int pin, int pinval) 466 { 467 struct qcomgpio_softc * const sc = priv; 468 uint32_t val; 469 470 if (pin < 0 || pin >= sc->sc_npins) { 471 return; 472 } 473 if ((sc->sc_pins[pin].pin_caps & GPIO_PIN_OUTPUT) == 0) { 474 return; 475 } 476 477 val = RD4(sc, TLMM_GPIO_IN_OUT(pin)); 478 if (pinval) { 479 val |= TLMM_GPIO_IN_OUT_GPIO_OUT; 480 } else { 481 val &= ~TLMM_GPIO_IN_OUT_GPIO_OUT; 482 } 483 WR4(sc, TLMM_GPIO_IN_OUT(pin), val); 484 } 485 486 static void 487 qcomgpio_pin_ctl(void *priv, int pin, int flags) 488 { 489 /* Nothing to do here, as firmware has already configured pins. */ 490 } 491 492 static void * 493 qcomgpio_intr_establish(void *priv, int pin, int ipl, int irqmode, 494 int (*func)(void *), void *arg) 495 { 496 struct qcomgpio_softc * const sc = priv; 497 struct qcomgpio_intr_handler *qih, *qihp; 498 uint32_t dect, pol; 499 uint32_t val; 500 501 if (pin < 0 || pin >= sc->sc_npins) { 502 return NULL; 503 } 504 if (ipl != IPL_VM) { 505 device_printf(sc->sc_dev, "%s: only IPL_VM supported\n", 506 __func__); 507 return NULL; 508 } 509 510 qih = kmem_alloc(sizeof(*qih), KM_SLEEP); 511 qih->ih_func = func; 512 qih->ih_arg = arg; 513 qih->ih_pin = pin; 514 qih->ih_type = (irqmode & GPIO_INTR_LEVEL_MASK) != 0 ? 515 IST_LEVEL : IST_EDGE; 516 517 mutex_enter(&sc->sc_lock); 518 519 LIST_FOREACH(qihp, &sc->sc_intrs, ih_list) { 520 if (qihp->ih_pin == qih->ih_pin) { 521 mutex_exit(&sc->sc_lock); 522 kmem_free(qih, sizeof(*qih)); 523 device_printf(sc->sc_dev, 524 "%s: pin %d already establish\n", __func__, pin); 525 return NULL; 526 } 527 } 528 529 LIST_INSERT_HEAD(&sc->sc_intrs, qih, ih_list); 530 531 if ((irqmode & GPIO_INTR_LEVEL_MASK) != 0) { 532 dect = TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_LEVEL; 533 pol = (irqmode & GPIO_INTR_HIGH_LEVEL) != 0 ? 534 TLMM_GPIO_INTR_CFG_INTR_POL_CTL : 0; 535 } else { 536 KASSERT((irqmode & GPIO_INTR_EDGE_MASK) != 0); 537 if ((irqmode & GPIO_INTR_NEG_EDGE) != 0) { 538 dect = TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_EDGE_NEG; 539 pol = TLMM_GPIO_INTR_CFG_INTR_POL_CTL; 540 } else if ((irqmode & GPIO_INTR_POS_EDGE) != 0) { 541 dect = TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_EDGE_POS; 542 pol = TLMM_GPIO_INTR_CFG_INTR_POL_CTL; 543 } else { 544 KASSERT((irqmode & GPIO_INTR_DOUBLE_EDGE) != 0); 545 dect = TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_EDGE_BOTH; 546 pol = 0; 547 } 548 } 549 550 val = RD4(sc, TLMM_GPIO_INTR_CFG(pin)); 551 val &= ~TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_MASK; 552 val |= __SHIFTIN(dect, TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_MASK); 553 val &= ~TLMM_GPIO_INTR_CFG_INTR_POL_CTL; 554 val |= pol; 555 val &= ~TLMM_GPIO_INTR_CFG_TARGET_PROC_MASK; 556 val |= __SHIFTIN(TLMM_GPIO_INTR_CFG_TARGET_PROC_RPM, 557 TLMM_GPIO_INTR_CFG_TARGET_PROC_MASK); 558 val |= TLMM_GPIO_INTR_CFG_INTR_RAW_STATUS_EN; 559 val |= TLMM_GPIO_INTR_CFG_INTR_ENABLE; 560 WR4(sc, TLMM_GPIO_INTR_CFG(pin), val); 561 562 mutex_exit(&sc->sc_lock); 563 564 return qih; 565 } 566 567 static void 568 qcomgpio_intr_disestablish(void *priv, void *ih) 569 { 570 struct qcomgpio_softc * const sc = priv; 571 struct qcomgpio_intr_handler *qih = ih; 572 uint32_t val; 573 574 mutex_enter(&sc->sc_lock); 575 576 LIST_REMOVE(qih, ih_list); 577 578 val = RD4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin)); 579 val &= ~TLMM_GPIO_INTR_CFG_INTR_ENABLE; 580 WR4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin), val); 581 582 mutex_exit(&sc->sc_lock); 583 584 kmem_free(qih, sizeof(*qih)); 585 } 586 587 static bool 588 qcomgpio_intr_str(void *priv, int pin, int irqmode, char *buf, size_t buflen) 589 { 590 struct qcomgpio_softc * const sc = priv; 591 int rv; 592 593 rv = snprintf(buf, buflen, "%s pin %d", device_xname(sc->sc_dev), pin); 594 595 return rv < buflen; 596 } 597 598 static void 599 qcomgpio_intr_mask(void *priv, void *ih) 600 { 601 struct qcomgpio_softc * const sc = priv; 602 struct qcomgpio_intr_handler *qih = ih; 603 uint32_t val; 604 605 val = RD4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin)); 606 if (qih->ih_type == IST_LEVEL) { 607 val &= ~TLMM_GPIO_INTR_CFG_INTR_RAW_STATUS_EN; 608 } 609 val &= ~TLMM_GPIO_INTR_CFG_INTR_ENABLE; 610 WR4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin), val); 611 } 612 613 static void 614 qcomgpio_intr_unmask(void *priv, void *ih) 615 { 616 struct qcomgpio_softc * const sc = priv; 617 struct qcomgpio_intr_handler *qih = ih; 618 uint32_t val; 619 620 val = RD4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin)); 621 if (qih->ih_type == IST_LEVEL) { 622 val |= TLMM_GPIO_INTR_CFG_INTR_RAW_STATUS_EN; 623 } 624 val |= TLMM_GPIO_INTR_CFG_INTR_ENABLE; 625 WR4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin), val); 626 } 627 628 static int 629 qcomgpio_intr(void *priv) 630 { 631 struct qcomgpio_softc * const sc = priv; 632 struct qcomgpio_intr_handler *qih; 633 int rv = 0; 634 635 mutex_enter(&sc->sc_lock); 636 637 LIST_FOREACH(qih, &sc->sc_intrs, ih_list) { 638 const int pin = qih->ih_pin; 639 uint32_t val; 640 641 val = RD4(sc, TLMM_GPIO_INTR_STATUS(pin)); 642 if ((val & TLMM_GPIO_INTR_STATUS_INTR_STATUS) != 0) { 643 rv |= qih->ih_func(qih->ih_arg); 644 645 val &= ~TLMM_GPIO_INTR_STATUS_INTR_STATUS; 646 WR4(sc, TLMM_GPIO_INTR_STATUS(pin), val); 647 } 648 } 649 650 mutex_exit(&sc->sc_lock); 651 652 return rv; 653 } 654
Indexes created Wed Sep 24 05:09:52 GMT 2025