qcomgpio.c revision 1.5
1 /* $NetBSD: qcomgpio.c,v 1.5 2024/12/12 21:51:19 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2024 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jared McNeill <jmcneill (at) invisible.ca>. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: qcomgpio.c,v 1.5 2024/12/12 21:51:19 jmcneill Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/cpu.h> 38 #include <sys/device.h> 39 #include <sys/gpio.h> 40 #include <sys/queue.h> 41 #include <sys/kmem.h> 42 #include <sys/mutex.h> 43 44 #include <dev/acpi/acpireg.h> 45 #include <dev/acpi/acpivar.h> 46 #include <dev/acpi/acpi_intr.h> 47 #include <dev/acpi/acpi_event.h> 48 #include <dev/acpi/acpi_gpio.h> 49 #include <dev/acpi/qcomgpioreg.h> 50 51 #include <dev/gpio/gpiovar.h> 52 53 typedef enum { 54 QCOMGPIO_X1E, 55 } qcomgpio_type; 56 57 struct qcomgpio_reserved { 58 int start; 59 int count; 60 }; 61 62 struct qcomgpio_config { 63 struct qcomgpio_reserved *reserved; 64 u_int num_reserved; 65 u_int *pdc_filter; 66 u_int num_pdc_filter; 67 }; 68 69 struct qcomgpio_intr_handler { 70 int (*ih_func)(void *); 71 void *ih_arg; 72 int ih_pin; 73 int ih_type; 74 LIST_ENTRY(qcomgpio_intr_handler) ih_list; 75 }; 76 77 struct qcomgpio_pdcmap { 78 int pm_pin; 79 u_int pm_irq; 80 }; 81 82 struct qcomgpio_softc { 83 device_t sc_dev; 84 device_t sc_gpiodev; 85 bus_space_handle_t sc_bsh; 86 bus_space_tag_t sc_bst; 87 const struct qcomgpio_config *sc_config; 88 struct gpio_chipset_tag sc_gc; 89 gpio_pin_t *sc_pins; 90 u_int sc_npins; 91 LIST_HEAD(, qcomgpio_intr_handler) sc_intrs; 92 kmutex_t sc_lock; 93 94 struct qcomgpio_pdcmap *sc_pdcmap; 95 u_int sc_npdcmap; 96 }; 97 98 #define RD4(sc, reg) \ 99 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 100 #define WR4(sc, reg, val) \ 101 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 102 103 static int qcomgpio_match(device_t, cfdata_t, void *); 104 static void qcomgpio_attach(device_t, device_t, void *); 105 106 static bool qcomgpio_pin_reserved(struct qcomgpio_softc *, int); 107 static int qcomgpio_pin_read(void *, int); 108 static void qcomgpio_pin_write(void *, int, int); 109 static void qcomgpio_pin_ctl(void *, int, int); 110 static void * qcomgpio_intr_establish(void *, int, int, int, 111 int (*)(void *), void *); 112 static void qcomgpio_intr_disestablish(void *, void *); 113 static bool qcomgpio_intr_str(void *, int, int, char *, size_t); 114 static void qcomgpio_intr_mask(void *, void *); 115 static void qcomgpio_intr_unmask(void *, void *); 116 117 static u_int qcomgpio_acpi_num_pins(device_t, ACPI_HANDLE); 118 static void qcomgpio_acpi_fill_pdcmap(struct qcomgpio_softc *, 119 ACPI_HANDLE); 120 static int qcomgpio_acpi_translate(void *, ACPI_RESOURCE_GPIO *, void **); 121 static void qcomgpio_register_event(void *, struct acpi_event *, 122 ACPI_RESOURCE_GPIO *); 123 static int qcomgpio_intr(void *); 124 125 CFATTACH_DECL_NEW(qcomgpio, sizeof(struct qcomgpio_softc), 126 qcomgpio_match, qcomgpio_attach, NULL, NULL); 127 128 static UINT8 qcomgpio_gpio_dsm_uuid[ACPI_UUID_LENGTH] = { 129 0xa4, 0xb2, 0xb9, 0x98, 0x63, 0x16, 0x5f, 0x4a, 130 0x82, 0xf2, 0xc6, 0xc9, 0x9a, 0x39, 0x47, 0x26 131 }; 132 #define QCOMGPIO_GPIO_DSM_REV 0 133 #define QCOMGPIO_GPIO_DSM_FUNC_NUM_PINS 2 134 135 static UINT8 qcomgpio_pdc_dsm_uuid[ACPI_UUID_LENGTH] = { 136 0xd4, 0x0f, 0x1b, 0x92, 0x7c, 0x56, 0xa0, 0x43, 137 0xbb, 0x14, 0x26, 0x48, 0xf7, 0xb2, 0xa1, 0x8c 138 }; 139 #define QCOMGPIO_PDC_DSM_REV 0 140 #define QCOMGPIO_PDC_DSM_FUNC_CIPR 2 141 142 static struct qcomgpio_reserved qcomgpio_x1e_reserved[] = { 143 { .start = 34, .count = 2 }, 144 { .start = 44, .count = 4 }, 145 { .start = 72, .count = 2 }, 146 { .start = 238, .count = 1 }, 147 }; 148 149 static int qcomgpio_x1e_pdc_filter[] = { 150 0x140, /* Interrupt storm due to missing SMI support. */ 151 }; 152 153 static struct qcomgpio_config qcomgpio_x1e_config = { 154 .reserved = qcomgpio_x1e_reserved, 155 .num_reserved = __arraycount(qcomgpio_x1e_reserved), 156 .pdc_filter = qcomgpio_x1e_pdc_filter, 157 .num_pdc_filter = __arraycount(qcomgpio_x1e_pdc_filter), 158 }; 159 160 static const struct device_compatible_entry compat_data[] = { 161 { .compat = "QCOM0C0C", .data = &qcomgpio_x1e_config }, 162 DEVICE_COMPAT_EOL 163 }; 164 165 static int 166 qcomgpio_match(device_t parent, cfdata_t cf, void *aux) 167 { 168 struct acpi_attach_args *aa = aux; 169 170 return acpi_compatible_match(aa, compat_data); 171 } 172 173 static void 174 qcomgpio_attach(device_t parent, device_t self, void *aux) 175 { 176 struct qcomgpio_softc * const sc = device_private(self); 177 struct acpi_attach_args *aa = aux; 178 struct gpiobus_attach_args gba; 179 ACPI_HANDLE hdl = aa->aa_node->ad_handle; 180 struct acpi_resources res; 181 struct acpi_mem *mem; 182 struct acpi_irq *irq; 183 ACPI_STATUS rv; 184 int error, pin, n; 185 void *ih; 186 187 sc->sc_dev = self; 188 sc->sc_config = acpi_compatible_lookup(aa, compat_data)->data; 189 sc->sc_bst = aa->aa_memt; 190 KASSERT(sc->sc_config != NULL); 191 LIST_INIT(&sc->sc_intrs); 192 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 193 194 rv = acpi_resource_parse(sc->sc_dev, hdl, "_CRS", 195 &res, &acpi_resource_parse_ops_default); 196 if (ACPI_FAILURE(rv)) { 197 return; 198 } 199 200 mem = acpi_res_mem(&res, 0); 201 if (mem == NULL) { 202 aprint_error_dev(self, "couldn't find mem resource\n"); 203 goto done; 204 } 205 206 irq = acpi_res_irq(&res, 0); 207 if (irq == NULL) { 208 aprint_error_dev(self, "couldn't find irq resource\n"); 209 goto done; 210 } 211 212 error = bus_space_map(sc->sc_bst, mem->ar_base, mem->ar_length, 0, 213 &sc->sc_bsh); 214 if (error) { 215 aprint_error_dev(self, "couldn't map registers\n"); 216 goto done; 217 } 218 219 sc->sc_npdcmap = res.ar_nirq; 220 sc->sc_pdcmap = kmem_zalloc(sizeof(*sc->sc_pdcmap) * sc->sc_npdcmap, 221 KM_SLEEP); 222 for (n = 0; n < sc->sc_npdcmap; n++) { 223 sc->sc_pdcmap[n].pm_irq = acpi_res_irq(&res, n)->ar_irq; 224 sc->sc_pdcmap[n].pm_pin = -1; 225 aprint_debug_dev(self, "IRQ resource %u -> %#x\n", 226 n, sc->sc_pdcmap[n].pm_irq); 227 } 228 qcomgpio_acpi_fill_pdcmap(sc, hdl); 229 230 sc->sc_npins = qcomgpio_acpi_num_pins(self, hdl); 231 if (sc->sc_npins == 0) { 232 aprint_error_dev(self, "couldn't determine pin count!\n"); 233 goto done; 234 } 235 sc->sc_pins = kmem_zalloc(sizeof(*sc->sc_pins) * sc->sc_npins, 236 KM_SLEEP); 237 for (pin = 0; pin < sc->sc_npins; pin++) { 238 sc->sc_pins[pin].pin_caps = qcomgpio_pin_reserved(sc, pin) ? 239 0 : (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT); 240 sc->sc_pins[pin].pin_num = pin; 241 sc->sc_pins[pin].pin_intrcaps = 242 GPIO_INTR_POS_EDGE | GPIO_INTR_NEG_EDGE | 243 GPIO_INTR_DOUBLE_EDGE | GPIO_INTR_HIGH_LEVEL | 244 GPIO_INTR_LOW_LEVEL | GPIO_INTR_MPSAFE; 245 } 246 247 sc->sc_gc.gp_cookie = sc; 248 sc->sc_gc.gp_pin_read = qcomgpio_pin_read; 249 sc->sc_gc.gp_pin_write = qcomgpio_pin_write; 250 sc->sc_gc.gp_pin_ctl = qcomgpio_pin_ctl; 251 sc->sc_gc.gp_intr_establish = qcomgpio_intr_establish; 252 sc->sc_gc.gp_intr_disestablish = qcomgpio_intr_disestablish; 253 sc->sc_gc.gp_intr_str = qcomgpio_intr_str; 254 sc->sc_gc.gp_intr_mask = qcomgpio_intr_mask; 255 sc->sc_gc.gp_intr_unmask = qcomgpio_intr_unmask; 256 257 rv = acpi_event_create_gpio(self, hdl, qcomgpio_register_event, sc); 258 if (ACPI_FAILURE(rv)) { 259 if (rv != AE_NOT_FOUND) { 260 aprint_error_dev(self, "failed to create events: %s\n", 261 AcpiFormatException(rv)); 262 } 263 goto done; 264 } 265 266 ih = acpi_intr_establish(self, (uint64_t)(uintptr_t)hdl, 267 IPL_VM, false, qcomgpio_intr, sc, device_xname(self)); 268 if (ih == NULL) { 269 aprint_error_dev(self, "couldn't establish interrupt\n"); 270 goto done; 271 } 272 273 memset(&gba, 0, sizeof(gba)); 274 gba.gba_gc = &sc->sc_gc; 275 gba.gba_pins = sc->sc_pins; 276 gba.gba_npins = sc->sc_npins; 277 sc->sc_gpiodev = config_found(self, &gba, gpiobus_print, 278 CFARGS(.iattr = "gpiobus")); 279 if (sc->sc_gpiodev != NULL) { 280 acpi_gpio_register(aa->aa_node, self, 281 qcomgpio_acpi_translate, sc); 282 } 283 284 done: 285 acpi_resource_cleanup(&res); 286 } 287 288 static u_int 289 qcomgpio_acpi_num_pins(device_t dev, ACPI_HANDLE hdl) 290 { 291 ACPI_STATUS rv; 292 ACPI_INTEGER npins; 293 294 rv = acpi_dsm_integer(hdl, qcomgpio_gpio_dsm_uuid, 295 QCOMGPIO_GPIO_DSM_REV, QCOMGPIO_GPIO_DSM_FUNC_NUM_PINS, 296 NULL, &npins); 297 if (ACPI_FAILURE(rv)) { 298 aprint_error_dev(dev, "GPIO _DSM failed: %s\n", 299 AcpiFormatException(rv)); 300 return 0; 301 } 302 303 aprint_debug_dev(dev, "GPIO pin count: %u\n", (u_int)npins); 304 305 return (u_int)npins; 306 } 307 308 static void 309 qcomgpio_acpi_fill_pdcmap(struct qcomgpio_softc *sc, 310 ACPI_HANDLE hdl) 311 { 312 ACPI_STATUS rv; 313 ACPI_OBJECT *obj; 314 u_int n, filt; 315 316 rv = acpi_dsm_typed(hdl, qcomgpio_pdc_dsm_uuid, 317 QCOMGPIO_PDC_DSM_REV, QCOMGPIO_PDC_DSM_FUNC_CIPR, 318 NULL, ACPI_TYPE_PACKAGE, &obj); 319 if (ACPI_FAILURE(rv)) { 320 aprint_error_dev(sc->sc_dev, "PDC _DSM failed: %s\n", 321 AcpiFormatException(rv)); 322 return; 323 } 324 325 for (n = 0; n < obj->Package.Count; n++) { 326 ACPI_OBJECT *map = &obj->Package.Elements[n]; 327 bool filter = false; 328 u_int irq, pdc; 329 int pin; 330 331 if (map->Type != ACPI_TYPE_PACKAGE || 332 map->Package.Count < 3 || 333 map->Package.Elements[0].Type != ACPI_TYPE_INTEGER || 334 map->Package.Elements[1].Type != ACPI_TYPE_INTEGER || 335 map->Package.Elements[2].Type != ACPI_TYPE_INTEGER) { 336 continue; 337 } 338 339 irq = (u_int)map->Package.Elements[2].Integer.Value; 340 pin = (int)map->Package.Elements[1].Integer.Value; 341 for (pdc = 0; pdc < sc->sc_npdcmap; pdc++) { 342 if (sc->sc_pdcmap[pdc].pm_irq == irq) { 343 for (filt = 0; 344 filt < sc->sc_config->num_pdc_filter; 345 filt++) { 346 if (sc->sc_config->pdc_filter[filt] == 347 pdc * 64) { 348 filter = true; 349 break; 350 } 351 } 352 353 if (!filter) { 354 sc->sc_pdcmap[pdc].pm_pin = pin; 355 } 356 break; 357 } 358 } 359 360 aprint_debug_dev(sc->sc_dev, 361 "PDC irq %#x -> pin %d%s%s\n", irq, pin, 362 filter ? " (filtered)" : "", 363 pdc == sc->sc_npdcmap ? " (unused)" : ""); 364 } 365 366 ACPI_FREE(obj); 367 } 368 369 static int 370 qcomgpio_acpi_translate(void *priv, ACPI_RESOURCE_GPIO *gpio, void **gpiop) 371 { 372 struct qcomgpio_softc * const sc = priv; 373 const ACPI_INTEGER vpin = gpio->PinTable[0]; 374 int pin = -1; 375 376 if (vpin < sc->sc_npins) { 377 /* Virtual pin number is 1:1 mapping with hardware. */ 378 pin = vpin; 379 } else if (vpin / 64 < sc->sc_npdcmap) { 380 /* Translate the virtual pin number to a hardware pin. */ 381 pin = sc->sc_pdcmap[vpin / 64].pm_pin; 382 } 383 384 aprint_debug_dev(sc->sc_dev, "translate %#lx -> %u\n", vpin, pin); 385 386 if (gpiop != NULL) { 387 if (sc->sc_gpiodev != NULL) { 388 *gpiop = device_private(sc->sc_gpiodev); 389 } else { 390 device_printf(sc->sc_dev, 391 "no gpiodev for pin %#lx -> %u\n", vpin, pin); 392 pin = -1; 393 } 394 } 395 396 return pin; 397 } 398 399 static int 400 qcomgpio_acpi_event(void *priv) 401 { 402 struct acpi_event * const ev = priv; 403 404 acpi_event_notify(ev); 405 406 return 1; 407 } 408 409 static void 410 qcomgpio_register_event(void *priv, struct acpi_event *ev, 411 ACPI_RESOURCE_GPIO *gpio) 412 { 413 struct qcomgpio_softc * const sc = priv; 414 int irqmode; 415 void *ih; 416 417 const int pin = qcomgpio_acpi_translate(sc, gpio, NULL); 418 419 if (pin < 0) { 420 aprint_error_dev(sc->sc_dev, 421 "ignoring event for pin %#x (out of range)\n", 422 gpio->PinTable[0]); 423 return; 424 } 425 426 if (gpio->Triggering == ACPI_LEVEL_SENSITIVE) { 427 irqmode = gpio->Polarity == ACPI_ACTIVE_HIGH ? 428 GPIO_INTR_HIGH_LEVEL : GPIO_INTR_LOW_LEVEL; 429 } else { 430 KASSERT(gpio->Triggering == ACPI_EDGE_SENSITIVE); 431 if (gpio->Polarity == ACPI_ACTIVE_LOW) { 432 irqmode = GPIO_INTR_NEG_EDGE; 433 } else if (gpio->Polarity == ACPI_ACTIVE_HIGH) { 434 irqmode = GPIO_INTR_POS_EDGE; 435 } else { 436 KASSERT(gpio->Polarity == ACPI_ACTIVE_BOTH); 437 irqmode = GPIO_INTR_DOUBLE_EDGE; 438 } 439 } 440 441 ih = qcomgpio_intr_establish(sc, pin, IPL_VM, irqmode, 442 qcomgpio_acpi_event, ev); 443 if (ih == NULL) { 444 aprint_error_dev(sc->sc_dev, 445 "couldn't register event for pin %#x\n", 446 gpio->PinTable[0]); 447 return; 448 } 449 if (gpio->Triggering == ACPI_LEVEL_SENSITIVE) { 450 acpi_event_set_intrcookie(ev, ih); 451 } 452 } 453 454 static bool 455 qcomgpio_pin_reserved(struct qcomgpio_softc *sc, int pin) 456 { 457 u_int n; 458 459 for (n = 0; n < sc->sc_config->num_reserved; n++) { 460 if (pin >= sc->sc_config->reserved[n].start && 461 pin < sc->sc_config->reserved[n].start + 462 sc->sc_config->reserved[n].count) { 463 return true; 464 } 465 } 466 467 return false; 468 } 469 470 static int 471 qcomgpio_pin_read(void *priv, int pin) 472 { 473 struct qcomgpio_softc * const sc = priv; 474 uint32_t val; 475 476 if (pin < 0 || pin >= sc->sc_npins) { 477 return 0; 478 } 479 if ((sc->sc_pins[pin].pin_caps & GPIO_PIN_INPUT) == 0) { 480 return 0; 481 } 482 483 val = RD4(sc, TLMM_GPIO_IN_OUT(pin)); 484 return (val & TLMM_GPIO_IN_OUT_GPIO_IN) != 0; 485 } 486 487 static void 488 qcomgpio_pin_write(void *priv, int pin, int pinval) 489 { 490 struct qcomgpio_softc * const sc = priv; 491 uint32_t val; 492 493 if (pin < 0 || pin >= sc->sc_npins) { 494 return; 495 } 496 if ((sc->sc_pins[pin].pin_caps & GPIO_PIN_OUTPUT) == 0) { 497 return; 498 } 499 500 val = RD4(sc, TLMM_GPIO_IN_OUT(pin)); 501 if (pinval) { 502 val |= TLMM_GPIO_IN_OUT_GPIO_OUT; 503 } else { 504 val &= ~TLMM_GPIO_IN_OUT_GPIO_OUT; 505 } 506 WR4(sc, TLMM_GPIO_IN_OUT(pin), val); 507 } 508 509 static void 510 qcomgpio_pin_ctl(void *priv, int pin, int flags) 511 { 512 /* Nothing to do here, as firmware has already configured pins. */ 513 } 514 515 static void * 516 qcomgpio_intr_establish(void *priv, int pin, int ipl, int irqmode, 517 int (*func)(void *), void *arg) 518 { 519 struct qcomgpio_softc * const sc = priv; 520 struct qcomgpio_intr_handler *qih, *qihp; 521 uint32_t dect, pol; 522 uint32_t val; 523 524 if (pin < 0 || pin >= sc->sc_npins) { 525 return NULL; 526 } 527 if (ipl != IPL_VM) { 528 device_printf(sc->sc_dev, "%s: only IPL_VM supported\n", 529 __func__); 530 return NULL; 531 } 532 533 qih = kmem_alloc(sizeof(*qih), KM_SLEEP); 534 qih->ih_func = func; 535 qih->ih_arg = arg; 536 qih->ih_pin = pin; 537 qih->ih_type = (irqmode & GPIO_INTR_LEVEL_MASK) != 0 ? 538 IST_LEVEL : IST_EDGE; 539 540 mutex_enter(&sc->sc_lock); 541 542 LIST_FOREACH(qihp, &sc->sc_intrs, ih_list) { 543 if (qihp->ih_pin == qih->ih_pin) { 544 mutex_exit(&sc->sc_lock); 545 kmem_free(qih, sizeof(*qih)); 546 device_printf(sc->sc_dev, 547 "%s: pin %d already establish\n", __func__, pin); 548 return NULL; 549 } 550 } 551 552 LIST_INSERT_HEAD(&sc->sc_intrs, qih, ih_list); 553 554 if ((irqmode & GPIO_INTR_LEVEL_MASK) != 0) { 555 dect = TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_LEVEL; 556 pol = (irqmode & GPIO_INTR_HIGH_LEVEL) != 0 ? 557 TLMM_GPIO_INTR_CFG_INTR_POL_CTL : 0; 558 } else { 559 KASSERT((irqmode & GPIO_INTR_EDGE_MASK) != 0); 560 if ((irqmode & GPIO_INTR_NEG_EDGE) != 0) { 561 dect = TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_EDGE_NEG; 562 pol = TLMM_GPIO_INTR_CFG_INTR_POL_CTL; 563 } else if ((irqmode & GPIO_INTR_POS_EDGE) != 0) { 564 dect = TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_EDGE_POS; 565 pol = TLMM_GPIO_INTR_CFG_INTR_POL_CTL; 566 } else { 567 KASSERT((irqmode & GPIO_INTR_DOUBLE_EDGE) != 0); 568 dect = TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_EDGE_BOTH; 569 pol = 0; 570 } 571 } 572 573 val = RD4(sc, TLMM_GPIO_INTR_CFG(pin)); 574 val &= ~TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_MASK; 575 val |= __SHIFTIN(dect, TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_MASK); 576 val &= ~TLMM_GPIO_INTR_CFG_INTR_POL_CTL; 577 val |= pol; 578 val &= ~TLMM_GPIO_INTR_CFG_TARGET_PROC_MASK; 579 val |= __SHIFTIN(TLMM_GPIO_INTR_CFG_TARGET_PROC_RPM, 580 TLMM_GPIO_INTR_CFG_TARGET_PROC_MASK); 581 val |= TLMM_GPIO_INTR_CFG_INTR_RAW_STATUS_EN; 582 val |= TLMM_GPIO_INTR_CFG_INTR_ENABLE; 583 WR4(sc, TLMM_GPIO_INTR_CFG(pin), val); 584 585 mutex_exit(&sc->sc_lock); 586 587 return qih; 588 } 589 590 static void 591 qcomgpio_intr_disestablish(void *priv, void *ih) 592 { 593 struct qcomgpio_softc * const sc = priv; 594 struct qcomgpio_intr_handler *qih = ih; 595 uint32_t val; 596 597 mutex_enter(&sc->sc_lock); 598 599 LIST_REMOVE(qih, ih_list); 600 601 val = RD4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin)); 602 val &= ~TLMM_GPIO_INTR_CFG_INTR_ENABLE; 603 WR4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin), val); 604 605 mutex_exit(&sc->sc_lock); 606 607 kmem_free(qih, sizeof(*qih)); 608 } 609 610 static bool 611 qcomgpio_intr_str(void *priv, int pin, int irqmode, char *buf, size_t buflen) 612 { 613 struct qcomgpio_softc * const sc = priv; 614 int rv; 615 616 rv = snprintf(buf, buflen, "%s pin %d", device_xname(sc->sc_dev), pin); 617 618 return rv < buflen; 619 } 620 621 static void 622 qcomgpio_intr_mask(void *priv, void *ih) 623 { 624 struct qcomgpio_softc * const sc = priv; 625 struct qcomgpio_intr_handler *qih = ih; 626 uint32_t val; 627 628 val = RD4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin)); 629 if (qih->ih_type == IST_LEVEL) { 630 val &= ~TLMM_GPIO_INTR_CFG_INTR_RAW_STATUS_EN; 631 } 632 val &= ~TLMM_GPIO_INTR_CFG_INTR_ENABLE; 633 WR4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin), val); 634 } 635 636 static void 637 qcomgpio_intr_unmask(void *priv, void *ih) 638 { 639 struct qcomgpio_softc * const sc = priv; 640 struct qcomgpio_intr_handler *qih = ih; 641 uint32_t val; 642 643 val = RD4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin)); 644 if (qih->ih_type == IST_LEVEL) { 645 val |= TLMM_GPIO_INTR_CFG_INTR_RAW_STATUS_EN; 646 } 647 val |= TLMM_GPIO_INTR_CFG_INTR_ENABLE; 648 WR4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin), val); 649 } 650 651 static int 652 qcomgpio_intr(void *priv) 653 { 654 struct qcomgpio_softc * const sc = priv; 655 struct qcomgpio_intr_handler *qih; 656 int rv = 0; 657 658 mutex_enter(&sc->sc_lock); 659 660 LIST_FOREACH(qih, &sc->sc_intrs, ih_list) { 661 const int pin = qih->ih_pin; 662 uint32_t val; 663 664 val = RD4(sc, TLMM_GPIO_INTR_STATUS(pin)); 665 if ((val & TLMM_GPIO_INTR_STATUS_INTR_STATUS) != 0) { 666 rv |= qih->ih_func(qih->ih_arg); 667 668 val &= ~TLMM_GPIO_INTR_STATUS_INTR_STATUS; 669 WR4(sc, TLMM_GPIO_INTR_STATUS(pin), val); 670 } 671 } 672 673 mutex_exit(&sc->sc_lock); 674 675 return rv; 676 } 677
Indexes created Tue Sep 23 20:09:58 GMT 2025