qcomgpio.c revision 1.6
1 /* $NetBSD: qcomgpio.c,v 1.6 2024/12/12 22:30:47 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2024 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jared McNeill <jmcneill (at) invisible.ca>. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: qcomgpio.c,v 1.6 2024/12/12 22:30:47 jmcneill Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/cpu.h> 38 #include <sys/device.h> 39 #include <sys/gpio.h> 40 #include <sys/queue.h> 41 #include <sys/kmem.h> 42 #include <sys/mutex.h> 43 #include <sys/evcnt.h> 44 45 #include <dev/acpi/acpireg.h> 46 #include <dev/acpi/acpivar.h> 47 #include <dev/acpi/acpi_intr.h> 48 #include <dev/acpi/acpi_event.h> 49 #include <dev/acpi/acpi_gpio.h> 50 #include <dev/acpi/qcomgpioreg.h> 51 52 #include <dev/gpio/gpiovar.h> 53 54 typedef enum { 55 QCOMGPIO_X1E, 56 } qcomgpio_type; 57 58 struct qcomgpio_reserved { 59 int start; 60 int count; 61 }; 62 63 struct qcomgpio_config { 64 struct qcomgpio_reserved *reserved; 65 u_int num_reserved; 66 u_int *pdc_filter; 67 u_int num_pdc_filter; 68 }; 69 70 struct qcomgpio_intr_handler { 71 int (*ih_func)(void *); 72 void *ih_arg; 73 int ih_pin; 74 int ih_type; 75 struct evcnt ih_evcnt; 76 char ih_name[16]; 77 LIST_ENTRY(qcomgpio_intr_handler) ih_list; 78 }; 79 80 struct qcomgpio_pdcmap { 81 int pm_pin; 82 u_int pm_irq; 83 }; 84 85 struct qcomgpio_softc { 86 device_t sc_dev; 87 device_t sc_gpiodev; 88 bus_space_handle_t sc_bsh; 89 bus_space_tag_t sc_bst; 90 const struct qcomgpio_config *sc_config; 91 struct gpio_chipset_tag sc_gc; 92 gpio_pin_t *sc_pins; 93 u_int sc_npins; 94 LIST_HEAD(, qcomgpio_intr_handler) sc_intrs; 95 kmutex_t sc_lock; 96 97 struct qcomgpio_pdcmap *sc_pdcmap; 98 u_int sc_npdcmap; 99 }; 100 101 #define RD4(sc, reg) \ 102 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 103 #define WR4(sc, reg, val) \ 104 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 105 106 static int qcomgpio_match(device_t, cfdata_t, void *); 107 static void qcomgpio_attach(device_t, device_t, void *); 108 109 static bool qcomgpio_pin_reserved(struct qcomgpio_softc *, int); 110 static int qcomgpio_pin_read(void *, int); 111 static void qcomgpio_pin_write(void *, int, int); 112 static void qcomgpio_pin_ctl(void *, int, int); 113 static void * qcomgpio_intr_establish(void *, int, int, int, 114 int (*)(void *), void *); 115 static void qcomgpio_intr_disestablish(void *, void *); 116 static bool qcomgpio_intr_str(void *, int, int, char *, size_t); 117 static void qcomgpio_intr_mask(void *, void *); 118 static void qcomgpio_intr_unmask(void *, void *); 119 120 static u_int qcomgpio_acpi_num_pins(device_t, ACPI_HANDLE); 121 static void qcomgpio_acpi_fill_pdcmap(struct qcomgpio_softc *, 122 ACPI_HANDLE); 123 static int qcomgpio_acpi_translate(void *, ACPI_RESOURCE_GPIO *, void **); 124 static void qcomgpio_register_event(void *, struct acpi_event *, 125 ACPI_RESOURCE_GPIO *); 126 static int qcomgpio_intr(void *); 127 128 CFATTACH_DECL_NEW(qcomgpio, sizeof(struct qcomgpio_softc), 129 qcomgpio_match, qcomgpio_attach, NULL, NULL); 130 131 static UINT8 qcomgpio_gpio_dsm_uuid[ACPI_UUID_LENGTH] = { 132 0xa4, 0xb2, 0xb9, 0x98, 0x63, 0x16, 0x5f, 0x4a, 133 0x82, 0xf2, 0xc6, 0xc9, 0x9a, 0x39, 0x47, 0x26 134 }; 135 #define QCOMGPIO_GPIO_DSM_REV 0 136 #define QCOMGPIO_GPIO_DSM_FUNC_NUM_PINS 2 137 138 static UINT8 qcomgpio_pdc_dsm_uuid[ACPI_UUID_LENGTH] = { 139 0xd4, 0x0f, 0x1b, 0x92, 0x7c, 0x56, 0xa0, 0x43, 140 0xbb, 0x14, 0x26, 0x48, 0xf7, 0xb2, 0xa1, 0x8c 141 }; 142 #define QCOMGPIO_PDC_DSM_REV 0 143 #define QCOMGPIO_PDC_DSM_FUNC_CIPR 2 144 145 static struct qcomgpio_reserved qcomgpio_x1e_reserved[] = { 146 { .start = 34, .count = 2 }, 147 { .start = 44, .count = 4 }, 148 { .start = 72, .count = 2 }, 149 { .start = 238, .count = 1 }, 150 }; 151 152 static int qcomgpio_x1e_pdc_filter[] = { 153 0x140, /* Interrupt storm due to missing SMI support. */ 154 }; 155 156 static struct qcomgpio_config qcomgpio_x1e_config = { 157 .reserved = qcomgpio_x1e_reserved, 158 .num_reserved = __arraycount(qcomgpio_x1e_reserved), 159 .pdc_filter = qcomgpio_x1e_pdc_filter, 160 .num_pdc_filter = __arraycount(qcomgpio_x1e_pdc_filter), 161 }; 162 163 static const struct device_compatible_entry compat_data[] = { 164 { .compat = "QCOM0C0C", .data = &qcomgpio_x1e_config }, 165 DEVICE_COMPAT_EOL 166 }; 167 168 static int 169 qcomgpio_match(device_t parent, cfdata_t cf, void *aux) 170 { 171 struct acpi_attach_args *aa = aux; 172 173 return acpi_compatible_match(aa, compat_data); 174 } 175 176 static void 177 qcomgpio_attach(device_t parent, device_t self, void *aux) 178 { 179 struct qcomgpio_softc * const sc = device_private(self); 180 struct acpi_attach_args *aa = aux; 181 struct gpiobus_attach_args gba; 182 ACPI_HANDLE hdl = aa->aa_node->ad_handle; 183 struct acpi_resources res; 184 struct acpi_mem *mem; 185 struct acpi_irq *irq; 186 ACPI_STATUS rv; 187 int error, pin, n; 188 void *ih; 189 190 sc->sc_dev = self; 191 sc->sc_config = acpi_compatible_lookup(aa, compat_data)->data; 192 sc->sc_bst = aa->aa_memt; 193 KASSERT(sc->sc_config != NULL); 194 LIST_INIT(&sc->sc_intrs); 195 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 196 197 rv = acpi_resource_parse(sc->sc_dev, hdl, "_CRS", 198 &res, &acpi_resource_parse_ops_default); 199 if (ACPI_FAILURE(rv)) { 200 return; 201 } 202 203 mem = acpi_res_mem(&res, 0); 204 if (mem == NULL) { 205 aprint_error_dev(self, "couldn't find mem resource\n"); 206 goto done; 207 } 208 209 irq = acpi_res_irq(&res, 0); 210 if (irq == NULL) { 211 aprint_error_dev(self, "couldn't find irq resource\n"); 212 goto done; 213 } 214 215 error = bus_space_map(sc->sc_bst, mem->ar_base, mem->ar_length, 0, 216 &sc->sc_bsh); 217 if (error) { 218 aprint_error_dev(self, "couldn't map registers\n"); 219 goto done; 220 } 221 222 sc->sc_npdcmap = res.ar_nirq; 223 sc->sc_pdcmap = kmem_zalloc(sizeof(*sc->sc_pdcmap) * sc->sc_npdcmap, 224 KM_SLEEP); 225 for (n = 0; n < sc->sc_npdcmap; n++) { 226 sc->sc_pdcmap[n].pm_irq = acpi_res_irq(&res, n)->ar_irq; 227 sc->sc_pdcmap[n].pm_pin = -1; 228 aprint_debug_dev(self, "IRQ resource %u -> %#x\n", 229 n, sc->sc_pdcmap[n].pm_irq); 230 } 231 qcomgpio_acpi_fill_pdcmap(sc, hdl); 232 233 sc->sc_npins = qcomgpio_acpi_num_pins(self, hdl); 234 if (sc->sc_npins == 0) { 235 aprint_error_dev(self, "couldn't determine pin count!\n"); 236 goto done; 237 } 238 sc->sc_pins = kmem_zalloc(sizeof(*sc->sc_pins) * sc->sc_npins, 239 KM_SLEEP); 240 for (pin = 0; pin < sc->sc_npins; pin++) { 241 sc->sc_pins[pin].pin_caps = qcomgpio_pin_reserved(sc, pin) ? 242 0 : (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT); 243 sc->sc_pins[pin].pin_num = pin; 244 sc->sc_pins[pin].pin_intrcaps = 245 GPIO_INTR_POS_EDGE | GPIO_INTR_NEG_EDGE | 246 GPIO_INTR_DOUBLE_EDGE | GPIO_INTR_HIGH_LEVEL | 247 GPIO_INTR_LOW_LEVEL | GPIO_INTR_MPSAFE; 248 } 249 250 sc->sc_gc.gp_cookie = sc; 251 sc->sc_gc.gp_pin_read = qcomgpio_pin_read; 252 sc->sc_gc.gp_pin_write = qcomgpio_pin_write; 253 sc->sc_gc.gp_pin_ctl = qcomgpio_pin_ctl; 254 sc->sc_gc.gp_intr_establish = qcomgpio_intr_establish; 255 sc->sc_gc.gp_intr_disestablish = qcomgpio_intr_disestablish; 256 sc->sc_gc.gp_intr_str = qcomgpio_intr_str; 257 sc->sc_gc.gp_intr_mask = qcomgpio_intr_mask; 258 sc->sc_gc.gp_intr_unmask = qcomgpio_intr_unmask; 259 260 rv = acpi_event_create_gpio(self, hdl, qcomgpio_register_event, sc); 261 if (ACPI_FAILURE(rv)) { 262 if (rv != AE_NOT_FOUND) { 263 aprint_error_dev(self, "failed to create events: %s\n", 264 AcpiFormatException(rv)); 265 } 266 goto done; 267 } 268 269 ih = acpi_intr_establish(self, (uint64_t)(uintptr_t)hdl, 270 IPL_VM, false, qcomgpio_intr, sc, device_xname(self)); 271 if (ih == NULL) { 272 aprint_error_dev(self, "couldn't establish interrupt\n"); 273 goto done; 274 } 275 276 memset(&gba, 0, sizeof(gba)); 277 gba.gba_gc = &sc->sc_gc; 278 gba.gba_pins = sc->sc_pins; 279 gba.gba_npins = sc->sc_npins; 280 sc->sc_gpiodev = config_found(self, &gba, gpiobus_print, 281 CFARGS(.iattr = "gpiobus")); 282 if (sc->sc_gpiodev != NULL) { 283 acpi_gpio_register(aa->aa_node, self, 284 qcomgpio_acpi_translate, sc); 285 } 286 287 done: 288 acpi_resource_cleanup(&res); 289 } 290 291 static u_int 292 qcomgpio_acpi_num_pins(device_t dev, ACPI_HANDLE hdl) 293 { 294 ACPI_STATUS rv; 295 ACPI_INTEGER npins; 296 297 rv = acpi_dsm_integer(hdl, qcomgpio_gpio_dsm_uuid, 298 QCOMGPIO_GPIO_DSM_REV, QCOMGPIO_GPIO_DSM_FUNC_NUM_PINS, 299 NULL, &npins); 300 if (ACPI_FAILURE(rv)) { 301 aprint_error_dev(dev, "GPIO _DSM failed: %s\n", 302 AcpiFormatException(rv)); 303 return 0; 304 } 305 306 aprint_debug_dev(dev, "GPIO pin count: %u\n", (u_int)npins); 307 308 return (u_int)npins; 309 } 310 311 static void 312 qcomgpio_acpi_fill_pdcmap(struct qcomgpio_softc *sc, 313 ACPI_HANDLE hdl) 314 { 315 ACPI_STATUS rv; 316 ACPI_OBJECT *obj; 317 u_int n, filt; 318 319 rv = acpi_dsm_typed(hdl, qcomgpio_pdc_dsm_uuid, 320 QCOMGPIO_PDC_DSM_REV, QCOMGPIO_PDC_DSM_FUNC_CIPR, 321 NULL, ACPI_TYPE_PACKAGE, &obj); 322 if (ACPI_FAILURE(rv)) { 323 aprint_error_dev(sc->sc_dev, "PDC _DSM failed: %s\n", 324 AcpiFormatException(rv)); 325 return; 326 } 327 328 for (n = 0; n < obj->Package.Count; n++) { 329 ACPI_OBJECT *map = &obj->Package.Elements[n]; 330 bool filter = false; 331 u_int irq, pdc; 332 int pin; 333 334 if (map->Type != ACPI_TYPE_PACKAGE || 335 map->Package.Count < 3 || 336 map->Package.Elements[0].Type != ACPI_TYPE_INTEGER || 337 map->Package.Elements[1].Type != ACPI_TYPE_INTEGER || 338 map->Package.Elements[2].Type != ACPI_TYPE_INTEGER) { 339 continue; 340 } 341 342 irq = (u_int)map->Package.Elements[2].Integer.Value; 343 pin = (int)map->Package.Elements[1].Integer.Value; 344 for (pdc = 0; pdc < sc->sc_npdcmap; pdc++) { 345 if (sc->sc_pdcmap[pdc].pm_irq == irq) { 346 for (filt = 0; 347 filt < sc->sc_config->num_pdc_filter; 348 filt++) { 349 if (sc->sc_config->pdc_filter[filt] == 350 pdc * 64) { 351 filter = true; 352 break; 353 } 354 } 355 356 if (!filter) { 357 sc->sc_pdcmap[pdc].pm_pin = pin; 358 } 359 break; 360 } 361 } 362 363 aprint_debug_dev(sc->sc_dev, 364 "PDC irq %#x -> pin %d%s%s\n", irq, pin, 365 filter ? " (filtered)" : "", 366 pdc == sc->sc_npdcmap ? " (unused)" : ""); 367 } 368 369 ACPI_FREE(obj); 370 } 371 372 static int 373 qcomgpio_acpi_translate(void *priv, ACPI_RESOURCE_GPIO *gpio, void **gpiop) 374 { 375 struct qcomgpio_softc * const sc = priv; 376 const ACPI_INTEGER vpin = gpio->PinTable[0]; 377 int pin = -1; 378 379 if (vpin < sc->sc_npins) { 380 /* Virtual pin number is 1:1 mapping with hardware. */ 381 pin = vpin; 382 } else if (vpin / 64 < sc->sc_npdcmap) { 383 /* Translate the virtual pin number to a hardware pin. */ 384 pin = sc->sc_pdcmap[vpin / 64].pm_pin; 385 } 386 387 aprint_debug_dev(sc->sc_dev, "translate %#lx -> %u\n", vpin, pin); 388 389 if (gpiop != NULL) { 390 if (sc->sc_gpiodev != NULL) { 391 *gpiop = device_private(sc->sc_gpiodev); 392 } else { 393 device_printf(sc->sc_dev, 394 "no gpiodev for pin %#lx -> %u\n", vpin, pin); 395 pin = -1; 396 } 397 } 398 399 return pin; 400 } 401 402 static int 403 qcomgpio_acpi_event(void *priv) 404 { 405 struct acpi_event * const ev = priv; 406 407 acpi_event_notify(ev); 408 409 return 1; 410 } 411 412 static void 413 qcomgpio_register_event(void *priv, struct acpi_event *ev, 414 ACPI_RESOURCE_GPIO *gpio) 415 { 416 struct qcomgpio_softc * const sc = priv; 417 int irqmode; 418 void *ih; 419 420 const int pin = qcomgpio_acpi_translate(sc, gpio, NULL); 421 422 if (pin < 0) { 423 aprint_error_dev(sc->sc_dev, 424 "ignoring event for pin %#x (out of range)\n", 425 gpio->PinTable[0]); 426 return; 427 } 428 429 if (gpio->Triggering == ACPI_LEVEL_SENSITIVE) { 430 irqmode = gpio->Polarity == ACPI_ACTIVE_HIGH ? 431 GPIO_INTR_HIGH_LEVEL : GPIO_INTR_LOW_LEVEL; 432 } else { 433 KASSERT(gpio->Triggering == ACPI_EDGE_SENSITIVE); 434 if (gpio->Polarity == ACPI_ACTIVE_LOW) { 435 irqmode = GPIO_INTR_NEG_EDGE; 436 } else if (gpio->Polarity == ACPI_ACTIVE_HIGH) { 437 irqmode = GPIO_INTR_POS_EDGE; 438 } else { 439 KASSERT(gpio->Polarity == ACPI_ACTIVE_BOTH); 440 irqmode = GPIO_INTR_DOUBLE_EDGE; 441 } 442 } 443 444 ih = qcomgpio_intr_establish(sc, pin, IPL_VM, irqmode, 445 qcomgpio_acpi_event, ev); 446 if (ih == NULL) { 447 aprint_error_dev(sc->sc_dev, 448 "couldn't register event for pin %#x\n", 449 gpio->PinTable[0]); 450 return; 451 } 452 if (gpio->Triggering == ACPI_LEVEL_SENSITIVE) { 453 acpi_event_set_intrcookie(ev, ih); 454 } 455 } 456 457 static bool 458 qcomgpio_pin_reserved(struct qcomgpio_softc *sc, int pin) 459 { 460 u_int n; 461 462 for (n = 0; n < sc->sc_config->num_reserved; n++) { 463 if (pin >= sc->sc_config->reserved[n].start && 464 pin < sc->sc_config->reserved[n].start + 465 sc->sc_config->reserved[n].count) { 466 return true; 467 } 468 } 469 470 return false; 471 } 472 473 static int 474 qcomgpio_pin_read(void *priv, int pin) 475 { 476 struct qcomgpio_softc * const sc = priv; 477 uint32_t val; 478 479 if (pin < 0 || pin >= sc->sc_npins) { 480 return 0; 481 } 482 if ((sc->sc_pins[pin].pin_caps & GPIO_PIN_INPUT) == 0) { 483 return 0; 484 } 485 486 val = RD4(sc, TLMM_GPIO_IN_OUT(pin)); 487 return (val & TLMM_GPIO_IN_OUT_GPIO_IN) != 0; 488 } 489 490 static void 491 qcomgpio_pin_write(void *priv, int pin, int pinval) 492 { 493 struct qcomgpio_softc * const sc = priv; 494 uint32_t val; 495 496 if (pin < 0 || pin >= sc->sc_npins) { 497 return; 498 } 499 if ((sc->sc_pins[pin].pin_caps & GPIO_PIN_OUTPUT) == 0) { 500 return; 501 } 502 503 val = RD4(sc, TLMM_GPIO_IN_OUT(pin)); 504 if (pinval) { 505 val |= TLMM_GPIO_IN_OUT_GPIO_OUT; 506 } else { 507 val &= ~TLMM_GPIO_IN_OUT_GPIO_OUT; 508 } 509 WR4(sc, TLMM_GPIO_IN_OUT(pin), val); 510 } 511 512 static void 513 qcomgpio_pin_ctl(void *priv, int pin, int flags) 514 { 515 /* Nothing to do here, as firmware has already configured pins. */ 516 } 517 518 static void * 519 qcomgpio_intr_establish(void *priv, int pin, int ipl, int irqmode, 520 int (*func)(void *), void *arg) 521 { 522 struct qcomgpio_softc * const sc = priv; 523 struct qcomgpio_intr_handler *qih, *qihp; 524 uint32_t dect, pol; 525 uint32_t val; 526 527 if (pin < 0 || pin >= sc->sc_npins) { 528 return NULL; 529 } 530 if (ipl != IPL_VM) { 531 device_printf(sc->sc_dev, "%s: only IPL_VM supported\n", 532 __func__); 533 return NULL; 534 } 535 536 qih = kmem_alloc(sizeof(*qih), KM_SLEEP); 537 qih->ih_func = func; 538 qih->ih_arg = arg; 539 qih->ih_pin = pin; 540 qih->ih_type = (irqmode & GPIO_INTR_LEVEL_MASK) != 0 ? 541 IST_LEVEL : IST_EDGE; 542 snprintf(qih->ih_name, sizeof(qih->ih_name), "pin %d", pin); 543 544 mutex_enter(&sc->sc_lock); 545 546 LIST_FOREACH(qihp, &sc->sc_intrs, ih_list) { 547 if (qihp->ih_pin == qih->ih_pin) { 548 mutex_exit(&sc->sc_lock); 549 kmem_free(qih, sizeof(*qih)); 550 device_printf(sc->sc_dev, 551 "%s: pin %d already establish\n", __func__, pin); 552 return NULL; 553 } 554 } 555 556 LIST_INSERT_HEAD(&sc->sc_intrs, qih, ih_list); 557 558 if ((irqmode & GPIO_INTR_LEVEL_MASK) != 0) { 559 dect = TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_LEVEL; 560 pol = (irqmode & GPIO_INTR_HIGH_LEVEL) != 0 ? 561 TLMM_GPIO_INTR_CFG_INTR_POL_CTL : 0; 562 } else { 563 KASSERT((irqmode & GPIO_INTR_EDGE_MASK) != 0); 564 if ((irqmode & GPIO_INTR_NEG_EDGE) != 0) { 565 dect = TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_EDGE_NEG; 566 pol = TLMM_GPIO_INTR_CFG_INTR_POL_CTL; 567 } else if ((irqmode & GPIO_INTR_POS_EDGE) != 0) { 568 dect = TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_EDGE_POS; 569 pol = TLMM_GPIO_INTR_CFG_INTR_POL_CTL; 570 } else { 571 KASSERT((irqmode & GPIO_INTR_DOUBLE_EDGE) != 0); 572 dect = TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_EDGE_BOTH; 573 pol = 0; 574 } 575 } 576 577 val = RD4(sc, TLMM_GPIO_INTR_CFG(pin)); 578 val &= ~TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_MASK; 579 val |= __SHIFTIN(dect, TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_MASK); 580 val &= ~TLMM_GPIO_INTR_CFG_INTR_POL_CTL; 581 val |= pol; 582 val &= ~TLMM_GPIO_INTR_CFG_TARGET_PROC_MASK; 583 val |= __SHIFTIN(TLMM_GPIO_INTR_CFG_TARGET_PROC_RPM, 584 TLMM_GPIO_INTR_CFG_TARGET_PROC_MASK); 585 val |= TLMM_GPIO_INTR_CFG_INTR_RAW_STATUS_EN; 586 val |= TLMM_GPIO_INTR_CFG_INTR_ENABLE; 587 WR4(sc, TLMM_GPIO_INTR_CFG(pin), val); 588 589 mutex_exit(&sc->sc_lock); 590 591 evcnt_attach_dynamic(&qih->ih_evcnt, EVCNT_TYPE_INTR, 592 NULL, device_xname(sc->sc_dev), qih->ih_name); 593 594 return qih; 595 } 596 597 static void 598 qcomgpio_intr_disestablish(void *priv, void *ih) 599 { 600 struct qcomgpio_softc * const sc = priv; 601 struct qcomgpio_intr_handler *qih = ih; 602 uint32_t val; 603 604 evcnt_detach(&qih->ih_evcnt); 605 606 mutex_enter(&sc->sc_lock); 607 608 LIST_REMOVE(qih, ih_list); 609 610 val = RD4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin)); 611 val &= ~TLMM_GPIO_INTR_CFG_INTR_ENABLE; 612 WR4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin), val); 613 614 mutex_exit(&sc->sc_lock); 615 616 kmem_free(qih, sizeof(*qih)); 617 } 618 619 static bool 620 qcomgpio_intr_str(void *priv, int pin, int irqmode, char *buf, size_t buflen) 621 { 622 struct qcomgpio_softc * const sc = priv; 623 int rv; 624 625 rv = snprintf(buf, buflen, "%s pin %d", device_xname(sc->sc_dev), pin); 626 627 return rv < buflen; 628 } 629 630 static void 631 qcomgpio_intr_mask(void *priv, void *ih) 632 { 633 struct qcomgpio_softc * const sc = priv; 634 struct qcomgpio_intr_handler *qih = ih; 635 uint32_t val; 636 637 val = RD4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin)); 638 if (qih->ih_type == IST_LEVEL) { 639 val &= ~TLMM_GPIO_INTR_CFG_INTR_RAW_STATUS_EN; 640 } 641 val &= ~TLMM_GPIO_INTR_CFG_INTR_ENABLE; 642 WR4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin), val); 643 } 644 645 static void 646 qcomgpio_intr_unmask(void *priv, void *ih) 647 { 648 struct qcomgpio_softc * const sc = priv; 649 struct qcomgpio_intr_handler *qih = ih; 650 uint32_t val; 651 652 val = RD4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin)); 653 if (qih->ih_type == IST_LEVEL) { 654 val |= TLMM_GPIO_INTR_CFG_INTR_RAW_STATUS_EN; 655 } 656 val |= TLMM_GPIO_INTR_CFG_INTR_ENABLE; 657 WR4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin), val); 658 } 659 660 static int 661 qcomgpio_intr(void *priv) 662 { 663 struct qcomgpio_softc * const sc = priv; 664 struct qcomgpio_intr_handler *qih; 665 int rv = 0; 666 667 mutex_enter(&sc->sc_lock); 668 669 LIST_FOREACH(qih, &sc->sc_intrs, ih_list) { 670 const int pin = qih->ih_pin; 671 uint32_t val; 672 673 val = RD4(sc, TLMM_GPIO_INTR_STATUS(pin)); 674 if ((val & TLMM_GPIO_INTR_STATUS_INTR_STATUS) != 0) { 675 qih->ih_evcnt.ev_count++; 676 677 rv |= qih->ih_func(qih->ih_arg); 678 679 val &= ~TLMM_GPIO_INTR_STATUS_INTR_STATUS; 680 WR4(sc, TLMM_GPIO_INTR_STATUS(pin), val); 681 } 682 } 683 684 mutex_exit(&sc->sc_lock); 685 686 return rv; 687 } 688
Indexes created Thu Sep 25 08:09:54 GMT 2025