satareg.h revision 1.2
1 /* $NetBSD: satareg.h,v 1.2 2003/12/17 16:16:36 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of Wasabi Systems, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _DEV_ATA_SATAREG_H_ 40 #define _DEV_ATA_SATAREG_H_ 41 42 /* 43 * Serial ATA register definitions. 44 * 45 * Reference: 46 * 47 * Serial ATA: High Speed Serialized AT Attachment 48 * Revsion 1.0 29-August-2001 49 * Serial ATA Working Group 50 */ 51 52 /* 53 * SStatus (SCR0) -- 54 * Serial ATA interface status register 55 */ 56 /* 57 * The DET value indicates the interface device detection and 58 * PHY state. 59 */ 60 #define SStatus_DET_NODEV (0x0 << 0) /* no device connected */ 61 #define SStatus_DET_DEV_NE (0x1 << 0) /* device, but PHY comm not 62 established */ 63 #define SStatus_DET_DEV (0x3 << 0) /* device, PHY comm 64 established */ 65 #define SStatus_DET_OFFLINE (0x4 << 0) /* PHY in offline mode */ 66 #define SStatus_DET_mask (0xf << 0) 67 #define SStatus_DET_shift 0 68 /* 69 * The SPD value indicates the negotiated interface communication 70 * speed established. 71 */ 72 #define SStatus_SPD_NONE (0x0 << 4) /* no negotiated speed */ 73 #define SStatus_SPD_G1 (0x1 << 4) /* Generation 1 (1.5Gb/s) */ 74 #define SStatus_SPD_G2 (0x2 << 4) /* Generation 2 (3.0Gb/s) */ 75 #define SStatus_SPD_mask (0xf << 4) 76 #define SStatus_SPD_shift 4 77 /* 78 * The IPM value indicates the current interface power managemnt 79 * state. 80 */ 81 #define SStatus_IPM_NODEV (0x0 << 8) /* no device connected */ 82 #define SStatus_IPM_ACTIVE (0x1 << 8) /* ACTIVE state */ 83 #define SStatus_IPM_PARTIAL (0x2 << 8) /* PARTIAL pm state */ 84 #define SStatus_IPM_SLUMBER (0x6 << 8) /* SLUMBER pm state */ 85 #define SStatus_IPM_mask (0xf << 8) 86 #define SStatus_IPM_shift 8 87 88 /* 89 * SError (SCR1) -- 90 * Serial ATA interface error register 91 */ 92 #define SError_ERR_I (1U << 0) /* Recovered data integrity 93 error */ 94 #define SError_ERR_M (1U << 1) /* Recovered communications 95 error */ 96 #define SError_ERR_T (1U << 8) /* Non-recovered transient 97 data integrity error */ 98 #define SError_ERR_C (1U << 9) /* Non-recovered persistent 99 communication or data 100 integrity error */ 101 #define SError_ERR_P (1U << 10) /* Protocol error */ 102 #define SError_ERR_E (1U << 11) /* Internal error */ 103 #define SError_DIAG_N (1U << 16) /* PhyRdy change */ 104 #define SError_DIAG_I (1U << 17) /* PHY internal error */ 105 #define SError_DIAG_W (1U << 18) /* Comm Wake */ 106 #define SError_DIAG_B (1U << 19) /* 10b to 8b decode error */ 107 #define SError_DIAG_D (1U << 20) /* Disparity error */ 108 #define SError_DIAG_C (1U << 21) /* CRC error */ 109 #define SError_DIAG_H (1U << 22) /* Handshake error */ 110 #define SError_DIAG_S (1U << 23) /* Link sequence error */ 111 #define SError_DIAG_T (1U << 24) /* Transport state transition 112 error */ 113 #define SError_DIAG_F (1U << 25) /* Unrecognized FIS type */ 114 #define SError_DIAG_X (1U << 26) /* Device Exchanged */ 115 116 /* 117 * SControl (SCR2) -- 118 * Serial ATA interface control register 119 */ 120 /* 121 * The DET field controls the host adapter device detection 122 * and interface initialization. 123 */ 124 #define SControl_DET_NONE (0x0 << 0) /* No device detection or 125 initialization action 126 requested */ 127 #define SControl_DET_INIT (0x1 << 0) /* Initialize interface 128 communication (equiv 129 of a hard reset) */ 130 #define SControl_DET_DISABLE (0x4 << 0) /* disable interface and 131 take PHY offline */ 132 /* 133 * The SPD field represents the highest allowed communication 134 * speed the interface is allowed to negotiate when communication 135 * is established. 136 */ 137 #define SControl_SPD_ANY (0x0 << 4) /* No restrictions */ 138 #define SControl_SPD_G1 (0x1 << 4) /* Generation 1 (1.5Gb/s) */ 139 #define SControl_SPD_G2 (0x2 << 4) /* Generation 2 (3.0Gb/s) */ 140 /* 141 * The IPM field represents the enabled interface power management 142 * states that can be invoked via the Serial ATA interface power 143 * management capabilities. 144 */ 145 #define SControl_IPM_ANY (0x0 << 8) /* No restrictions */ 146 #define SControl_IPM_NOPARTIAL (0x1 << 8) /* PARTIAL disabled */ 147 #define SControl_IPM_NOSLUMBER (0x2 << 8) /* SLUMBER disabled */ 148 #define SControl_IPM_NONE (0x3 << 8) /* No power management */ 149 /* 150 * The SPM field selects a power management state. A non-zero 151 * value written to this field causes initiation of the selected 152 * power management state. 153 */ 154 #define SControl_SPM_PARTIAL (0x1 << 12) /* transition to PARTIAL */ 155 #define SControl_SPM_SLUMBER (0x2 << 12) /* transition to SLUBMER */ 156 #define SControl_SPM_ComWake (0x4 << 12) /* transition from PM */ 157 /* 158 * The PMP field identifies the selected Port Multiplier Port 159 * for accessing the SActive register. 160 */ 161 #define SControl_PMP(x) ((x) << 16) 162 163 #endif /* _DEV_ATA_SATAREG_H_ */ 164
Indexes created Sun Sep 28 16:09:52 GMT 2025