if_cemac.c revision 1.1.2.7
1 1.1.2.7 skrll /* $NetBSD: if_cemac.c,v 1.1.2.7 2017/02/05 13:40:27 skrll Exp $ */ 2 1.1.2.2 skrll 3 1.1.2.2 skrll /* 4 1.1.2.2 skrll * Copyright (c) 2015 Genetec Corporation. All rights reserved. 5 1.1.2.2 skrll * Written by Hashimoto Kenichi for Genetec Corporation. 6 1.1.2.2 skrll * 7 1.1.2.2 skrll * Based on arch/arm/at91/at91emac.c 8 1.1.2.2 skrll * 9 1.1.2.2 skrll * Copyright (c) 2007 Embedtronics Oy 10 1.1.2.2 skrll * All rights reserved. 11 1.1.2.2 skrll * 12 1.1.2.2 skrll * Copyright (c) 2004 Jesse Off 13 1.1.2.2 skrll * All rights reserved. 14 1.1.2.2 skrll * 15 1.1.2.2 skrll * Redistribution and use in source and binary forms, with or without 16 1.1.2.2 skrll * modification, are permitted provided that the following conditions 17 1.1.2.2 skrll * are met: 18 1.1.2.2 skrll * 1. Redistributions of source code must retain the above copyright 19 1.1.2.2 skrll * notice, this list of conditions and the following disclaimer. 20 1.1.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 21 1.1.2.2 skrll * notice, this list of conditions and the following disclaimer in the 22 1.1.2.2 skrll * documentation and/or other materials provided with the distribution. 23 1.1.2.2 skrll * 24 1.1.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 1.1.2.2 skrll * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 1.1.2.2 skrll * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 1.1.2.2 skrll * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 1.1.2.2 skrll * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 1.1.2.2 skrll * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 1.1.2.2 skrll * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 1.1.2.2 skrll * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 1.1.2.2 skrll * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 1.1.2.2 skrll * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 1.1.2.2 skrll * POSSIBILITY OF SUCH DAMAGE. 35 1.1.2.2 skrll */ 36 1.1.2.2 skrll 37 1.1.2.2 skrll /* 38 1.1.2.2 skrll * Cadence EMAC/GEM ethernet controller IP driver 39 1.1.2.2 skrll * used by arm/at91, arm/zynq SoC 40 1.1.2.2 skrll */ 41 1.1.2.2 skrll 42 1.1.2.2 skrll #include <sys/cdefs.h> 43 1.1.2.7 skrll __KERNEL_RCSID(0, "$NetBSD: if_cemac.c,v 1.1.2.7 2017/02/05 13:40:27 skrll Exp $"); 44 1.1.2.2 skrll 45 1.1.2.2 skrll #include <sys/types.h> 46 1.1.2.2 skrll #include <sys/param.h> 47 1.1.2.2 skrll #include <sys/systm.h> 48 1.1.2.2 skrll #include <sys/ioctl.h> 49 1.1.2.2 skrll #include <sys/kernel.h> 50 1.1.2.2 skrll #include <sys/proc.h> 51 1.1.2.2 skrll #include <sys/malloc.h> 52 1.1.2.2 skrll #include <sys/time.h> 53 1.1.2.2 skrll #include <sys/device.h> 54 1.1.2.2 skrll #include <uvm/uvm_extern.h> 55 1.1.2.2 skrll 56 1.1.2.2 skrll #include <sys/bus.h> 57 1.1.2.2 skrll #include <machine/intr.h> 58 1.1.2.2 skrll 59 1.1.2.2 skrll #include <arm/cpufunc.h> 60 1.1.2.2 skrll 61 1.1.2.2 skrll #include <net/if.h> 62 1.1.2.2 skrll #include <net/if_dl.h> 63 1.1.2.2 skrll #include <net/if_types.h> 64 1.1.2.2 skrll #include <net/if_media.h> 65 1.1.2.2 skrll #include <net/if_ether.h> 66 1.1.2.2 skrll 67 1.1.2.2 skrll #include <dev/mii/mii.h> 68 1.1.2.2 skrll #include <dev/mii/miivar.h> 69 1.1.2.2 skrll 70 1.1.2.2 skrll #ifdef INET 71 1.1.2.2 skrll #include <netinet/in.h> 72 1.1.2.2 skrll #include <netinet/in_systm.h> 73 1.1.2.2 skrll #include <netinet/in_var.h> 74 1.1.2.2 skrll #include <netinet/ip.h> 75 1.1.2.2 skrll #include <netinet/if_inarp.h> 76 1.1.2.2 skrll #endif 77 1.1.2.2 skrll 78 1.1.2.2 skrll #include <net/bpf.h> 79 1.1.2.2 skrll #include <net/bpfdesc.h> 80 1.1.2.2 skrll 81 1.1.2.2 skrll #ifdef IPKDB_AT91 // @@@ 82 1.1.2.2 skrll #include <ipkdb/ipkdb.h> 83 1.1.2.2 skrll #endif 84 1.1.2.2 skrll 85 1.1.2.2 skrll #include <dev/cadence/cemacreg.h> 86 1.1.2.2 skrll #include <dev/cadence/if_cemacvar.h> 87 1.1.2.2 skrll 88 1.1.2.2 skrll #define DEFAULT_MDCDIV 32 89 1.1.2.2 skrll 90 1.1.2.2 skrll #define CEMAC_READ(x) \ 91 1.1.2.2 skrll bus_space_read_4(sc->sc_iot, sc->sc_ioh, (x)) 92 1.1.2.2 skrll #define CEMAC_WRITE(x, y) \ 93 1.1.2.2 skrll bus_space_write_4(sc->sc_iot, sc->sc_ioh, (x), (y)) 94 1.1.2.2 skrll #define CEMAC_GEM_WRITE(x, y) \ 95 1.1.2.2 skrll do { \ 96 1.1.2.2 skrll if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) \ 97 1.1.2.2 skrll bus_space_write_4(sc->sc_iot, sc->sc_ioh, (GEM_##x), (y)); \ 98 1.1.2.2 skrll else \ 99 1.1.2.2 skrll bus_space_write_4(sc->sc_iot, sc->sc_ioh, (ETH_##x), (y)); \ 100 1.1.2.2 skrll } while(0) 101 1.1.2.2 skrll 102 1.1.2.2 skrll #define RX_QLEN 64 103 1.1.2.2 skrll #define TX_QLEN 2 /* I'm very sorry but that's where we can get */ 104 1.1.2.2 skrll 105 1.1.2.2 skrll struct cemac_qmeta { 106 1.1.2.2 skrll struct mbuf *m; 107 1.1.2.2 skrll bus_dmamap_t m_dmamap; 108 1.1.2.2 skrll }; 109 1.1.2.2 skrll 110 1.1.2.2 skrll struct cemac_softc { 111 1.1.2.2 skrll device_t sc_dev; 112 1.1.2.2 skrll bus_space_tag_t sc_iot; 113 1.1.2.2 skrll bus_space_handle_t sc_ioh; 114 1.1.2.2 skrll bus_dma_tag_t sc_dmat; 115 1.1.2.2 skrll uint8_t sc_enaddr[ETHER_ADDR_LEN]; 116 1.1.2.2 skrll struct ethercom sc_ethercom; 117 1.1.2.2 skrll mii_data_t sc_mii; 118 1.1.2.2 skrll 119 1.1.2.2 skrll void *rbqpage; 120 1.1.2.2 skrll unsigned rbqlen; 121 1.1.2.2 skrll bus_addr_t rbqpage_dsaddr; 122 1.1.2.2 skrll bus_dmamap_t rbqpage_dmamap; 123 1.1.2.2 skrll void *tbqpage; 124 1.1.2.2 skrll unsigned tbqlen; 125 1.1.2.2 skrll bus_addr_t tbqpage_dsaddr; 126 1.1.2.2 skrll bus_dmamap_t tbqpage_dmamap; 127 1.1.2.2 skrll 128 1.1.2.2 skrll volatile struct eth_dsc *RDSC; 129 1.1.2.2 skrll int rxqi; 130 1.1.2.2 skrll struct cemac_qmeta rxq[RX_QLEN]; 131 1.1.2.2 skrll volatile struct eth_dsc *TDSC; 132 1.1.2.2 skrll int txqi, txqc; 133 1.1.2.2 skrll struct cemac_qmeta txq[TX_QLEN]; 134 1.1.2.2 skrll callout_t cemac_tick_ch; 135 1.1.2.2 skrll 136 1.1.2.2 skrll int cemac_flags; 137 1.1.2.2 skrll }; 138 1.1.2.2 skrll 139 1.1.2.2 skrll static void cemac_init(struct cemac_softc *); 140 1.1.2.2 skrll static int cemac_gctx(struct cemac_softc *); 141 1.1.2.2 skrll static int cemac_mediachange(struct ifnet *); 142 1.1.2.2 skrll static void cemac_mediastatus(struct ifnet *, struct ifmediareq *); 143 1.1.2.2 skrll static int cemac_mii_readreg(device_t, int, int); 144 1.1.2.2 skrll static void cemac_mii_writereg(device_t, int, int, int); 145 1.1.2.2 skrll static void cemac_statchg(struct ifnet *); 146 1.1.2.2 skrll static void cemac_tick(void *); 147 1.1.2.2 skrll static int cemac_ifioctl(struct ifnet *, u_long, void *); 148 1.1.2.2 skrll static void cemac_ifstart(struct ifnet *); 149 1.1.2.2 skrll static void cemac_ifwatchdog(struct ifnet *); 150 1.1.2.2 skrll static int cemac_ifinit(struct ifnet *); 151 1.1.2.2 skrll static void cemac_ifstop(struct ifnet *, int); 152 1.1.2.2 skrll static void cemac_setaddr(struct ifnet *); 153 1.1.2.2 skrll 154 1.1.2.2 skrll #ifdef CEMAC_DEBUG 155 1.1.2.2 skrll int cemac_debug = CEMAC_DEBUG; 156 1.1.2.2 skrll #define DPRINTFN(n,fmt) if (cemac_debug >= (n)) printf fmt 157 1.1.2.2 skrll #else 158 1.1.2.2 skrll #define DPRINTFN(n,fmt) 159 1.1.2.2 skrll #endif 160 1.1.2.2 skrll 161 1.1.2.2 skrll CFATTACH_DECL_NEW(cemac, sizeof(struct cemac_softc), 162 1.1.2.2 skrll cemac_match, cemac_attach, NULL, NULL); 163 1.1.2.2 skrll 164 1.1.2.2 skrll int 165 1.1.2.2 skrll cemac_match_common(device_t parent, cfdata_t match, void *aux) 166 1.1.2.2 skrll { 167 1.1.2.2 skrll if (strcmp(match->cf_name, "cemac") == 0) 168 1.1.2.2 skrll return 1; 169 1.1.2.2 skrll return 0; 170 1.1.2.2 skrll } 171 1.1.2.2 skrll 172 1.1.2.2 skrll void 173 1.1.2.2 skrll cemac_attach_common(device_t self, bus_space_tag_t iot, 174 1.1.2.2 skrll bus_space_handle_t ioh, bus_dma_tag_t dmat, int flags) 175 1.1.2.2 skrll { 176 1.1.2.2 skrll struct cemac_softc *sc = device_private(self); 177 1.1.2.2 skrll prop_data_t enaddr; 178 1.1.2.2 skrll uint32_t u; 179 1.1.2.2 skrll 180 1.1.2.2 skrll 181 1.1.2.2 skrll sc->sc_dev = self; 182 1.1.2.2 skrll sc->sc_ioh = ioh; 183 1.1.2.2 skrll sc->sc_iot = iot; 184 1.1.2.2 skrll sc->sc_dmat = dmat; 185 1.1.2.2 skrll sc->cemac_flags = flags; 186 1.1.2.2 skrll 187 1.1.2.2 skrll aprint_naive("\n"); 188 1.1.2.2 skrll if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 189 1.1.2.2 skrll aprint_normal(": Cadence Gigabit Ethernet Controller\n"); 190 1.1.2.2 skrll else 191 1.1.2.2 skrll aprint_normal(": Cadence Ethernet Controller\n"); 192 1.1.2.2 skrll 193 1.1.2.2 skrll /* configure emac: */ 194 1.1.2.2 skrll CEMAC_WRITE(ETH_CTL, 0); // disable everything 195 1.1.2.2 skrll CEMAC_WRITE(ETH_IDR, -1); // disable interrupts 196 1.1.2.2 skrll CEMAC_WRITE(ETH_RBQP, 0); // clear receive 197 1.1.2.2 skrll CEMAC_WRITE(ETH_TBQP, 0); // clear transmit 198 1.1.2.2 skrll if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 199 1.1.2.2 skrll CEMAC_WRITE(ETH_CFG, 200 1.1.2.2 skrll GEM_CFG_CLK_64 | GEM_CFG_GEN | ETH_CFG_SPD | ETH_CFG_FD); 201 1.1.2.2 skrll else 202 1.1.2.2 skrll CEMAC_WRITE(ETH_CFG, 203 1.1.2.2 skrll ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 204 1.1.2.2 skrll //CEMAC_WRITE(ETH_TCR, 0); // send nothing 205 1.1.2.2 skrll //(void)CEMAC_READ(ETH_ISR); 206 1.1.2.2 skrll u = CEMAC_READ(ETH_TSR); 207 1.1.2.2 skrll CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 208 1.1.2.2 skrll | ETH_TSR_IDLE | ETH_TSR_RLE 209 1.1.2.2 skrll | ETH_TSR_COL|ETH_TSR_OVR))); 210 1.1.2.2 skrll u = CEMAC_READ(ETH_RSR); 211 1.1.2.2 skrll CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR|ETH_RSR_REC|ETH_RSR_BNA))); 212 1.1.2.2 skrll 213 1.1.2.2 skrll /* Fetch the Ethernet address from property if set. */ 214 1.1.2.2 skrll enaddr = prop_dictionary_get(device_properties(self), "mac-address"); 215 1.1.2.2 skrll 216 1.1.2.2 skrll if (enaddr != NULL) { 217 1.1.2.2 skrll KASSERT(prop_object_type(enaddr) == PROP_TYPE_DATA); 218 1.1.2.2 skrll KASSERT(prop_data_size(enaddr) == ETHER_ADDR_LEN); 219 1.1.2.2 skrll memcpy(sc->sc_enaddr, prop_data_data_nocopy(enaddr), 220 1.1.2.2 skrll ETHER_ADDR_LEN); 221 1.1.2.2 skrll } else { 222 1.1.2.2 skrll static const uint8_t hardcoded[ETHER_ADDR_LEN] = { 223 1.1.2.2 skrll 0x00, 0x0d, 0x10, 0x81, 0x0c, 0x94 224 1.1.2.2 skrll }; 225 1.1.2.2 skrll memcpy(sc->sc_enaddr, hardcoded, ETHER_ADDR_LEN); 226 1.1.2.2 skrll } 227 1.1.2.2 skrll 228 1.1.2.2 skrll cemac_init(sc); 229 1.1.2.2 skrll } 230 1.1.2.2 skrll 231 1.1.2.2 skrll static int 232 1.1.2.2 skrll cemac_gctx(struct cemac_softc *sc) 233 1.1.2.2 skrll { 234 1.1.2.2 skrll struct ifnet * ifp = &sc->sc_ethercom.ec_if; 235 1.1.2.2 skrll uint32_t tsr; 236 1.1.2.2 skrll 237 1.1.2.2 skrll tsr = CEMAC_READ(ETH_TSR); 238 1.1.2.2 skrll if (!ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 239 1.1.2.2 skrll // no space left 240 1.1.2.2 skrll if (!(tsr & ETH_TSR_BNQ)) 241 1.1.2.2 skrll return 0; 242 1.1.2.2 skrll } else { 243 1.1.2.2 skrll if (tsr & GEM_TSR_TXGO) 244 1.1.2.2 skrll return 0; 245 1.1.2.2 skrll } 246 1.1.2.2 skrll CEMAC_WRITE(ETH_TSR, tsr); 247 1.1.2.2 skrll 248 1.1.2.2 skrll // free sent frames 249 1.1.2.2 skrll while (sc->txqc > (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM) ? 0 : 250 1.1.2.2 skrll (tsr & ETH_TSR_IDLE ? 0 : 1))) { 251 1.1.2.2 skrll int bi = sc->txqi % TX_QLEN; 252 1.1.2.2 skrll 253 1.1.2.2 skrll DPRINTFN(3,("%s: TDSC[%i].Addr 0x%08x\n", 254 1.1.2.2 skrll __FUNCTION__, bi, sc->TDSC[bi].Addr)); 255 1.1.2.2 skrll DPRINTFN(3,("%s: TDSC[%i].Info 0x%08x\n", 256 1.1.2.2 skrll __FUNCTION__, bi, sc->TDSC[bi].Info)); 257 1.1.2.2 skrll 258 1.1.2.2 skrll bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 259 1.1.2.2 skrll sc->txq[bi].m->m_pkthdr.len, BUS_DMASYNC_POSTWRITE); 260 1.1.2.2 skrll bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 261 1.1.2.2 skrll m_freem(sc->txq[bi].m); 262 1.1.2.2 skrll DPRINTFN(2,("%s: freed idx #%i mbuf %p (txqc=%i)\n", 263 1.1.2.2 skrll __FUNCTION__, bi, sc->txq[bi].m, sc->txqc)); 264 1.1.2.2 skrll sc->txq[bi].m = NULL; 265 1.1.2.2 skrll sc->txqi = (bi + 1) % TX_QLEN; 266 1.1.2.2 skrll sc->txqc--; 267 1.1.2.2 skrll } 268 1.1.2.2 skrll 269 1.1.2.2 skrll // mark we're free 270 1.1.2.2 skrll if (ifp->if_flags & IFF_OACTIVE) { 271 1.1.2.2 skrll ifp->if_flags &= ~IFF_OACTIVE; 272 1.1.2.2 skrll /* Disable transmit-buffer-free interrupt */ 273 1.1.2.2 skrll /*CEMAC_WRITE(ETH_IDR, ETH_ISR_TBRE);*/ 274 1.1.2.2 skrll } 275 1.1.2.2 skrll 276 1.1.2.2 skrll return 1; 277 1.1.2.2 skrll } 278 1.1.2.2 skrll 279 1.1.2.2 skrll int 280 1.1.2.2 skrll cemac_intr(void *arg) 281 1.1.2.2 skrll { 282 1.1.2.2 skrll struct cemac_softc *sc = (struct cemac_softc *)arg; 283 1.1.2.2 skrll struct ifnet * ifp = &sc->sc_ethercom.ec_if; 284 1.1.2.2 skrll uint32_t imr, isr, ctl; 285 1.1.2.2 skrll #ifdef CEMAC_DEBUG 286 1.1.2.2 skrll uint32_t rsr; 287 1.1.2.2 skrll #endif 288 1.1.2.2 skrll int bi; 289 1.1.2.2 skrll 290 1.1.2.2 skrll imr = ~CEMAC_READ(ETH_IMR); 291 1.1.2.2 skrll if (!(imr & (ETH_ISR_RCOM|ETH_ISR_TBRE|ETH_ISR_TIDLE|ETH_ISR_RBNA|ETH_ISR_ROVR|ETH_ISR_TCOM))) { 292 1.1.2.2 skrll // interrupt not enabled, can't be us 293 1.1.2.2 skrll return 0; 294 1.1.2.2 skrll } 295 1.1.2.2 skrll 296 1.1.2.2 skrll isr = CEMAC_READ(ETH_ISR); 297 1.1.2.2 skrll CEMAC_WRITE(ETH_ISR, isr); 298 1.1.2.2 skrll isr &= imr; 299 1.1.2.2 skrll #ifdef CEMAC_DEBUG 300 1.1.2.2 skrll rsr = CEMAC_READ(ETH_RSR); // get receive status register 301 1.1.2.2 skrll #endif 302 1.1.2.2 skrll DPRINTFN(2, ("%s: isr=0x%08X rsr=0x%08X imr=0x%08X\n", __FUNCTION__, isr, rsr, imr)); 303 1.1.2.2 skrll 304 1.1.2.2 skrll if (isr & ETH_ISR_RBNA) { // out of receive buffers 305 1.1.2.2 skrll CEMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear interrupt 306 1.1.2.2 skrll ctl = CEMAC_READ(ETH_CTL); // get current control register value 307 1.1.2.2 skrll CEMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); // disable receiver 308 1.1.2.2 skrll CEMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear BNA bit 309 1.1.2.2 skrll CEMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); // re-enable receiver 310 1.1.2.2 skrll ifp->if_ierrors++; 311 1.1.2.2 skrll ifp->if_ipackets++; 312 1.1.2.2 skrll DPRINTFN(1,("%s: out of receive buffers\n", __FUNCTION__)); 313 1.1.2.2 skrll } 314 1.1.2.2 skrll if (isr & ETH_ISR_ROVR) { 315 1.1.2.2 skrll CEMAC_WRITE(ETH_RSR, ETH_RSR_OVR); // clear interrupt 316 1.1.2.2 skrll ifp->if_ierrors++; 317 1.1.2.2 skrll ifp->if_ipackets++; 318 1.1.2.2 skrll DPRINTFN(1,("%s: receive overrun\n", __FUNCTION__)); 319 1.1.2.2 skrll } 320 1.1.2.2 skrll 321 1.1.2.2 skrll if (isr & ETH_ISR_RCOM) { // packet has been received! 322 1.1.2.2 skrll uint32_t nfo; 323 1.1.2.2 skrll DPRINTFN(2,("#2 RDSC[%i].INFO=0x%08X\n", sc->rxqi % RX_QLEN, sc->RDSC[sc->rxqi % RX_QLEN].Info)); 324 1.1.2.2 skrll while (sc->RDSC[(bi = sc->rxqi % RX_QLEN)].Addr & ETH_RDSC_F_USED) { 325 1.1.2.4 skrll int fl, csum; 326 1.1.2.2 skrll struct mbuf *m; 327 1.1.2.2 skrll 328 1.1.2.2 skrll nfo = sc->RDSC[bi].Info; 329 1.1.2.2 skrll fl = (nfo & ETH_RDSC_I_LEN) - 4; 330 1.1.2.2 skrll DPRINTFN(2,("## nfo=0x%08X\n", nfo)); 331 1.1.2.2 skrll 332 1.1.2.2 skrll MGETHDR(m, M_DONTWAIT, MT_DATA); 333 1.1.2.2 skrll if (m != NULL) MCLGET(m, M_DONTWAIT); 334 1.1.2.2 skrll if (m != NULL && (m->m_flags & M_EXT)) { 335 1.1.2.2 skrll bus_dmamap_sync(sc->sc_dmat, sc->rxq[bi].m_dmamap, 0, 336 1.1.2.2 skrll MCLBYTES, BUS_DMASYNC_POSTREAD); 337 1.1.2.2 skrll bus_dmamap_unload(sc->sc_dmat, 338 1.1.2.2 skrll sc->rxq[bi].m_dmamap); 339 1.1.2.6 skrll m_set_rcvif(sc->rxq[bi].m, ifp); 340 1.1.2.2 skrll sc->rxq[bi].m->m_pkthdr.len = 341 1.1.2.2 skrll sc->rxq[bi].m->m_len = fl; 342 1.1.2.4 skrll switch (nfo & ETH_RDSC_I_CHKSUM) { 343 1.1.2.4 skrll case ETH_RDSC_I_CHKSUM_IP: 344 1.1.2.4 skrll csum = M_CSUM_IPv4; 345 1.1.2.4 skrll break; 346 1.1.2.4 skrll case ETH_RDSC_I_CHKSUM_UDP: 347 1.1.2.4 skrll csum = M_CSUM_IPv4 | M_CSUM_UDPv4 | 348 1.1.2.4 skrll M_CSUM_UDPv6; 349 1.1.2.4 skrll break; 350 1.1.2.4 skrll case ETH_RDSC_I_CHKSUM_TCP: 351 1.1.2.4 skrll csum = M_CSUM_IPv4 | M_CSUM_TCPv4 | 352 1.1.2.4 skrll M_CSUM_TCPv6; 353 1.1.2.4 skrll break; 354 1.1.2.4 skrll default: 355 1.1.2.4 skrll csum = 0; 356 1.1.2.4 skrll break; 357 1.1.2.4 skrll } 358 1.1.2.4 skrll sc->rxq[bi].m->m_pkthdr.csum_flags = csum; 359 1.1.2.2 skrll DPRINTFN(2,("received %u bytes packet\n", fl)); 360 1.1.2.5 skrll if_percpuq_enqueue(ifp->if_percpuq, 361 1.1.2.5 skrll sc->rxq[bi].m); 362 1.1.2.2 skrll if (mtod(m, intptr_t) & 3) 363 1.1.2.2 skrll m_adj(m, mtod(m, intptr_t) & 3); 364 1.1.2.2 skrll sc->rxq[bi].m = m; 365 1.1.2.2 skrll bus_dmamap_load(sc->sc_dmat, 366 1.1.2.2 skrll sc->rxq[bi].m_dmamap, 367 1.1.2.2 skrll m->m_ext.ext_buf, MCLBYTES, 368 1.1.2.2 skrll NULL, BUS_DMA_NOWAIT); 369 1.1.2.2 skrll bus_dmamap_sync(sc->sc_dmat, sc->rxq[bi].m_dmamap, 0, 370 1.1.2.2 skrll MCLBYTES, BUS_DMASYNC_PREREAD); 371 1.1.2.2 skrll sc->RDSC[bi].Info = 0; 372 1.1.2.2 skrll sc->RDSC[bi].Addr = 373 1.1.2.2 skrll sc->rxq[bi].m_dmamap->dm_segs[0].ds_addr 374 1.1.2.2 skrll | (bi == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0); 375 1.1.2.2 skrll } else { 376 1.1.2.2 skrll /* Drop packets until we can get replacement 377 1.1.2.2 skrll * empty mbufs for the RXDQ. 378 1.1.2.2 skrll */ 379 1.1.2.2 skrll if (m != NULL) 380 1.1.2.2 skrll m_freem(m); 381 1.1.2.2 skrll ifp->if_ierrors++; 382 1.1.2.2 skrll } 383 1.1.2.2 skrll sc->rxqi++; 384 1.1.2.2 skrll } 385 1.1.2.2 skrll } 386 1.1.2.2 skrll 387 1.1.2.2 skrll if (cemac_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) 388 1.1.2.2 skrll cemac_ifstart(ifp); 389 1.1.2.2 skrll #if 0 // reloop 390 1.1.2.2 skrll irq = CEMAC_READ(IntStsC); 391 1.1.2.2 skrll if ((irq & (IntSts_RxSQ|IntSts_ECI)) != 0) 392 1.1.2.2 skrll goto begin; 393 1.1.2.2 skrll #endif 394 1.1.2.2 skrll 395 1.1.2.2 skrll return (1); 396 1.1.2.2 skrll } 397 1.1.2.2 skrll 398 1.1.2.2 skrll 399 1.1.2.2 skrll static void 400 1.1.2.2 skrll cemac_init(struct cemac_softc *sc) 401 1.1.2.2 skrll { 402 1.1.2.2 skrll bus_dma_segment_t segs; 403 1.1.2.2 skrll int rsegs, err, i; 404 1.1.2.2 skrll struct ifnet * ifp = &sc->sc_ethercom.ec_if; 405 1.1.2.2 skrll uint32_t u; 406 1.1.2.2 skrll #if 0 407 1.1.2.2 skrll int mdcdiv = DEFAULT_MDCDIV; 408 1.1.2.2 skrll #endif 409 1.1.2.2 skrll 410 1.1.2.2 skrll callout_init(&sc->cemac_tick_ch, 0); 411 1.1.2.2 skrll 412 1.1.2.2 skrll // ok... 413 1.1.2.2 skrll CEMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 414 1.1.2.2 skrll CEMAC_WRITE(ETH_IDR, -1); // disable interrupts 415 1.1.2.2 skrll CEMAC_WRITE(ETH_RBQP, 0); // clear receive 416 1.1.2.2 skrll CEMAC_WRITE(ETH_TBQP, 0); // clear transmit 417 1.1.2.2 skrll if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 418 1.1.2.2 skrll CEMAC_WRITE(ETH_CFG, 419 1.1.2.2 skrll GEM_CFG_CLK_64 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 420 1.1.2.2 skrll else 421 1.1.2.2 skrll CEMAC_WRITE(ETH_CFG, 422 1.1.2.2 skrll ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 423 1.1.2.2 skrll if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 424 1.1.2.2 skrll CEMAC_WRITE(GEM_DMA_CFG, 425 1.1.2.2 skrll __SHIFTIN((MCLBYTES + 63) / 64, GEM_DMA_CFG_RX_BUF_SIZE) | 426 1.1.2.2 skrll __SHIFTIN(3, GEM_DMA_CFG_RX_PKTBUF_MEMSZ_SEL) | 427 1.1.2.2 skrll GEM_DMA_CFG_TX_PKTBUF_MEMSZ_SEL | 428 1.1.2.2 skrll __SHIFTIN(16, GEM_DMA_CFG_AHB_FIXED_BURST_LEN) | 429 1.1.2.2 skrll GEM_DMA_CFG_DISC_WHEN_NO_AHB); 430 1.1.2.2 skrll } 431 1.1.2.2 skrll // CEMAC_WRITE(ETH_TCR, 0); // send nothing 432 1.1.2.2 skrll // (void)CEMAC_READ(ETH_ISR); 433 1.1.2.2 skrll u = CEMAC_READ(ETH_TSR); 434 1.1.2.2 skrll CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 435 1.1.2.2 skrll | ETH_TSR_IDLE | ETH_TSR_RLE 436 1.1.2.2 skrll | ETH_TSR_COL|ETH_TSR_OVR))); 437 1.1.2.2 skrll u = CEMAC_READ(ETH_RSR); 438 1.1.2.2 skrll CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR|ETH_RSR_REC|ETH_RSR_BNA))); 439 1.1.2.2 skrll 440 1.1.2.2 skrll #if 0 441 1.1.2.2 skrll if (device_cfdata(sc->sc_dev)->cf_flags) 442 1.1.2.2 skrll mdcdiv = device_cfdata(sc->sc_dev)->cf_flags; 443 1.1.2.2 skrll #endif 444 1.1.2.2 skrll /* set ethernet address */ 445 1.1.2.2 skrll CEMAC_GEM_WRITE(SA1L, (sc->sc_enaddr[3] << 24) 446 1.1.2.2 skrll | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8) 447 1.1.2.2 skrll | (sc->sc_enaddr[0])); 448 1.1.2.2 skrll CEMAC_GEM_WRITE(SA1H, (sc->sc_enaddr[5] << 8) 449 1.1.2.2 skrll | (sc->sc_enaddr[4])); 450 1.1.2.2 skrll CEMAC_GEM_WRITE(SA2L, 0); 451 1.1.2.2 skrll CEMAC_GEM_WRITE(SA2H, 0); 452 1.1.2.2 skrll CEMAC_GEM_WRITE(SA3L, 0); 453 1.1.2.2 skrll CEMAC_GEM_WRITE(SA3H, 0); 454 1.1.2.2 skrll CEMAC_GEM_WRITE(SA4L, 0); 455 1.1.2.2 skrll CEMAC_GEM_WRITE(SA4H, 0); 456 1.1.2.2 skrll 457 1.1.2.2 skrll /* Allocate a page of memory for receive queue descriptors */ 458 1.1.2.2 skrll sc->rbqlen = (ETH_DSC_SIZE * (RX_QLEN + 1) * 2 + PAGE_SIZE - 1) / PAGE_SIZE; 459 1.1.2.2 skrll sc->rbqlen *= PAGE_SIZE; 460 1.1.2.2 skrll DPRINTFN(1,("%s: rbqlen=%i\n", __FUNCTION__, sc->rbqlen)); 461 1.1.2.2 skrll 462 1.1.2.2 skrll err = bus_dmamem_alloc(sc->sc_dmat, sc->rbqlen, 0, 463 1.1.2.2 skrll MAX(16384, PAGE_SIZE), // see EMAC errata why forced to 16384 byte boundary 464 1.1.2.2 skrll &segs, 1, &rsegs, BUS_DMA_WAITOK); 465 1.1.2.2 skrll if (err == 0) { 466 1.1.2.2 skrll DPRINTFN(1,("%s: -> bus_dmamem_map\n", __FUNCTION__)); 467 1.1.2.2 skrll err = bus_dmamem_map(sc->sc_dmat, &segs, 1, sc->rbqlen, 468 1.1.2.2 skrll &sc->rbqpage, (BUS_DMA_WAITOK|BUS_DMA_COHERENT)); 469 1.1.2.2 skrll } 470 1.1.2.2 skrll if (err == 0) { 471 1.1.2.2 skrll DPRINTFN(1,("%s: -> bus_dmamap_create\n", __FUNCTION__)); 472 1.1.2.2 skrll err = bus_dmamap_create(sc->sc_dmat, sc->rbqlen, 1, 473 1.1.2.2 skrll sc->rbqlen, MAX(16384, PAGE_SIZE), BUS_DMA_WAITOK, 474 1.1.2.2 skrll &sc->rbqpage_dmamap); 475 1.1.2.2 skrll } 476 1.1.2.2 skrll if (err == 0) { 477 1.1.2.2 skrll DPRINTFN(1,("%s: -> bus_dmamap_load\n", __FUNCTION__)); 478 1.1.2.2 skrll err = bus_dmamap_load(sc->sc_dmat, sc->rbqpage_dmamap, 479 1.1.2.2 skrll sc->rbqpage, sc->rbqlen, NULL, BUS_DMA_WAITOK); 480 1.1.2.2 skrll } 481 1.1.2.2 skrll if (err != 0) 482 1.1.2.2 skrll panic("%s: Cannot get DMA memory", device_xname(sc->sc_dev)); 483 1.1.2.2 skrll 484 1.1.2.2 skrll sc->rbqpage_dsaddr = sc->rbqpage_dmamap->dm_segs[0].ds_addr; 485 1.1.2.2 skrll memset(sc->rbqpage, 0, sc->rbqlen); 486 1.1.2.2 skrll 487 1.1.2.2 skrll /* Allocate a page of memory for transmit queue descriptors */ 488 1.1.2.2 skrll sc->tbqlen = (ETH_DSC_SIZE * (TX_QLEN + 1) * 2 + PAGE_SIZE - 1) / PAGE_SIZE; 489 1.1.2.2 skrll sc->tbqlen *= PAGE_SIZE; 490 1.1.2.2 skrll DPRINTFN(1,("%s: tbqlen=%i\n", __FUNCTION__, sc->tbqlen)); 491 1.1.2.2 skrll 492 1.1.2.2 skrll err = bus_dmamem_alloc(sc->sc_dmat, sc->tbqlen, 0, 493 1.1.2.2 skrll MAX(16384, PAGE_SIZE), // see EMAC errata why forced to 16384 byte boundary 494 1.1.2.2 skrll &segs, 1, &rsegs, BUS_DMA_WAITOK); 495 1.1.2.2 skrll if (err == 0) { 496 1.1.2.2 skrll DPRINTFN(1,("%s: -> bus_dmamem_map\n", __FUNCTION__)); 497 1.1.2.2 skrll err = bus_dmamem_map(sc->sc_dmat, &segs, 1, sc->tbqlen, 498 1.1.2.2 skrll &sc->tbqpage, (BUS_DMA_WAITOK|BUS_DMA_COHERENT)); 499 1.1.2.2 skrll } 500 1.1.2.2 skrll if (err == 0) { 501 1.1.2.2 skrll DPRINTFN(1,("%s: -> bus_dmamap_create\n", __FUNCTION__)); 502 1.1.2.2 skrll err = bus_dmamap_create(sc->sc_dmat, sc->tbqlen, 1, 503 1.1.2.2 skrll sc->tbqlen, MAX(16384, PAGE_SIZE), BUS_DMA_WAITOK, 504 1.1.2.2 skrll &sc->tbqpage_dmamap); 505 1.1.2.2 skrll } 506 1.1.2.2 skrll if (err == 0) { 507 1.1.2.2 skrll DPRINTFN(1,("%s: -> bus_dmamap_load\n", __FUNCTION__)); 508 1.1.2.2 skrll err = bus_dmamap_load(sc->sc_dmat, sc->tbqpage_dmamap, 509 1.1.2.2 skrll sc->tbqpage, sc->tbqlen, NULL, BUS_DMA_WAITOK); 510 1.1.2.2 skrll } 511 1.1.2.2 skrll if (err != 0) 512 1.1.2.2 skrll panic("%s: Cannot get DMA memory", device_xname(sc->sc_dev)); 513 1.1.2.2 skrll 514 1.1.2.2 skrll sc->tbqpage_dsaddr = sc->tbqpage_dmamap->dm_segs[0].ds_addr; 515 1.1.2.2 skrll memset(sc->tbqpage, 0, sc->tbqlen); 516 1.1.2.2 skrll 517 1.1.2.2 skrll /* Set up pointers to start of each queue in kernel addr space. 518 1.1.2.2 skrll * Each descriptor queue or status queue entry uses 2 words 519 1.1.2.2 skrll */ 520 1.1.2.2 skrll sc->RDSC = (void *)sc->rbqpage; 521 1.1.2.2 skrll sc->TDSC = (void *)sc->tbqpage; 522 1.1.2.2 skrll 523 1.1.2.2 skrll /* init TX queue */ 524 1.1.2.2 skrll for (i = 0; i < TX_QLEN; i++) { 525 1.1.2.2 skrll sc->TDSC[i].Addr = 0; 526 1.1.2.2 skrll sc->TDSC[i].Info = ETH_TDSC_I_USED | 527 1.1.2.2 skrll (i == (TX_QLEN - 1) ? ETH_TDSC_I_WRAP : 0); 528 1.1.2.2 skrll } 529 1.1.2.2 skrll 530 1.1.2.2 skrll /* Populate the RXQ with mbufs */ 531 1.1.2.2 skrll sc->rxqi = 0; 532 1.1.2.2 skrll for(i = 0; i < RX_QLEN; i++) { 533 1.1.2.2 skrll struct mbuf *m; 534 1.1.2.2 skrll 535 1.1.2.2 skrll err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, PAGE_SIZE, 536 1.1.2.2 skrll BUS_DMA_WAITOK, &sc->rxq[i].m_dmamap); 537 1.1.2.2 skrll if (err) { 538 1.1.2.2 skrll panic("%s: dmamap_create failed: %i\n", __FUNCTION__, err); 539 1.1.2.2 skrll } 540 1.1.2.2 skrll MGETHDR(m, M_WAIT, MT_DATA); 541 1.1.2.2 skrll MCLGET(m, M_WAIT); 542 1.1.2.2 skrll sc->rxq[i].m = m; 543 1.1.2.2 skrll if (mtod(m, intptr_t) & 3) { 544 1.1.2.2 skrll m_adj(m, mtod(m, intptr_t) & 3); 545 1.1.2.2 skrll } 546 1.1.2.2 skrll err = bus_dmamap_load(sc->sc_dmat, sc->rxq[i].m_dmamap, 547 1.1.2.2 skrll m->m_ext.ext_buf, MCLBYTES, NULL, 548 1.1.2.2 skrll BUS_DMA_WAITOK); 549 1.1.2.2 skrll if (err) { 550 1.1.2.2 skrll panic("%s: dmamap_load failed: %i\n", __FUNCTION__, err); 551 1.1.2.2 skrll } 552 1.1.2.2 skrll sc->RDSC[i].Addr = sc->rxq[i].m_dmamap->dm_segs[0].ds_addr 553 1.1.2.2 skrll | (i == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0); 554 1.1.2.2 skrll sc->RDSC[i].Info = 0; 555 1.1.2.2 skrll bus_dmamap_sync(sc->sc_dmat, sc->rxq[i].m_dmamap, 0, 556 1.1.2.2 skrll MCLBYTES, BUS_DMASYNC_PREREAD); 557 1.1.2.2 skrll } 558 1.1.2.2 skrll 559 1.1.2.2 skrll /* prepare transmit queue */ 560 1.1.2.2 skrll for (i = 0; i < TX_QLEN; i++) { 561 1.1.2.2 skrll err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 562 1.1.2.2 skrll (BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW), 563 1.1.2.2 skrll &sc->txq[i].m_dmamap); 564 1.1.2.2 skrll if (err) 565 1.1.2.2 skrll panic("ARGH #1"); 566 1.1.2.2 skrll sc->txq[i].m = NULL; 567 1.1.2.2 skrll } 568 1.1.2.2 skrll 569 1.1.2.2 skrll /* Program each queue's start addr, cur addr, and len registers 570 1.1.2.2 skrll * with the physical addresses. 571 1.1.2.2 skrll */ 572 1.1.2.2 skrll CEMAC_WRITE(ETH_RBQP, (uint32_t)sc->rbqpage_dsaddr); 573 1.1.2.2 skrll CEMAC_WRITE(ETH_TBQP, (uint32_t)sc->tbqpage_dsaddr); 574 1.1.2.2 skrll 575 1.1.2.2 skrll /* Divide HCLK by 32 for MDC clock */ 576 1.1.2.2 skrll sc->sc_ethercom.ec_mii = &sc->sc_mii; 577 1.1.2.2 skrll sc->sc_mii.mii_ifp = ifp; 578 1.1.2.2 skrll sc->sc_mii.mii_readreg = cemac_mii_readreg; 579 1.1.2.2 skrll sc->sc_mii.mii_writereg = cemac_mii_writereg; 580 1.1.2.2 skrll sc->sc_mii.mii_statchg = cemac_statchg; 581 1.1.2.2 skrll ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, cemac_mediachange, 582 1.1.2.2 skrll cemac_mediastatus); 583 1.1.2.2 skrll mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 584 1.1.2.2 skrll MII_OFFSET_ANY, 0); 585 1.1.2.2 skrll ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 586 1.1.2.2 skrll 587 1.1.2.2 skrll #if 0 588 1.1.2.2 skrll // enable / disable interrupts 589 1.1.2.2 skrll CEMAC_WRITE(ETH_IDR, -1); 590 1.1.2.2 skrll CEMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 591 1.1.2.2 skrll | ETH_ISR_RBNA | ETH_ISR_ROVR | ETH_ISR_TCOM); 592 1.1.2.2 skrll // (void)CEMAC_READ(ETH_ISR); // why 593 1.1.2.2 skrll 594 1.1.2.2 skrll // enable transmitter / receiver 595 1.1.2.2 skrll CEMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 596 1.1.2.2 skrll | ETH_CTL_CSR | ETH_CTL_MPE); 597 1.1.2.2 skrll #endif 598 1.1.2.2 skrll /* 599 1.1.2.4 skrll * We can support hardware checksumming. 600 1.1.2.4 skrll */ 601 1.1.2.4 skrll ifp->if_capabilities |= 602 1.1.2.4 skrll IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 603 1.1.2.4 skrll IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 604 1.1.2.4 skrll IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 605 1.1.2.4 skrll IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_TCPv6_Rx | 606 1.1.2.4 skrll IFCAP_CSUM_UDPv6_Tx | IFCAP_CSUM_UDPv6_Rx; 607 1.1.2.4 skrll 608 1.1.2.4 skrll /* 609 1.1.2.2 skrll * We can support 802.1Q VLAN-sized frames. 610 1.1.2.2 skrll */ 611 1.1.2.2 skrll sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 612 1.1.2.2 skrll 613 1.1.2.2 skrll strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 614 1.1.2.2 skrll ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 615 1.1.2.2 skrll ifp->if_ioctl = cemac_ifioctl; 616 1.1.2.2 skrll ifp->if_start = cemac_ifstart; 617 1.1.2.2 skrll ifp->if_watchdog = cemac_ifwatchdog; 618 1.1.2.2 skrll ifp->if_init = cemac_ifinit; 619 1.1.2.2 skrll ifp->if_stop = cemac_ifstop; 620 1.1.2.2 skrll ifp->if_timer = 0; 621 1.1.2.2 skrll ifp->if_softc = sc; 622 1.1.2.2 skrll IFQ_SET_READY(&ifp->if_snd); 623 1.1.2.2 skrll if_attach(ifp); 624 1.1.2.2 skrll ether_ifattach(ifp, (sc)->sc_enaddr); 625 1.1.2.2 skrll } 626 1.1.2.2 skrll 627 1.1.2.2 skrll static int 628 1.1.2.2 skrll cemac_mediachange(struct ifnet *ifp) 629 1.1.2.2 skrll { 630 1.1.2.2 skrll if (ifp->if_flags & IFF_UP) 631 1.1.2.2 skrll cemac_ifinit(ifp); 632 1.1.2.2 skrll return (0); 633 1.1.2.2 skrll } 634 1.1.2.2 skrll 635 1.1.2.2 skrll static void 636 1.1.2.2 skrll cemac_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 637 1.1.2.2 skrll { 638 1.1.2.2 skrll struct cemac_softc *sc = ifp->if_softc; 639 1.1.2.2 skrll 640 1.1.2.2 skrll mii_pollstat(&sc->sc_mii); 641 1.1.2.2 skrll ifmr->ifm_active = sc->sc_mii.mii_media_active; 642 1.1.2.2 skrll ifmr->ifm_status = sc->sc_mii.mii_media_status; 643 1.1.2.2 skrll } 644 1.1.2.2 skrll 645 1.1.2.2 skrll 646 1.1.2.2 skrll static int 647 1.1.2.2 skrll cemac_mii_readreg(device_t self, int phy, int reg) 648 1.1.2.2 skrll { 649 1.1.2.2 skrll struct cemac_softc *sc; 650 1.1.2.2 skrll 651 1.1.2.2 skrll sc = device_private(self); 652 1.1.2.2 skrll 653 1.1.2.2 skrll CEMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_RD 654 1.1.2.2 skrll | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA) 655 1.1.2.2 skrll | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA) 656 1.1.2.2 skrll | ETH_MAN_CODE_IEEE802_3)); 657 1.1.2.2 skrll while (!(CEMAC_READ(ETH_SR) & ETH_SR_IDLE)); 658 1.1.2.2 skrll 659 1.1.2.2 skrll return (CEMAC_READ(ETH_MAN) & ETH_MAN_DATA); 660 1.1.2.2 skrll } 661 1.1.2.2 skrll 662 1.1.2.2 skrll static void 663 1.1.2.2 skrll cemac_mii_writereg(device_t self, int phy, int reg, int val) 664 1.1.2.2 skrll { 665 1.1.2.2 skrll struct cemac_softc *sc; 666 1.1.2.2 skrll 667 1.1.2.2 skrll sc = device_private(self); 668 1.1.2.2 skrll 669 1.1.2.2 skrll CEMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_WR 670 1.1.2.2 skrll | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA) 671 1.1.2.2 skrll | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA) 672 1.1.2.2 skrll | ETH_MAN_CODE_IEEE802_3 673 1.1.2.2 skrll | (val & ETH_MAN_DATA))); 674 1.1.2.2 skrll while (!(CEMAC_READ(ETH_SR) & ETH_SR_IDLE)) ; 675 1.1.2.2 skrll } 676 1.1.2.2 skrll 677 1.1.2.2 skrll 678 1.1.2.2 skrll static void 679 1.1.2.2 skrll cemac_statchg(struct ifnet *ifp) 680 1.1.2.2 skrll { 681 1.1.2.2 skrll struct cemac_softc *sc = ifp->if_softc; 682 1.1.2.2 skrll struct mii_data *mii = &sc->sc_mii; 683 1.1.2.2 skrll uint32_t reg; 684 1.1.2.2 skrll 685 1.1.2.2 skrll /* 686 1.1.2.2 skrll * We must keep the MAC and the PHY in sync as 687 1.1.2.2 skrll * to the status of full-duplex! 688 1.1.2.2 skrll */ 689 1.1.2.2 skrll reg = CEMAC_READ(ETH_CFG); 690 1.1.2.2 skrll reg &= ~ETH_CFG_FD; 691 1.1.2.2 skrll if (sc->sc_mii.mii_media_active & IFM_FDX) 692 1.1.2.2 skrll reg |= ETH_CFG_FD; 693 1.1.2.2 skrll 694 1.1.2.2 skrll reg &= ~ETH_CFG_SPD; 695 1.1.2.2 skrll if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 696 1.1.2.2 skrll reg &= ~GEM_CFG_GEN; 697 1.1.2.2 skrll switch (IFM_SUBTYPE(mii->mii_media_active)) { 698 1.1.2.2 skrll case IFM_10_T: 699 1.1.2.2 skrll break; 700 1.1.2.2 skrll case IFM_100_TX: 701 1.1.2.2 skrll reg |= ETH_CFG_SPD; 702 1.1.2.2 skrll break; 703 1.1.2.2 skrll case IFM_1000_T: 704 1.1.2.2 skrll reg |= ETH_CFG_SPD | GEM_CFG_GEN; 705 1.1.2.2 skrll break; 706 1.1.2.2 skrll default: 707 1.1.2.2 skrll break; 708 1.1.2.2 skrll } 709 1.1.2.2 skrll CEMAC_WRITE(ETH_CFG, reg); 710 1.1.2.2 skrll } 711 1.1.2.2 skrll 712 1.1.2.2 skrll static void 713 1.1.2.2 skrll cemac_tick(void *arg) 714 1.1.2.2 skrll { 715 1.1.2.2 skrll struct cemac_softc* sc = (struct cemac_softc *)arg; 716 1.1.2.2 skrll struct ifnet * ifp = &sc->sc_ethercom.ec_if; 717 1.1.2.2 skrll int s; 718 1.1.2.2 skrll 719 1.1.2.4 skrll if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 720 1.1.2.4 skrll ifp->if_collisions += CEMAC_READ(GEM_SCOL) + CEMAC_READ(GEM_MCOL); 721 1.1.2.4 skrll else 722 1.1.2.4 skrll ifp->if_collisions += CEMAC_READ(ETH_SCOL) + CEMAC_READ(ETH_MCOL); 723 1.1.2.4 skrll 724 1.1.2.2 skrll /* These misses are ok, they will happen if the RAM/CPU can't keep up */ 725 1.1.2.2 skrll if (!ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 726 1.1.2.2 skrll uint32_t misses = CEMAC_READ(ETH_DRFC); 727 1.1.2.2 skrll if (misses > 0) 728 1.1.2.4 skrll aprint_normal_ifnet(ifp, "%d rx misses\n", misses); 729 1.1.2.2 skrll } 730 1.1.2.2 skrll 731 1.1.2.2 skrll s = splnet(); 732 1.1.2.2 skrll if (cemac_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) 733 1.1.2.2 skrll cemac_ifstart(ifp); 734 1.1.2.2 skrll splx(s); 735 1.1.2.2 skrll 736 1.1.2.2 skrll mii_tick(&sc->sc_mii); 737 1.1.2.2 skrll callout_reset(&sc->cemac_tick_ch, hz, cemac_tick, sc); 738 1.1.2.2 skrll } 739 1.1.2.2 skrll 740 1.1.2.2 skrll 741 1.1.2.2 skrll static int 742 1.1.2.2 skrll cemac_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 743 1.1.2.2 skrll { 744 1.1.2.2 skrll struct cemac_softc *sc = ifp->if_softc; 745 1.1.2.2 skrll struct ifreq *ifr = (struct ifreq *)data; 746 1.1.2.2 skrll int s, error; 747 1.1.2.2 skrll 748 1.1.2.2 skrll s = splnet(); 749 1.1.2.2 skrll switch(cmd) { 750 1.1.2.2 skrll case SIOCSIFMEDIA: 751 1.1.2.2 skrll case SIOCGIFMEDIA: 752 1.1.2.2 skrll error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 753 1.1.2.2 skrll break; 754 1.1.2.2 skrll default: 755 1.1.2.2 skrll error = ether_ioctl(ifp, cmd, data); 756 1.1.2.4 skrll if (error != ENETRESET) 757 1.1.2.4 skrll break; 758 1.1.2.4 skrll error = 0; 759 1.1.2.4 skrll 760 1.1.2.4 skrll if (cmd == SIOCSIFCAP) { 761 1.1.2.4 skrll error = (*ifp->if_init)(ifp); 762 1.1.2.4 skrll } else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 763 1.1.2.4 skrll ; 764 1.1.2.4 skrll else if (ifp->if_flags & IFF_RUNNING) { 765 1.1.2.4 skrll cemac_setaddr(ifp); 766 1.1.2.2 skrll } 767 1.1.2.2 skrll } 768 1.1.2.2 skrll splx(s); 769 1.1.2.2 skrll return error; 770 1.1.2.2 skrll } 771 1.1.2.2 skrll 772 1.1.2.2 skrll static void 773 1.1.2.2 skrll cemac_ifstart(struct ifnet *ifp) 774 1.1.2.2 skrll { 775 1.1.2.2 skrll struct cemac_softc *sc = (struct cemac_softc *)ifp->if_softc; 776 1.1.2.2 skrll struct mbuf *m; 777 1.1.2.2 skrll bus_dma_segment_t *segs; 778 1.1.2.2 skrll int s, bi, err, nsegs; 779 1.1.2.2 skrll 780 1.1.2.2 skrll s = splnet(); 781 1.1.2.2 skrll start: 782 1.1.2.2 skrll if (cemac_gctx(sc) == 0) { 783 1.1.2.2 skrll /* Enable transmit-buffer-free interrupt */ 784 1.1.2.2 skrll CEMAC_WRITE(ETH_IER, ETH_ISR_TBRE); 785 1.1.2.2 skrll ifp->if_flags |= IFF_OACTIVE; 786 1.1.2.2 skrll ifp->if_timer = 10; 787 1.1.2.2 skrll splx(s); 788 1.1.2.2 skrll return; 789 1.1.2.2 skrll } 790 1.1.2.2 skrll 791 1.1.2.2 skrll ifp->if_timer = 0; 792 1.1.2.2 skrll 793 1.1.2.2 skrll IFQ_POLL(&ifp->if_snd, m); 794 1.1.2.2 skrll if (m == NULL) { 795 1.1.2.2 skrll splx(s); 796 1.1.2.2 skrll return; 797 1.1.2.2 skrll } 798 1.1.2.2 skrll 799 1.1.2.2 skrll bi = (sc->txqi + sc->txqc) % TX_QLEN; 800 1.1.2.2 skrll if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 801 1.1.2.2 skrll BUS_DMA_NOWAIT)) || 802 1.1.2.2 skrll sc->txq[bi].m_dmamap->dm_segs[0].ds_addr & 0x3 || 803 1.1.2.2 skrll sc->txq[bi].m_dmamap->dm_nsegs > 1) { 804 1.1.2.2 skrll /* Copy entire mbuf chain to new single */ 805 1.1.2.2 skrll struct mbuf *mn; 806 1.1.2.2 skrll 807 1.1.2.2 skrll if (err == 0) 808 1.1.2.2 skrll bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 809 1.1.2.2 skrll 810 1.1.2.2 skrll MGETHDR(mn, M_DONTWAIT, MT_DATA); 811 1.1.2.2 skrll if (mn == NULL) goto stop; 812 1.1.2.2 skrll if (m->m_pkthdr.len > MHLEN) { 813 1.1.2.2 skrll MCLGET(mn, M_DONTWAIT); 814 1.1.2.2 skrll if ((mn->m_flags & M_EXT) == 0) { 815 1.1.2.2 skrll m_freem(mn); 816 1.1.2.2 skrll goto stop; 817 1.1.2.2 skrll } 818 1.1.2.2 skrll } 819 1.1.2.2 skrll m_copydata(m, 0, m->m_pkthdr.len, mtod(mn, void *)); 820 1.1.2.2 skrll mn->m_pkthdr.len = mn->m_len = m->m_pkthdr.len; 821 1.1.2.2 skrll IFQ_DEQUEUE(&ifp->if_snd, m); 822 1.1.2.2 skrll m_freem(m); 823 1.1.2.2 skrll m = mn; 824 1.1.2.2 skrll bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 825 1.1.2.2 skrll BUS_DMA_NOWAIT); 826 1.1.2.2 skrll } else { 827 1.1.2.2 skrll IFQ_DEQUEUE(&ifp->if_snd, m); 828 1.1.2.2 skrll } 829 1.1.2.2 skrll 830 1.1.2.2 skrll bpf_mtap(ifp, m); 831 1.1.2.2 skrll 832 1.1.2.2 skrll nsegs = sc->txq[bi].m_dmamap->dm_nsegs; 833 1.1.2.2 skrll segs = sc->txq[bi].m_dmamap->dm_segs; 834 1.1.2.2 skrll if (nsegs > 1) 835 1.1.2.2 skrll panic("#### ARGH #2"); 836 1.1.2.2 skrll 837 1.1.2.2 skrll sc->txq[bi].m = m; 838 1.1.2.2 skrll sc->txqc++; 839 1.1.2.2 skrll 840 1.1.2.2 skrll DPRINTFN(2,("%s: start sending idx #%i mbuf %p (txqc=%i, phys %p), len=%u\n", 841 1.1.2.2 skrll __FUNCTION__, bi, sc->txq[bi].m, sc->txqc, (void*)segs->ds_addr, 842 1.1.2.2 skrll (unsigned)m->m_pkthdr.len)); 843 1.1.2.2 skrll #ifdef DIAGNOSTIC 844 1.1.2.2 skrll if (sc->txqc > TX_QLEN) 845 1.1.2.2 skrll panic("%s: txqc %i > %i", __FUNCTION__, sc->txqc, TX_QLEN); 846 1.1.2.2 skrll #endif 847 1.1.2.2 skrll 848 1.1.2.2 skrll bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 849 1.1.2.2 skrll sc->txq[bi].m_dmamap->dm_mapsize, 850 1.1.2.2 skrll BUS_DMASYNC_PREWRITE); 851 1.1.2.2 skrll 852 1.1.2.2 skrll if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 853 1.1.2.2 skrll sc->TDSC[bi].Addr = segs->ds_addr; 854 1.1.2.2 skrll sc->TDSC[bi].Info = __SHIFTIN(m->m_pkthdr.len, ETH_TDSC_I_LEN) | 855 1.1.2.2 skrll ETH_TDSC_I_LAST_BUF | (bi == (TX_QLEN - 1) ? ETH_TDSC_I_WRAP : 0); 856 1.1.2.2 skrll 857 1.1.2.2 skrll DPRINTFN(3,("%s: TDSC[%i].Addr 0x%08x\n", 858 1.1.2.2 skrll __FUNCTION__, bi, sc->TDSC[bi].Addr)); 859 1.1.2.2 skrll DPRINTFN(3,("%s: TDSC[%i].Info 0x%08x\n", 860 1.1.2.2 skrll __FUNCTION__, bi, sc->TDSC[bi].Info)); 861 1.1.2.2 skrll 862 1.1.2.2 skrll uint32_t ctl = CEMAC_READ(ETH_CTL) | GEM_CTL_STARTTX; 863 1.1.2.2 skrll CEMAC_WRITE(ETH_CTL, ctl); 864 1.1.2.2 skrll DPRINTFN(3,("%s: ETH_CTL 0x%08x\n", __FUNCTION__, CEMAC_READ(ETH_CTL))); 865 1.1.2.2 skrll } else { 866 1.1.2.2 skrll CEMAC_WRITE(ETH_TAR, segs->ds_addr); 867 1.1.2.2 skrll CEMAC_WRITE(ETH_TCR, m->m_pkthdr.len); 868 1.1.2.2 skrll } 869 1.1.2.2 skrll if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 870 1.1.2.2 skrll goto start; 871 1.1.2.2 skrll stop: 872 1.1.2.2 skrll 873 1.1.2.2 skrll splx(s); 874 1.1.2.2 skrll return; 875 1.1.2.2 skrll } 876 1.1.2.2 skrll 877 1.1.2.2 skrll static void 878 1.1.2.2 skrll cemac_ifwatchdog(struct ifnet *ifp) 879 1.1.2.2 skrll { 880 1.1.2.2 skrll struct cemac_softc *sc = (struct cemac_softc *)ifp->if_softc; 881 1.1.2.2 skrll 882 1.1.2.2 skrll if ((ifp->if_flags & IFF_RUNNING) == 0) 883 1.1.2.2 skrll return; 884 1.1.2.4 skrll aprint_error_ifnet(ifp, "device timeout, CTL = 0x%08x, CFG = 0x%08x\n", 885 1.1.2.4 skrll CEMAC_READ(ETH_CTL), CEMAC_READ(ETH_CFG)); 886 1.1.2.2 skrll } 887 1.1.2.2 skrll 888 1.1.2.2 skrll static int 889 1.1.2.2 skrll cemac_ifinit(struct ifnet *ifp) 890 1.1.2.2 skrll { 891 1.1.2.2 skrll struct cemac_softc *sc = ifp->if_softc; 892 1.1.2.4 skrll uint32_t dma, cfg; 893 1.1.2.2 skrll int s = splnet(); 894 1.1.2.2 skrll 895 1.1.2.2 skrll callout_stop(&sc->cemac_tick_ch); 896 1.1.2.2 skrll 897 1.1.2.4 skrll if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 898 1.1.2.4 skrll 899 1.1.2.4 skrll if (ifp->if_capenable & 900 1.1.2.4 skrll (IFCAP_CSUM_IPv4_Tx | 901 1.1.2.4 skrll IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx | 902 1.1.2.4 skrll IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx)) { 903 1.1.2.4 skrll dma = CEMAC_READ(GEM_DMA_CFG); 904 1.1.2.4 skrll dma |= GEM_DMA_CFG_CHKSUM_GEN_OFFLOAD_EN; 905 1.1.2.4 skrll CEMAC_WRITE(GEM_DMA_CFG, dma); 906 1.1.2.4 skrll } 907 1.1.2.4 skrll if (ifp->if_capenable & 908 1.1.2.4 skrll (IFCAP_CSUM_IPv4_Rx | 909 1.1.2.4 skrll IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 910 1.1.2.4 skrll IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx)) { 911 1.1.2.4 skrll cfg = CEMAC_READ(ETH_CFG); 912 1.1.2.4 skrll cfg |= GEM_CFG_RX_CHKSUM_OFFLD_EN; 913 1.1.2.4 skrll CEMAC_WRITE(ETH_CFG, cfg); 914 1.1.2.4 skrll } 915 1.1.2.4 skrll } 916 1.1.2.4 skrll 917 1.1.2.2 skrll // enable interrupts 918 1.1.2.2 skrll CEMAC_WRITE(ETH_IDR, -1); 919 1.1.2.2 skrll CEMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 920 1.1.2.2 skrll | ETH_ISR_RBNA | ETH_ISR_ROVR | ETH_ISR_TCOM); 921 1.1.2.2 skrll 922 1.1.2.2 skrll // enable transmitter / receiver 923 1.1.2.2 skrll CEMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 924 1.1.2.2 skrll | ETH_CTL_CSR | ETH_CTL_MPE); 925 1.1.2.2 skrll 926 1.1.2.2 skrll mii_mediachg(&sc->sc_mii); 927 1.1.2.2 skrll callout_reset(&sc->cemac_tick_ch, hz, cemac_tick, sc); 928 1.1.2.2 skrll ifp->if_flags |= IFF_RUNNING; 929 1.1.2.2 skrll splx(s); 930 1.1.2.2 skrll return 0; 931 1.1.2.2 skrll } 932 1.1.2.2 skrll 933 1.1.2.2 skrll static void 934 1.1.2.2 skrll cemac_ifstop(struct ifnet *ifp, int disable) 935 1.1.2.2 skrll { 936 1.1.2.2 skrll // uint32_t u; 937 1.1.2.2 skrll struct cemac_softc *sc = ifp->if_softc; 938 1.1.2.2 skrll 939 1.1.2.2 skrll #if 0 940 1.1.2.2 skrll CEMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 941 1.1.2.2 skrll CEMAC_WRITE(ETH_IDR, -1); // disable interrupts 942 1.1.2.2 skrll // CEMAC_WRITE(ETH_RBQP, 0); // clear receive 943 1.1.2.2 skrll if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 944 1.1.2.2 skrll CEMAC_WRITE(ETH_CFG, 945 1.1.2.2 skrll GEM_CFG_CLK_64 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 946 1.1.2.2 skrll else 947 1.1.2.2 skrll CEMAC_WRITE(ETH_CFG, 948 1.1.2.2 skrll ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 949 1.1.2.2 skrll // CEMAC_WRITE(ETH_TCR, 0); // send nothing 950 1.1.2.2 skrll // (void)CEMAC_READ(ETH_ISR); 951 1.1.2.2 skrll u = CEMAC_READ(ETH_TSR); 952 1.1.2.2 skrll CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 953 1.1.2.2 skrll | ETH_TSR_IDLE | ETH_TSR_RLE 954 1.1.2.2 skrll | ETH_TSR_COL|ETH_TSR_OVR))); 955 1.1.2.2 skrll u = CEMAC_READ(ETH_RSR); 956 1.1.2.2 skrll CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR|ETH_RSR_REC|ETH_RSR_BNA))); 957 1.1.2.2 skrll #endif 958 1.1.2.2 skrll callout_stop(&sc->cemac_tick_ch); 959 1.1.2.2 skrll 960 1.1.2.2 skrll /* Down the MII. */ 961 1.1.2.2 skrll mii_down(&sc->sc_mii); 962 1.1.2.2 skrll 963 1.1.2.2 skrll ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 964 1.1.2.2 skrll ifp->if_timer = 0; 965 1.1.2.2 skrll sc->sc_mii.mii_media_status &= ~IFM_ACTIVE; 966 1.1.2.2 skrll } 967 1.1.2.2 skrll 968 1.1.2.2 skrll static void 969 1.1.2.2 skrll cemac_setaddr(struct ifnet *ifp) 970 1.1.2.2 skrll { 971 1.1.2.2 skrll struct cemac_softc *sc = ifp->if_softc; 972 1.1.2.2 skrll struct ethercom *ac = &sc->sc_ethercom; 973 1.1.2.2 skrll struct ether_multi *enm; 974 1.1.2.2 skrll struct ether_multistep step; 975 1.1.2.2 skrll uint8_t ias[3][ETHER_ADDR_LEN]; 976 1.1.2.2 skrll uint32_t h, nma = 0, hashes[2] = { 0, 0 }; 977 1.1.2.2 skrll uint32_t ctl = CEMAC_READ(ETH_CTL); 978 1.1.2.2 skrll uint32_t cfg = CEMAC_READ(ETH_CFG); 979 1.1.2.2 skrll 980 1.1.2.2 skrll /* disable receiver temporarily */ 981 1.1.2.2 skrll CEMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); 982 1.1.2.2 skrll 983 1.1.2.2 skrll cfg &= ~(ETH_CFG_MTI | ETH_CFG_UNI | ETH_CFG_CAF | ETH_CFG_UNI); 984 1.1.2.2 skrll 985 1.1.2.2 skrll if (ifp->if_flags & IFF_PROMISC) { 986 1.1.2.2 skrll cfg |= ETH_CFG_CAF; 987 1.1.2.2 skrll } else { 988 1.1.2.2 skrll cfg &= ~ETH_CFG_CAF; 989 1.1.2.2 skrll } 990 1.1.2.2 skrll 991 1.1.2.2 skrll // ETH_CFG_BIG? 992 1.1.2.2 skrll 993 1.1.2.2 skrll ifp->if_flags &= ~IFF_ALLMULTI; 994 1.1.2.2 skrll 995 1.1.2.2 skrll ETHER_FIRST_MULTI(step, ac, enm); 996 1.1.2.2 skrll while (enm != NULL) { 997 1.1.2.2 skrll if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 998 1.1.2.2 skrll /* 999 1.1.2.2 skrll * We must listen to a range of multicast addresses. 1000 1.1.2.2 skrll * For now, just accept all multicasts, rather than 1001 1.1.2.2 skrll * trying to set only those filter bits needed to match 1002 1.1.2.2 skrll * the range. (At this time, the only use of address 1003 1.1.2.2 skrll * ranges is for IP multicast routing, for which the 1004 1.1.2.2 skrll * range is big enough to require all bits set.) 1005 1.1.2.2 skrll */ 1006 1.1.2.4 skrll cfg |= ETH_CFG_MTI; 1007 1.1.2.2 skrll hashes[0] = 0xffffffffUL; 1008 1.1.2.2 skrll hashes[1] = 0xffffffffUL; 1009 1.1.2.2 skrll ifp->if_flags |= IFF_ALLMULTI; 1010 1.1.2.2 skrll nma = 0; 1011 1.1.2.2 skrll break; 1012 1.1.2.2 skrll } 1013 1.1.2.2 skrll 1014 1.1.2.2 skrll if (nma < 3) { 1015 1.1.2.2 skrll /* We can program 3 perfect address filters for mcast */ 1016 1.1.2.2 skrll memcpy(ias[nma], enm->enm_addrlo, ETHER_ADDR_LEN); 1017 1.1.2.2 skrll } else { 1018 1.1.2.2 skrll /* 1019 1.1.2.2 skrll * XXX: Datasheet is not very clear here, I'm not sure 1020 1.1.2.2 skrll * if I'm doing this right. --joff 1021 1.1.2.2 skrll */ 1022 1.1.2.2 skrll h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1023 1.1.2.2 skrll 1024 1.1.2.2 skrll /* Just want the 6 most-significant bits. */ 1025 1.1.2.2 skrll h = h >> 26; 1026 1.1.2.4 skrll #if 0 1027 1.1.2.2 skrll hashes[h / 32] |= (1 << (h % 32)); 1028 1.1.2.4 skrll #else 1029 1.1.2.4 skrll hashes[0] = 0xffffffffUL; 1030 1.1.2.4 skrll hashes[1] = 0xffffffffUL; 1031 1.1.2.4 skrll #endif 1032 1.1.2.2 skrll cfg |= ETH_CFG_MTI; 1033 1.1.2.2 skrll } 1034 1.1.2.2 skrll ETHER_NEXT_MULTI(step, enm); 1035 1.1.2.2 skrll nma++; 1036 1.1.2.2 skrll } 1037 1.1.2.2 skrll 1038 1.1.2.2 skrll // program... 1039 1.1.2.2 skrll DPRINTFN(1,("%s: en0 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 1040 1.1.2.2 skrll sc->sc_enaddr[0], sc->sc_enaddr[1], sc->sc_enaddr[2], 1041 1.1.2.2 skrll sc->sc_enaddr[3], sc->sc_enaddr[4], sc->sc_enaddr[5])); 1042 1.1.2.2 skrll CEMAC_GEM_WRITE(SA1L, (sc->sc_enaddr[3] << 24) 1043 1.1.2.2 skrll | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8) 1044 1.1.2.2 skrll | (sc->sc_enaddr[0])); 1045 1.1.2.2 skrll CEMAC_GEM_WRITE(SA1H, (sc->sc_enaddr[5] << 8) 1046 1.1.2.2 skrll | (sc->sc_enaddr[4])); 1047 1.1.2.4 skrll if (nma > 0) { 1048 1.1.2.2 skrll DPRINTFN(1,("%s: en1 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 1049 1.1.2.2 skrll ias[0][0], ias[0][1], ias[0][2], 1050 1.1.2.2 skrll ias[0][3], ias[0][4], ias[0][5])); 1051 1.1.2.2 skrll CEMAC_WRITE(ETH_SA2L, (ias[0][3] << 24) 1052 1.1.2.2 skrll | (ias[0][2] << 16) | (ias[0][1] << 8) 1053 1.1.2.2 skrll | (ias[0][0])); 1054 1.1.2.2 skrll CEMAC_WRITE(ETH_SA2H, (ias[0][4] << 8) 1055 1.1.2.2 skrll | (ias[0][5])); 1056 1.1.2.2 skrll } 1057 1.1.2.4 skrll if (nma > 1) { 1058 1.1.2.2 skrll DPRINTFN(1,("%s: en2 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 1059 1.1.2.2 skrll ias[1][0], ias[1][1], ias[1][2], 1060 1.1.2.2 skrll ias[1][3], ias[1][4], ias[1][5])); 1061 1.1.2.2 skrll CEMAC_WRITE(ETH_SA3L, (ias[1][3] << 24) 1062 1.1.2.2 skrll | (ias[1][2] << 16) | (ias[1][1] << 8) 1063 1.1.2.2 skrll | (ias[1][0])); 1064 1.1.2.2 skrll CEMAC_WRITE(ETH_SA3H, (ias[1][4] << 8) 1065 1.1.2.2 skrll | (ias[1][5])); 1066 1.1.2.2 skrll } 1067 1.1.2.4 skrll if (nma > 2) { 1068 1.1.2.2 skrll DPRINTFN(1,("%s: en3 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 1069 1.1.2.2 skrll ias[2][0], ias[2][1], ias[2][2], 1070 1.1.2.2 skrll ias[2][3], ias[2][4], ias[2][5])); 1071 1.1.2.4 skrll CEMAC_WRITE(ETH_SA4L, (ias[2][3] << 24) 1072 1.1.2.2 skrll | (ias[2][2] << 16) | (ias[2][1] << 8) 1073 1.1.2.2 skrll | (ias[2][0])); 1074 1.1.2.4 skrll CEMAC_WRITE(ETH_SA4H, (ias[2][4] << 8) 1075 1.1.2.2 skrll | (ias[2][5])); 1076 1.1.2.2 skrll } 1077 1.1.2.2 skrll CEMAC_GEM_WRITE(HSH, hashes[0]); 1078 1.1.2.2 skrll CEMAC_GEM_WRITE(HSL, hashes[1]); 1079 1.1.2.2 skrll CEMAC_WRITE(ETH_CFG, cfg); 1080 1.1.2.2 skrll CEMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); 1081 1.1.2.2 skrll } 1082
Indexes created Wed Oct 22 13:09:56 GMT 2025