if_cemac.c revision 1.1
1 /* $NetBSD: if_cemac.c,v 1.1 2015/01/23 12:34:09 hkenken Exp $ */ 2 3 /* 4 * Copyright (c) 2015 Genetec Corporation. All rights reserved. 5 * Written by Hashimoto Kenichi for Genetec Corporation. 6 * 7 * Based on arch/arm/at91/at91emac.c 8 * 9 * Copyright (c) 2007 Embedtronics Oy 10 * All rights reserved. 11 * 12 * Copyright (c) 2004 Jesse Off 13 * All rights reserved. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * Cadence EMAC/GEM ethernet controller IP driver 39 * used by arm/at91, arm/zynq SoC 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: if_cemac.c,v 1.1 2015/01/23 12:34:09 hkenken Exp $"); 44 45 #include <sys/types.h> 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/ioctl.h> 49 #include <sys/kernel.h> 50 #include <sys/proc.h> 51 #include <sys/malloc.h> 52 #include <sys/time.h> 53 #include <sys/device.h> 54 #include <uvm/uvm_extern.h> 55 56 #include <sys/bus.h> 57 #include <machine/intr.h> 58 59 #include <arm/cpufunc.h> 60 61 #include <net/if.h> 62 #include <net/if_dl.h> 63 #include <net/if_types.h> 64 #include <net/if_media.h> 65 #include <net/if_ether.h> 66 67 #include <dev/mii/mii.h> 68 #include <dev/mii/miivar.h> 69 70 #ifdef INET 71 #include <netinet/in.h> 72 #include <netinet/in_systm.h> 73 #include <netinet/in_var.h> 74 #include <netinet/ip.h> 75 #include <netinet/if_inarp.h> 76 #endif 77 78 #ifdef NS 79 #include <netns/ns.h> 80 #include <netns/ns_if.h> 81 #endif 82 83 #include <net/bpf.h> 84 #include <net/bpfdesc.h> 85 86 #ifdef IPKDB_AT91 // @@@ 87 #include <ipkdb/ipkdb.h> 88 #endif 89 90 #include <dev/cadence/cemacreg.h> 91 #include <dev/cadence/if_cemacvar.h> 92 93 #define DEFAULT_MDCDIV 32 94 95 #define CEMAC_READ(x) \ 96 bus_space_read_4(sc->sc_iot, sc->sc_ioh, (x)) 97 #define CEMAC_WRITE(x, y) \ 98 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (x), (y)) 99 #define CEMAC_GEM_WRITE(x, y) \ 100 do { \ 101 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) \ 102 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (GEM_##x), (y)); \ 103 else \ 104 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (ETH_##x), (y)); \ 105 } while(0) 106 107 #define RX_QLEN 64 108 #define TX_QLEN 2 /* I'm very sorry but that's where we can get */ 109 110 struct cemac_qmeta { 111 struct mbuf *m; 112 bus_dmamap_t m_dmamap; 113 }; 114 115 struct cemac_softc { 116 device_t sc_dev; 117 bus_space_tag_t sc_iot; 118 bus_space_handle_t sc_ioh; 119 bus_dma_tag_t sc_dmat; 120 uint8_t sc_enaddr[ETHER_ADDR_LEN]; 121 struct ethercom sc_ethercom; 122 mii_data_t sc_mii; 123 124 void *rbqpage; 125 unsigned rbqlen; 126 bus_addr_t rbqpage_dsaddr; 127 bus_dmamap_t rbqpage_dmamap; 128 void *tbqpage; 129 unsigned tbqlen; 130 bus_addr_t tbqpage_dsaddr; 131 bus_dmamap_t tbqpage_dmamap; 132 133 volatile struct eth_dsc *RDSC; 134 int rxqi; 135 struct cemac_qmeta rxq[RX_QLEN]; 136 volatile struct eth_dsc *TDSC; 137 int txqi, txqc; 138 struct cemac_qmeta txq[TX_QLEN]; 139 callout_t cemac_tick_ch; 140 141 int cemac_flags; 142 }; 143 144 static void cemac_init(struct cemac_softc *); 145 static int cemac_gctx(struct cemac_softc *); 146 static int cemac_mediachange(struct ifnet *); 147 static void cemac_mediastatus(struct ifnet *, struct ifmediareq *); 148 static int cemac_mii_readreg(device_t, int, int); 149 static void cemac_mii_writereg(device_t, int, int, int); 150 static void cemac_statchg(struct ifnet *); 151 static void cemac_tick(void *); 152 static int cemac_ifioctl(struct ifnet *, u_long, void *); 153 static void cemac_ifstart(struct ifnet *); 154 static void cemac_ifwatchdog(struct ifnet *); 155 static int cemac_ifinit(struct ifnet *); 156 static void cemac_ifstop(struct ifnet *, int); 157 static void cemac_setaddr(struct ifnet *); 158 159 #ifdef CEMAC_DEBUG 160 int cemac_debug = CEMAC_DEBUG; 161 #define DPRINTFN(n,fmt) if (cemac_debug >= (n)) printf fmt 162 #else 163 #define DPRINTFN(n,fmt) 164 #endif 165 166 CFATTACH_DECL_NEW(cemac, sizeof(struct cemac_softc), 167 cemac_match, cemac_attach, NULL, NULL); 168 169 int 170 cemac_match_common(device_t parent, cfdata_t match, void *aux) 171 { 172 if (strcmp(match->cf_name, "cemac") == 0) 173 return 1; 174 return 0; 175 } 176 177 void 178 cemac_attach_common(device_t self, bus_space_tag_t iot, 179 bus_space_handle_t ioh, bus_dma_tag_t dmat, int flags) 180 { 181 struct cemac_softc *sc = device_private(self); 182 prop_data_t enaddr; 183 uint32_t u; 184 185 186 sc->sc_dev = self; 187 sc->sc_ioh = ioh; 188 sc->sc_iot = iot; 189 sc->sc_dmat = dmat; 190 sc->cemac_flags = flags; 191 192 aprint_naive("\n"); 193 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 194 aprint_normal(": Cadence Gigabit Ethernet Controller\n"); 195 else 196 aprint_normal(": Cadence Ethernet Controller\n"); 197 198 /* configure emac: */ 199 CEMAC_WRITE(ETH_CTL, 0); // disable everything 200 CEMAC_WRITE(ETH_IDR, -1); // disable interrupts 201 CEMAC_WRITE(ETH_RBQP, 0); // clear receive 202 CEMAC_WRITE(ETH_TBQP, 0); // clear transmit 203 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 204 CEMAC_WRITE(ETH_CFG, 205 GEM_CFG_CLK_64 | GEM_CFG_GEN | ETH_CFG_SPD | ETH_CFG_FD); 206 else 207 CEMAC_WRITE(ETH_CFG, 208 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 209 //CEMAC_WRITE(ETH_TCR, 0); // send nothing 210 //(void)CEMAC_READ(ETH_ISR); 211 u = CEMAC_READ(ETH_TSR); 212 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 213 | ETH_TSR_IDLE | ETH_TSR_RLE 214 | ETH_TSR_COL|ETH_TSR_OVR))); 215 u = CEMAC_READ(ETH_RSR); 216 CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR|ETH_RSR_REC|ETH_RSR_BNA))); 217 218 /* Fetch the Ethernet address from property if set. */ 219 enaddr = prop_dictionary_get(device_properties(self), "mac-address"); 220 221 if (enaddr != NULL) { 222 KASSERT(prop_object_type(enaddr) == PROP_TYPE_DATA); 223 KASSERT(prop_data_size(enaddr) == ETHER_ADDR_LEN); 224 memcpy(sc->sc_enaddr, prop_data_data_nocopy(enaddr), 225 ETHER_ADDR_LEN); 226 } else { 227 static const uint8_t hardcoded[ETHER_ADDR_LEN] = { 228 0x00, 0x0d, 0x10, 0x81, 0x0c, 0x94 229 }; 230 memcpy(sc->sc_enaddr, hardcoded, ETHER_ADDR_LEN); 231 } 232 233 cemac_init(sc); 234 } 235 236 static int 237 cemac_gctx(struct cemac_softc *sc) 238 { 239 struct ifnet * ifp = &sc->sc_ethercom.ec_if; 240 uint32_t tsr; 241 242 tsr = CEMAC_READ(ETH_TSR); 243 if (!ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 244 // no space left 245 if (!(tsr & ETH_TSR_BNQ)) 246 return 0; 247 } else { 248 if (tsr & GEM_TSR_TXGO) 249 return 0; 250 } 251 CEMAC_WRITE(ETH_TSR, tsr); 252 253 // free sent frames 254 while (sc->txqc > (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM) ? 0 : 255 (tsr & ETH_TSR_IDLE ? 0 : 1))) { 256 int bi = sc->txqi % TX_QLEN; 257 258 DPRINTFN(3,("%s: TDSC[%i].Addr 0x%08x\n", 259 __FUNCTION__, bi, sc->TDSC[bi].Addr)); 260 DPRINTFN(3,("%s: TDSC[%i].Info 0x%08x\n", 261 __FUNCTION__, bi, sc->TDSC[bi].Info)); 262 263 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 264 sc->txq[bi].m->m_pkthdr.len, BUS_DMASYNC_POSTWRITE); 265 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 266 m_freem(sc->txq[bi].m); 267 DPRINTFN(2,("%s: freed idx #%i mbuf %p (txqc=%i)\n", 268 __FUNCTION__, bi, sc->txq[bi].m, sc->txqc)); 269 sc->txq[bi].m = NULL; 270 sc->txqi = (bi + 1) % TX_QLEN; 271 sc->txqc--; 272 } 273 274 // mark we're free 275 if (ifp->if_flags & IFF_OACTIVE) { 276 ifp->if_flags &= ~IFF_OACTIVE; 277 /* Disable transmit-buffer-free interrupt */ 278 /*CEMAC_WRITE(ETH_IDR, ETH_ISR_TBRE);*/ 279 } 280 281 return 1; 282 } 283 284 int 285 cemac_intr(void *arg) 286 { 287 struct cemac_softc *sc = (struct cemac_softc *)arg; 288 struct ifnet * ifp = &sc->sc_ethercom.ec_if; 289 uint32_t imr, isr, ctl; 290 #ifdef CEMAC_DEBUG 291 uint32_t rsr; 292 #endif 293 int bi; 294 295 imr = ~CEMAC_READ(ETH_IMR); 296 if (!(imr & (ETH_ISR_RCOM|ETH_ISR_TBRE|ETH_ISR_TIDLE|ETH_ISR_RBNA|ETH_ISR_ROVR|ETH_ISR_TCOM))) { 297 // interrupt not enabled, can't be us 298 return 0; 299 } 300 301 isr = CEMAC_READ(ETH_ISR); 302 CEMAC_WRITE(ETH_ISR, isr); 303 isr &= imr; 304 #ifdef CEMAC_DEBUG 305 rsr = CEMAC_READ(ETH_RSR); // get receive status register 306 #endif 307 DPRINTFN(2, ("%s: isr=0x%08X rsr=0x%08X imr=0x%08X\n", __FUNCTION__, isr, rsr, imr)); 308 309 if (isr & ETH_ISR_RBNA) { // out of receive buffers 310 CEMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear interrupt 311 ctl = CEMAC_READ(ETH_CTL); // get current control register value 312 CEMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); // disable receiver 313 CEMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear BNA bit 314 CEMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); // re-enable receiver 315 ifp->if_ierrors++; 316 ifp->if_ipackets++; 317 DPRINTFN(1,("%s: out of receive buffers\n", __FUNCTION__)); 318 } 319 if (isr & ETH_ISR_ROVR) { 320 CEMAC_WRITE(ETH_RSR, ETH_RSR_OVR); // clear interrupt 321 ifp->if_ierrors++; 322 ifp->if_ipackets++; 323 DPRINTFN(1,("%s: receive overrun\n", __FUNCTION__)); 324 } 325 326 if (isr & ETH_ISR_RCOM) { // packet has been received! 327 uint32_t nfo; 328 DPRINTFN(2,("#2 RDSC[%i].INFO=0x%08X\n", sc->rxqi % RX_QLEN, sc->RDSC[sc->rxqi % RX_QLEN].Info)); 329 while (sc->RDSC[(bi = sc->rxqi % RX_QLEN)].Addr & ETH_RDSC_F_USED) { 330 int fl; 331 struct mbuf *m; 332 333 nfo = sc->RDSC[bi].Info; 334 fl = (nfo & ETH_RDSC_I_LEN) - 4; 335 DPRINTFN(2,("## nfo=0x%08X\n", nfo)); 336 337 MGETHDR(m, M_DONTWAIT, MT_DATA); 338 if (m != NULL) MCLGET(m, M_DONTWAIT); 339 if (m != NULL && (m->m_flags & M_EXT)) { 340 bus_dmamap_sync(sc->sc_dmat, sc->rxq[bi].m_dmamap, 0, 341 MCLBYTES, BUS_DMASYNC_POSTREAD); 342 bus_dmamap_unload(sc->sc_dmat, 343 sc->rxq[bi].m_dmamap); 344 sc->rxq[bi].m->m_pkthdr.rcvif = ifp; 345 sc->rxq[bi].m->m_pkthdr.len = 346 sc->rxq[bi].m->m_len = fl; 347 bpf_mtap(ifp, sc->rxq[bi].m); 348 DPRINTFN(2,("received %u bytes packet\n", fl)); 349 (*ifp->if_input)(ifp, sc->rxq[bi].m); 350 if (mtod(m, intptr_t) & 3) 351 m_adj(m, mtod(m, intptr_t) & 3); 352 sc->rxq[bi].m = m; 353 bus_dmamap_load(sc->sc_dmat, 354 sc->rxq[bi].m_dmamap, 355 m->m_ext.ext_buf, MCLBYTES, 356 NULL, BUS_DMA_NOWAIT); 357 bus_dmamap_sync(sc->sc_dmat, sc->rxq[bi].m_dmamap, 0, 358 MCLBYTES, BUS_DMASYNC_PREREAD); 359 sc->RDSC[bi].Info = 0; 360 sc->RDSC[bi].Addr = 361 sc->rxq[bi].m_dmamap->dm_segs[0].ds_addr 362 | (bi == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0); 363 } else { 364 /* Drop packets until we can get replacement 365 * empty mbufs for the RXDQ. 366 */ 367 if (m != NULL) 368 m_freem(m); 369 ifp->if_ierrors++; 370 } 371 sc->rxqi++; 372 } 373 } 374 375 if (cemac_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) 376 cemac_ifstart(ifp); 377 #if 0 // reloop 378 irq = CEMAC_READ(IntStsC); 379 if ((irq & (IntSts_RxSQ|IntSts_ECI)) != 0) 380 goto begin; 381 #endif 382 383 return (1); 384 } 385 386 387 static void 388 cemac_init(struct cemac_softc *sc) 389 { 390 bus_dma_segment_t segs; 391 int rsegs, err, i; 392 struct ifnet * ifp = &sc->sc_ethercom.ec_if; 393 uint32_t u; 394 #if 0 395 int mdcdiv = DEFAULT_MDCDIV; 396 #endif 397 398 callout_init(&sc->cemac_tick_ch, 0); 399 400 // ok... 401 CEMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 402 CEMAC_WRITE(ETH_IDR, -1); // disable interrupts 403 CEMAC_WRITE(ETH_RBQP, 0); // clear receive 404 CEMAC_WRITE(ETH_TBQP, 0); // clear transmit 405 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 406 CEMAC_WRITE(ETH_CFG, 407 GEM_CFG_CLK_64 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 408 else 409 CEMAC_WRITE(ETH_CFG, 410 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 411 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 412 CEMAC_WRITE(GEM_DMA_CFG, 413 __SHIFTIN((MCLBYTES + 63) / 64, GEM_DMA_CFG_RX_BUF_SIZE) | 414 __SHIFTIN(3, GEM_DMA_CFG_RX_PKTBUF_MEMSZ_SEL) | 415 GEM_DMA_CFG_TX_PKTBUF_MEMSZ_SEL | 416 __SHIFTIN(16, GEM_DMA_CFG_AHB_FIXED_BURST_LEN) | 417 GEM_DMA_CFG_DISC_WHEN_NO_AHB); 418 } 419 // CEMAC_WRITE(ETH_TCR, 0); // send nothing 420 // (void)CEMAC_READ(ETH_ISR); 421 u = CEMAC_READ(ETH_TSR); 422 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 423 | ETH_TSR_IDLE | ETH_TSR_RLE 424 | ETH_TSR_COL|ETH_TSR_OVR))); 425 u = CEMAC_READ(ETH_RSR); 426 CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR|ETH_RSR_REC|ETH_RSR_BNA))); 427 428 #if 0 429 if (device_cfdata(sc->sc_dev)->cf_flags) 430 mdcdiv = device_cfdata(sc->sc_dev)->cf_flags; 431 #endif 432 /* set ethernet address */ 433 CEMAC_GEM_WRITE(SA1L, (sc->sc_enaddr[3] << 24) 434 | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8) 435 | (sc->sc_enaddr[0])); 436 CEMAC_GEM_WRITE(SA1H, (sc->sc_enaddr[5] << 8) 437 | (sc->sc_enaddr[4])); 438 CEMAC_GEM_WRITE(SA2L, 0); 439 CEMAC_GEM_WRITE(SA2H, 0); 440 CEMAC_GEM_WRITE(SA3L, 0); 441 CEMAC_GEM_WRITE(SA3H, 0); 442 CEMAC_GEM_WRITE(SA4L, 0); 443 CEMAC_GEM_WRITE(SA4H, 0); 444 445 /* Allocate a page of memory for receive queue descriptors */ 446 sc->rbqlen = (ETH_DSC_SIZE * (RX_QLEN + 1) * 2 + PAGE_SIZE - 1) / PAGE_SIZE; 447 sc->rbqlen *= PAGE_SIZE; 448 DPRINTFN(1,("%s: rbqlen=%i\n", __FUNCTION__, sc->rbqlen)); 449 450 err = bus_dmamem_alloc(sc->sc_dmat, sc->rbqlen, 0, 451 MAX(16384, PAGE_SIZE), // see EMAC errata why forced to 16384 byte boundary 452 &segs, 1, &rsegs, BUS_DMA_WAITOK); 453 if (err == 0) { 454 DPRINTFN(1,("%s: -> bus_dmamem_map\n", __FUNCTION__)); 455 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, sc->rbqlen, 456 &sc->rbqpage, (BUS_DMA_WAITOK|BUS_DMA_COHERENT)); 457 } 458 if (err == 0) { 459 DPRINTFN(1,("%s: -> bus_dmamap_create\n", __FUNCTION__)); 460 err = bus_dmamap_create(sc->sc_dmat, sc->rbqlen, 1, 461 sc->rbqlen, MAX(16384, PAGE_SIZE), BUS_DMA_WAITOK, 462 &sc->rbqpage_dmamap); 463 } 464 if (err == 0) { 465 DPRINTFN(1,("%s: -> bus_dmamap_load\n", __FUNCTION__)); 466 err = bus_dmamap_load(sc->sc_dmat, sc->rbqpage_dmamap, 467 sc->rbqpage, sc->rbqlen, NULL, BUS_DMA_WAITOK); 468 } 469 if (err != 0) 470 panic("%s: Cannot get DMA memory", device_xname(sc->sc_dev)); 471 472 sc->rbqpage_dsaddr = sc->rbqpage_dmamap->dm_segs[0].ds_addr; 473 memset(sc->rbqpage, 0, sc->rbqlen); 474 475 /* Allocate a page of memory for transmit queue descriptors */ 476 sc->tbqlen = (ETH_DSC_SIZE * (TX_QLEN + 1) * 2 + PAGE_SIZE - 1) / PAGE_SIZE; 477 sc->tbqlen *= PAGE_SIZE; 478 DPRINTFN(1,("%s: tbqlen=%i\n", __FUNCTION__, sc->tbqlen)); 479 480 err = bus_dmamem_alloc(sc->sc_dmat, sc->tbqlen, 0, 481 MAX(16384, PAGE_SIZE), // see EMAC errata why forced to 16384 byte boundary 482 &segs, 1, &rsegs, BUS_DMA_WAITOK); 483 if (err == 0) { 484 DPRINTFN(1,("%s: -> bus_dmamem_map\n", __FUNCTION__)); 485 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, sc->tbqlen, 486 &sc->tbqpage, (BUS_DMA_WAITOK|BUS_DMA_COHERENT)); 487 } 488 if (err == 0) { 489 DPRINTFN(1,("%s: -> bus_dmamap_create\n", __FUNCTION__)); 490 err = bus_dmamap_create(sc->sc_dmat, sc->tbqlen, 1, 491 sc->tbqlen, MAX(16384, PAGE_SIZE), BUS_DMA_WAITOK, 492 &sc->tbqpage_dmamap); 493 } 494 if (err == 0) { 495 DPRINTFN(1,("%s: -> bus_dmamap_load\n", __FUNCTION__)); 496 err = bus_dmamap_load(sc->sc_dmat, sc->tbqpage_dmamap, 497 sc->tbqpage, sc->tbqlen, NULL, BUS_DMA_WAITOK); 498 } 499 if (err != 0) 500 panic("%s: Cannot get DMA memory", device_xname(sc->sc_dev)); 501 502 sc->tbqpage_dsaddr = sc->tbqpage_dmamap->dm_segs[0].ds_addr; 503 memset(sc->tbqpage, 0, sc->tbqlen); 504 505 /* Set up pointers to start of each queue in kernel addr space. 506 * Each descriptor queue or status queue entry uses 2 words 507 */ 508 sc->RDSC = (void *)sc->rbqpage; 509 sc->TDSC = (void *)sc->tbqpage; 510 511 /* init TX queue */ 512 for (i = 0; i < TX_QLEN; i++) { 513 sc->TDSC[i].Addr = 0; 514 sc->TDSC[i].Info = ETH_TDSC_I_USED | 515 (i == (TX_QLEN - 1) ? ETH_TDSC_I_WRAP : 0); 516 } 517 518 /* Populate the RXQ with mbufs */ 519 sc->rxqi = 0; 520 for(i = 0; i < RX_QLEN; i++) { 521 struct mbuf *m; 522 523 err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, PAGE_SIZE, 524 BUS_DMA_WAITOK, &sc->rxq[i].m_dmamap); 525 if (err) { 526 panic("%s: dmamap_create failed: %i\n", __FUNCTION__, err); 527 } 528 MGETHDR(m, M_WAIT, MT_DATA); 529 MCLGET(m, M_WAIT); 530 sc->rxq[i].m = m; 531 if (mtod(m, intptr_t) & 3) { 532 m_adj(m, mtod(m, intptr_t) & 3); 533 } 534 err = bus_dmamap_load(sc->sc_dmat, sc->rxq[i].m_dmamap, 535 m->m_ext.ext_buf, MCLBYTES, NULL, 536 BUS_DMA_WAITOK); 537 if (err) { 538 panic("%s: dmamap_load failed: %i\n", __FUNCTION__, err); 539 } 540 sc->RDSC[i].Addr = sc->rxq[i].m_dmamap->dm_segs[0].ds_addr 541 | (i == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0); 542 sc->RDSC[i].Info = 0; 543 bus_dmamap_sync(sc->sc_dmat, sc->rxq[i].m_dmamap, 0, 544 MCLBYTES, BUS_DMASYNC_PREREAD); 545 } 546 547 /* prepare transmit queue */ 548 for (i = 0; i < TX_QLEN; i++) { 549 err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 550 (BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW), 551 &sc->txq[i].m_dmamap); 552 if (err) 553 panic("ARGH #1"); 554 sc->txq[i].m = NULL; 555 } 556 557 /* Program each queue's start addr, cur addr, and len registers 558 * with the physical addresses. 559 */ 560 CEMAC_WRITE(ETH_RBQP, (uint32_t)sc->rbqpage_dsaddr); 561 CEMAC_WRITE(ETH_TBQP, (uint32_t)sc->tbqpage_dsaddr); 562 563 /* Divide HCLK by 32 for MDC clock */ 564 sc->sc_ethercom.ec_mii = &sc->sc_mii; 565 sc->sc_mii.mii_ifp = ifp; 566 sc->sc_mii.mii_readreg = cemac_mii_readreg; 567 sc->sc_mii.mii_writereg = cemac_mii_writereg; 568 sc->sc_mii.mii_statchg = cemac_statchg; 569 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, cemac_mediachange, 570 cemac_mediastatus); 571 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 572 MII_OFFSET_ANY, 0); 573 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 574 575 #if 0 576 // enable / disable interrupts 577 CEMAC_WRITE(ETH_IDR, -1); 578 CEMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 579 | ETH_ISR_RBNA | ETH_ISR_ROVR | ETH_ISR_TCOM); 580 // (void)CEMAC_READ(ETH_ISR); // why 581 582 // enable transmitter / receiver 583 CEMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 584 | ETH_CTL_CSR | ETH_CTL_MPE); 585 #endif 586 /* 587 * We can support 802.1Q VLAN-sized frames. 588 */ 589 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 590 591 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 592 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 593 ifp->if_ioctl = cemac_ifioctl; 594 ifp->if_start = cemac_ifstart; 595 ifp->if_watchdog = cemac_ifwatchdog; 596 ifp->if_init = cemac_ifinit; 597 ifp->if_stop = cemac_ifstop; 598 ifp->if_timer = 0; 599 ifp->if_softc = sc; 600 IFQ_SET_READY(&ifp->if_snd); 601 if_attach(ifp); 602 ether_ifattach(ifp, (sc)->sc_enaddr); 603 } 604 605 static int 606 cemac_mediachange(struct ifnet *ifp) 607 { 608 if (ifp->if_flags & IFF_UP) 609 cemac_ifinit(ifp); 610 return (0); 611 } 612 613 static void 614 cemac_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 615 { 616 struct cemac_softc *sc = ifp->if_softc; 617 618 mii_pollstat(&sc->sc_mii); 619 ifmr->ifm_active = sc->sc_mii.mii_media_active; 620 ifmr->ifm_status = sc->sc_mii.mii_media_status; 621 } 622 623 624 static int 625 cemac_mii_readreg(device_t self, int phy, int reg) 626 { 627 struct cemac_softc *sc; 628 629 sc = device_private(self); 630 631 CEMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_RD 632 | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA) 633 | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA) 634 | ETH_MAN_CODE_IEEE802_3)); 635 while (!(CEMAC_READ(ETH_SR) & ETH_SR_IDLE)); 636 637 return (CEMAC_READ(ETH_MAN) & ETH_MAN_DATA); 638 } 639 640 static void 641 cemac_mii_writereg(device_t self, int phy, int reg, int val) 642 { 643 struct cemac_softc *sc; 644 645 sc = device_private(self); 646 647 CEMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_WR 648 | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA) 649 | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA) 650 | ETH_MAN_CODE_IEEE802_3 651 | (val & ETH_MAN_DATA))); 652 while (!(CEMAC_READ(ETH_SR) & ETH_SR_IDLE)) ; 653 } 654 655 656 static void 657 cemac_statchg(struct ifnet *ifp) 658 { 659 struct cemac_softc *sc = ifp->if_softc; 660 struct mii_data *mii = &sc->sc_mii; 661 uint32_t reg; 662 663 /* 664 * We must keep the MAC and the PHY in sync as 665 * to the status of full-duplex! 666 */ 667 reg = CEMAC_READ(ETH_CFG); 668 reg &= ~ETH_CFG_FD; 669 if (sc->sc_mii.mii_media_active & IFM_FDX) 670 reg |= ETH_CFG_FD; 671 672 reg &= ~ETH_CFG_SPD; 673 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 674 reg &= ~GEM_CFG_GEN; 675 switch (IFM_SUBTYPE(mii->mii_media_active)) { 676 case IFM_10_T: 677 break; 678 case IFM_100_TX: 679 reg |= ETH_CFG_SPD; 680 break; 681 case IFM_1000_T: 682 reg |= ETH_CFG_SPD | GEM_CFG_GEN; 683 break; 684 default: 685 break; 686 } 687 CEMAC_WRITE(ETH_CFG, reg); 688 } 689 690 static void 691 cemac_tick(void *arg) 692 { 693 struct cemac_softc* sc = (struct cemac_softc *)arg; 694 struct ifnet * ifp = &sc->sc_ethercom.ec_if; 695 int s; 696 697 ifp->if_collisions += CEMAC_READ(ETH_SCOL) + CEMAC_READ(ETH_MCOL); 698 /* These misses are ok, they will happen if the RAM/CPU can't keep up */ 699 if (!ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 700 uint32_t misses = CEMAC_READ(ETH_DRFC); 701 if (misses > 0) 702 printf("%s: %d rx misses\n", device_xname(sc->sc_dev), misses); 703 } 704 705 s = splnet(); 706 if (cemac_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) 707 cemac_ifstart(ifp); 708 splx(s); 709 710 mii_tick(&sc->sc_mii); 711 callout_reset(&sc->cemac_tick_ch, hz, cemac_tick, sc); 712 } 713 714 715 static int 716 cemac_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 717 { 718 struct cemac_softc *sc = ifp->if_softc; 719 struct ifreq *ifr = (struct ifreq *)data; 720 int s, error; 721 722 s = splnet(); 723 switch(cmd) { 724 case SIOCSIFMEDIA: 725 case SIOCGIFMEDIA: 726 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 727 break; 728 default: 729 error = ether_ioctl(ifp, cmd, data); 730 if (error == ENETRESET) { 731 if (ifp->if_flags & IFF_RUNNING) 732 cemac_setaddr(ifp); 733 error = 0; 734 } 735 } 736 splx(s); 737 return error; 738 } 739 740 static void 741 cemac_ifstart(struct ifnet *ifp) 742 { 743 struct cemac_softc *sc = (struct cemac_softc *)ifp->if_softc; 744 struct mbuf *m; 745 bus_dma_segment_t *segs; 746 int s, bi, err, nsegs; 747 748 s = splnet(); 749 start: 750 if (cemac_gctx(sc) == 0) { 751 /* Enable transmit-buffer-free interrupt */ 752 CEMAC_WRITE(ETH_IER, ETH_ISR_TBRE); 753 ifp->if_flags |= IFF_OACTIVE; 754 ifp->if_timer = 10; 755 splx(s); 756 return; 757 } 758 759 ifp->if_timer = 0; 760 761 IFQ_POLL(&ifp->if_snd, m); 762 if (m == NULL) { 763 splx(s); 764 return; 765 } 766 767 bi = (sc->txqi + sc->txqc) % TX_QLEN; 768 if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 769 BUS_DMA_NOWAIT)) || 770 sc->txq[bi].m_dmamap->dm_segs[0].ds_addr & 0x3 || 771 sc->txq[bi].m_dmamap->dm_nsegs > 1) { 772 /* Copy entire mbuf chain to new single */ 773 struct mbuf *mn; 774 775 if (err == 0) 776 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 777 778 MGETHDR(mn, M_DONTWAIT, MT_DATA); 779 if (mn == NULL) goto stop; 780 if (m->m_pkthdr.len > MHLEN) { 781 MCLGET(mn, M_DONTWAIT); 782 if ((mn->m_flags & M_EXT) == 0) { 783 m_freem(mn); 784 goto stop; 785 } 786 } 787 m_copydata(m, 0, m->m_pkthdr.len, mtod(mn, void *)); 788 mn->m_pkthdr.len = mn->m_len = m->m_pkthdr.len; 789 IFQ_DEQUEUE(&ifp->if_snd, m); 790 m_freem(m); 791 m = mn; 792 bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 793 BUS_DMA_NOWAIT); 794 } else { 795 IFQ_DEQUEUE(&ifp->if_snd, m); 796 } 797 798 bpf_mtap(ifp, m); 799 800 nsegs = sc->txq[bi].m_dmamap->dm_nsegs; 801 segs = sc->txq[bi].m_dmamap->dm_segs; 802 if (nsegs > 1) 803 panic("#### ARGH #2"); 804 805 sc->txq[bi].m = m; 806 sc->txqc++; 807 808 DPRINTFN(2,("%s: start sending idx #%i mbuf %p (txqc=%i, phys %p), len=%u\n", 809 __FUNCTION__, bi, sc->txq[bi].m, sc->txqc, (void*)segs->ds_addr, 810 (unsigned)m->m_pkthdr.len)); 811 #ifdef DIAGNOSTIC 812 if (sc->txqc > TX_QLEN) 813 panic("%s: txqc %i > %i", __FUNCTION__, sc->txqc, TX_QLEN); 814 #endif 815 816 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 817 sc->txq[bi].m_dmamap->dm_mapsize, 818 BUS_DMASYNC_PREWRITE); 819 820 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) { 821 sc->TDSC[bi].Addr = segs->ds_addr; 822 sc->TDSC[bi].Info = __SHIFTIN(m->m_pkthdr.len, ETH_TDSC_I_LEN) | 823 ETH_TDSC_I_LAST_BUF | (bi == (TX_QLEN - 1) ? ETH_TDSC_I_WRAP : 0); 824 825 DPRINTFN(3,("%s: TDSC[%i].Addr 0x%08x\n", 826 __FUNCTION__, bi, sc->TDSC[bi].Addr)); 827 DPRINTFN(3,("%s: TDSC[%i].Info 0x%08x\n", 828 __FUNCTION__, bi, sc->TDSC[bi].Info)); 829 830 uint32_t ctl = CEMAC_READ(ETH_CTL) | GEM_CTL_STARTTX; 831 CEMAC_WRITE(ETH_CTL, ctl); 832 DPRINTFN(3,("%s: ETH_CTL 0x%08x\n", __FUNCTION__, CEMAC_READ(ETH_CTL))); 833 } else { 834 CEMAC_WRITE(ETH_TAR, segs->ds_addr); 835 CEMAC_WRITE(ETH_TCR, m->m_pkthdr.len); 836 } 837 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 838 goto start; 839 stop: 840 841 splx(s); 842 return; 843 } 844 845 static void 846 cemac_ifwatchdog(struct ifnet *ifp) 847 { 848 struct cemac_softc *sc = (struct cemac_softc *)ifp->if_softc; 849 850 if ((ifp->if_flags & IFF_RUNNING) == 0) 851 return; 852 printf("%s: device timeout, CTL = 0x%08x, CFG = 0x%08x\n", 853 device_xname(sc->sc_dev), CEMAC_READ(ETH_CTL), CEMAC_READ(ETH_CFG)); 854 } 855 856 static int 857 cemac_ifinit(struct ifnet *ifp) 858 { 859 struct cemac_softc *sc = ifp->if_softc; 860 int s = splnet(); 861 862 callout_stop(&sc->cemac_tick_ch); 863 864 // enable interrupts 865 CEMAC_WRITE(ETH_IDR, -1); 866 CEMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 867 | ETH_ISR_RBNA | ETH_ISR_ROVR | ETH_ISR_TCOM); 868 869 // enable transmitter / receiver 870 CEMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 871 | ETH_CTL_CSR | ETH_CTL_MPE); 872 873 mii_mediachg(&sc->sc_mii); 874 callout_reset(&sc->cemac_tick_ch, hz, cemac_tick, sc); 875 ifp->if_flags |= IFF_RUNNING; 876 splx(s); 877 return 0; 878 } 879 880 static void 881 cemac_ifstop(struct ifnet *ifp, int disable) 882 { 883 // uint32_t u; 884 struct cemac_softc *sc = ifp->if_softc; 885 886 #if 0 887 CEMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 888 CEMAC_WRITE(ETH_IDR, -1); // disable interrupts 889 // CEMAC_WRITE(ETH_RBQP, 0); // clear receive 890 if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) 891 CEMAC_WRITE(ETH_CFG, 892 GEM_CFG_CLK_64 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 893 else 894 CEMAC_WRITE(ETH_CFG, 895 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 896 // CEMAC_WRITE(ETH_TCR, 0); // send nothing 897 // (void)CEMAC_READ(ETH_ISR); 898 u = CEMAC_READ(ETH_TSR); 899 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 900 | ETH_TSR_IDLE | ETH_TSR_RLE 901 | ETH_TSR_COL|ETH_TSR_OVR))); 902 u = CEMAC_READ(ETH_RSR); 903 CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR|ETH_RSR_REC|ETH_RSR_BNA))); 904 #endif 905 callout_stop(&sc->cemac_tick_ch); 906 907 /* Down the MII. */ 908 mii_down(&sc->sc_mii); 909 910 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 911 ifp->if_timer = 0; 912 sc->sc_mii.mii_media_status &= ~IFM_ACTIVE; 913 } 914 915 static void 916 cemac_setaddr(struct ifnet *ifp) 917 { 918 struct cemac_softc *sc = ifp->if_softc; 919 struct ethercom *ac = &sc->sc_ethercom; 920 struct ether_multi *enm; 921 struct ether_multistep step; 922 uint8_t ias[3][ETHER_ADDR_LEN]; 923 uint32_t h, nma = 0, hashes[2] = { 0, 0 }; 924 uint32_t ctl = CEMAC_READ(ETH_CTL); 925 uint32_t cfg = CEMAC_READ(ETH_CFG); 926 927 /* disable receiver temporarily */ 928 CEMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); 929 930 cfg &= ~(ETH_CFG_MTI | ETH_CFG_UNI | ETH_CFG_CAF | ETH_CFG_UNI); 931 932 if (ifp->if_flags & IFF_PROMISC) { 933 cfg |= ETH_CFG_CAF; 934 } else { 935 cfg &= ~ETH_CFG_CAF; 936 } 937 938 // ETH_CFG_BIG? 939 940 ifp->if_flags &= ~IFF_ALLMULTI; 941 942 ETHER_FIRST_MULTI(step, ac, enm); 943 while (enm != NULL) { 944 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 945 /* 946 * We must listen to a range of multicast addresses. 947 * For now, just accept all multicasts, rather than 948 * trying to set only those filter bits needed to match 949 * the range. (At this time, the only use of address 950 * ranges is for IP multicast routing, for which the 951 * range is big enough to require all bits set.) 952 */ 953 cfg |= ETH_CFG_CAF; 954 hashes[0] = 0xffffffffUL; 955 hashes[1] = 0xffffffffUL; 956 ifp->if_flags |= IFF_ALLMULTI; 957 nma = 0; 958 break; 959 } 960 961 if (nma < 3) { 962 /* We can program 3 perfect address filters for mcast */ 963 memcpy(ias[nma], enm->enm_addrlo, ETHER_ADDR_LEN); 964 } else { 965 /* 966 * XXX: Datasheet is not very clear here, I'm not sure 967 * if I'm doing this right. --joff 968 */ 969 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 970 971 /* Just want the 6 most-significant bits. */ 972 h = h >> 26; 973 974 hashes[h / 32] |= (1 << (h % 32)); 975 cfg |= ETH_CFG_MTI; 976 } 977 ETHER_NEXT_MULTI(step, enm); 978 nma++; 979 } 980 981 // program... 982 DPRINTFN(1,("%s: en0 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 983 sc->sc_enaddr[0], sc->sc_enaddr[1], sc->sc_enaddr[2], 984 sc->sc_enaddr[3], sc->sc_enaddr[4], sc->sc_enaddr[5])); 985 CEMAC_GEM_WRITE(SA1L, (sc->sc_enaddr[3] << 24) 986 | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8) 987 | (sc->sc_enaddr[0])); 988 CEMAC_GEM_WRITE(SA1H, (sc->sc_enaddr[5] << 8) 989 | (sc->sc_enaddr[4])); 990 if (nma > 1) { 991 DPRINTFN(1,("%s: en1 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 992 ias[0][0], ias[0][1], ias[0][2], 993 ias[0][3], ias[0][4], ias[0][5])); 994 CEMAC_WRITE(ETH_SA2L, (ias[0][3] << 24) 995 | (ias[0][2] << 16) | (ias[0][1] << 8) 996 | (ias[0][0])); 997 CEMAC_WRITE(ETH_SA2H, (ias[0][4] << 8) 998 | (ias[0][5])); 999 } 1000 if (nma > 2) { 1001 DPRINTFN(1,("%s: en2 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 1002 ias[1][0], ias[1][1], ias[1][2], 1003 ias[1][3], ias[1][4], ias[1][5])); 1004 CEMAC_WRITE(ETH_SA3L, (ias[1][3] << 24) 1005 | (ias[1][2] << 16) | (ias[1][1] << 8) 1006 | (ias[1][0])); 1007 CEMAC_WRITE(ETH_SA3H, (ias[1][4] << 8) 1008 | (ias[1][5])); 1009 } 1010 if (nma > 3) { 1011 DPRINTFN(1,("%s: en3 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 1012 ias[2][0], ias[2][1], ias[2][2], 1013 ias[2][3], ias[2][4], ias[2][5])); 1014 CEMAC_WRITE(ETH_SA3L, (ias[2][3] << 24) 1015 | (ias[2][2] << 16) | (ias[2][1] << 8) 1016 | (ias[2][0])); 1017 CEMAC_WRITE(ETH_SA3H, (ias[2][4] << 8) 1018 | (ias[2][5])); 1019 } 1020 CEMAC_GEM_WRITE(HSH, hashes[0]); 1021 CEMAC_GEM_WRITE(HSL, hashes[1]); 1022 CEMAC_WRITE(ETH_CFG, cfg); 1023 CEMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); 1024 } 1025
Indexes created Tue Sep 23 07:09:52 GMT 2025